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1 /03/ /03/18 yyyy/mm/dd

2 2000/03/

3 VHDL VHDL Identifiers) (operator) function procedure ( generics) package FSM Comments TAB Latch VHDL VHDL VERILOG Verilog Modules Net and Register Expressions IF case Writing functions Assignment Combinatorial Vs Sequential Logic Macros Comments FSM

4 RAM process Latch inout std_logic VHDL VHDL ALTERA SETRESET ASIC ASIC ASIC ASIC testbench Module

5 IF Case if loop Pipelining fanout Xilinx Xilinx VHDL Barrel Shifter CLBIOB IOB Buffer Set/Reset Buffer I/O JTAG CoreGen/LogiBLOX VHDLArchitecture HDL Generic VHDL Entity_ArchitectureConfiguration LOOP IEEE

6 5.3 package VHDLVerilog... 6ClockReset Buffer LATCH

7 VHDL 1 VHDL VHDL ASIC/FPGA 2 VHDL VHDL 3 VHDL FSM simulate Very high speed IC Hardware Description Language, Finite Status Machine, RTL C 4 VHDL For Programmable Logic Mr,Kevin Shahill USA VHDL

8 VHDL VHDL RTL behavioral, gate_level) Identifiers) VHDL 1. Packet_addr, Data_in, Mem_wr, Mem_ce VHDL Addr address Clk clock Clr clear Cnt counter En enable Inc increase Lch latch Mem memory Pntr pointer Pst preset Rst reset Reg register Rd reader Wr write ROM RAM CPU FIFO ALU CS CE 4. Addr_in Addr_en en RAM_addr Rd_CPU_en

9 Data_in Cnt8_q Din FIFO_out 8 _clk _d _q _z _L _s _en _n _xi _xo _xod _xz _xbio FIFO _L _L1 1. D _L, _L1 _L2... L lock 2. _s s same VHDL VHDL Cnt8_q STD_LOGIC_VECTOR + Cnt8_q <= Cnt8_q use IEEE.std_logic_arith.all 2. signal Addr STD_LOGIC_VECTOR(31 downto 0); alias Top_addr STD_LOGIC_VECTOR(3 downto 0) is Addr(31 downto 28) 3. Z z

10 VHDL 3. VHDL (signal) process Sig_p process(a B C end D <= A X <= C or D ignored!! D <= B ---- overrids!! Y <= C xor D B D C xor B X Y Ver_p process(a B C variable d d = A X <= C or d d end process = B Y <= C xor d X <= C or A STD_LOGIC Y<= C xor B 1. library IEEE use IEEE.std_logic_1164.all IEEE buffer

11 Count signal Cnt8_q STD_LOGIC_VECTOR(7 downto 0) Cnt8_q Count <= Cnt8_q IEEE std_logic_1164 STD_ULOGIC STD_LOGIC IEEE 1076 /93 BIT BITINTEGER % -- Filename -- Author -- Description -- Called by Top module -- Revision History Revision Company Huawei Technologies.Inc --Copyright(c) 1999, Huawei Technologies Inc, All right reserved library IEEE; use IEEE.std_logic_1164.all; entity ENTITY_NAME port( Port1 : in STD_LOGIC; Port2 : in STD_LOGIC; Port3 : out STD_LOGIC;.. Portn : out STD_LOGIC

12 ); end ENTITY_NAME ; architecture BEHAVIOR of ENTITY_NAME is Statements; end BEHAVIOR ; 2. COUNTER8 8 DECODER BEHAVIOR A B... architecture BEHAVIOR of COUNTER8 is... end BEHAVIOR; STRUCTURE configuration BOOLEAN VHDL Core VHDL 3. VHDL VHDL Top-To-down in out buffer inout in out VHDL VHDL with-select-when

13 with- select - when with selection_signal select Select_name <= value_a when value_1_of_selection_signal value_b when value_2_of_selection_signal value_c when value_3_of_selection_signal... value_x when last_value_of_selection_signal with- select - when selection_signal others S X RTL RTL with S select with- select - when X <= A when when_else when_else Signal_name <= value_a when condition1 else when else

14 value_c when condition3 else... value_x when a = b and C= 1 else if else else process( Clk,Rst) if ( Rst = '1') then Q <= '0'; elsif ( Clk event and Clk = 1 ) then end process; Q <= D; else case- when with-select-when case- selection_signal is when value1_of _selection signal => Statements1; when value2_of _selection signal =>... Statements2; when last_value_of _selection signal => Statements x ; when others => end case; Statements x; case_when when others if -else case-when process Clk process ClkRst clkprocess Lab process Clk, Rst

15 list1 list2,... process lable process D_p : process(clk,rst, D1,D2,...,Dn) if (Rst = '1' ) then Q1 <= '0' ; Q2 <= '0' ;... Qn <= Dn; elsif (Clk 'event and Clk = '1') then end process; Q1 <= D1; Q2 <= D2;... Qn <= Dn; generate 32 Gen_lab1: for I in 0 to 31 generate end generate; inst_lab: threestate port map( Din => Value(i), Rd => Rd, Dout => Value_out(i) Gen_lab1 ); if -then else elsif G1 for I in 0 to 3 generate G2 for j in 0 to 7 generate G3 if (I <1 ) then generate end generate; Ua : thrst port map( Val(j),Rd,Val_out(j));

16 G4 if (i = 1) then generate... port map Uxx Module_name port map port1 => port 1, port2 => port2,... portn => port n ) port map => port map X downto Y X downto Y port map module RAM entity Uxxcell Core Vxx 2. VHDL - with tmp select X <= A when 1---, B when -1--, C when --1-, D when ---1, 0 when others RTL wait 3. VHDL when_else when if-else when-else If --elsif ---elsif ---else (operator) 1. X <= ( A and B ) and ( C or not D )

17 2. warningerror numeric_std function 1. function function function FUNCTION_NAME ( return is end function IEEE1164 VHDL std_logic bit numeric_std + 3. function procedure 1. procedure procedure procedure PROCEDURE_NAME end procedure... is 2. procedure signal signal in ( generics)

18 1. generic rise fall load Uxx : generic map port map ( 6.5 map package 1. package component use all use work..yourpacketname.all; yourpacketname packet 2. package FSM 1. FSM VHDL FSM VHDLFSM one-hot Comments 1. Comments

19 TAB TAB 4 VHDL TOP MID CORE TOP MID MID 1 2 CORE CORE VHDL R <= ( A + B) when (Source = 1 ) else ( C + D)

20 Resource Sharing A B CDR Source R R <= A when (Source = 1 ) else C; S <= B when (Source = 1 ) else D; F <= R + S; 7.2 4bit C <= A and B; C 3 <= A 3 and B 3 C 2 <= A 2 and B 2 ; C 1 <= A 1 and B 1 ; C 0 <= A 0 and B 0 ; for I in 3 downto 0 loop C i < = A i and B i ; end loop;. 7.3 scripts scripts

21 7.4 Latch Latch Latch if else case others if case latch DataOut process Cond) if (Cond = 1 ) then end end process Data_out <= Data_in 7.5 Tri_p1: process (Sel_a,A) if (Sel_a = 1 ) then else end process; T <= A; T <= Z ; Tri_p2: process (Sel_b,B) if (Sel_b = 1 ) then else end process; T <= B; T <= Z ; process Error : process (Sel_a,A,Sel_b,B) if (Sel_a = 1 ) then

22 else T <= A; T <= Z ; if (Sel_b = 1 ) then else end process; T <= B; T <= Z ; if T if process process VHDL VHDL absaccess after alias all and architecture array assert attribute block buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port postponed procedure process pure range record register reject rem report return rol ror select severity signal shared sla sll sra srl subtype then to transport type unaffected units until use variablewait when while with xnor xor 8.2 VHDL -- Filename Div5.vhd -- Author zhouzhijian

23 -- Description Five division -- Called by Top module -- Revision History library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity DIV5 is port( Rst : in STD_LOGIC; Mclk : in STD_LOGIC; Div5_clk : out STD_LOGIC ); end DIV5; architecture BEHAVIOR of DIV5 is signal Cnt3_q : STD_LOGIC_VECTOR(2 downto 0); signal Cnt3_d : STD_LOGIC_VECTOR(2 downto 0); signal Div0 : STD_LOGIC; signal Div1 : STD_LOGIC; Cnt_pd : process(cnt3_q) if (Cnt3_q = 100 ) then Cnt3_d <= 000 ; else Cnt3_d <= Cnt3_q + 1; end process; Cnt_pq : process(rst,mclk) if (Rst = '1') then Cnt3_q <= "000"; elsif (Mclk = '1' and Mclk'event) then Cnt3_q <= Cnt3_d;

24 end process ; Div0_P : process(rst,mclk) if (Rst = '1') then Div0 <= '1'; elsif( Mclk = '1' and Mclk'event ) then if (Cnt3_q = "100") then Div0 <= '1'; elsif (Cnt3_q = "001") then Div0 <= '0'; else Div0 <= Div0; end process ; Div1_P : process(rst,mclk) if (Rst = '1') then Div1 <= '0'; elsif (Mclk = '0' and Mclk'event) then Div1 <= Div0; end process ; Div_clk <= Div0 or Div1; end BEHAVIOR; Div Filename FullAdd.vhd

25 -- Author suwenbiao -- Description A example of function -- Called by Top module -- Revision History library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FULLADD is port( A : in STD_LOGIC; B : in STD_LOGIC; Carry_in : in STD_LOGIC; Sum : out STD_LOGIC; Carry_out : out STD_LOGIC ); end FULLADD; architecture BEHAVIOR of FULLADD is function Majority (A,B,C : STD_LOGIC) return STD_LOGIC is return (( A and b) or (A and C) or ( B and C )); end Majority; Sum <= A xor B xor Carry_in; Carry_out <= Majority(A,B,Carry_in); end BEHAVIOR; Filename My_pkg.vhd -- Author suwenbiao -- Description A example of Package -- Called by Top module -- Revision History

26 library IEEE; use IEEE.std_logic_1164.all; package MY_PKG is -- Defined constant constant NUM64K : integer := 65636; constant EXT_RAM_ADD_WIDTH : integer := 16; constant HW_NUM : integer := 4; constant CELL_OUTPUT_CHANNEL_WIDTH : integer := 5; constant INPUT_CHANNEL_WIDTH : integer := ADDRESS_BUS_WIDTH; constant QUEUE_WIDTH : integer := 5; constant WORD_LENGTH_WIDTH : integer := 6; --Define subtype constant QUEUE_OVERFLOAT_WIDTH : integer := 16; subtype QUEUE_OVERFLOAT_VECTOR is STD_LOGIC_VECTOR(QUEUE_OVERFLOAT_WIDTH-1 downto 0); --Defined Reg group component Rddf1 port( Clk : in STD_LOGIC; Rst : in STD_LOGIC; D : in STD_LOGIC; Q :out STD_LOGIC ); end component; component Rreg1 port( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Load : in STD_LOGIC; D : in STD_LOGIC; Q :out STD_LOGIC );

27 end component; component Rreg generic(size : integer := 2); port( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Load : in STD_LOGIC; D : in STD_LOGIC_VECTOR( Size - 1 downto 0); Q :out STD_LOGIC _VECTOR( Size - 1 downto 0) ); end component; end Reg_pkg; Filename Reg_group.vhd -- Author suwenbiao -- Description A example of Reg Group with generic size -- Called by Top module -- Revision History library IEEE; use IEEE.std_logic_1164.all entity REG_GROUP is generic (Size : integer : = 2); port( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Load : in STD_LOGIC; D :in STD_LOGIC_VECTOR(Size - 1 downto 0); Q : out STD_LOGIC_VECTOR(Size - 1 downto 0) ); end REG_GROUP; architecture BEHAVIOR of REG_GROUP is R_p: process(clk,rst)

28 if (Rst = 1 ) then Q <= (others => 0 ) ; elsif(clk event and Clk = 1 ) then Q <= D; end process; end BEHAVIOR; U1 REG_GROUP map(4) port map ( ); Clk => Clk, Rst => Rst, Load => Load, D => D, Q => Q

29 VERILOG 1 VerilogHDL ASIC hardware model) 2 Verilog HDL Testbench Verilog model RTL behavioral, gate_level) 3 Verilog HDL FSM Verilog STA 4 Verilog Style and Coding Guidelines Actel HDL Coding Style Guider Sun Microsystems Revision Verilog Verilog model RTL behavioral, gate_level)

30 For ( I = 0; I < 1024; I = I + 1 ) Mem[I] <= #1 32 b0; For I loop_index Clk Rst Addr Pntr clock reset address pointer Rst_ Trdy_, Irdy_ Idsel. parameter, integer Packet_addr, Data_in, Mem_wr Mem_ce_ D_addr[7:2] D (Decoder module) parameter CYCLE=100 in out x z _Clk _next _z _f _xi _xo _xod _xz -xbio Modules

31 Verilog reg Synopsys design compiler /* *\ Filename RX_MUX.v Author Description Called by Top module Revision History Revision 1.0 Company Huawei Technology.Inc Copyright(c) 1999, Huawei Technology Inc, All right reserved \* */ Inpu t, module warning module Uxx name_based Instance order_based UInstance2(.DataOut (DOUT ),.DataIn (DIN ),.Cs_ (Cs_ ) ); Clock Posedge Clk_

32 Module Module DFF_ASYNC_RST( IO (pads) Reset, Clk, Data, Qout ); JTAG (CORE) 1-1 DC DC DC DC Net and Register reg always Data[-4 0] LSB[0][-1][-2][-3][-4]MSB Data[0 4]

33 LSB[4][3][2][1][0]MSB Expressions IF Data[4 0] netregister PORT Verilog wire If ((alpha < beta) && (gamma >= delta))... If (alpha < beta && gamma >= delta)... (function) (task) verilog 0... Reg Abc [7:0]; Reg Bca [3:0]; If (Abc = = {4 b0, Bca})... If (Abc = = 8 b0) If else else RTL End // Else if (Cond) DataOut <= DataIn; DataOut. If..else if...else if...else

34 If-else case V1 = 2 b00; V2 = 2 b00; V3 = 2 b00; If (a = = b) End V1 = 2 b01; V2 = 2 b10; Else if (a = = c) End Else case V2 = 2 b10; V3 = 2 b11; //V3 is not assigned //V1 is not assigned case if-then-else case if case Case default case Writing functions Default : ; function function Function CompareVectors; // (Vector1, Vector2, Length) Input [199:0] Vector1, Vector2; Input [31:0] Length; //local variables Integer i;

35 Reg Equal; Begin i = 0; Equal = 1; While ((i<length) && Equal) If (Vector 2[i]!== 1 bx) If (Vector1[i]!== Vector2[i]) Equal = 0; Else ; End i = i + 1; End CompareVectors = Equal; End Endfunction //comparevectors HDL function ByteCompare input [15:0] Vector1 input [15:0] Vector2 input [7:0] Length if (ByteSel) // compare the upper byte else // compare the lower byte end endfunction // ByteCompare ByteSel Assignment Verilog (procedural) (continuous) initial, always, task or function) reg integertime\realtime real wire

36 or Clr) if (Clr) q = 1'b0; else if (e) q = d; e, Assign/deassign Force/release debug Disable reg reg == End Clk or negedge Rst_) Begin If (!Rst_) Begin Rega <= 0; Regb <= 0; End Else if (Soft_rst_all) Begin // prioritize the if conditions in if statement //non_blocking assignment Rega <= #u_dly 0; //add unit delay Regb <= #u_dly 0; End Else if (Load_init) Else Begin Rega <= #u_dly Regb <= #u_dly End Begin init_rega; init_regb; Rega <= #u_dly Rega << 1; Regb <= #u_dly End St_1; // end Rega, Regb assignment Combinatorial Vs Sequential Logic

37 Wire Ct_24_e4; //it ccarries info. Last over several clock cycles Assign Ct_24_e4 = (count8bit[7:0] >= 8 h24) & (count8bit[7:0] <= 8 he4); 8 Reg Ct_24_e4; Clk or negedge Rst_) Begin If (!Rst_) Ct_24_e4 <= 1 b0; Else if (count8bit[7:0] = = 8 he4) Ct_24_e4 <= #u_dly 1 b0; Else if (count8bit[7:0] = = 8 h23) Esle ; Ct_24_e4 <= #u_dly 1 b1; default Wire Assign OE_default; OE_default =!(oe1 oe2 oe3); Assign bus[31:0] = oe1? Data1[31:0] : oe2? Data2[31:0] : oe3? Data3[31:0] : oe_default? 32 h0000_0000 : 32 hzzzz_zzzz; Macros `define `define parameter Comments `define `define //style 1 If (~OE_ && (state!= PENDING))... End // if enable = = ture and ready

38 //style identical lables on and end If (~OE_ && (state!= PENDING)) //drive data End... //drive data // Comment end<unit> with the name of the <unit> Function Calcparity... Endfunction // Calcparity //Data, ParityErr FSM VerilogHDL VerilogHDL parameter, VHDLVHDL Mealy,Moore Mealy :... reg CurrentState, NextState, Out1; Parameter S0=0,S1=1; Clk or negedge Rst_) // state vector flip-flops (sequential) if (!Reset) CurrentState = S0; else CurrentState <= #u_dly NextState; or In2 or CurrentState) // output and state vector decode (combinational) case (CurrentState) S0: NextState <= #u_dly S1; Out1 <= #u_dly 1'b0;

39 end S1: if (In1) NextState <= #u_dly S0; Out1 <= #u_dly In2; end else NextState <= #u_dly S1; Out1 <= #u_dly!in2; end endcase endmodule 5.2 for-loop for (i=0;i<4;i=i+1) end Sig1 = Sig2; DataOut[i] = DataIn[i]; for-loop,. z = (cond)? (a + b) : (c + d); ; if-then-else if (Cond) else z = a + b; z = c + d;, module COUNT (AndBits, Clk, Rst); Output Input Reg //internal reg Andbits; Clk, Rst; AndBits;

40 Reg [2:0] Count; Clk) if (Rst) else End End Count <= #u_dly 0; Count <= #u_dly Count + 1; //end if AndBits <= #u_dly & Count; endmodule //end always,4; module COUNT (AndBits, Clk, Rst); Output Input Reg //internal reg AndBits; Clk, Rst; AndBits; Reg [2:0] Count; Clk) //synchronous if (Rst) Count <= #u_dly 0; else Count <= #u_dly Count + 1; End //end always //asynchronous AndBits = & Count; End //end always Endmodule //end COUNT, 3. module COUNT (Z, Enable, Clk, Rst); Output [2:0] Z; Input Rst,

41 Enable, Clk; reg [2:0] Z; Clk) if (Rst) end Z <= #u_dly 1'b0; else if (Enable == 1'b1) End Else ; End If (Z == 3'd7) End Z <= #u_dly 1'b0; else end Endmodule Z <= #u_dly Z + 1'b1; //end always //end COUNT,.. module COUNT (Z, Enable, Clk, Rst); Output [2:0] Z; Input Rst, Enable, Clk; Reg [2:0] Z; //internal wire wire GATED_Clk = Clk & Enable; GATED_Clk or posedge Rst) if (Rst) Z <= #u_dly 1'b0; end else if (Z == 3'd7) Z <= #u_dly 1'b0;

42 end else Z <= #u_dly Z + 1'b1; end End //end if End //end always Endmodule //end module c = a &b; c[3:0] = a[3:0] & b[3:0]; c[3] = a[3] & b[3]; c[2] = a[2] & b[2]; c[1] = a[1] & b[1]; c[0] = a[0] & b[0]; for ( i=0; i<=3; i = i + 1) c[i] = a[i] & b[i];. scripts scripts 500~5000 Point-to-point exception (False path)

43 STA warning Latch Latch All_registers -level_sensitive Latch Latch if else case defaults Latch ifcase latch DataOut end if (Cond) DataOut <= DataIn (Gated clock) Power compiler : module COUNT (Reset Enable Clk Qout) module COUNT (Reset Enable input Reset Enable Clk input Reset Enable Clk Clk Qout) output [2:0] Qout output [2:0] Qout reg [2:0] Qout reg [2:0] Qout

44 wire GATED_Clk = Clk & Enable Clk) if (Reset) GATED_Clk or posedge Reset) Qout = 1'b0 end if (Reset) else if (Enable == 1'b1) Qout = 1'b0 if (Qout == 3'd7) end Qout = 1'b0 else end if (Qout == 3'd7) else Qout= 1'b0 Qout = Qout + 1'b1 end end else end Qout = Qout + 1'b1 end end endmodule end end endmodule Module /* *\ Filename Author Description Called by Revision History mm/dd/yy Revision 1.0 M@sz.huawei.com.cn Company Huawei Technology.Inc Copyright(c) 1999, Huawei Technology Inc, All right reserved

45 \* */ Module module_name( //port declarations Output_ports, Input_ports, Io_ports, Clk_port, Rst_port Output [31:;0] Dataout; Input [31:0] Datain; Inout Input ); Bi_dir_signal; input1, Input2; //comment ; port description //comment ; port description //comment ; port descripttion //comment ; port description //comment ; port description //interrnal wire/reg declarations Wire [31:0] internal_data; Reg output_enable; //module instantiations, Self-build module Module_name1 Uinstance_name1(...); Module_name2 Uinstance_name2(...); // TSC4000 cell DTC12 V1 (.Clk(Clk),.CLRZ(Clr),.D(Data),.Q(Qout)); //continuous assignment Assign Data_out = out_enable? Internal_data : 32 hz; //always block Begin... End //function and task definitions Functiom [function_type] function_name; Declarations_of_inputs;

46 [declarations_of_local_variables]; Begin Behavirol_statement; Function_name = function_express; End Endfunction //end function_name Endmodule //end module_name 6.2 testbench module TB_GRAY; reg Clock; reg Reset; wire [7:0] Qout; integer fout; // parameter CYC = 20; GRAY DUT(.Clock(Clock),.Reset(Reset),.Qout(Qout)); initial Clock = 1'b0; Reset =1'b1; #(5*CYC) Reset = 1'b0; #(5*CYC) Reset = 1'b1; #(5000*CYC) $fclose(fout); $finish; end initial $shm_open("gray.shm"); $shm_probe("as"); fout=$fopen("gray.dat"); end

47 always #CYC Clock = ~ Clock; // gray.dat Clock) end $fwrite(fout,"%d %b\n",qout,qout); endmodule a testbench,#20,#15#(cyc+15), parameter, #(CYC+OFF0), ; b GRAY.shm gray.dat simwave c ASIC ASIC FPGA 1 SOC Xilinx FPGA Virtex-E MHz ASIC SOC ASIC ASIC ASIC ASIC ASIC

48 ASIC ASIC ASIC ASIC ASIC ASIC ASIC ASIC EDA

49 SOC System On a Chip ASIC

50 ASIC ASIC 2. 3 ASIC 3.1 ASIC VHDLVerilog 4. EDA 3.2 ASIC

51 ASIC ASIC ASIC DIN A RAM 2567 DOUT DIN A 326 RAM CLK WENA0 WENA1 DOUT DATA

52 XilinxFPGA 4062xla MHz CLK 60ns DATA 256x7 RAM RAM 60ns 256x7RAM RAM 60ns 60ns DATA 60ns VHDLVerilog ASIC Verilog EDA RTL 1. RTL RTL 90 RTL RTL RTL

53 100 RTL RTL RTL RTL I/O Xilinx FPGA ucf 3. ASIC RTL RTL RTL

54 ASIC 3.3 ASIC ASIC IP VHDL Verilog ASIC 80% 15% 5% ASIC ASIC 128 SD K

55 2 8K UHW DHW 2 Verilog FPGA

56 1 2 FPGA FPGA FPGA ASIC ASIC 128 SD530 ASIC ASIC SD530 ASIC ASIC

57 DFT SD530 SD530 SD530 CPU UHW SD530 CPU UHW SD530 SD530 SD530 UHW UHW SD530 SD

58 SD530 1 UHW HDLC RAM Verilog

59 1 ( - 2 D Q D Q REG1 REG2 CLK CLKCREG1 REG2(D) CLK(REG2) REG2(Q) T1 T_cycle T1 n T Ts Th T n+1 n n REG2 T_setup T_hold T1 T2 T

60 T_cycle Ts T_cycle T T1 Th T1 T T T3 T2 1. T_setup < Ts T_setup < T_cycle T T1 T_setup REG2D 2. T_hold < Th T_hold < T1 T BUFF 12 T > 0 T_hold < 0 T_setup CLK PAD T 0 BUFF T D Q D Q REG1 REG2 CLK / XilinxFPGA 4062xla MHz CLK 60ns DATA 256x7 RAM 60ns 256x7RAM 60ns 60ns DATA 60ns

61 DIN A RAM 2567 DOUT DIN A 326 RAM CLK WENA0 WENA1 DOUT DATA FPGA T

62 1.. D Q / clk D Q D Q D Q Q2 Q1 Q0 1.5 T / VHDL 4 Counter4: Process(nreset,clk) Begin If nreset = 0 then Cnt <= ( others => 0 );

63 Elsif clk = 1 and clk event then Cnt <= cnt + 1; End if; End process counter4; Q[50] clk D Q 6 CLRN = bit bit > Q[50] "000000" clk D Q 6 = MHz 8kMHz( 2430)

64 +1 0 clk D Q 11 =1214 D ENA Q clkout MCLK DIV5_CLK MCLK MCLK COUNTO DIVO COUNT DIV1 DIV5_CLK COUNT0 COUNT1 DIV0DIV1 DIV5_CLKDIV0DIV1 HDL 1 DIV0DIV1DIV5_CLK 1:1 2 MCLK 3 COUNT1 COUNT

65 D D D D Q Q Q Q REG2 REG3 REG4 REG1 CLK1 CLK CLK1CLK2 REG2REG3 REG1 1 0 REG1 CLK CLK1 D Q D D Q Q REG2 REG3 REG4 D Q REG1 CLK2 D Q REG

66 CLK1 D Q D D Q Q REG2 REG3 REG4 D Q REG1 CLK2 D Q REG5 D Q D D Q Q REG8 REG9 REG10 D Q REG6 D Q REG RS R S Q Q 1.13 RS R=S= D

67 VHDL Process(nreset,clk) Begin If nreset = 0 then Rs <= 0 ; Elsif clk = 1 and clk event then Case r&s is End case; End if; End precess; When 00 => Rs <= rs; When 01 => Rs <= 1 ; When 10 => Rs <= 0 ; When 11 => -- R=S=1 When others => Rs <= 0 ; 8. '1' In D Q CLRN out clrn 1.15 IN

68 Q D Q D clk In out >1 9. Q D CLRN In '1' 1.17 Q D Q D clk In out >0 10. /

69 Q D Q D clk In out 1.19 / out clk out clk 1.20 Gray (PLD)One-hot (FPGA). 12. Q D input clk

70 Q D input clk ENA Q D D LE LE Q 1.23 D 373 IC Q D ENA D LE CLK Q FPGA 1.25 clk clk2 SEL 1SEL

71

72 4 / 5 RS 6 4 SETRESET /Reset AHDL SUBDESIGN example ( ) VARIABLE clock : INPUT ; /reset : INPUT ; -- State Machine declaration poll -- Varible & Counter declaration var1 var2 counter[5..0] : MACHINE WITH STATES (Idle,s1,s2); : DFF; : DFFE; : DFF;

73 BEGIN -- global reset & clock, initial set to 1 var1.clk = GLOBAL(clock); var1.prn = GLOBAL(/reset); -- global reset & clock, initial set to 0 var2.clk = GLOBAL(clock); var2.clrn = GLOBAL(/reset); -- global reset & clock for counter, initial value set to 0 counter[].clk = GLOBAL (clock); counter[].clrn = GLOBAL (/reset); IF counter[] == 53 THEN counter[] = 0; ELSE counter[] = counter[] + 1; END IF; -- state machine global clock & reset, initial state set to idle poll.clk = GLOBAL (Clk25m); poll.reset = not GLOBAL (/Reset); CASE poll IS WHEN idle => poll = s1; WHEN s1 => poll = s2; WHEN s2 => poll = s1; END CASE; WHEN OTHERS => poll = idle;

74 END 5 Buffer

75 1.27 CLOCKSEL CLOCKSEL FPGA CLOCK SEL SEL CLOCK

76 1.28 BAD CLKA CLKB GOOD SELECT CLKA,CLKB SELECT REGA REGA_CLK REGB REGB_CLK OUT_CLK

77 GOOD REGA CLKA REGA_CLK REGBREGB_CLKB OUT_CLK GOOD REGAREGB 1. SELECT CLK CLOCK CLOCK

78 RC RC FPGA 1 2 UCF NET *** MAXSKEW=3 T < T1 T_hold Xilinx MAXSKEW PAD IBUF 3 I/O MHz

79 5 20ns, 50MHz 8 ALTERA Ensure Clock, Preset, and Clear configurations are free of glitches. Never use Clocks consisting of more than one level of combinatorial logic. Carefully calculate setup times and hold times for multi-clock systems. Synchronize signals between flipflops in multi-clock systems when the setup and hold time requirements cannot be met. Ensure that Preset and Clear signals do not contain race conditions. Ensure that no other internal race conditions exist. Register all glitch-sensitive outputs. Synchronize all asynchronous inputs. Never rely on delay chains for pin-to-pin or internal delays. Do not rely on Power-On Reset. Use a master Reset pin to clear all flipflops. Remove any stuck states from state machines or synchronous logic

80 VHDL VHDL FSM DFT VHDL Very High speed IC Hardware Description Language Finite Status Machine Design For Test VHDL 1 VHDL VHDL VHDL VHDL 2 VHDL packagegeneric process

81 6. VHDL Design Partition glue A B C BAD A B C GOOD 1 glue TOP MID CORE TOP MID MID 1 2 CORE CORE

82 VHDL variable SUM:interger = ASIC Delay Buffer FPGA Delay Buffer FPGA wait for 10 ns Data_in <= 55 after MCLK_PERIOD MCLK_PERIOD 3.2 std_logic VHDL STD_LOGIC port map BIT BIT Synopsys VHDL STD_LOGIC 3.3 inout D A_s A A entity inout

83 ... A : inout STD_LOGIC ;... inout A 3 A_ss same 1. architecture A_s signal A_s : std_logic ; 2. entity A_s A_s 3. A A <= A_s 3.4 Latch process A B C Cntr if Cntr = '1' then else end process ; A <= '1' B <= '1' C <= '1' A B C LATCH process A B C Cntr if Cntr = '1' then else A <= '1' B <= '1' C <= '0' -- LATCH

84 end process ; A <= '0' B <= '0' C <= '1' case case process A B C D S A <= '0' ; B <= '0' ; C <= '0' ; D <= '0' ; case S is end case ; end process ; when "00" => A <= '1' ; when "01" => B <= '1' ; when "10" => C <= '1' ; when "11" => D <= '1' ; when others => null ; 3.5 process process 3.6 VHDL VHDL

85 -- XOR_SIG.VHD -- May 1997 Library IEEE; use IEEE.std_logic_1164.all; entity xor_sig is port (A, B, C: in STD_LOGIC; X, Y: out STD_LOGIC); end xor_sig; architecture SIG_ARCH of xor_sig is signal D: STD_LOGIC; SIG:process (A,B,C) D <= A; -- ignored!! X <= C xor D; D <= B; -- overrides!! Y <= C xor D; end process; end SIG_ARCH; XOR_VAR.VHD -- May 1997 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity xor_var is port (A, B, C: in STD_LOGIC; X, Y: out STD_LOGIC); end xor_var; architecture VAR_ARCH of xor_var is VAR:process (A,B,C)

86 variable D: STD_LOGIC; D := A; X <= C xor D; D := B; Y <= C xor D; end process; end VAR_ARCH; 5 3 P1:process CLK) if (CLK = 1 and CLK event ) then X <= A and B; Y <= X; Z <= Y; end process; P2:process CLK) if (CLK = 1 and CLK event ) then Z <= Y; Y <= X; X <= A and B; end process; p1, p

87 A B Z CLK 6 4 P1:process (CLK) variable X, Y : std_logic; if (CLK event and CLK = 1 ) then X := A and B; Y := X; Z <= Y; end process; P2:process (CLK) variable X, Y : std_logic; if (CLK event and CLK = 1 ) then Z <= Y; Y := X; X := A and B; end process; P1 P2 A B Z A B Z CLK CLK

88 CRC bit 3.7 RAM RAM 64X16 RAM 1 2 RAM RAM 3.8 VERILOG 1 2 ASIC ASIC DFT Design For Test ASIC ASIC 2 A B T Tri_p1: process (Sel_a,A) if (Sel_a = 1 ) then else end process; T <= A; T <= Z ; Tri_p2: process (Sel_b,B) if (Sel_b = 1 ) then T <= B; else T <= Z ;

89 end process; process Error : process (Sel_a,A,Sel_b,B) if (Sel_a = 1 ) then else T <= A; T <= Z ; if (Sel_b = 1 ) then else end process; T <= B; T <= Z ; if T if process CPU process Mclk CPU_reset Hard_reset if ( CPU_reset = '1' or Hard_reset = '1') then D <= '0' ; elsif Mclk = '1' and Mclk'event then end process ;... entity process

90 Rst <= CPU_reset = '1' or Hard_reset = '1' ; process Mclk CPU_reset Hard_reset if ( Rst ='1' ) then D <= '0' ; elsif Mclk = '1' and Mclk'event then end process ;... Rst FPGA Rst startup Set/Reset 3.10 buffer clk 2 process Mclk Reset if Reset = '1' then Mclk_d2 <= '0' ; elsif Mclk = '1' and Mclk'event then end process ; Mclk_d2 <= not Mclk_d2 ; process Mclk_d2 Reset if Reset = '1' then D_out <= '0' ; elsif Mclk_d2 = '1' and Mclk_d2'event then end process ; D_out <= D_in ;

91 process Mclk Reset if Reset = '1' then D_out <= '0' ; elsif Mclk = '1' and Mclk'event then end process ; if Mclk_d2 = '0' then end if ; D_out <= D_in ; PAD buffer 2 buffer 3 buffer buffer xilinx MAXDELAYMAXSKEW

92 VHDL VHDL -- A is the addend -- B is the augend -- C is the carry -- Cin is the carry in C0 <= (A0 and B0) or ((A0 or B0) and Cin); C1 <= (A1 and B1) or ((A1 or B1) and C0); -- Ps are propagate -- Gs are generate p0 <= a0 or b0; g0 <= a0 and b0; p1 <= a1 or b1;

93 g1 <= a1 and b1; c0 <= g0 or (p0 and cin); c1 <= g1 or (p1 and g0) or (p1 and p0 and cin); Z <= A + B + C + D; 10 Z <= (A + B) + (C + D);

94 D A B C D A B C D C ATEMPATEMP 8TEMP B B<16 C4TEMP 4 0 TEMP BYTE TEMPNIBBLE function ADD_IT_16 (A, B: BYTE; C: NIBBLE) return BYTE is variable TEMP: BYTE; end; if B < 16 then else TEMP := B; TEMP := C; return A + TEMP; 2 function ADD_IT_16 (A, B: BYTE; C: NIBBLE) return BYTE is end; variable TEMP: NIBBLE; -- Now only 4 bits if B < 16 then else TEMP := NIBBLE(B); -- Cast BYTE to NIBBLE TEMP := C; return A + TEMP; -- Single adder BYTE 8bits BIBBLE 4bits 4.2 AB 5bit 16 if A >= B then else end if ;

95 5bits if ( A(4) = '1' ) or ( B(4) = '0' and (A(3 downto 0) >= B(3 downto 0) ) ) then else end if ; 4bit 4.3 IF Case IF Case IF Case Case Case IF-Else IF-Else IF IF IF speed-critical paths Critical Signal Case IF IF

96 IF-Case IF IF-Case IF 3ns XC4005E

97 IF-Then-Else Critical Signal in[0] IF-Then-Else 81 MUX6to1:process(sel,in) if(sel= "000") then out <= in(0); elseif(sel = "001") then out <= in(1); elseif(sel = "010") then out <= in(2); elseif(sel = "011") then out <= in(3); elseif(sel = "100") then else out <= in(4); end process; out <= in(5); 12 if-else Case 81 VHDL FPGA CLB 41 Virtex CLB 81 IF-Else CLB Case Case 81 MUX8to1 process( C, D, E, F, G, H, I, J, S ) case S is when 000 => Z <= C; when 001 => Z <= D; when 010 => Z <= E; when 011 => Z <= F; when 100 => Z <= G; when 101 => Z <= H; when 110 => Z <= I;

98 end case; end process; when others => Z <= J; 13 case 4.4 FPGA critical path critical 2 if (clk'event and clk ='1') then if (non_critical='1' and critical='1') then else out1 <= in1; out1 <= in2; 14 critical 2 critical critical signal out_temp : std_logic; process (non_critical, in1, in2) else if (non_critical='1') then end process; out_temp <= in1; out_temp <= in2;

99 process(clk) if (clk'event and clk ='1') then if (critical='1') then out1 <= out_temp; else out1 <= in2; end process; 15 critical if HDL HDL VHDL 4 if (...(siz = "0001")...) then count <= count + "0001"; else if (...((siz = "0010")...) then count <= count + "0010"; else if (...(siz = "0011")...) then count <= count + "0011"; else if (...(siz == "0000")...)then count <= count + "0100"; 2 if (...(siz = "0000")...) then count <= count + "0100"; else if (...) then count <= count + siz; 2 if (select = '1') then else sum<=a +B; sum<=c +D;

100 if (sel ='1') then else temp1 <=A; temp2 <=B; temp1 <=C; temp2 <=D; sum <= temp1 + temp2; loop 17 1 VHDL 4 req for i in 0 to 3 loop if (req(i)='1') then end loop; sum <= vsum + offset(i);

101 req 18 4 for i in 0 to 3 loop if (req(i)='1') then end loop; offset_1 <= offset(i); sum <= vsum + offset_1; VHDL a+b temp <= a + b; x <= temp; y <= temp + c; CLB FPGA CompilerII/FPGA Express

102 1. * + - > < >= <= 2. position sum1 <= A + B + C; sum2 <= D + A +B; sum3 <= E + (A +B); sum1sum3 (A +B), sum2 3. block process if (cond1 =..) then else end if ; S1 <= A +B ; if (cond2...) then else end if ; S2 <= E + F ; S3 <= G+ H ; S2 S3 S1 4.6 Pipelining FPGA FPGA clock-to-out process(clk, a, b, c) if(clk'event and clk = '1') then a_temp <= a; b_temp <= b; c_temp <= c;

103 end process; Process(clk, a_temp, b_temp, c_temp) if(clk'event and clk = '1') then out <= (a_temp * b_temp) + c_temp; end process; 5 process(clk, a, b, c) if(clk'event and clk = '1') then a_temp <= a; b_temp <= b; c_temp1 <= c; end process; process(clk, a_temp, b_temp, c_temp1) if(clk'event and clk = '1') then mult_temp <= a_temp * b_temp c_temp2 <= c_temp1; end process; process(clk, mult_temp, c_temp2)

104 if(clk'event and clk = '1') then out <= mult_temp + c_temp2; end process; Mealy Mealy 7 Mealy Mealy Mealy VHDL 5 Mealy -- Example of a 5-state Mealy FSM library ieee; use ieee.std_logic_1164.all;

105 entity mealy is port (clock, reset: in std_logic; data_out: out std_logic; data_in: in std_logic_vector (1 downto 0)); end mealy; architecture behave of mealy is type state_values is (st0, st1, st2, st3, st4); signal pres_state, next_state: state_values; -- FSM register statereg: process (clock, reset) if (reset = '0') then pres_state <= st0; elsif (clock'event and clock ='1') then pres_state <= next_state; end process statereg; -- FSM combinational block fsm: process (pres_state, data_in) case pres_state is when st0 => case data_in is when "00" => next_state <= st0; when "01" => next_state <= st4; when "10" => next_state <= st1; when "11" => next_state <= st2; when others => next_state <= (others <= 'x'); end case; when st1 => case data_in is when "00" => next_state <= st0; when "10" => next_state <= st2; when others => next_state <= st1; end case; when st2 => case data_in is when "00" => next_state <= st1; when "01" => next_state <= st1; when "10" => next_state <= st3; when "11" => next_state <= st3; when others => next_state <= (others <= 'x'); end case; when st3 => case data_in is

106 when "01" => next_state <= st4; when "11" => next_state <= st4; when others => next_state <= st3; end case; when st4 => case data_in is when "11" => next_state <= st4; when others => next_state <= st0; end case; when others => next_state <= st0; end case; end process fsm; -- Mealy output definition using pres_state w/ data_in outputs: process (pres_state, data_in) case pres_state is when st0 => case data_in is when "00" => data_out <= '0'; when others => data_out <= '1'; end case; when st1 => data_out <= '0'; when st2 => case data_in is when "00" => data_out <= '0'; when "01" => data_out <= '0'; when others => data_out <= '1'; end case; when st3 => data_out <= '1'; when st4 => case data_in is when "10" => data_out <= '1'; when "11" => data_out <= '1'; when others => data_out <= '0'; end case; when others => data_out <= '0'; end case; end process outputs; end behave; 4.8 a b

107 process (clk, a, b) if (clk'event and clk = '1') then a1 <= a; b1 <=b; end process; 8 process (a1, b1) end process; c <=a1 +b1; a b c process (clk, a, b) if (clk'event and clk = '1') then c <=a +b; end process; fanout FPGA VHDLTri_en architecture load of four_load is

108 signal Tri_en std_logic; loadpro: process (Clk) if (clk'event and clk ='1') then Tri_end <= Tri_en; end process loadpro; endpro : process (Tri_end, Data_in) if (Tri_end = '1') then out <= Data_in; else out <= (others => 'Z'); end process endpro; end load; architecture loada of two_load is signal Tri_en1, Tri_en2 : std_logic; loadpro: process (Clk) if (clk'event and clk ='1') then Tri_en1 <= Tri_en; Tri_en2 <= Tri_en;

109 end process loadpro; process (Tri_en1, Data_in) if (Tri_en1 = '1') then out(23:12) <= Data_in(23:12); else out(23:12) <= (others => 'Z'); end process; process (Tri_en2, Data_in) if (Tri_en2 = '1') then out(11:0) <= Data_in(11:0); else out(11:0) <= (others => 'Z'); end process; end loada; 24 buffer 5 Xilinx 5.1 Xilinx XilinxFPGA CLB CLB FPGA CLB CLB /

110 IOB IOB IOBCLB 4000 CLB LUT CLB LUT RAM LUT 4 RAM 16X1 RAM VirtexVirtex-ECLB CLB CLB CLB slice 4000 Virtex IOB IOB CLB RAM CLBIOB Xilinx PAL FPGA CLB FPGA FPGA one-hot one-hot CPLDXC9500 one-hot n n 1 hot FPGA FPGA one-hot HDL one-hot FPGA one-hot 8 FPGACLB 4 LUT one-hot

111 Fault Tolerance 27 case present_state is

112 when others =>next_state <= ; end case; one-hot one-hotn 2n n one-hot when others => next_state <= ; VHDL 7 VHDL BINARY.VHD Version Example of a binary encoded state machine May Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all;

113 entity binary is port (CLOCK, RESET : in STD_LOGIC; A, B, C, D, E: in BOOLEAN; SINGLE, MULTI, CONTIG: out STD_LOGIC); end binary; architecture BEHV of binary is type STATE_TYPE is (S1, S2, S3, S4, S5, S6, S7); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE:type is " "; signal CS, NS: STATE_TYPE; SYNC_PROC: process (CLOCK, RESET) if (RESET='1')then CS <= S1; elsif (CLOCK'event and CLOCK = '1')then CS <= NS; end process; --End REG_PROC COMB_PROC: process (CS, A, B, C, D, E) case CS is when S1 => MULTI <= '0'; CONTIG <= '0'; SINGLE <= '0'; if (A and not B and C) then NS <= S2; elsif (A and B and not C) then NS <= S4; else NS <= S1; when S2 => MULTI <= '1'; CONTIG <= '0'; SINGLE <= '0'; if (not D) then NS <= S3; else

114 NS <= S4; when S3 => MULTI <= '0'; CONTIG <= '1'; SINGLE <= '0'; if (A or D) then NS <= S4; else NS <= S3; when S4 => MULTI <= '1'; CONTIG <= '1'; SINGLE <= '0'; if (A and B and not C) then NS <= S5; else NS <= S4; when S5 => MULTI <= '1'; CONTIG <= '0'; SINGLE <= '0'; NS <= S6; when S6 => MULTI <= '0'; CONTIG <= '1'; SINGLE <= '1'; if (not E) then NS <= S7; else NS <= S6; when S7 => MULTI <= '0'; CONTIG <= '1'; SINGLE <= '0'; if (E) then NS <= S1; else NS <= S7; end case; end process; -- End COMB_PROC end BEHV;

115 Library IEEE; use IEEE.std_logic_1164.all; entity enum is port (CLOCK, RESET : in STD_LOGIC; A, B, C, D, E: in BOOLEAN; SINGLE, MULTI, CONTIG: out STD_LOGIC); end enum; architecture BEHV of enum is type STATE_TYPE is (S1, S2, S3, S4, S5, S6, S7); signal CS, NS: STATE_TYPE; SYNC_PROC: process (CLOCK, RESET) if (RESET= '1') then CS <= S1; elsif (CLOCK'vent and CLOCK = '1') then CS <= NS; end process; --End SYNC_PROC COMB_PROC: process (CS, A, B, C, D, E) case CS is when S1 => MULTI <= '0'; CONTIG <= '0'; SINGLE <= '0';... one-hot Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity one_hot is port (CLOCK, RESET : in STD_LOGIC; A, B, C, D, E: in BOOLEAN; SINGLE, MULTI, CONTIG: out STD_LOGIC); end one_hot; architecture BEHV of one_hot is type STATE_TYPE is (S1, S2, S3, S4, S5, S6, S7); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is " ";

116 signal CS, NS: STATE_TYPE; SYNC_PROC: process (CLOCK, RESET) if (RESET='1') then CS <= S1; elsif (CLOCK'event and CLOCK ='1') then CS <= NS; end process; --End SYNC_PROC COMB_PROC: process (CS, A, B, C, D, E) case CS is when S1 => MULTI <= '0'; CONTIG <= '0'; SINGLE <= '0'; if (A and not B and C) then NS <= S2; elsif (A and B and not C) then NS <= S4; else NS <= S1; Barrel Shifter 16Barrel shifter VHDL Barrel shifter FPGA XC CLB 80CLB Barrel shifter VHDL Model for a 16-bit Barrel Shifter barrel_org.vhd -- --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! THIS EXAMPLE IS FOR COMPARISON ONLY May USE barrel.vhd

117 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity barrel_org is port (S:in STD_LOGIC_VECTOR (3 downto 0); A_P:in STD_LOGIC_VECTOR (15 downto 0); B_P:out STD_LOGIC_VECTOR (15 downto 0)); end barrel_org; architecture RTL of barrel_org is SHIFT: process (S, A_P) case S is when "0000" => B_P <= A_P; when "0001" => B_P(14 downto 0) <= A_P(15 downto 1); B_P(15) <= A_P(0); when "0010" => B_P(13 downto 0) <= A_P(15 downto 2); B_P(15 downto 14) <= A_P(1 downto 0); when "0011" => B_P(12 downto 0) <= A_P(15 downto 3); B_P(15 downto 13) <= A_P(2 downto 0); when "0100" => B_P(11 downto 0) <= A_P(15 downto 4); B_P(15 downto 12) <= A_P(3 downto 0); when "0101" => B_P(10 downto 0) <= A_P(15 downto 5); B_P(15 downto 11) <= A_P(4 downto 0); when "0110" => B_P(9 downto 0) <= A_P(15 downto 6); B_P(15 downto 10) <= A_P(5 downto 0); when "0111" => B_P(8 downto 0) <= A_P(15 downto 7); B_P(15 downto 9) <= A_P(6 downto 0); when "1000" => B_P(7 downto 0) <= A_P(15 downto 8); B_P(15 downto 8) <= A_P(7 downto 0); when "1001" => B_P(6 downto 0) <= A_P(15 downto 9); B_P(15 downto 7) <= A_P(8 downto 0); when "1010" => B_P(5 downto 0) <= A_P(15 downto 10); B_P(15 downto 6) <= A_P(9 downto 0); when "1011" =>

118 B_P(4 downto 0) <= A_P(15 downto 11); B_P(15 downto 5) <= A_P(10 downto 0); when "1100" => B_P(3 downto 0) <= A_P(15 downto 12); B_P(15 downto 4) <= A_P(11 downto 0); when "1101" => B_P(2 downto 0) <= A_P(15 downto 13); B_P(15 downto 3) <= A_P(12 downto 0); when "1110" => B_P(1 downto 0) <= A_P(15 downto 14); B_P(15 downto 2) <= A_P(13 downto 0); when "1111" => B_P(0) <= A_P(15); B_P(15 downto 1) <= A_P(14 downto 0); when others => end case; B_P <= A_P; end process; -- End SHIFT end RTL; VHDL 16Barrel Shifter CLB 41 32CLB Barrel shifter -- BARREL.VHD -- Based on XAPP 26 (see bit barrel shifter (shift right) -- May 1997 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity barrel is port (S: in STD_LOGIC_VECTOR(3 downto 0); A_P: in STD_LOGIC_VECTOR(15 downto 0); B_P: out STD_LOGIC_VECTOR(15 downto 0)); end barrel; architecture RTL of barrel is signal SEL1,SEL2: STD_LOGIC_VECTOR(1 downto 0); signal C: STD_LOGIC_VECTOR(15 downto 0); FIRST_LVL: process (A_P, SEL1) case SEL1 is

119 when "00"=> -- Shift by 0 C <= A_P; when "01"=> -- Shift by 1 C(15) <= A_P(0); C(14 downto 0) <= A_P(15 downto 1); when "10"=> -- Shift by 2 C(15 downto 14) <= A_P(1 downto 0); C(13 downto 0) <= A_P(15 downto 2); when "11"=> -- Shift by 3 C(15 downto 13) <= A_P(2 downto 0); C(12 downto 0) <= A_P(15 downto 3); when others => C <= A_P; end case; end process; --End FIRST_LVL SECND_LVL: process (C, SEL2) case SEL2 is end case; when "00"=> --Shift by 0 B_P <= C; when "01"=> --Shift by 4 B_P(15 downto 12) <= C(3 downto 0); B_P(11 downto 0) <= C(15 downto 4); when "10"=> --Shift by 8 B_P(7 downto 0) <= C(15 downto 8); B_P(15 downto 8) <= C(7 downto 0); when "11"=> --Shift by 12 B_P(3 downto 0) <= C(15 downto 12); B_P(15 downto 4) <= C(11 downto 0); when others => B_P <= C; end process; -- End SECOND_LVL SEL1 <= S(1 downto 0); SEL2 <= S(3 downto 2); end rtl; XC4005E-2 64% 88CLB 32CLB 19%35.58ns ns CLBIOB FPGACLB FPGA CLB spartan CLB 3 LUT X1 F-LUTG-LUT

120 H-LUT 3 29 CLBspartan 4 FG 3 H spartan CLB 4 CLB (a) 4 (b) 6 (c) 5 F-G-H (d) 9 CLB CLB XilinxVirtex CLB 81 CLB ns CLB

121 30 1 (b) CLB

122 VHDL (a) 2CLB a 2CLB temp <= a and b one : process (clk, temp, d, en) if (clk'event and clk ='1') then if (en = '1') then end process one; q2 <= temp or d; part_two: process (clk, temp, c) if (clk'event and clk ='1') then q1 <= temp or c; end process part_two; 2 (b) CLB part_one: process (clk, a, b, c, d, en) if (clk'event and clk ='1') then if (en = '1') then q2 <= a and b or d; end process part_one; part_two: process (clk, a, b, c) if (clk'event and clk ='1') then end process part_two; q1 <= a and b or c;

123 33 a&b instantiation IOB CLB IOB Virtex IOB 34 IOB Virtex IOB D NODELAY UCF IOB buffer IOB IOB Xilinx IOB FPGA IOB IOB IOB IOB CLB IOB IOB clock-to-output

124 35 IOB I/O Slew rate I/O IOB IOB Xilinx FPGAIOB buffer IBUF FPGA buffer OBUFT FPGA I/O I/O I/O I/O 1 I/O 2 IOB 3 LogiBLOX 1 2 VHDL LATCH 1 IO Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity bidir_infer is port (DATA : inout STD_LOGIC_VECTOR(1 downto 0); READ_WRITE : in STD_LOGIC); end bidir_infer;

125 architecture XILINX of bidir_infer is signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0); process(read_write, DATA) if (READ_WRITE = '1') then LATCH_OUT <= DATA; end process; process(read_write, LATCH_OUT) if (READ_WRITE = '0') then DATA(0) <= LATCH_OUT(0) and LATCH_OUT(1); DATA(1) <= LATCH_OUT(0) or LATCH_OUT(1); else DATA(0) <= 'Z'; DATA(1) <= 'Z'; end process; end XILINX; Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity bidir_instantiate is port (DATA : inout STD_LOGIC_VECTOR(1 downto 0); READ_WRITE : in STD_LOGIC); end bidir_instantiate; architecture XILINX of bidir_instantiate is signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0); signal DATA_OUT : STD_LOGIC_VECTOR(1 downto 0); signal GATE : STD_LOGIC; component ILD_1 port (D, G : in STD_LOGIC; Q : out STD_LOGIC); end component; component OBUFT_S port (I, T : in STD_LOGIC; end component; O : out STD_LOGIC);

126 DATA_OUT(0) <= LATCH_OUT(0) and LATCH_OUT(1); DATA_OUT(1) <= LATCH_OUT(0) or LATCH_OUT(1); GATE <= not READ_WRITE; INPUT_PATH_0 : ILD_1 port map (D => DATA(0), G => GATE, Q => LATCH_OUT(0)); INPUT_PATH_1 : ILD_1 port map (D => DATA(1), G => GATE, Q => LATCH_OUT(1)); OUPUT_PATH_0 : OBUFT_S port map (I => DATA_OUT(0), T => READ_WRITE, O => DATA(0)); OUPUT_PATH_1 : OBUFT_S end XILINX; port map (I => DATA_OUT(1), T => READ_WRITE, O => DATA(1)); IOB 1. IOB 2. IOB CLB IOB Buffer xlinx IOB Buffer BUFGP Buffer buffer buffer BUFGP buffer XC4000E/LSpartan 4 primary 4 secondary 8 buffer

127 36 BUFGPBUFGS FPGA buffer BUFGS BUFGS BUFGP BUFGS FPGA buffer BUFGPsemi-dedicated BUFGP BUFGS buffer buffer CLBIOB K 4 buffer Xilinx BUFGS buffer Xilinx buffer instantiate VHDL buffer LOC VHDL insert pads BUFG VHDL pad BUFG attribute LOC: string; attribute LOC of CLOCKBUF: label is "BR";... CLOCKBUF:BUFG port map(i=>oscout,o=>clkint);

128 BUFGPBUFGS bufferz Set/Reset X4000Spartan /GSR CLB IOB flip-flops, RAM, and ROM GSR STARTUPGSRSTARTBUFGSRIN GSR GSR

129 37 CLB GSR /SR SR 4062xla spartan CLB / SR / GSR GSR SRGSR 38 SRGSR X4000SpartanGSR CLB /SR INIT=S VHDL STARTUP GSR U1: STARTUP port map (GSR => RESET);

130 Set/Reset Buffer CLB 41 XC4000 Spartan CLB F GH 41 CLB CLB Xilinx buffer BUFT BUFT 1 2 buffer 3 BUFTCLB CLB 4 one-hot VHDL SEL_PROCESS: process (SEL,A,B,C,D,E) case SEL is end case; when "000" => SIG <= A; when "001" => SIG <= B; when "010" => SIG <= C; when "011" => SIG <= D; when others => SIG <= E; end process SEL_PROCESS;

131 39 BUFT SIG <= A when (SEL(0)= '0') else 'Z'; SIG <= B when (SEL(1)= '0') else 'Z'; SIG <= C when (SEL(2)= '0') else 'Z'; SIG <= D when (SEL(3)= '0') else 'Z'; SIG <= E when (SEL(4)= '0') else 'Z'; 40 xilinx CLB XC4000ESpartan FPGA RAMROM CLB ROM ROM16X1 ROM32X1 RAM RAM16X1 RAM32X1 RAM RAM16X1S RAM32X1S RAM RAM16X1D Spartan RAM RAM LIFO RAM FIFO ROM 1 16X132X1ROM ROM Set ROM INIT 2 LogiBLOX ROM

132 RTL RAM RAM 1 16X132X1RAM 2 LogiBLOX RAM 3 RAM 1 VHDL RAM0 : RAM16X1S port map (O => DATA_OUT(0), D => DATA_IN(0), A3 => ADDR(3), A2 => ADDR(2), A1 => ADDR(1), A0 => ADDR(0), WE => WE, WCLK => CLOCK); RAM RAM16X1S RAM32X1S RAM16X1D RAM VirtexRAM LUT Block RAM RAM RAM LUT RAM I/O XC IOB CLB 44 IO HDL XC4000 DECODE1_IO DECODE1_INT DECODE4 DECODE8 DECCODE16 PULLUP VHDL Instantiation of Edge Decoder: Output "DECODE(0)" A0: DECODE4 port map (ADR(3), ADR(2), ADR(1), ADR_INV(0), DECODE(0)); A1: DECODE1_IO port map (ADR(4), DECODE(0)); A2: DECODE1_INT port map (CLB_INV(0), DECODE(0)); A3: DECODE1_INT port map (CLB_INT(1), DECODE(0)); A4: DECODE1_INT port map (CLB_INT(2), DECODE(0)); A5: DECODE1_INT port map (CLB_INT(3), DECODE(0));