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1 Verilog HDL Verilog HDL 邏令列邏路例練

2 數度 (top-down design) 行 (concurrency)

3 2.1 Verilog HDL (module) 邏 HDL 理

4 HDL 邏料數邏邏路 module module_name (port_list) // 列 <port_declarations> // <wire_register declaration> // <parameter_declarations> // 參數 <statements> // 邏 endmodule

5 料例 module and (a, b, c) input a, b // output c assign c = a & b; // 邏 endmodule

6 2.1.1 ) ) 例 wire w1, w2 // wire [31 0] w3, w4 // 32 reg a // 1 reg [7 0] b,c // 8 (input) (output) (inout) [msb lsb] 若 ( 例 always )

7 2.1.2 讀讀料讀例 reg [10 0] counter // 11 reg a // 1 reg [2 0] b // 3 a = counter[9] //counter 9 a b = counter[5 3] //counter 5 3 b reg [10 0] table[0 31] //table table[11] = 68 // 68 table 12

8 2.1.3 參數例 module vadder (a, b, c) // 路 16 parameter wlen = 15 input [wlen 0] a, b output [wlen + 1 0] c assign c = a + b endmodule module tben1 // 路 vadder #(31) ad1(a1, b1, c1) // vadder #(63) ad2(a2, b2, c2) // endmodule

9 例 module tben2 vadder ad1(a1, b1, c1) vadder ad2(a2, b2, c2) defparam ad1.wlen = 31, ad2.wlen = 63 //ad1 ad2 更 endmodule

10 2.2 Verilog HDL 邏 Begin End 林林 Default If Always Initial

11 2.2.1 (Module Instantiation) 兩 module_name instance_name(port1, port2, ); module_name instance_name(.mod_port1(inst_port1),.mod_port2(inst_port2), ); 例 module adder (a, b, c) // input a, b output c <expressions> endmodule module top (a1, a2, b1, c2) // adder input a1, a2, b1 output c2 wire c1 adder adder_1 (a1, b1, c1) // adder adder_2 (.a(a2),.c(c2),.b(c1)) // endmodule

12 例 moduledriver (out, in, en) output [2 0] out input [2 0] in input en buf u2 (out[2], in[2], en) buf u1 (out[1], in[1], en) buf u0 (out[0], in[0], en) endmodule moduledriver (out, in, en) output [2 0] out input [2 0] in input en buf u[2 0] (out, in, en) // u[2] u[1] u[0] endmodule

13 2.2.2 Verilog 邏 and nand or nor xor xnor buf tran not 令 (Operators in assignments) 降列 1. (concatenation and replications) { } {{ }} 2. (unary)! ~ & ˆ 3. 數 (arithmetic) * / % 4. 數 (arithmetic) (bitwise shift) << >> 6. (relational) > >= < <= 7. (equality) = = = = = = = = 8. 邏 (binary logical) &&!! 9. 邏 (binary bitwise) & ˆ ˆ 10. (conditional)

14 例 wire [15 0] new_word = {word[7 0],word[15 8]}; //byte 例 module add_32 (co, sum, a, b, ci) //32 output co output [31 0] sum input [31 0] a, b input ci assign {co, sum} = a + b + ci endmodule 例 initial begin byte = { 4 { 2 b01}} // 兩 word = {{ 8 { byte[7]}}, byte} // end

15 <LHS> = <condition> <if_expression> <else_expression> 例 // assign out = enable in bz 例 // wire [3 0] mux_out, in1, in2, in3, in4 wire [1 0] sel assign mux_out = (sel = = 2 b00) in1 (sel = = 2 b01) in2 (sel = = 2 b10) in3 (sel = = 2 b11) in4 4 bx

16 2.2.4 令連令 (Continuous assignments) assign 連 (procedural block) 邏數不數

17 例 wire out assign out = a & b // 數 wire #10 inv = inv // 數 wire and_net = a1 & a2, or_net = a1 a2 // 兩 assign out[7 4] = in1[4 1] //

18 塞塞 (Blocking and Non-blocking Assignments 塞令 = 句數路利行路路不塞令 <= 句行塞令

19 例 // out 路不 clk) out = outˆa1 clk) a1 = outˆin // 利 begin end 行 ok reg temp clk) temp = dout dout = tempˆa1 a1 = tempˆin end // 塞令 <= clk) out <= outˆa1 clk) a1 <= outˆin begin

20 2.2.5 (Conditional Statements) If and If-else

21 Case

22 2.2.6 (Procedural Blocks) 行 initial always 兩 begin end 列行錄 (activation list) (timing control, TC) 行

23 例 #n n 行 wait 數立行 or posedge negedge

24 Initial initial 行 initial ( $display $gr_waves) Always always 路連行錄 (activation list) (reg)

25 例

26 2.3 令 (Compiler Directives)

27 2.4 列邏路狀 (Finite-State Machines)

28 2.4.2 狀狀 (FSM State Transition Diagram )

29 2.4.3 狀 Verilog HDL

30 2.5 例 Moore Machine

32 2.5.2 Mealy Machine

34 2.6 練 1. Verilog HDL 立 I. 2-3 II. III. 2-4 D 立 D 2-5

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untitled Verilog 1 錄料 7. 邏 8. 料流 9. 行 10. 令 11. 邏路例 2 1. Verilog 路 (Flexibility) 易更更易連林數 (Portability) 不不易 C 3 2. Verilog Verilog (model) (switch level) (transistor) 邏 (gate level) 料流 (data flow) (register