1 1

Save this PDF as:

Size: px
Start display at page:

Download "1 1"

Transcription

1 1 1

2 2 Idea Architecture Design IC Fabrication Wafer (hundreds of dies) Sawing & Packaging Block diagram Final chips Circuit & Layout Design Testing Layout Bad chips Good chips customers 3 2

3 4 IC Fabless Design Houses Integrated service EDA: Electronic Design Automation IP: silicon Intellectual Property SOC: System-On-A-Chip design IDM: Integrated Device Manufacturer EDA Tools Companies Design Service Companies Library & IP Providers Dedicated IC Manufacturers (Foundry) Packaging & Testing Houses 5 3

4 6 Behavioral Domain Structural Domain program subroutines Design Process: instructions ( -> -> ) architecture block diagram cell schematic layout placement floorplan Physical Domain 7 4

5 Routing Channel SRAM SRAM Data paths Standard cells Video-encoder chip [Brodersen92] 8 9 5

6 (Algorithm) Function Specification: A / B = Q + R Procedure of sequential divider (using shift-and-subtract) Example : A = 1011, B = 0010 iteration Partial Reminder Quotient iteration Partial Reminder Quotient ???? ? ??? ??01 Result A/B = (11/2) = B ( ) R (Partial Remainder) Q ( ) ??? S R = R << 1; computation of i-th iteration if R [7:4] > B Next_R = R Next_Q[i] = 0 Next_R = R - B Next_Q[i] = 1 E 11 6

7 (Flow-Chart) If (!start) Start If (start) count = 4; Y1 States = {Start, Y1, Y2} If (count!= 0) R = R << 1; count ++; if R [7:4] > B Next_R = R Next_Q[i] = 0 Next_R = R - B Next_Q[i] = 1 Y2 If (count == 0) 12 (Synthesis) Start Y1 R = R << 1; count ++; if R [7:4] > B Next_R = R Next_R = R - B Next_Q[i] = 0 Next_Q[i] = 1 Register-Transfer Level (RTL) code (Verilog or VHDL) Y2 synthesis Standard cell library (INV, BUF) (NAND, NOR) (AOI, AIO, MUX), (Full-Adder, Half-Adder) (Flip-Flop) 13 7

8 A cell can be decomposed into a number of transistors D S N-channel G P-channel G S D MOS transistor 14 NOR-gate schematic NOR-gate Layout VDD V OUT GND V A V B 15 8

9 16 Inputs: two natural numbers x1 and x2 Output: the greatest common divisor of x1 and x2 Example: (9, 6) (3, 6) (3, 3) Found GCD = 3 START u=x1; v=x2; Flow-Chart of GCD yes u = u-v; u > v no no u==v yes v = v-u; done = 1; GCD = u; END 17 9

10 START u=x1; v=x2; α no u > v yes u = u-v; no v = v-u; u==v β Flow-Chart yes done = 1; GCD = u; END EFSM model if(! start ); if( u>v ) u=u-v; if( start ) {u=x1; v=x2;} if(! (u>v) ); if( u==v ) S0 S1 done=1; GCD=u; if( u!= v ) S2 v = v u; S3 if(1); 18 case(state) `S0: if(start) begin next_u <= x1; next_v <= x2; next_state <= `S1; end `S1: if(u > v) next_u <= u v; else next_state <= `S2; `S2: if(u==v) done<=1; GCD<=u; next_state <= `S3; else next_v = v u; next_state <= `S1; `S3: begin end endcase if(! start ); if( u>v ) u=u-v; if( start ) S0 {u=x1; v=x2;} if(! (u>v) ); if( u==v ) S1 done=1; if( u!= v ) S2 GCD=u; v = v u; S3 if(1); 19 10

11 20 image sensor array decoder and controller CDS (correlated double sampling) Multiplexor Analog-to-Digital Converter clock enable 8-bit digital output 21 11

12 (Sensor Cell) Operation of a cell V DD V DD source follower (1) Reset (2) Integration reset X A sensor cell RS photo diode Con. CDS MUX RS: row select ADC column line 22 Voltage at node X integration time Reset X weak illumination stronger illumination E D A B C 1 ms Time 23 12

13 analog output after CDS (volt) Dynamic range ~ 20 log (4000) ~ 70 db saturation region Illumination (Lux) (1) (Step 1) Logarithmic Output Response (Step 2) Dynamic Range Dark Current and others Output (volt) Output (volt) Illumination (Lux) enhance response under low-light Illumination (Lux) 25 13

14 (2) Output (volt) (Step 1) Logarithmic Output Response (Step 2) Dynamic Range Dark Current and others Output (volt) higher dynamic range enhance response under high-light Illumination (Lux) Illumination (Lux) 26 Logarithm is approximated via a nonlinear ADC CDS output output code 255 x = code Illumination (Lux) analog input to ADC Illumination (Lux) 27 14

15 ADC? Input: Given an analog voltage, say 0.35 Output: What is the digital output code? 0.35 V Analog Voltage 0 V 0.25 V 0.5 V 0.75 V 1 V Digital Code 28 Narrow down the possible code ranges quickly 0 V 0.25 V 0.5 V 0.75 V 1 V Output bit D 3 =0 0 V 0.25 V 0.5 V 0.75 V 1 V 0 V 0.25 V 0.5 V 0.75 V 1 V 0 V 0.25 V 0.5 V 0.75 V 1 V D 2 =1 D 1 =0 D 0 =0 Final output code for 0.35 V is D 3 D 2 D 1 D 0 =

16 ADC 30 ADC Linear ADC Table lookup V in clk S/H comparator 10-bit code 1024 x 8 mapping table 8-bit code 10-bit DAC control logic 10-bit SAR 8-bit S/H: sample-and-hold clk 10-bit 31 16

17 Advantages: (1) conversion time is reduced from 11 to 9 cycles (2) table size is reduced to ~ 1/4 V in clk S/H comparator 8-bit 10-bit DAC 256 x 10 mapping table control logic 8-bit SAR 10-bit 8-bit code clk 32 ADC Integral Noise Level 0.42 LSB (Least Significant Bit Level) INL (LSB) Output code 33 17

18 34 Controller 176 x 144 Sensor Array Buf CDS ADC Periphery 35 18

19 Technology power supply resolution frame rate pixel size chip size power dissipation TSMC 0.35 µm 1P4M 3.3 V 176 x 144 (QCIF) 30 frame/s 7.5 x 7.5 µm x 3041 µm 2 30 mwatt 36 Signal Path: Pixel CDS MUX ADC 37 19

20 (1/5) 38 (2/5) 39 20

21 (3/5) 40 (4/5) Original Ours 41 21

22 (5/5) Original Ours

23 IC CS EE & CS CS EE & CS EE & CS CS EE & CS EE & CS EE EE & CS EE & CS EE, EE EE 44 23

9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如

9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如 FPGA 工 程 师 面 试 试 题 一 1 同 步 电 路 和 异 步 电 路 的 区 别 是 什 么?( 仕 兰 微 电 子 ) 2 什 么 是 同 步 逻 辑 和 异 步 逻 辑?( 汉 王 笔 试 ) 同 步 逻 辑 是 时 钟 之 间 有 固 定 的 因 果 关 系 异 步 逻 辑 是 各 时 钟 之 间 没 有 固 定 的 因 果 关 系 3 什 么 是 " 线 与 " 逻 辑, 要 实

More information

Microsoft PowerPoint - STU_EC_Ch08.ppt

Microsoft PowerPoint - STU_EC_Ch08.ppt 樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters

More information

enews174_2

enews174_2 103 CMOS Seal-Ring 104 e-learning 104 104 / http://www.cic.org.tw/login/login.jsp CIC Introduction to Conversational French - Syllabus Summer 2004 1 4 21 CMOS MorSensor MorFPGA DUO 2 MorSensor 3 103 (

More information

2/80 2

2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application

More information

a b c d e f g C2 C1 2

a b c d e f g C2 C1 2 a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4

More information

12 Differential Low-Power 6x6 12 bit multiply 1

12 Differential Low-Power 6x6 12 bit multiply 1 12 Differential Low-Power 6x6 12 bit multiply 1 2 07 1.1 07 1.2 07 1.2.1 (Sequential Structure Multiplier )07 1.2.2 (Array Structure Multiplier) 09 1.2.3 (Parallel Multiplier) 10 1.2.3.1 10 1.2.3.2 10

More information

untitled

untitled Portable Electrode B91901070 B91901133 量 ECG 路 更 量 路 performance RF 量 路 Portable Electrode 便利 量 portable electrode 路 濾 濾 行 electrode 類 FM modulation scheme ECG 類 數 RF RF demodulate 利 Elvis Labview ECG

More information

混訊設計流程_04.PDF

混訊設計流程_04.PDF CIC Referenced Flow for Mixed-signal IC Design Version 1.0 (Date) (Description) (Version) V. 1.0 2010/11/ Abstract CIC IC (Mixed-signal Design Flow) IC (Front End) (Back End) Function Timing Power DRC

More information

B 6 A A N A S A +V B B B +V 2

B 6 A A N A S A +V B B B +V 2 B 6 A A N A S A +V B B B +V 2 V A A B B 3 C Vcc FT7 B B 1 C 1 V cc C 2 B 2 G G B 3 C 3V cc C B ND ND GND V A A B B C 1 C 3 C 2 C V cc V cc V 220Ωx B 1 B 2 B 3 B GND GND A B A B 1 1 0 0 0 2 0 1 0 0 3 0

More information

AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING

AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING 前言 - Andrew Payne 目录 1 2 Firefly Basics 3 COMPONENT TOOLBOX 目录 4 RESOURCES 致谢

More information

iml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi

iml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi iml88-0v C / 8W T Tube EVM - pplication Notes iml88 0V C 8W T Tube EVM pplication Notes Table of Content. IC Description.... Features.... Package and Pin Diagrams.... pplication Circuit.... PCB Layout

More information

52C-14266-5

52C-14266-5 逻 辑 分 析 仪 基 础 知 识 入 门 手 册 www.tektronix.com.cn/logic_analyzers 15 入 门 手 册 目 录 引 言 3-4 起 源 3 数 字 示 波 器 3 逻 辑 分 析 仪 4 逻 辑 分 析 仪 操 作 5-13 连 接 被 测 系 统 5 探 头 5 设 置 逻 辑 分 析 仪 7 设 置 时 钟 模 式 7 设 置 触 发 7 采 集 状

More information

Microsoft PowerPoint - Sens-Tech WCNDT [兼容模式]

Microsoft PowerPoint - Sens-Tech WCNDT [兼容模式] X-ray data acquisition systems for NDT applications 技股份有限公司 先锋科技股份有限公司 科技股份有限公司 先锋科技股份有限公司 www Sens-Tech Ltd UK based company 40 Staff Specialise in detection and data acquisition systems for light and

More information

60C-6-20160802091614

60C-6-20160802091614 推 薦 序 防 災 是 全 球 未 來 的 必 須 面 對 的 首 要 工 作, 台 灣 值 在 這 方 面 進 步 非 常 快, 可 說 在 世 界 上 居 於 領 先 國 家 之 一, 其 中 有 一 項 技 術, 就 是 防 災 的 監 測 我 們 的 團 隊, 利 用 國 科 會 計 畫, 在 民 國 89 年 研 發 出 台 灣 第 一 座 土 石 流 監 測 與 預 報 系 統, 當 初

More information

LHAASO-WFCTA SiPM成像探头研制进展

LHAASO-WFCTA  SiPM成像探头研制进展 THE PROGRESS OF SIPM-BASED CAMERA FOR LHAASO-WFCTA Baiyang Bi, Shoushan Zhang, Lingling Ma, Liqiao Yin for the LHAASO Collaboration Outline Introduction LHAASO-WFCTA Why SiPM? Progress Design of Camera/Sub-Cluster

More information

untitled

untitled EDM12864-GR 1 24 1. ----------------------------------------------------3 2. ----------------------------------------------------3 3. ----------------------------------------------------3 4. -------------------------------------------------------6

More information

(02)2809-4742 (02)2809-4742 27 28 (02)2809-4742 85 3 (02)3343-3300 156 12 (02

(02)2809-4742 (02)2809-4742 27 28 (02)2809-4742 85 3 (02)3343-3300  156 12 (02 3475 http://mops.tse.com.tw http://www.ic-fortune.com (02)2809-4742 denis.lee@ic-fortune.com (02)2809-4742 nanhui.lee@ic-fortune.com 27 28 (02)2809-4742 85 3 (02)3343-3300 http://www.fhs.com.tw 156 12

More information

专业主干课程与主要专业课程教学大纲(2009年、2011年).doc

专业主干课程与主要专业课程教学大纲(2009年、2011年).doc ... 1... 4... 9... 12... 16... 20... 23... 26... 30... 33... 36 Electric Circuits 00440021 64 0 0 4 1 2 Y- 3 4 ZYT H 5 Analog Electronic Technique 00440041 54 14 0 3.5 1. 2. 1. 2. 3. RC 4. 5. 1. 20 2.

More information

iml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur

iml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur iml8683-220v C / 4W Down-Light EVM - pplication Notes iml8683 220V C 4W Down Light EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication

More information

untitled

untitled ( ) 2005 2 27 1 70 :SSI(Small Scale Integration), 1 10,MSI (Medium Scale Integration),,, 80 LSI(Large Scale Integration),, 16,Motoral M68000(7 ),Intel 80286 (12.5 ),80386 (27.5 ) 90 : VLSI(Very Large Scale

More information

SPHE8202R Design Guide Important Notice SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provi

SPHE8202R Design Guide Important Notice SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provi SPHE8202R Design Guide V2.0 JUN, 2007 19, Innovation First Road Science Park Hsin-Chu Taiwan 300 R.O.C. Tel: 886-3-578-6005 Fax: 886-3-578-4418 Web: www.sunplus.com SPHE8202R Design Guide Important Notice

More information

場效電晶體簡介.doc

場效電晶體簡介.doc (field effect transistor FET) FET (gate G ) FET (source S ) FET (drain D ) n (n-channel FET) p (p-channel FET) n FET n (channel) p FET p (channel) 1 n p FET FET (unipolar devices) 1 n p FET FET BJT FET

More information

Outline Speech Signals Processing Dual-Tone Multifrequency Signal Detection 云南大学滇池学院课程 : 数字信号处理 Applications of Digital Signal Processing 2

Outline Speech Signals Processing Dual-Tone Multifrequency Signal Detection 云南大学滇池学院课程 : 数字信号处理 Applications of Digital Signal Processing 2 CHAPTER 10 Applications of Digital Signal Processing Wang Weilian wlwang@ynu.edu.cn School of Information Science and Technology Yunnan University Outline Speech Signals Processing Dual-Tone Multifrequency

More information

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin.

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin. Features Wide 3.6V to 32V Input Voltage Range Output Adjustable from 0.8V to 30V Maximum Duty Cycle 100% Minimum Drop Out 0.6V Fixed 300KHz Switching Frequency 12A Constant Output Current Capability Internal

More information

The BIST Scheme for Digital-to Analog converters 1

The BIST Scheme for Digital-to Analog converters 1 The BIST Scheme for Digital-to Analog converters . :... 03.DAC :... 05. :... 08 ( ) :... 08 ( ) :... 08. :... ( ) OP AMP... ( ) Charge Pump Circuit... 3 ( ) Analog Summer Circuit... 4 ( ) CMOS Schmitt

More information

(baking powder) 1 ( ) ( ) 1 10g g (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal D

(baking powder) 1 ( ) ( ) 1 10g g (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal D ( ) 4 1 1 1 145 1 110 1 (baking powder) 1 ( ) ( ) 1 10g 1 1 2.5g 1 1 1 1 60 10 (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal Design 1. 60 120 2. 3. 40 10

More information

!!

!! !! Noise Suppression by EMIFILr Application Guide Application Manual Cat.No.C35C !! 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 YYYYYYYYYYYYYYYYYYYYYY........................ YYYYYYYYYYYYYYYYYYYY........................

More information

iml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin

iml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin iml8683-220v C / 0W EVM - pplication Notes iml8683 220V C 0W EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication Circuit... 3 5. PCB

More information

USB - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - DES Module FSM CONTROLLER 8 6 8 Key ROM 8 8 Data_in RAM Data_out RAM 8 USB Board - 8 - - 9 - - 10 - - 11 - - 12 - USB device INF Windows INF Device Function

More information

Cube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family

Cube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family small, speedy, safe Eextremely modular Up to 64 modules per bus de Quick reaction time: up to 20 µs A new Member of the Cube Family Murrelektronik s modular I/O system expands the field-tested Cube family

More information

LK110_ck

LK110_ck Ck 电子琴 LK110CK1A Ck-1 1. 2. 1. 2. 3. (+) ( ) Ck-2 1. 2. 3. * 1. 2. 3. Ck-3 Ck-4 LCD LCD LCD LCD LCD LCD 15 * * / MIDI Ck-5 100 50 100 100 100 1 2 MIDI MIDI Ck-6 ... Ck-1... Ck-6... Ck-8... Ck-9... Ck-10...

More information

GH1220 Hall Switch

GH1220 Hall Switch Unipolar Hall Switch - Medium Sensitivity Product Description The DH220 is a unipolar h all switch designed in CMOS technology. The IC internally includes a voltage regulator, Hall sensor with dynamic

More information

untitled

untitled 2006-4-25 2006-4-26 2 2006-4-26 3 20 50 6 2006-4-26 4 µ 2006-4-26 5 CERN LEP/LHC 2006-4-26 6 L3 Detector 2006-4-26 7 2006-4-26 8 ATLAS Detector (A Toroidal LHC ApparatuS) 2006-4-26 9 CMS Detector 2006-4-26

More information

MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C

MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C MSO MCU DSP MSO MCU DSP MSO MSO MSO MCU/DSP I/O MSO 16 Microchip IC18 turn-on MSO chirp MCU I/O I 2 C 03 Keysight MSO MSO MSO DSO holdoff infinite-persistence / de-skew MSO 1 MSO MSO MSO MSO MCU DSP 1

More information

MODEL 62000H SERIES 5KW / 10KW / 15KW 0 ~ 375A 0 ~ 1000V/2000V( ) : 200/220Vac, 380/400Vac, 440/480Vac 3U/15KW / & 150KW / ( 10 ms ~ 99 hours)

MODEL 62000H SERIES 5KW / 10KW / 15KW 0 ~ 375A 0 ~ 1000V/2000V( ) : 200/220Vac, 380/400Vac, 440/480Vac 3U/15KW / & 150KW / ( 10 ms ~ 99 hours) MODEL 62000H SERIES 5KW / 10KW / 15KW 0 ~ 375A 0 ~ 1000V/2000V( ) : 200/220Vac, 380/400Vac, 440/480Vac 3U/15KW / &150KW / ( 10 ms ~ 99 hours) 10 100 / PROGRAMMABLE DC POWER SUPPLY MODEL 62000H SERIES USB

More information

Microsoft PowerPoint - ATF2015.ppt [相容模式]

Microsoft PowerPoint - ATF2015.ppt [相容模式] Improving the Video Totalized Method of Stopwatch Calibration Samuel C.K. Ko, Aaron Y.K. Yan and Henry C.K. Ma The Government of Hong Kong Special Administrative Region (SCL) 31 Oct 2015 1 Contents Introduction

More information

CH01.indd

CH01.indd 3D ios Android Windows 10 App Apple icloud Google Wi-Fi 4G 1 ( 3D ) 2 3 4 5 CPU / / 2 6 App UNIX OS X Windows Linux (ios Android Windows 8/8.1/10 BlackBerry OS) 7 ( ZigBee UWB) (IEEE 802.11/a/b/g/n/ad/ac

More information

VHDL(Statements) (Sequential Statement) (Concurrent Statement) VHDL (Architecture)VHDL (PROCESS)(Sub-program) 2

VHDL(Statements) (Sequential Statement) (Concurrent Statement) VHDL (Architecture)VHDL (PROCESS)(Sub-program) 2 VHDL (Statements) VHDL(Statements) (Sequential Statement) (Concurrent Statement) VHDL (Architecture)VHDL (PROCESS)(Sub-program) 2 (Assignment Statement) (Signal Assignment Statement) (Variable Assignment

More information

Microsoft PowerPoint - Ch5 The Bipolar Junction Transistor

Microsoft PowerPoint - Ch5 The Bipolar Junction Transistor O2005: Electronics The Bipolar Junction Transistor (BJT) 張大中 中央大學通訊工程系 dcchang@ce.ncu.edu.tw 中央大學通訊系張大中 Electronics, Neamen 3th Ed. 1 Bipolar Transistor Structures N P 17 10 N D 19 10 N D 15 10 中央大學通訊系張大中

More information

68369 (ppp quickstart guide)

68369 (ppp quickstart guide) Printed in USA 04/02 P/N 68369 rev. B PresencePLUS Pro PC PresencePLUS Pro PresencePLUS Pro CD Pass/Fails page 2 1 1. C-PPCAM 2. PPC.. PPCAMPPCTL 3. DB9D.. STPX.. STP.. 01 Trigger Ready Power 02 03 TRIGGER

More information

NAC-300 user manual

NAC-300 user manual NAC-300N/ NAC-300P - 1 - NAC-300N/ NAC-300P ( 1.0.0) 2006 2006 1 27-2 - - 3 - NAC-300... 6 1.1... 6 1.2... 7 1.3... 8 1.4... 9 NAC-300... 10 2.1 NAC-300...10 2.2 NAC-300...12 NAC-300... 14 3.1...14 3.2

More information

行動電話面板產業

行動電話面板產業 TFT-LCD IC LCD TV Monitor TFT LCD IC 2005 Samsung IC - IC LCD TV LCD monitor LCD TV 2004~2007 69% LCD Monitor 2004~2007 18% IC 2004 ~2009 16.26% 2004 ~2009 10.39% ASP (Fine Pitch) IC Pin IC IC IC TCP COF

More information

時脈樹設計原則

時脈樹設計原則 時 脈 樹 設 計 原 則 在 高 效 能 應 用 中, 例 如 通 訊 無 線 基 礎 設 施 伺 服 器 廣 播 視 訊 以 及 測 試 和 測 量 裝 置, 當 系 統 整 合 更 多 功 能 並 需 要 提 高 效 能 水 準 時, 硬 體 設 計 就 變 得 日 益 複 雜, 這 種 趨 勢 進 一 步 影 響 到 為 系 統 提 供 參 考 時 序 的 電 路 板 設 計 階 段 (board-level)

More information

IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I

IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I 2004 5 IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I Abstract The techniques of digital video processing, transferring

More information

附件1:

附件1: 2013 年 增 列 硕 士 专 业 学 位 授 权 点 申 请 表 硕 士 专 业 学 位 类 别 ( 工 程 领 域 ): 工 程 ( 集 成 电 路 工 程 ) 申 报 单 位 名 称 : 南 开 大 学 国 务 院 学 位 委 员 会 办 公 室 制 表 2013 年 12 月 18 日 填 一 申 请 增 列 硕 士 专 业 学 位 授 权 点 论 证 报 告 集 成 电 路 产 业 是

More information

(Pattern Recognition) 1 1. CCD

(Pattern Recognition) 1 1. CCD ********************************* ********************************* (Pattern Recognition) 1 1. CCD 2. 3. 4. 1 ABSTRACT KeywordsMachine Vision, Real Time Inspection, Image Processing The purpose of this

More information

untitled

untitled Verilog 1 錄 料 7. 邏 8. 料流 9. 行 10. 令 11. 邏 路 例 2 1. Verilog 路 (Flexibility) 易 更 更 易 連 林 數 (Portability) 不 不 易 C 3 2. Verilog Verilog (model) (switch level) (transistor) 邏 (gate level) 料流 (data flow) (register

More information

z x / +/- < >< >< >< >< > 3 b10x b10x 0~9,a~f,A~F, 0~9,a~f,A~F, x,x,z,z,?,_ x,x,z,z,?,_ h H 0~9,_ 0~9,_ d D 0~7,x,X,z,Z

z x / +/- < >< >< >< >< > 3 b10x b10x 0~9,a~f,A~F, 0~9,a~f,A~F, x,x,z,z,?,_ x,x,z,z,?,_ h H 0~9,_ 0~9,_ d D 0~7,x,X,z,Z Verilog Verilog HDL HDL Verilog Verilog 1. 1. 1.1 1.1 TAB TAB VerilogHDL VerilogHDL C 1.2 1.2 C // // /* /* /* /* SYNOPSY SYNOPSY Design Compiler Design Compiler // //synopsys synopsys /* /*synopsys synopsys

More information

<4D6963726F736F667420576F7264202D20CEDECEFDD0C5BDDDB5E7C6F8B9C9B7DDD3D0CFDEB9ABCBBECAD7B4CEB9ABBFAAB7A2D0D0B9C9C6B1D5D0B9C9CBB5C3F7CAE9A3A8C9EAB1A8B8E532303136C4EA36D4C238C8D5B1A8CBCDA3A92E646F63>

<4D6963726F736F667420576F7264202D20CEDECEFDD0C5BDDDB5E7C6F8B9C9B7DDD3D0CFDEB9ABCBBECAD7B4CEB9ABBFAAB7A2D0D0B9C9C6B1D5D0B9C9CBB5C3F7CAE9A3A8C9EAB1A8B8E532303136C4EA36D4C238C8D5B1A8CBCDA3A92E646F63> 无 锡 信 捷 电 气 股 份 有 限 公 司 WuXi Xinje Electric Co.,Ltd. ( 无 锡 市 滨 湖 区 胡 埭 工 业 园 北 区 刘 塘 路 9 号 ) 首 次 公 开 发 行 股 票 招 股 说 明 书 ( 申 报 稿 ) 保 荐 人 ( 主 承 销 商 ) ( 深 圳 市 红 岭 中 路 1012 号 国 信 证 券 大 厦 16-26 层 ) 声 明 本 公 司

More information

(Microsoft Word - \245\274\244\300\246\250\301Z\260\252\247C13.doc)

(Microsoft Word - \245\274\244\300\246\250\301Z\260\252\247C13.doc) VHDL 實 習 報 告 四 資 工 二 指 導 教 授 : 徐 演 政 學 生 : 廖 雅 竹 B9515010 陳 緯 琪 B9515044 敗 LED 史 上 無 敵 超 級 賭 骰 子 模 擬 機 以 廖 雅 竹 陳 緯 琪 Project Title: 骰 硬 件 啟 動 後, 可 以 明 顯 的 觀 察 到 實 驗 板 上 方 的 兩 個 骰 子 器 高 速 地 跳 動 Participants:

More information

Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii

Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii 10384 200024024 UDC 2003 5 2003 6 2003 2003 5 i Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii System On-Chip Design and Performance

More information

USB解决方案.ppt

USB解决方案.ppt USB USB? RS232 USB USB HID U modem ADSL cable modem IrDA Silabs USB CP210x USB UART USB RS-232 USB MCU 15 USB 12 FLASH MCU 3 USB MCU USB MCU C8051F32x 10 ADC 1.5%, Vref CPU 25MIPS 8051 16KB Flash -AMUX

More information

BC04 Module_antenna__ doc

BC04 Module_antenna__ doc http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 1 of 10 http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 2 of 10 http://www.infobluetooth.com TEL:+86-23-68798999

More information

ebook105-1

ebook105-1 C D 1.1 0 1 0 1 2 ( 0 1 ) ( b i t s ) 0 1 1. 2. 0 1 3. ( ) 1-1 1-1 2 A B C A B C X Y 1.2 1.2.1 ( C D ) ( H D L ) H D L H D L J a v a C + + 1.2.2 C P U ( ) 1 3 1-2 C RT ( ) 1-2 ( C P U ) C P U C P U C P

More information

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94 NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz 23 90 CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94/188GHz LC class-b 0.70 0.75 mm 2 pad 1 V 19.6 ma (ƒ

More information

untitled

untitled 年 年 度 年 度 821 路 路 1821 (07)607-7777 12081209 () (07)607-7765 http://www.kyu.edu.tw 1 年 度 理 理 六 路 六 六 六 理 理 錄 錄 六 年 度 理 2 錄....... 1 年.......1 參.......1... 1 年 錄... 2 陸.....15.....16 理 錄. 17. 18 拾.....

More information

EMI LOOPS FILTERING EMI ferrite noise suppressors

EMI LOOPS FILTERING EMI ferrite noise suppressors (HighSpeedBoardDesign) (HIGHSPEEDBOARDDESIGN) 1 1 3 1.1 3 1.1.1 3 1.1.2 vs 4 1.1.3 5 1.1.4 8 1.2 9 1.2.1 9 1.2.2 vs 1 1.3 1 1.3.1 11 1.3.1.1 11 1.3.1.2 12 1.3.1.3 12 1.3.1.4 12 1.3.1.5 12 2. 2.1 14 2.1.1

More information

GC-APPI-MasCom

GC-APPI-MasCom GC-APPI Interface MasCom Technologies Founded in January 1991 as MasCom Analysengeräte Service GmbH Office at Sophie-Germain-Str. 4, 281 Bremen, Germany 18 Employees 6 Electronic engineers 4 Precision

More information

Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11

Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11 Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs

More information

02 看 見 躍 動 的 創 新 力 量 04 矽 數 十 年 金 矽 創 意 十 年 有 成 16 築 夢 之 際 18 20 22 24 26 28 30 32 34 36 38 你 所 不 知 道 的 金 矽 獎 40 樂 在 其 中

02 看 見 躍 動 的 創 新 力 量 04 矽 數 十 年 金 矽 創 意 十 年 有 成 16 築 夢 之 際 18 20 22 24 26 28 30 32 34 36 38 你 所 不 知 道 的 金 矽 獎 40 樂 在 其 中 02 看 見 躍 動 的 創 新 力 量 04 矽 數 十 年 金 矽 創 意 十 年 有 成 16 築 夢 之 際 18 20 22 24 26 28 30 32 34 36 38 你 所 不 知 道 的 金 矽 獎 40 樂 在 其 中 我 們 相 信, 科 技 創 新 是 影 響 台 灣 競 爭 力 的 主 軸, 而 培 育 國 內 高 科 技 人 才, 正 是 金 矽 獎 創 辦 的 理 念

More information

audiogram3 Owners Manual

audiogram3 Owners Manual USB AUDIO INTERFACE ZH 2 AUDIOGRAM 3 ( ) * Yamaha USB Yamaha USB ( ) ( ) USB Yamaha (5)-10 1/2 AUDIOGRAM 3 3 MIC / INST (XLR ) (IEC60268 ): 1 2 (+) 3 (-) 2 1 3 Yamaha USB Yamaha Yamaha Steinberg Media

More information

untitled

untitled Verilog HDL Verilog HDL 邏 令 列邏 路 例 練 數 度 (top-down design) 行 (concurrency) 2.1 Verilog HDL (module) 邏 HDL 理 HDL 邏 料 數 邏 邏 路 module module_name (port_list) // 列 //

More information

1 VLBI VLBI 2 32 MHz 2 Gbps X J VLBI [3] CDAS IVS [4,5] CDAS MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz [6] CDAS VLBI CDAS 2 CDAS CDAS 5 2

1 VLBI VLBI 2 32 MHz 2 Gbps X J VLBI [3] CDAS IVS [4,5] CDAS MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz [6] CDAS VLBI CDAS 2 CDAS CDAS 5 2 32 1 Vol. 32, No. 1 2014 2 PROGRESS IN ASTRONOMY Feb., 2014 doi: 10.3969/j.issn.1000-8349.2014.01.07 VLBI 1,2 1,2 (1. 200030 2. 200030) VLBI (Digital Baseband Convertor DBBC) CDAS (Chinese VLBI Data Acquisition

More information

Microsoft Word - LR1122B-B.doc

Microsoft Word - LR1122B-B.doc UNISONIC TECHNOLOGIES CO., LTD LOW NOISE ma LDO REGULATOR DESCRIPTION The UTC is a typical LDO (linear regulator) with the features of High output voltage accuracy, low supply current, low ON-resistance,

More information

邏輯分析儀的概念與原理-展示版

邏輯分析儀的概念與原理-展示版 PC Base Standalone LA-100 Q&A - - - - - - - SCOPE - - LA - - ( Embedded ) ( Skew ) - Data In External CLK Internal CLK Display Buffer ASIC CPU Memory Trigger Level - - Clock BUS Timing State - ( Timing

More information

Chroma 61500/ bit / RMS RMS VA ()61500 DSP THD /61508/61507/61609/61608/ (61500 ) Chroma STEP PULSE : LISTLIST 100 AC DC

Chroma 61500/ bit / RMS RMS VA ()61500 DSP THD /61508/61507/61609/61608/ (61500 ) Chroma STEP PULSE : LISTLIST 100 AC DC MODEL 61509/61508/61507/ 61609/61608/61607 PROGRAMMABLE AC POWER SOURCE MODEL 61509/61508/61507/ 61609/61608/61607 61509/61609: 6kVA 61508/61608: 4.5kVA 61507/61607: 3kVA : 0-175V/0-350V/Auto : DC, 15Hz-2kHz

More information

IEC 传输帧格式

IEC 传输帧格式 IEC 60870-5-1 GB GB/T XXXXX XXXX idt IEC 60870-5-1:1990 Telecontrol Equipment and Systems Part 5:Transmission Protocol Section 1: Transmission frame formats ( ) 1998.6.28 2000.2.10 2000.5.7 200x-xx-xx

More information

UDC

UDC UDC P GB 50339 2003 Code for acceptance of quality of Intelligent building systems 2003-07-01 2003-10-01 1 Code for acceptance of quality of Intelligent building systems GB 50339 2003 2003 1 0 0 1 2 159

More information

FM1935X智能非接触读写器芯片

FM1935X智能非接触读写器芯片 FM33A0xx MCU 2017. 05 2.0 1 (http://www.fmsh.com/) 2.0 2 ... 3 1... 4 1.1... 4 1.2... 4 1.3... 5 1.3.1... 5 1.3.2... 5 1.4... 8 1.4.1 LQFP100... 8 1.4.2 LQFP80... 9 1.4.3... 9 2... 15 2.1 LQFP100... 15

More information

TH2512/TH2512A Tonghui Electronics reserves the right to make changes at any time without notice in order to improve design and supply the best possib

TH2512/TH2512A Tonghui Electronics reserves the right to make changes at any time without notice in order to improve design and supply the best possib TH2512/TH2512A 2 3 SPECFICATIONS 5 6 6 8 Handler 9 10 11 12 14 17 17-1 - TH2512/TH2512A Tonghui Electronics reserves the right to make changes at any time without notice in order to improve design and

More information

History 97 97Universal Universal 98Universal 98Magnetek Magnetek ighting Group Universal Technologies ighting Energy Saving Incorporation

History 97 97Universal Universal 98Universal 98Magnetek Magnetek ighting Group Universal Technologies ighting Energy Saving Incorporation 00V EECTROIC BAAST History 97 97Universal Universal 98Universal 98Magnetek 997 00Magnetek ighting Group Universal Technologies ighting 999 00Energy Saving Incorporation P. Company Profile Universal ighting

More information

UDC 厦门大学博硕士论文摘要库

UDC 厦门大学博硕士论文摘要库 10384 9924012 UDC 2002 5 2002 2002 2002 5 1 Study on High Speed Switch System and Their ASIC Frontend Design Thesis for MS By Shuicheng Cai Supervisor: Prof. Donghui Guo Department of Physics Xiamen Unviersity

More information

SuperMap 系列产品介绍

SuperMap 系列产品介绍 wuzhihong@scu.edu.cn 3 / 1 / 16 / John M. Yarbrough: Digital Logic Applications and Design + + 30% 70% 1 CHAPTER 1 Digital Concepts and Number Systems 1.1 Digital and Analog: Basic Concepts P1 1.1 1.1

More information

D4

D4 4 020 Application Trend and Fabrication Introduction of 3D Integrated Circuits Through Silicon Vias Technology Abstract The three-dimensional integrated circuits through silicon vias (3D IC TSV) technology

More information

Microsoft PowerPoint - Lecture7II.ppt

Microsoft PowerPoint - Lecture7II.ppt Lecture 8II SUDOKU PUZZLE SUDOKU New Play Check 軟體實作與計算實驗 1 4x4 Sudoku row column 3 2 } 4 } block 1 4 軟體實作與計算實驗 2 Sudoku Puzzle Numbers in the puzzle belong {1,2,3,4} Constraints Each column must contain

More information

EUTECH INSTRUMENTS αlpha-con1000 / Conductivity Controller αlpha CON1000 MEAS ms o C ATC ALARM CAL REL A REL B REL A ENTER ESC AUTO MANU REL

EUTECH INSTRUMENTS αlpha-con1000 / Conductivity Controller αlpha CON1000 MEAS ms o C ATC ALARM CAL REL A REL B REL A ENTER ESC AUTO MANU REL EUTECH INSTRUMENTS αlpha-con1000 / Conductivity Controller αlpha CON1000 MEAS 8.08 25.0 ms o C ATC ALARM CAL REL A REL B REL A ENTER ESC AUTO MANU REL B αlpha-con1000 / αlpha-con 1000 / Eutech Eutech Eutech

More information

Microsoft Word - LD5515_5V1.5A-DB-01 Demo Board Manual

Microsoft Word - LD5515_5V1.5A-DB-01 Demo Board Manual Subject LD5515 Demo Board Model Name (5V/1.5A) Key Features Built-In Pump Express TM Operation Flyback topology with PSR Control Constant Voltage Constant Current High Efficiency with QR Operation (Meet

More information

Microsoft Word 電子構裝結構分析1221.doc

Microsoft Word 電子構裝結構分析1221.doc 電 子 構 裝 結 構 分 析 徐 祥 禎 ( 義 守 大 學 機 械 與 自 動 化 工 程 學 系 副 教 授 ) 前 言 電 子 構 裝 (Electronic Packaging), 主 要 是 利 用 固 定 接 著 技 術, 將 積 體 電 路 (Integrated Circuit, IC) 晶 片 固 定 在 承 載 襯 墊 (Die Pad) 上, 並 利 用 細 微 連 接 技

More information

Embargoed until May 4, 2004 EXPRESS 40 NI HQ 3000 1000 5000 ~ 500 10% / 500 85% NI LabVIEW 7 Express Express EXPRESS : #1 GPS Navigation PC/WWW/Email CD+RW Mobile Phone PDA DVD+RW Satellite Car Alarm/Radio

More information

Master Thesis_專門用來製作目錄.doc

Master Thesis_專門用來製作目錄.doc Introduction All-IP [1-4] All-IP packet switching long delay time, jitter packet loss All-IP Budget-Based QoS End-to-End QoS (real time on demand) 1 1.1 Circuit Switching Packet Switching DWDM IP VoIP

More information

Open topic Bellman-Ford算法与负环

Open topic   Bellman-Ford算法与负环 Open topic Bellman-Ford 2018 11 5 171860508@smail.nju.edu.cn 1/15 Contents 1. G s BF 2. BF 3. BF 2/15 BF G Bellman-Ford false 3/15 BF G Bellman-Ford false G c = v 0, v 1,..., v k (v 0 = v k ) k w(v i 1,

More information

Microsoft Word - KSAE06-S0262.doc

Microsoft Word - KSAE06-S0262.doc Stereo Vision based Forward Collision Warning and Avoidance System Yunhee LeeByungjoo KimHogi JungPaljoo Yoon Central R&D Center, MANDO Corporation, 413-5, Gomae-Ri, Gibeung-Eub, Youngin-Si, Kyonggi-Do,

More information

User ID 150 Password - User ID 150 Password Mon- Cam-- Invalid Terminal Mode No User Terminal Mode No User Mon- Cam-- 2

User ID 150 Password - User ID 150 Password Mon- Cam-- Invalid Terminal Mode No User Terminal Mode No User Mon- Cam-- 2 Terminal Mode No User User ID 150 Password - User ID 150 Password Mon- Cam-- Invalid Terminal Mode No User Terminal Mode No User Mon- Cam-- 2 Mon1 Cam-- Mon- Cam-- Prohibited M04 Mon1 Cam03 Mon1 Cam03

More information

D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK =

D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK = VHDL (Sequential Logic) D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK = '1' then Q

More information

OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot

OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot OSI OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Protocol OSI OSI OSI OSI OSI O S I 2-1 Application

More information

untitled

untitled 1 1. 1 1. 1. 1 image I(x,y,z,t) object to image 1. 1. 2 1 X Rays, Gamma-Rays, X Rays CT 1. 1. 3 INPUT Processing OUTPUT 1. 1. 4 Anolog Image Processing 2 25 / 1. 1. 5 Digital Image Processing Digitizing,

More information

<4D6963726F736F667420576F7264202D20C9CFBAA3BFC6BCBCB4F3D1A7D0C5CFA2D1A7D4BA32303136C4EAC7EFBCBEC8EBD1A7B2A9CABFD7CAB8F1BFBCCAD4CAB5CAA9CFB8D4F22D30343036C8B7B6A8B8E5>

<4D6963726F736F667420576F7264202D20C9CFBAA3BFC6BCBCB4F3D1A7D0C5CFA2D1A7D4BA32303136C4EAC7EFBCBEC8EBD1A7B2A9CABFD7CAB8F1BFBCCAD4CAB5CAA9CFB8D4F22D30343036C8B7B6A8B8E5> 上 海 科 技 大 学 信 息 科 学 与 技 术 学 院 年 度 博 士 资 格 考 试 实 施 细 则 一 总 则 本 细 则 由 上 海 科 技 大 学 信 息 科 学 与 技 术 学 院 ( 以 下 简 称 信 息 学 院 ) 教 学 指 导 委 员 会 讨 论 制 定, 适 用 于 信 息 学 院 2014 级 硕 士 研 究 生 的 年 度 博 士 资 格 考 试 信 息 学 院 2014

More information

行业

行业 PCI-1710 1.1...2 1.1.1...2 1.1.2...2 1.1.3 FIFO( )...2 1.1.4...2 1.1.5...2 1.1.6 16 16...3 1.1.7...3 1.2...3 1.3...3 2.1...3 2.2...4 2.2.1...4 2.2.2...5 2.3...9 2.3.1...10 2.3.2... 11 2.3.3...12 2.3.4...12

More information

ebook122-11

ebook122-11 11 (test bench) Verilog HDL 11.1 1) ( ) 2) 3) Verilog HDL module T e s t _ B e n c h; // L o c a l _ r e g _ a n d _ n e t _ d e c l a r a t i o n s G e n e r a t e _ w a v e f o r m s _ u s i n g & s

More information

行业

行业 PCL-1800 PCL-1800 1.1...2 1.1.1 1K FIFO...2 1.1.2...2 1.1.3 16...3 1.1.4...3 1.1.5...3 1.1.6...3 1.2...3 1.3...4 1.4...5 2.1...5 2.2...6 2.2.1...6 2.2.2...6 2.2.3 D/A...7 2.2.4...7 2.2.5 TRIG0 GATE0...8

More information

Microsoft PowerPoint - Aqua-Sim.pptx

Microsoft PowerPoint - Aqua-Sim.pptx Peng Xie, Zhong Zhou, Zheng Peng, Hai Yan, Tiansi Hu, Jun-Hong Cui, Zhijie Shi, Yunsi Fei, Shengli Zhou Underwater Sensor Network Lab 1 Outline Motivations System Overview Aqua-Sim Components Experimental

More information

JOURNAL OF EARTHQUAKE ENGINEERING AND ENGINEERING VIBRATION Vol. 31 No. 5 Oct /35 TU3521 P315.

JOURNAL OF EARTHQUAKE ENGINEERING AND ENGINEERING VIBRATION Vol. 31 No. 5 Oct /35 TU3521 P315. 31 5 2011 10 JOURNAL OF EARTHQUAKE ENGINEERING AND ENGINEERING VIBRATION Vol. 31 No. 5 Oct. 2011 1000-1301 2011 05-0075 - 09 510405 1 /35 TU3521 P315. 8 A Earthquake simulation shaking table test and analysis

More information

热设计网

热设计网 例 例 Agenda Popular Simulation software in PC industry * CFD software -- Flotherm * Advantage of Flotherm Flotherm apply to Cooler design * How to build up the model * Optimal parameter in cooler design

More information

行业

行业 PCI-1711/1711L 1.1...2 1.1.1...2 1.1.2...2 1.1.3 FIFO...2 1.1.4...2 1.1.5 16 16...3 1.2...3 2.1...3 2.2...3 2.2.1... 2.2.2...8 2.3...10 2.3.1...10 2.3.2... 11 2.3.3...12 2.3.4...13 2.4.5...14 3.1...16

More information

行业

行业 PCL-818HD/HG/L PCL-818HD/HG/L 1.1...2 1.1.1 /...2 1.1.2 ID...2 1.2...3 1.3...3 2.1...3 2.2...3 2.2.1...4 2.2.2...4 2.2.3 DMA...5 2.2.4...5 2.2.5 D/A...5 2.2.6...6 2.2.7 EXE.trigger GATE0...6 2.2.8 FIFO

More information

Microsoft Word - AP1515V02

Microsoft Word - AP1515V02 Document No. Rev.: V0.20 Page: 1 of 9 Revision History Rev. DRN # History Initiator Effective Date V01 V02 Initial document 黃宗文 Add second package description 葉宗榮 2014/05/15 2015/09/08 Initiator: 雷晨妤 (DCC)

More information

積體電路設計方法

積體電路設計方法 積體電路設計方法 賴源泰 電機系 成功大學 1 積體電路時代 Transistors integrated on a single chip 10-100 in 1960 1K-20K in 1970 20K-500K in 1980 10M-20M in 1990 2 積體電路時代 Minimum line width in mass production 5μm in 1977 2μm in 1984

More information

三維空間之機械手臂虛擬實境模擬

三維空間之機械手臂虛擬實境模擬 VRML Model of 3-D Robot Arm VRML Model of 3-D Robot Arm MATLAB VRML MATLAB Simulink i MATLAB Simulink V-Realm Build Joystick ii Abstract The major purpose of this thesis presents the procedure of VRML

More information

untitled

untitled LBS Research and Application of Location Information Management Technology in LBS TP319 10290 UDC LBS Research and Application of Location Information Management Technology in LBS , LBS PDA LBS

More information