z x / +/- < >< >< >< >< > 3 b10x b10x 0~9,a~f,A~F, 0~9,a~f,A~F, x,x,z,z,?,_ x,x,z,z,?,_ h H 0~9,_ 0~9,_ d D 0~7,x,X,z,Z

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意采崔
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1 Verilog Verilog HDL HDL Verilog Verilog TAB TAB VerilogHDL VerilogHDL C C // // /* /* /* /* SYNOPSY SYNOPSY Design Compiler Design Compiler // //synopsys synopsys /* /*synopsys synopsys

2 z x / +/- < >< >< >< >< > 3 b10x b10x 0~9,a~f,A~F, 0~9,a~f,A~F, x,x,z,z,?,_ x,x,z,z,?,_ h H 0~9,_ 0~9,_ d D 0~7,x,X,z,Z,? 0~7,x,X,z,Z,?,_,_ o O 0,1,x,X,z,Z,?, 0,1,x,X,z,Z,?, _ b B z _ MSB MSB x z x z

3 _1010(32 ) 4ac h4ac 32 9 o _111_ e12 9 o e-2 6 hf3 6 11_0011, 2e3 6h f 6 00_1111, 0 12_34.56_78_e b10x 3 10x h2x _xxxx_0110.3e2 6 hx 6 xx_xxxx, x 3. C \n \t Tab \\ \ \ddd %% ASCII % module test_string; reg [8*14:1] str_var; initial begin str_var= Hello world ; $display( display( %s is stored as %h, str_var,str_var); str_var={ ={str_var,!!!!!! }; $display( display( %s is stored as %h, str_var,str_var); end endmodule

4 _bus1 \~( ~(a+b) net a*b_net 2. 0~9 $ $display,$write,$monitor $time,$realtime $finish,$stop $readmem 4.3 always,and assign begin case cmos default edge else end endmodule enent for if initial inout input integer nand negedge nor not or output posedge reg wait while wor xnor

5 1. assign (initial always) VerilogHDL ztriregx trireg wire,tri wor,trior wand,triand trireg tri1 tri0 supply1 supply0 1bit wire wire tri trireg DRAM DRAM pullup pulldown) 1 0

6 2. reg C initial always x reg integer real time MUX module mux_str(out,a,b,sel); output out; initial always Gate2 Input a,b,sel; a net2 not gate1(net1,sel); Gate1 Gate4 integer realtime and gate2(net2,a,net); sel net1 and gate3(net3,b,sel); out integer or gate4(out,net2,net3); b net3 real endmodule Gate3 time reg reg not andorveriloghdl gatex netx

7 3. MUX module test_for_mux; reg a,b,sel; mux_str mux1(out,a,b,s); initial begin a=0;b=1;s=0; #10 a=1; #10 b=0; #10 s=1; #10 b=1; #10 a=0; #10 $finish end initial $monitor($time, a=%b b=%b s=%b out=%b,a,b,s,out,a,b,s,out); endmodule 1 wire a,b,c; reg d,e,f; 1 wire[7:0] bus_a,bus_b; reg[15:0] reg_d,reg_e; MSB LSB scalared reg scalared [7:0] reg_a; scalared vectored reg vectored [31:0] bus32; vectored parameter wordsize=16,memsize=1024 =16,memsize=1024 reg[wordsize-1:0] mem_ram[memsize- 1],write_reg,read_reg; write_reg=8 =8 b0001_1010; write_reg[2]=1 b1; // 2 write_reg[2:0]=3 b101; mem_ram[2]=8 b1000_1011;// b1000_1011;// 2

8 reg [7:0] a; reg b[7:0]; 1. parameter << > parameter msb=7,lsb=0,delay=2; verilog timescale << >/< > define << > << > define MSB 7 define LSB 0 define delay_and and #1 reg[ MSB: MSB: LSB] ] a; delay_and (x,y,z);

9 ?:?: {} {} <<,>> <<,>> ==,!=,===,!== ==,!=,===,!== <,>,< <,>,<=,>= =,>=!,&&,!,&&, &,~&,,~,^,^~(~^) &,~&,,~,^,^~(~^) ~,&,,^,^~(~^) ~,&,,^,^~(~^) +, +,-,*,/,%,*,/,%!,~!,~ *,/,%,/,% +, +,- <<,>> <<,>> <,<=,>, <,<=,>,>= >= ==,!=,===,!== ==,!=,===,!== &,~& &,~& ^,~^ ^,~^,~,~ && &&?:?: , +,-,*,/,%,*,/,% / x

10 ~ & 0&x 1&x 0 x 1 x ^ 0^x 1^x ~^(^~) a=4 b0100,b=4 b0100,b=4 b1111; b1111; ~a 1011 ~b 0000 a&b 0100 a b 1111 a^b 1011 a~^b 0100 a=4 b0110 &a 0 ~&a 1 a 1 ~ a 0 ^a 0 ~^a 1 4. (1) (0) && (&), ( ), ( ), (^), ~&,~,~^ ~ a&&b a& &b

11 a=4 b0010,b=4 b0010,b=4 b0000b0000!a 0!b 1 a&&b 0 a b < > <= >= 6.!, &&, (z) (x) (a>b)&&(x>y) a>b && x>y x (!a) (a>b)!a a>b!=: a=4 b0100,b=4 b0100,b=4 b1010 b1010 a<b 1 a>b 0 a<=b 1 a>=b 0

12 << (x) (z) >> 0 10!== a=b=4 b0100,c=d=4 b0100,c=d=4 b10x0b10x0 a==b 1 c==d x a!=b 0 a===b 1 a!==b 0 c!=d x c===d 1 c!==d 0 7. module demo_shift; reg [4:1] reg_start,reg_stop; initial begin reg_start=4 =4 b1011; #100 reg_stop=reg_start reg_start<<2; #100 $display( before shift is %b,after shift is\ %b,reg_start,reg_stop); #100 finish; end endmodule before shift is 1011,after shift is {a,b,c,3 b101} b101} a,c a,c b4 9 {a,b[3],b[2],b[1],b[0],c,1 b1,1 b1,1 b0,1 b1} b1} {n{w}} {a,{3{b}},{2{c,d}}}

13 Verilog HDL 0 xz < >?< >:< > assign tri_bus=(drv_enble)?data:16 =(drv_enble)?data:16 hzzzz module adder(...); wire [7:0] a,b,sum; assign sum=a+b>>1; endmodule module adder(...); wire [7:0] a,b,sum; assign sum=0+a+b>>1; endmodule VerilogHDL VerilogHDL

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untitled Verilog HDL Verilog HDL 邏令列邏路例練數度 (top-down design) 行 (concurrency) 2.1 Verilog HDL (module) 邏 HDL 理 HDL 邏料數邏邏路 module module_name (port_list) // 列 //