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谓昭张
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1 niosii H:\DB2005\project\niosDK\Example\NiosSmall QuartusII4.2 File -> New Project Wizard Diectory,Name,Top-Level Entity Add Files

2 EDA Tools Setting Finish, OK H:\DB2005\project\niosDK\Example\NiosSmall name Setup.tcl file

3 #Setup.tcl # Setup pin setting set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON set_location_assignment PIN_16 -to OSC0 set_location_assignment PIN_125 -to RESET_ set_location_assignment PIN_28 -to LED\[0\] set_location_assignment PIN_85 -to LED\[1\] set_location_assignment PIN_96 -to LED\[2\] set_location_assignment PIN_97 -to LED\[3\] Script, 1 TRI-STATED 2 INIT_DONE_OUTPUT 3 map Tools -> Tcl Scripts, Script Setup, Run nios Tools -> SopcBuilder, Altera SOPC Builder Altera SOPC Builder SOPC Builder System Name, sopc_niossmall HDL Language, verilog

4 OK Board Target, Unspecified Board Target Device Family, Cyclone Clock, 16M Nios II Nios II Processor -Altera Corporation, Altera niosii NiosII core Nios II/e Nios II/e, Next,

5 JTAG Debug Module Level 1, Next, Custom Instructions

6 Finish, niosii cpu_0 cpu_niossmall On-Chip Memory(RAM or ROM),( Avalon Modules -> Memory -> RAM. Memory Type RAM Data Width 32bits,Total Memory Size 4K bytes, Finish

7 name onchip_memory_0 ram, onchip_ram_0 PIO( Parallel I/O)( Avalon Modules -> Other Width 4bits, Finish

8 name pio_0 PIO, led_pio System ->Auto-Assign Base Addresses,

9 Sysetm->Auto-Assign IRQs, Nios II More "cpu_niossmall" settings Reset Address Exceptiong Address Break Location System Generation HDL.Generate system module logic in Verilog, Simulation.Create ModelSim(tm) project files Generate,

10 SUCCESS: SYSTEM GENERATION COMPLETED. QuartusII niosii

11 SOPC Builder QuartusII SOPC Builder sopc_niossmall.bsf, niosii_e input:clk,reset_n, output:out_port_from_the_piop[3:0] sopc_niossmall, NisoSmall.bdf, sopc_niossmall niosclktoclk niso reset_n to VCC out_port_from_the_pio_0[3:0] to LED[3:0], LPM_INV) Alter SOPC Builder Run Nios II IDE, Nios II IDE,

12 Nios II IDE File -> New -> Project, New Project C/C++ Application, Next, Project Name, ExampleNiosSmall_hello_led_0 Select Project Template Hello LED( sram 4kbytes, Template Next,

13 Create a new system library named Finish, hello_led.c, while(i<200000) while(i<40000). System library Project->Build All(Ctrl+B), Build completed.

14 LED_PIO_BASE SOPC PIO(Parallel I/O)( Avalon Modules -> Other LED_PIO, PIO_0 IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, led); 1 hello_led.c, IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, led) PIO 2 sopc PIO LED_PIO QuartusII Processing -> Star Compilation,

15 Tools ->Programmer, FPGA LED

16 OK,

KT-SOPCx开发套件简明教程

KT-SOPCx开发套件简明教程 V2.03 2005-9-1 FPGA SOC FPGA/SOPC IT QuartusII NiosII IDE FPGA/SOPC FPGA/SOPC FPGA/SOPC CT-SOPCx FPGA/SOPC CPLD/FPGA www.fpga.com.cn CPLD/FPGA FPGA QuartusII NiosII CPU SOPC SOPC Builder NiosII IDE 1 www.21control.com