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1 IP Verification 國立中山大學資訊工程學系黃英哲

2 nlint - Rule Checker

3 Course Objects Rule Definition nlint Utilizing 中山大學資工系黃英哲 3

4 Rule Definition Rule Group Coding style Language Construct Design style DFT Simulation Synthesis HDL translation Naming Convention 中山大學資工系黃英哲 4

5 Rule unconventional vector range definition Range declaration uses descending bit order and zero bound on LSB module initval; reg clock, reset; wire [1:8] count; //warning on "count[1:8]", //"count[7:0]" is recommended endmodule 中山大學資工系黃英哲 5

6 Rule (verilog) more than one module in file (vhdl) more than one primary unit in file See if each source file contains only one module or one primary unit // File: test.v module test(); //file test.v contains only one module //and the module name should be same //with file name... endmodule 中山大學資工系黃英哲 6

7 Rule bit width mismatch in assignment See if there is any width mismatch in assignment statements wire [3:0] a; wire [2:0] b; assign a = b; //warning on "a" and "b 中山大學資工系黃英哲 7

8 Rule bit width mismatch in bitwise operation Any width mismatch in bitwise operation. module test(result, a, b, c, d); output [1:0] result; input [2:0] a, b; //a, b is 3 bit width input [3:0] c, d; //c, d is 4 bit width reg [1:0] result; or b or c or d) if ((a+b) > (c+d)) //warning on "a"(3) and "c"(4) else if ((a+b) == (c+d)) result = 'b1; else result = 'b11; endmodule 中山大學資工系黃英哲 8

9 Rule (verilog) expression connected to port instance Any expression directly connected to a port of instance module andtest; wire a,b1,b2; wire c; and and1(c, a, b1+b2); //warning on b1+b2 as port instance; endmodule 中山大學資工系黃英哲 9

10 Rule combinational loop will control the behavior of module andtest( b, c ); input b; output c; wire a, b, c;... assign a = c; and and1(c, a, b); //warning on "c->a->c" endmodule 中山大學資工系黃英哲 10

11 Rule asynchronous loop Signal oscillate out of the clock control in asynchronous loop module counter(count, clk ); parameter number = 10; output [3:0] count; input clk; reg [3:0] count; reg i_rst; clk or posedge i_rst) //warning on "count->i_rst->count" if ( i_rst ) count < = 0; else count < = count + 1; count ) if ( count == number ) i_rst = 1; else i_rst = 0; endmodule 中山大學資工系黃英哲 11

12 Rule more than one statement per line If there are multiple statements on a line or inc_dec) begin: COMBINATIONAL_PROC if ( inc_dec == 0) sum = a + 1; else sum = a - 1; end //good coding style using separate line for each HDL //statement 中山大學資工系黃英哲 12

13 Rule (verilog) implicit port connection (vhdl) implicit port association Name association used on the port instance list module testini;... test u_test_0(sel, a, b, c, y); //warning here endmodule module test(sel, a, b, c, y);... endmodule 中山大學資工系黃英哲 13

14 Rule gated clock Gated clock in the design module test ( q, clk, en, reset, d ); output q; input clk, en, reset, d; reg q; wire clk, en, reset, d; wire clk_en; and U_and_1(clk_en, clk, en); //warning on "clk_en", is gated posedge clk_en or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule 中山大學資工系黃英哲 14

15 Rule Invertor clock Invertor clock in the design module test ( q, clk, reset, d ); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i; inv U_buf_1(clk_i, clk); //warning on "clk_i", clk_i is drived //by a buffer posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule 中山大學資工系黃英哲 15

16 Rule buffered clock Explicit buffered clock in the design module test ( q, clk, reset, d ); output q; input clk, reset, d; reg q; wire clk, reset, d; wire clk_i; buf U_buf_1(clk_i, clk); //warning on "clk_i", clk_i is drived //by a buffer posedge clk_i or negedge reset ) if ( ~reset ) q <= 1'b0; else q <= d; endmodule 中山大學資工系黃英哲 16

17 Rule (verilog) single-bit logical operation on vectors Single-bit logic operator (&&, ) taking vectors as operands 中山大學資工系黃英哲 17 module test(.pc(c),.pa(a),.pb(b)); input [2:0] a, b; output [2:0] c; reg [2:0] c; or b) begin if (a && b) //warning on "a" and "b", both of them are //vector; this expression is equal to //"( a) && ( b)" c = 1; if (!(a b)) //warning on "a" and "b", both of them are //vector; it is equal to "( a) ( b)" c = 0; end endmodule

18 Rule (verilog) wire not explicitly declared All wires are declared explicitly module test(a, b, c, d, f); input a, b, c, d; output f; //wire f1, f2; assign d = f; and and1(f1, a, b); //warning on "f1", implicit wire or or1(f2, c, d); //warning on "f2", implicit wire or or2(f, f1, f2); endmodule 中山大學資工系黃英哲 18

19 Rule multiple clock signals More than one clock signal in a module or an architecture module block1(clock1,clock2,clock3,reset,count,data,data1,y,y1); input clock1, clock2, clock3, reset, data, data1; clock1 or negedge reset) //clock signal "clock1" begin end clock2) //warning on "clock2", another clock signal begin end clock3) //warning on "clock3", another clock signal begin end endmodule 中山大學資工系黃英哲 19

20 Rule clock signal active on both edges Clock signal that is on both the rising and falling active edge 中山大學資工系黃英哲 20 module block1(clock, reset, count, data, y); input clock, reset, data; output [8:0] count; reg [8:0] count; output y; reg y; initial count <= 0; clock or negedge reset) //posedge "clock" begin end clock) //negedge "clock", warning on "clock" begin end endmodule

21 Rule (verilog) delay in non-blocking assignment Any delay used in a non-blocking assignment module test(q, clock, reset, d); output q; input clock, reset, d; reg q; wire clock, reset, d; parameter D_RQ = 1, D_CQ = 2; clock or negedge reset) if (~reset) #D_RQ q <= 0; //delay control "#D_RQ" may cause //non-blocking effect invalid, warning else #D_CQ q <= d; //delay control "#D_CQ" may cause //non-blocking effect invalid, warning endmodule 中山大學資工系黃英哲 21

22 Rule (verilog) inferred storage not in library (vhdl) inferred storage Check and report all inferred storages that are not in library module test(c, a, b); input [1:0] a, b; output [1:0] c; reg [1:0] c; or b) if (a) c = b; //a latch "c" inferred endmodule 中山大學資工系黃英哲 22

23 Rule (verilog) case statement not fully-specified (vhdl) case/select statement not fully-specified Case (select) statement that does not cover all cases and has no default module test(out0, in1, in2, in3, sel); input [1:0] in1, in2, in3, sel; output [1:0] out0; reg [1:0] out0; or in2 or sel) case (sel) 2'b00: out0 = in1; 2'b01: out0 = in2; 2'b10: out0 = in3; //case not full, warning endcase endmodule 中山大學資工系黃英哲 23

24 Rule incomplete sensitivity list Any incomplete sensitivity list //"b" is also sensitive signal, which will cause //simulation problem, warning c = a + b; 中山大學資工系黃英哲 24

25 Rule extra signal in sensitivity list Any extraneous signal in the sensitivity list or in2 or in3) //"in3" is not referenced in block, //not a sensitive signal, warning out = in1 & in2; 中山大學資工系黃英哲 25

26 Rule (verilog) illegal assignment in edge-triggered block 中山大學資工系黃英哲 26 Not allowed assignment by default used in an edge triggered block, ex: blocking assignment clock) begin a = b; c = a; // choose BLOCKING, IGNORE_DEPEND; //block assignment in edge-trigger block will cause //mismatch between pre-synthesis and //post-synthesis simulation end suppressed by synopsys compile directive "synopsys translate_off" clock) begin a = b; c = a; // choose BLOCKING, CHECK_DEPEND; //no warning here end

27 Rule (verilog) illegal assignment in combinational block Not allowed assignment like non-blocking assignment by default used in a combinational block begin a <= in; o <= a; //choose NONBLOCKING, IGNORE_DEPEND; //non-block assignment in combinational block will //cause mismatch between pre-synthesis and //post-synthesis simulation end suppressed by synopsys compile directive "synopsys translate_off" 中山大學資工系黃英哲 27 begin a <= in; o <= a; //choose NONBLOCKING, CHECK_DEPEND; //no warning end

28 Rule race condition in sequential logic Potential race condition due to a signal being updated in one block and, simultaneously, being referenced in another module test(y1, y2, clk, a, b); output y1, y2; input clk, a, b; reg y1, y2; (posedge clk) begin : first y1 = a; //"y1" is assigned when "posedge clk" end clk) begin : second if (y1 == 1) //"y1" is referenced when "posedge clk", the //value will depend on simulator, warning y2 = b; else y2 = 0; end endmodule 中山大學資工系黃英哲 28

29 Rule race condition in combinational logic A signal is shared in two blocks under same condition, the simulation result will be implement-dependent and difference 中山大學資工系黃英哲 29 module tt( d2, a, b, sel ); output d2; input a, b, sel; wire a, b, sel; reg d1, d2; sel or a or b ) if ( sel ) d1 = a; else d1 = b; // "d1" assigned when (!sel) sel or a ) if ( sel ) d2 = ~a; else d2 = ~d1; // "d1" referenced when (!sel) endmodule

30 Rule (verilog) Z or X used in conditional expression Usage of 'x' or 'z' in conditional expression (vhdl) metalogic value in conditional expression Metalogic values used in conditional expression 中山大學資工系黃英哲 30 module test(dataout, s, datain); parameter WIDTH = 4; output dataout; input s; input [WIDTH-1:0] datain; reg dataout; or datain) begin if (s == 'bz) //"'bz" in conditional expression, warning dataout = datain[0]; else if (s == 'bx) //"'bx" in conditional expression, warning dataout = datain[1]; else if (s == 'b0) dataout = datain[2]; else dataout = datain[3]; end endmodule

31 Rule (verilog) UDP instance not synthesizable UDP invocation because it cannot be synthesized 中山大學資工系黃英哲 31 module testing; reg a, b, cin; wire sum; test u_test_0(sum, cin, a, b); //non-synthesizable, warning endmodule primitive test(sum, cin, a, b); output sum; input cin,a,b; table : 0; : 1; : 1; : 0; : 1; : 0; : 0; : 1; endtable endprimitive

32 Rule (verilog) initial block not synthesizable Any initial block cannot be synthesized initial //non-synthesizable, warning begin... end 中山大學資工系黃英哲 32

33 Rule (verilog) task not synthesizable Any task used because it cannot be synthesized task multiply; //non-synthesizable, warning begin... end endtask 中山大學資工系黃英哲 33

34 Rule (verilog) delay ignored by synthesis Any delay which may cause difference between simulation result of pre-synthesis and post-synthesis and #(3,5) and_test(c, a, b); //ignored by synthesizer, warning 中山大學資工系黃英哲 34

35 Rule (verilog) operation on X/Z not make sense Any operation performed on metalogic value X/Z or directly assigned by X/Z, which will cause simulation mismatch between pre-synthesis and post-synthesis module test( a, b ); input b; output a; wire c; assign c = 1'bz; //warning here, Z is directly assigned to some signal assign a = b & 1'bx c; //warning here, X is operated endmodule 中山大學資工系黃英哲 35

36 Rule (verilog) VHDL reserved words Check any VHDL reserved word used do not use VHDL reserved words to avoid translation error VHDL reserved words: "abs", "access", "after", "alias", "all", "and","architecture", "array", "assert", "attribute", "begin", "block","body", "buffer", "bus", "case", "component", "configuration","constant", "disconnect", "downto", "else", "elsif", "end","entity", "exit", "file", "for", "function", "generate", "generic", "group", "guarded", "if", "impure", "in", "inertial","inout", "is", "label", "library", "linkage", "literal", "loop","map", "mod", "nand", "new", "next", "nor", "not", "null", "of","on", "open", "or", "others", "out", "package", "port","postponed", "procedure", "process", "pure", "range", "record","register", "reject", "rem", "report", "return", "rol", "ror", "select", "severity", "shared", "signal", "sla", "sll", "sra", "srl", "subtype", "then", "to", "transport", "type","unaffected", "units", "until", "use", "variable", "wait","when", "while", "with", "xnor", "xor" 中山大學資工系黃英哲 36

37 Rule (vhdl) Verilog reserved words Do not use Verilog reserved words to avoid translation error Verilog reserved words: "always", "and", "assign", "begin", "buf", "bufif0", "bufif1", "case", "casex", "casez", "cmos", "deassign", "default", "defparam", "disable", "edge", "else", "end",? "endcase", "endmodule", "endfunction", "endprimitive", "endspecify", "endtable", "endtask", "event", "for", "force", "forever", "fork", "function", "highz0", "highz1", "if", "ifnono", "initial", "inout", "input", "integer", "join", "large", "macromodule", "medium", "module", "nand", "negedge", "nmos", "nor", "not", "notif0", "notif1", "or", "output", "parameter", "pmos", "posedge", "primitive", "pull0", "pull1", "pullup", "pulldown", "rcmos", "real", "realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "scalared", "small", "specify", "specparam", "strong0", "strong1", "supply0", "sypply1", "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand", "trior", "trireg", "vectored", "wait", "wand", "weak0", "weak1", "while", "wire", "wor", "xnor", "xor 中山大學資工系黃英哲 37

38 Rule (verilog) names distinguishable in letter case only Any pair of names that differ in cases only module test; reg reg1, reg2, reg3, REG1, Reg2, WIRE1; //warning "REG1"<->"reg1"... wire wire1, wire2, wire3, Wire2, test; //warning "test"<->"test"... Test u_test(wire3, reg3); Test u_test(wire1, reg1); //warning "u_test"<->"u_test" endmodule 中山大學資工系黃英哲 38

39 Rule unknown synopsys directive Check any unknown synopsys directive being used module test(); // synopsys aaa warning here endmodule 中山大學資工系黃英哲 39

40 nlint Utilization Main frame of nlint Import file of *.v, *.f Hierarchy under compilation 中山大學資工系黃英哲 40

41 nlint Profile Rule Organizer Choose the rules for code checking Report Viewer Code violation enclosed by rectangular box 中山大學資工系黃英哲 41

42 Quick Start on nlint Unix-like command line Import Design > nlint gui Start nlint GUI interface Use File->Import Design to specify your design 中山大學資工系黃英哲 42

43 Import Design File-> Import Design-> From File Select our design file (e.g. *.v, *.f) press OK to import file 中山大學資工系黃英哲 43

44 Open Another Window Choose file by left click -> Open Edit different files on another window mouse left click 中山大學資工系黃英哲 44

45 Unchecked File Check/uncheck bottom Choose files that don t want to be rule checking click the bottom choose the file 中山大學資工系黃英哲 45

46 Hierarchy View Expand the design hierarchically Need to wait for compiling time 中山大學資工系黃英哲 46

47 Rule Organizer Choose the rules that we want to check Rules store by different groups Some rules distribute into two or more groups rule organizer group page 中山大學資工系黃英哲 47

48 Rule Specification Select rule by mouse click Enable/disable group synopsys support enable/disable 中山大學資工系黃英哲 48

49 Linting Run->lint Linting our design after rule specified Violation store by Group Rule number Rule description 中山大學資工系黃英哲 49

50 Source Modification Editor window Click the rule description to allocate the violated code Output window shows the warning and error message output window 中山大學資工系黃英哲 50

51 Tool Preference Tools->Preference Report page->general page Change the report viewer options ntrace/nschema can turn on Debussy for debugging 中山大學資工系黃英哲 51

52 Appendix Rule List (I) Rule Group Serial No. Rule Contents Coding Style unconventional vector range definition Coding Style (verilog) more than one module in file Coding Style (vhdl) more than one primary unit in file Language Construct bit width mismatch in assignment Language Construct bit width mismatch in bitwise operation DFT, Design Style (verilog) expression connected to port instance Simulation, DFT, Design Style combinational loop Simulation, DFT, Design Style asynchronous loop Coding Style more than one statement per line Coding Style (verilog) implicit port connection 中山大學資工系黃英哲 52

53 Rule List (II) Rule Group Serial No. Rule Contents Coding Style (vhdl) implicit port association DFT, Design Style gated clock DFT, Design Style invertor clock DFT, Design Style buffered clock Simulation, Language Construct (verilog) single-bit logical operation on vector Coding Style (verilog) wire not explicitly declared DFT, Design Style multiple clock signals Design Style clock signal active on both edges Simulation, Language Construct (verilog) delay in non-blocking assignment Synthesis (verilog) inferred storage not in library 中山大學資工系黃英哲 53

54 Rule List (III) Rule Group Serial No. Rule Contents Synthesis (vhdl) inferred storage Language Construct (verilog) case statement not fully-specified Language Construct (vhdl) case/select statement not fully-specified Simulation, Synthesis incomplete sensitivity list Simulation extra signal in sensitivity list Synthesis (verilog) illegal assignment in edge-triggered Synthesis (verilog) illegal assignment in combinational block Simulation, Language Construct Simulation, Language Construct Synthesis, Language Construct race condition in sequential logic race condition in combinational logic (verilog) Z or X used in combinational expression 中山大學資工系黃英哲 54

55 Rule List (IV) 中山大學資工系黃英哲 55 Rule Group Serial No. Rule Contents Synthesis, Language Construct (vhdl) metalogic used in combinational expression Synthesis (verilog) UDP instance not synthesizable Synthesis (verilog) initial block not synthesizable Synthesis (verilog) task not synthesizable Synthesis (verilog) delay ignored by synthesis Simulation (verilog) operation on X/Z not make sense HDL Translation (verilog) VHDL reserved words HDL Translation (vhdl) Verilog reserved words HDL Translation, Naming Convention (verilog) names distinguishable in letter case Language Construct unknown synopsys directive

56 VN-Cover Utilization

57 Course Objects VN-Cover Code Coverage FSM Coverage Tool Utilizing Verification Flow Simulation Results Analysis 中山大學資工系黃英哲 57

58 VN-Cover Code Coverage Statement Branch Condition Path Toggle Triggering Tracing FSM Coverage State Arc Path 中山大學資工系黃英哲 58

59 Statement Coverage Sequential and concurrent assignments (Number of statement executed) Statement coverage = 100 (Total number of executable statements) 中山大學資工系黃英哲 59

60 Branch Coverage Branch definition Branch not taken If always b=a in test bench 中山大學資工系黃英哲 60

61 Branch coverage (cont.) Calculating branch coverage (Number of branches taken) Branch coverage = 100 (Total no. of possible branches) branch taken 中山大學資工系黃英哲 61

62 Condition Coverage Definition Which expression in condition be executed expression Four types of condition coverage EXPR (Sum-of-Product Expression Coverage) BSC (Basic Sub-condition Coverage) MSC (Multiple Sub-condition Coverage) FEC (Focused Expression Coverage) 中山大學資工系黃英哲 62

63 EXPR Coverage Definition (Verilog only) The combination of value to achieve 100% EXPR: 中山大學資工系黃英哲 63

64 BSC Coverage Definition Sub-expression be both true and false 中山大學資工系黃英哲 64

65 MSC Coverage Definition Explore all sub-condition value combinations Useful on testing infeasible sub-condition 中山大學資工系黃英哲 65

66 FEC Coverage Definition (default for VHDL circuit) testing minimum input combinations which reduced by Boolean expression : 3 inputs need 3+1 tests FEC vector 中山大學資工系黃英哲 66

67 Path Coverage Definition Sequence statements executed in a particular order (combination of sequential branches) 中山大學資工系黃英哲 67

68 Path Coverage (cont.) Infeasible paths Can t achieve 100% path coverage Inefficient logic could be merged into one 中山大學資工系黃英哲 68

69 Toggle Coverage Full toggled At least one rising edge and falling edge 中山大學資工系黃英哲 69

70 Verilog Toggle Type Toggle type Init: Known value at the end Full : 0->[X Z]->1 or 1->[X Z]->0 accepted activity : Only X->0 can start count toggle 中山大學資工系黃英哲 70

71 Triggering Coverage Definition Signals in the sensitivity list Only applied in VHDL 中山大學資工系黃英哲 71

72 Tracing Coverage Trace methodology Signal names file must be supplied Utilizing to error condition detection (deadlock, bus contention) of system Signal names file Contain the signal information we want to trace 中山大學資工系黃英哲 72

73 Tracing Results Tracing example We use Done and LSB for tracing VN-Cover accumulate the count of traced signals 中山大學資工系黃英哲 73

74 FSM Coverage Control functionality State Arc Possible state in FSM Transition between two adjacent states Path A valid sequence of states 中山大學資工系黃英哲 74

75 Path Coverage Automatic recognition Cycle Link Supercycle : basic traverse unit 中山大學資工系黃英哲 75

76 State Machine Properties Preview FSM properties before simulation select the file within FSM State Machine Properties 中山大學資工系黃英哲 76

77 FSM Extraction Preview state machine diagram and state path 中山大學資工系黃英哲 77

78 FSM Path Diagram Use codeview option to display path diagram Tool utilization (page 35 & 36) 中山大學資工系黃英哲 78

traversed Red color : not attached supercycle, and fail traverse

79 State and Arc Analysis Path view information Black color : not attached supercycle Green color : attached supercycle, and be traversed Red color : not attached supercycle, and fail traverse choose the recognized cycle chose cycle will be highlight 中山大學資工系黃英哲 79

80 Verification Flow Verification flow of VN-Cover Set simulator & library Select property option Run simulation View results 中山大學資工系黃英哲 80

81 Simulator Selection We can choose the suitable HDL and whose simulator (Ex: Cadance Verilog-XL) 中山大學資工系黃英哲 81

82 VN-Cover Option Select the Verilog+ to include the top level module 中山大學資工系黃英哲 82

83 HDL Files Loading Code and FSM default value VN-Cover set default options for verification code within FSM 中山大學資工系黃英哲 83

84 Coverage Criteria Select coverage criteria Choose all the module exclude the test module 2. select coverage criteria 1. select files 中山大學資工系黃英哲 84

85 Instrument Instrument HDL files Produce command file (vnavigator.f) for simulation default value 中山大學資工系黃英哲 85

86 Specify Test Bench Verilog HDL Using command file (vnavigator.f) produced at previous step choose command file 中山大學資工系黃英哲 86

87 Simulation Produce results Progress reported in Log window Notice the Note and message in the log window 中山大學資工系黃英哲 87

88 Results Stage Load results files We load the file of simulation result (default: vnavigator.index) 中山大學資工系黃英哲 88

89 Loading Result File Coverage results Blank means no such coverage for analysis Red proportion means the unfilled coverage (not achieve 100%) 中山大學資工系黃英哲 89

90 Results Analysis module hierarchy for code view code classify 中山大學資工系黃英哲 90

91 Code View and Detail Code View Display the coverage belong to statement Choose the coverage in Metrics View can display drawback code in Code View 中山大學資工系黃英哲 91

92 Detail View Coverage information Red line indicate untested situation Coverage = really test / should be test 中山大學資工系黃英哲 92

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untitled Verilog HDL Verilog HDL 邏令列邏路例練數度 (top-down design) 行 (concurrency) 2.1 Verilog HDL (module) 邏 HDL 理 HDL 邏料數邏邏路 module module_name (port_list) // 列 //