VHDL(Statements) (Sequential Statement) (Concurrent Statement) VHDL (Architecture)VHDL (PROCESS)(Sub-program) 2

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1 VHDL (Statements)

2 VHDL(Statements) (Sequential Statement) (Concurrent Statement) VHDL (Architecture)VHDL (PROCESS)(Sub-program) 2

3 (Assignment Statement) (Signal Assignment Statement) (Variable Assignment Statement) : Target <= ; Target := ; 3

4 (PROCESS) (Sub-programs) (PROCESS)(Sub-programs) := <= PROCESS PROCESS (Local) PROCESS (Architecture) (Block) 4

5 Target : MY_VARMY_SIG MY_VEC : MY_VEC(5) : MY_VEC(7 downto 4) Field: My_RECORD.A_FIELD : (MY_SIG1, MY_SIG2) 5

6 Target <= ; = ; 6

7 (Indexed)Target <= ; = ; () (Non-Computable) 7

8 (Sliced)Target <= ; = ; Target (Array) l 2(Computable) todownto 8

9 Field Target Field Target Field <= ; := ; 9

10 (Aggregate) Target (1) : (1 => 1, 2 => 2,..... N => N) <= ; (1 => 1, 2 => 2,..... N => N) := ; (2): (1, 2,, N) <= ; (1, 2,, N) := ; 10

11 (Sequential) v.s (Concurrent) (PROCESS) PROCESS VHDL(Subprogram) PROCESS 11

12 12

13 (PROCESS) (Concurrent Signal Assignment) (Block Statement) (Component Instatiations) (Generate Statement) (Procedure Call) 13

14 VHDL(PROCESS) (FunctionProcedure) (PROCESS) (V ariable Assignment) (Signal Assignment) IF CASE LOOP NEXT EXIT RETURN WAIT NULL 14

15 (Concurrent Signal Assignment) (PROCESS) () (Conditional Signal Assignment) (Selected Signal Assignment) 15

16 (Direct Signal Assignment) <= ; 16

17 (Conditional Signal Assignment) WHEN...ELSE when...else A <= B when () else C; AB AC WHEN...ELSE (Decoder) 17

18 WHEN...ELSE Y <= A when (A) else B when (A) else..... M when (M) else N; Y (Priority)A B... ( N) 18

19 (Selected Signal Assignment) WITH...SELECT...WHEN with...select...whenwith...select...when with select Y <= A when T, B when U,..... N when ; WITH...SELECT...WHEN WHENWHEN (Mutually Exclusive) OTHERS 19

20 PROCESS 1 PROCESSVHDL (Behavior) [:] process [()] {PROCESS} begin {PROCESS()} end process [:]; 20

21 PROCESS 2 PROCESS () PROCESS(Sensitivity List) PROCESS(Evaluate) PROCESSWAITPROCESS WAIT VHDL PROCESS VHDL PROCESS 21

22 PROCESS 3 PROCESS PROCESS (Local Area): USE (Procedures and Functions) 22

23 PROCESS PROCESS WAITIF( EVENT...) IF (Latches) 23

24 IF IF (PROCESS)(Subprograms) 24

25 IF... END IF; if () then {;} end if; (Flip-Flop)(Latch)... process (CLK) begin if (CLK EVENT and CLK= 1 ) then Q <= D; end if; end process; 25

26 IF... ELSE... END IF; if () then {1;} else {2;} end if; (Multiplexer) process (S, A, B) begin if (S = 0 ) then Y <= A; else Y <= B; end if; end process; 26

27 IF ELSIF... ELSE... END IF; if (1) then {1;} elsif (2) then {2;} elsif (3) then {3;} elsif..... else {n;} end if; 27

28 (Nested)IF if (1) then if (2) then {A;} else {B;} end if; else {C;} end if; 28

29 CASE 1 CASE... WHEN (Process)(Subprograms) CASE 29

30 CASE 2 case is when 1 => 1; when 2 => 2;..... when others => N; end case; 11 l 22when others CASE end case; 30

31 LOOP VHDLLOOP VHDLLOOP FOR... LOOP WHILE LOOP LOOP-EXIT 31

32 FOR LOOP for I in ( downto ) loop end loop; for I in ( to ) loop end loop; FOR... LOOPLOOP(Index) FOR... LOOP LOOP for I in ( downto ) loop for I in ( to ) loop 32

33 WHILE-LOOP while loop end loop; end loop; WHILE... LOOP "" "" 33

34 LOOP LOOPLOOP (Iterations) LOOP EXITNEXT LOOP loop end loop; 34

35 NEXT NEXT ( ) next when " " "" 35

36 EXIT VHDLEXIT exit when ""( )"" 36

37 WAIT VHDLWAIT VHDLWAIT WAIT ON : wait on SIG_A, SIG_B; WAIT FOR : wait for 20 ns; WAIT UNTIL () : wait until CLK= 1 ; wait until CLK EVENT and CLK= 1 ; wait until not CLK STABLE and CLK= 1 ; 37

38 NULL NULLVHDL null; NULLCASECASE NULL 38

a b c d e f g C2 C1 2

a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4