Huawei Technologies Co

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费玮桂
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1 Testbench Preliminary itator

2 1 TESTBENCH TESTBENCH Testbench HDL PLI TESTBENCH testbench BFM

3 Testbench_Preliminary Testbench TESTBENCH 1 TESTBENCH TESTBENCH HDL TESTBENCH TESTBENCH 2.1 Testbench module test_bench ; // Testbench always module Testbench NOT U1(. I ( in_ ),. O ( out_ ) ) ; I O in_ out_ 3

4 NOT U2 ( in_, out_ ); in_ out_ NOT HDL HDL HDL CPU / / CPU cs_n = 1 ; // CPU wr_n = 1 ; rd_n = 1 ; addr = 8'hxx ; data = 8'hzz ; # 1000 ; // cs_n = 0 ; wr_n = 0 ; addr = 8'h80 ; data = 8'h00 ; # 100 ; cs_n = 1 ; wr_n = 1 ; 10 addr = 8'hxx ; data = 8'hzz ; 4

5 2.2.2 HDL IP HDLHDL C/C verilog $readmemb/$readmemh verilog memory verilog memory C verilog PLI C C PLI program language interface ) PLI C HDL C HDL PLI C HDL PLI 5

6 2.3 LOG LOG LOG Clk = 0 ; # delay ; forever #(period/2) Clk = ~ Clk ; z z z 2 always Clk = 0 ; always # (period/2) Clk = ~ Clk ; 6

7 3 repeat Clk = 0 ; repeat ( 6 ) #(period/2) Clk = ~ Clk ; repeat % Clk = 0 ; always # 3 Clk = ~ Clk ; # 2 Clk = ~ Clk ; Rst = 1 ; # 100 ; Rst = 0 ; # 500 ; Rst 1 7

8 2 1 Rst = 1 negedge Clk) ; Rst = 0 ; # 30 negedge Clk) ; Rst = 1 ; // // 2 2 Rst = 1 negedge Clk) ; // repeat ( 3 negedge Clk) ; Rst = 1 ; // 3 8

9 3 TESTBENCH TESTBENCH `timescale 1ns/100ps module dec2x4 ( A, B, Enable, Z ) ; input A, B, Enable ; output [3:0] Z ; A or B or Enable ) if ( Enable == 1'b0 ) Z = 4'b1111 ; else case ( A, B ) 2'b00 : Z = 4'b1110 ; 2'b01 : Z = 4'b1101 ; 2'b10 : Z = 4'b1011 ; 2'b11 : Z = 4'b0111 ; default : Z = 4'b1111 case module module testbench ; reg a, b, en ; wire [3:0] z ; // dec2x4 DUT (. A ( a ),. B ( b ),. Enable ( en ),. Z ( z ) 9

10 ); // en = 0 ; a = 0 ; b = 0 ; #10 en = 1 ; #10 b = 1 ; #10 a = 1 ; #10 b = 0 ; #10 a = 0 ; #10 $stop ; // or a or b or z) $display ("At time %t, input is %b%b%b, output is %b", $time, a, b, en, z ) ; module At time 0, input is 000, output is 1111 At time 10, input is 001, output is 1110 At time 20, input is 011, output is 1101 At time 30, input is 111, output is 0111 At time 40, input is 101, output is 1011 At time 50, input is 001, output is module Count3_ls (Data, Clock, Detect3_ls ) ; input Data, Clock; output Detect3_ ls ; integer Count ; 10

11 reg Detect3_1s ; Count = 0; Detect3_ls = 0; Clock) if ( Data == 1) Count = Count + 1; else Count = 0; if (Count >= 3) Detect3_ls = 1 ; else Detect3_ls = 0 ; module module test ; reg Data, Clock, Detect ; integer Out_File ; / / Count3_ls DUT (Data, Clock, Detect ) ; Clock = 0 ; forever #5 Clock = ~ Clock ; Data = 0 ; #5 Data = 1; #40 Data = 0; #10 Data = 1; #40 Data = 0; 11

12 #20 $stop; // // Out_file = $fopen ( "results.txt"); // Clock) if ( Detect == 1'b1 ) $fwrite ( Out_file, "At time %t, Detect out is 1\n"); module 4 testbench testbench testbench testbench harness testcase Testcase Reusable Verification Components Harness Bus Funct. Model DUV Bus Funct. Model RAM harness module testcase testcase harness Testbench 12

13 Testbench testbench 4.1 BFM BFM Bus functional model BFM testcase C++ C++ read() write() Bus Functional Model addr data cs rd wr CPU CPU CPU 13

ebook122-11

ebook122-11 11 (test bench) Verilog HDL 11.1 1) ( ) 2) 3) Verilog HDL module T e s t _ B e n c h; // L o c a l _ r e g _ a n d _ n e t _ d e c l a r a t i o n s G e n e r a t e _ w a v e f o r m s _ u s i n g & s