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1 93 年度路 Xilinx FPGA 類 CAM. 參 CIC FPGA Development Kit( 參錄 A) 來類 CAM 令狀來行料參錄 B 例來參 CIC 參 I/O Response 來參錄 C 了利 FPGA 參參錄 D CIC 路錄行 IC 9: : IC CIC 行了便參參錄 E 列.. CLK RST_ OP Test Bench DIN 6 HIT BANKNO ENTRYNO 3 CAM-like Storage System --

2 不論參 Verilog VHDL module SS 若參 Verilog module SS(HIT, BANKNO, ENTRYNO, OP, DIN, RST_, CLK); input RST_, CLK; input [:] OP; input [5:] DIN; output HIT; output BANKNO; output [:] ENTRYNO; endmodule 若參 VHDL LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY SS IS PORT( HIT :OUT STD_LOGIC; BANKNO :OUT STD_LOGIC; ENTRYNO :OUT STD_LOGIC_VECTOR( DOWNTO ); OP :IN STD_LOGIC_VECTOR( DOWNTO ); DIN :IN STD_LOGIC_VECTOR(5 DOWNTO ); RST :IN STD_LOGIC; CLK :IN STD_LOGIC); END SS; ARCHITECTURE A OF SS IS BEGIN END A; --

3 . / Table I - / Signal Name I/O Width Simple Description CLK I It is the clock of the storage system. RST_ I It resets the storage system when de-asserting (=). DIN I 6 It is the data input of the storage system. OP I The desired operation of the storage system. HIT O It asserts (=) if DIN match any stored data. BANKNO O It outputs the bank index according to the operation and system status. ENTRYNO O 3 It outputs the entry index according to the operation and system status..3 料錄類 CAM (memory bank) 7 8 (memory entry) 6 (bit) 料類 CAM -3-

4 類 CAM 狀 (status) OP (input) 來狀狀兩狀數 (state variable) 來狀數 wentry 錄 (weight) 5 狀數 lock 錄錄狀 (overwrite) 料狀 wbank 狀數 wbank 狀數料 wentry 例 wbank ( ) = 5 類 CAM MATCH WRITE TEST CLEAR 令 ( OP ) 來行行狀狀來落行 (initialization) 說 OP 狀更不更狀更 Table II Table III 參參 Table II Table III 念料 Table II Input Combinations Expected Outputs OP DIN data HIT BANKNO & ENTRYNO MATC HIT case Matched Bank/Entry H MISS case LRU Bank/Entry WRITE Any LRU Bank/Entry TEST HIT case Matched Bank/Entry MISS case UC CLEA HIT case Matched Bank/Entry R MISS case UC. HIT case, MISS case, Matched entry and LRU Entry will be defined later.. UC means the value will be held (the same as the previous value). Table III Input Combinations System Status Stored Data OP DIN wentry lock Stored Data MATC HIT case C C UC H MISS case C UC C WRITE Any C UC C TEST HIT case UC UC UC MISS case UC UC UC CLEA HIT case C C UC R MISS case UC UC UC i. C means the value will be updated according to the specification defined in the following paragraphs while UC means the value will be held (the same as the previous value). -4-

5 料狀數 (wentry lock wbank) 都 MATCH OP: 行 DIN 來料了便說說 : HIT case MISS case : DIN 料錄料若料 HIT case MISS case : Matched Entry Matched Bank : HIT case Matched Entry Matched Bank 若兩料 DIN Matched Entry 若兩 Matched Entry Matched Entry HIT case HIT (assert) ENTRYNO BANKNO Matched Entry Matched Bank MISS case HIT (de-assert) 狀 ENTRYNO BANKNO LRU Entry LRU Bank LRU Entry LRU Bank : LRU Entry LRU Bank : MISS case wbank 狀數 wbank 狀數 LRU Bank 若兩 wbank 狀數 LRU Bank LRU Bank lock 狀數 wentry 狀數 LRU Entry 若兩 wentry 狀數 -5-

6 LRU Entry 狀更 : HIT case wentry 更更 Matched Entry wentry 狀數更 5 更 Matched Bank Matched Entry wentry 狀數更 Matched Bank wentry 狀數不 HIT case lock 更更 Matched Entry lock 狀數更 Matched Entry lock 狀數例 ( 例 ) 7 6 ( 例 )) 更 Matched Bank Matched Entry Matched Entry lock 狀數更 Matched Bank lock 狀數不 MISS case wentry 更更 LRU Entry wentry 狀數更 5 更 LRU Bank LRU Entry wentry 狀數更 LRU Bank wentry 狀數不 MISS case lock 更 lock 狀數不料更 HIT case 料不 MISS case 更 DIN LRU Entry HIT case 例參錄 B 例 MISS case 例 -6-

7 參錄 B 例. WRITE OP: 行 DIN LRU Entry HIT (de-assert) ENTRYNO BANKNO LRU Entry LRU Bank 狀更 WRITE wentry 更更 LRU Entry wentry 狀數更 5 更 LRU Bank LRU Entry wentry 狀數更 LRU Bank wentry 狀數不 WRITE lock 更 lock 狀數不料更更 DIN LRU Entry 例參錄 B 例 3 TEST OP: 行 TEST MATCH 了料說 TEST 狀料都不更 HIT case HIT 狀 ENTRYNO BANKNO Matched Entry Matched Bank ( HIT case MISS case Matched Bank Matched Entry LRU Bank LRU Entry MATCH ) MISS case HIT 狀 ENTRYNO BANKNO 不狀更 TEST wentry 更 -7-

8 wentry 狀數不 TEST lock 更 lock 狀數不料更料不例參錄 B 例 4 5 CLEAR OP: 行 CLEAR MATCH CLEAR 行狀更不行料 CLEAR 狀更 MATCH 更不 CLEAR (reset) Matched Entry 狀數 MATCH 不 HIT case HIT 狀 ENTRYNO BANKNO Matched Entry Matched Bank MISS case HIT 狀 ENTRYNO BANKNO 不狀更 HIT case wentry 更更 Matched Entry wentry 狀數更更 Matched Entry wentry 狀數不 HIT case lock 更更 Matched Entry lock 狀數更更 Matched Entry lock 狀數不 MISS case wentry 更更 wentry 狀數不 MISS case lock 更更 lock 狀數不料更料不例參錄 B 例

9 .4 CLK T cycle RST_ OP DIN OP OP Test Sequence # Test Sequence # DIN DIN HIT BANKNO ENTRYNO T os T oh 3 / Table IV Symbol Description Value T cycle clock period user defined T os T oh setup time (from the time at which output is valid to.5ns the clock rising edge) for all outputs hold time (from the clock rising edge to the time at.5ns which output is invalid) for all outputs / 3 料來參路料了連令料料參路 RST_ 令料 OP DIN 兩更令料令料 CLK (positive edge) HIT BANKNO ENTRYNO 狀料更 3 例來說令 OP 料 DIN 料了 HIT case 狀 Matched Entry -9-

10 Matched Bank 3 CLK 狀料.3 行更.5 FPGA 參參路路了便參錄 D ( 路 ) CIC 路 Synthesis Implementation FPGA 路說 Verilog RTL Code 參錄 D 錄 F 說 --

11 3. 兩參行參錄 E 行參兩行參錄 E 錄行參路 FPGA 來參 FPGA 錄 C (Pass) 不 (Fail) 兩參路路行 RTL code Timing simulation 若參 Pass 參離若參 Fail 行行參 Fail Pass 若參利行離不論律 9: 了離錄離行 RTL simulation timing simulation 率來行 --

12 錄錄 A 說錄 B 錄例錄 C 錄 CIC 料錄 D 路說錄 E 錄參錄 F 路 Verilog Code --

13 錄 A (Table V) 列 Functionality Design Entry Logic Simulator Logic Synthesizer FPGA Implementation Table V Corresponding EDA tools VHDL / Verilog Mentor Graphic ModelSim v5.8e Synplicity Synplify Pro v7.x Xilinx ISE Foundation v6.x ModelSim Synplify Pro 不參利 ModelSim Synplify Pro 來 FPGA Xilinx ISE 來不行 ( 參 3 說 ) -3-

14 錄 B 例例 MATCH operation HIT case DIN 狀料 4 了料了料 HIT case.3 Matched Entry Matched Bank 例 Matched Bank Matched Entry 7 狀料更 5 ( 綠更 )

15 例 MATCH operation MISS case DIN 狀料 6 兩不 5566 料 MISS case.3 例 LRU Bank LRU Entry 3 ( 都 lock 狀 ) 狀料更 7 ( 綠更 )

16 例 3 WRITE operation DIN 狀料 8.3 例 LRU Bank LRU Entry 狀料更 9 ( 綠更 )

17 例 4 TEST operation HIT case DIN 狀料了料了料 HIT case.3 Matched Entry Matched Bank 例 Matched Bank Matched Entry 7 TEST 狀料不 Memory Banks Input ABCD 3456 FFFF DCBA FFF EEFF 5 9 Output ENTRYNO=7 BANKNO= bank index = bank index = entry index wentry lock -7-

18 例 5 TEST operation MISS case DIN 狀料兩不 5566 料 MISS case 狀料不 ( 3) Memory Banks Input ABCD 3456 FFFF DCBA FFF Output ENTRYNO= the previous value BANKNO= the previous value EEFF bank index = bank index = entry index wentry lock

19 例 6 CLEAR operation HIT case DIN 狀料 4 了料了料 HIT case.3 Matched Entry Matched Bank 例 Matched Bank Matched Entry 7 CLEAR 狀更 5 ( 綠更 ) Memory Banks Input ABCD 3456 FFFF DCBA FFF EEFF 5 9 Output ENTRYNO=7 BANKNO= bank index = bank index = entry index wentry lock

20 例 7 CLEAR operation MISS case DIN 狀料 6 兩不 5566 料 MISS case 狀料不 ( 7) Memory Banks Input ABCD 3456 FFFF DCBA FFF EEFF 5 9 Output ENTRYNO= the previous value BANKNO= the previous value bank index = bank index = entry index wentry lock

21 錄 C I/O 參參 FPGA 參利 FPGA 路 FPGA 行 OP DIN HIT BankNo EntryNo Table VI 欄了 FPGA HIT BankNo EntryNo 欄欄 FPGA 來數 3 列 Table VI Input Output OP DIN HIT BankNo EntryNo Seven segment Display AAAA BBBB 列 5 6 AAAA BBBB a CCCC 8888 列 AAAA --

22 BBBB 4444 CCCC 列 AAAA 3333 BBBB AAAA 4444 列 a AAAA 3333 BBBB 4444 CCCC 列 a 列

23 a -3-

24 錄 D 路說 RTL 了路路路 Verilog RTL Code 錄 F 路路行 Synthesis Implementation FPGA 路說 : 8 兩兩兩路了數路數讀料數 Button 數 Button 便數讀料讀料路 test pattern Button 料 Button 路 LED 9 路 RTL FPGA 若 Reset Button Button Top LED [7:] 數 LED [7:] Reset {HIT, BANKNO, ENTRYNO} LED3 [7:] {OP, DIN} 路 LED4 [7:] 8 路 9 FPGA 路 Reset Button 兩 SW SW3 兩 LED LED LED3 LED4 HDA HDB HDA HDB Table III Pin Assignment -4-

25 9 FPGA 路參 FPGA FPGA 參 FPGA (device) I/O 料 (Table VII VIII) Table VII- Target Device Setting Xilinx Target Family Spartan II-E Target Device XCS5E Target Package PQ Pin Count 8 Target Speed grade 6 Table VIII FPGA JP Device HDA_F HDB_F -5-

26 -6-

27 錄 E 參 c:\icc5\score 錄參行參 c:\icc5\score 錄行漏參益律行 ()RTL design 參 RTL code 若 module 來行 ()Post-layout gate-level design FPGA Post-layout gate-level netlist *_timesim.v *_timesim.vh SDF (3)Programming file FPGA 行錄 *.bit (4)report file 參 report.txt 便行 report.txt 8 了 Programming file 路 () () 兩路理 (Table IX) File *.v or *.vhd File *_timesim.v or *_timesim.vhd *.sdf File *.bit Table IX RTL category Description Verilog (or VHDL) synthesizable RTL code Gate-Level category Description Verilog/VHDL gate-level netlist generated by FPGA Development Tool, and SDF file Programming category Description The programming file gerenated by FPGA Development Tool Report category File Description report.txt design report 例來說參 Verilog 切 SS.v Sub.v Sub.v FPGA post-layout gate-level netlist SS_timesim.v SDF SS_timesim.sdf 路錄 Top.bit 參 SS.v Sub.v Sub.v SS_timesim.v SS_timesim.sdf Top.bit report.txt c:\icc5\score 錄 report.txt -7-

28 (Team number): HDL : Verilog RTL : SS.v, Sub.v, Sub.v Post-layout gate-level: SS_timesim.v, SS_timesim.sdf Programming: Top.bit Report: report.txt RTL Top module SS.v ( 參 ) timing simulation clock=mhz (ModelSim). report.txt -8-

29 錄 F 路 Verilog Code //////////////////////////////////////////////////////////////////////////////// // Team number: // Project Name: // Target Device: // Tool versions: // Description: // // Dependencies: // // Revision: // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module top (Rest,Button,LED, LED, LED3, LED4); input Button; input Rest; output [7:] LED, LED, LED3, LED4; wire Button; wire Rest; wire [6:]Cnt_out; wire [7:]Mem_out; wire [:]Entryno; wire [3:]A; wire Hit; wire Bankno; wire [6:] Test_out; assign A[3]=(Hit^Bankno); assign A[]=(Entryno[]); assign A[]=(Entryno[]); assign A[]=(Entryno[]); assign LED = {Test_out, 'b}; -9-

30 assign LED = {Test_out, 'b}; assign LED3 = {Test_out, 'b}; assign LED4 = {Test_out, 'b}; wire clk; IBUF io_buf(.i(button),.o (clk)); SS SS(.CLK(clk),.RST_(Rest),.OP(Mem_out[7:6]),.DIN(Mem_out[5:]),.HIT(Hit),.BANKNO(Bankno),.ENTRYNO(Entryno) ); decoderxx decoder(.a(a),.y(test_out),.button(!clk) ); mem memory(.a(cnt_out),.y(mem_out),.button(!clk) ); cnto Counter(.reset(Rest),.button(!clk),.cnt_out(Cnt_out) ); endmodule -3-

31 //======= memory =======// module mem(a,y,button); //input En; input [4:]A; input Button; output [7:]Y; reg [7:]Y; or A) Button) begin case (A) :Y=8'h_; :Y=8'h_; :Y=8'h_; 3:Y=8'h_; 4:Y=8'h_3; 5:Y=8'h_3; 6:Y=8'h_; 7:Y=8'h_; 8:Y=8'h_5; 9:Y=8'h_5; :Y=8'h_3; :Y=8'h_3; :Y=8'h_6; 3:Y=8'h_6; 4:Y=8'h_7; 5:Y=8'h_7; 6:Y=8'h_8; -3-

32 7:Y=8'h_8; 8:Y=8'h_9; 9:Y=8'h_9; default:y=8'hx; endcase end endmodule //=======7 segment decoder=======// module decoderxx(a,y,button); //input En; input [3:]A; input Button; output [6:]Y; reg [6:]Y; or A) Button) begin // if(!en) // Y=7'b; // else // Y[6]=a; // Y[5]=b; // Y[4]=c; // Y[3]=d; // Y[]=e; // Y[]=f; // Y[]=g; case (A) :Y=7'b_; -3-

33 :Y=7'b_; :Y=7'b_; 3:Y=7'b_; 4:Y=7'b_; 5:Y=7'b_; 6:Y=7'b_; 7:Y=7'b_; 8:Y=7'b_; 9:Y=7'b_; :Y=7'b_; :Y=7'b_; :Y=7'b_; 3:Y=7'b_; 4:Y=7'b_; 5:Y=7'b_; default:y=7'b_; endcase end endmodule //======= counter =======// module cnto(reset,button,cnt_out); input button; input reset; output [4:]cnt_out; reg [4:]cnt_out; button or negedge reset) begin -33-

34 if (!reset) cnt_out<=; else if (cnt_out==5'b) cnt_out<=; else cnt_out<=cnt_out+; end endmodule -34-

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untitled 93 年度路 Altera FPGA 類 CAM. 參 CIC FPGA Development Kit( 參錄 A) 來類 CAM 令狀來行料參錄 B 例來參 CIC 參 I/O Response 來參錄 C 了利 FPGA 參參錄 D CIC 路錄行 IC 9: : IC CIC 行了便參參錄 E 列.. CLK RST_ OP Test Bench