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1 Workshop on Fully Layout Technology Altera Nios XilinxAltera 2002 Workshop on Fully Layout Technology IT % 2 IC 8.6% IC IC Feb

2 250 IC IC IC IC Fully Layout RF GHz Prototyping and Layout Consortium P&L IEEE CAS IC IC IC ( ) :30~12:00 Fully Layout Engineering Deputy Department Manager 13:00~15:00 Practice for Mixed Signal Layout Manager 91/3/23 15:30~17:30 The Art of Analog Layout President 17:30~18:00 Q&A Layout & Tooling Service Department Layout Engineering Department array@cic.edu.tw 2 Feb 2002

3 C C NEW S 16 Altera Nios 8051 PIC TIDSP SoC(System on Chip) SoC ( icroprocessor) DSP I/O (Mixed-Signal Blocks ) IP Design Reuse ASIC FPGA DesignReuse Time-To-Market FPGA (Embedded Programmable) SoPC(System on apogrammable Chip) ALTERA Excalibur SoPC (Soft Core) NIOS Processor (Hard Core) MIPS ProcessorARM Processor Altera APEX Soft Core APEX Hard Core ALTERA Embedded Processor NIOS ALTERAExcalibur Nios Altera-Nios Soft Core APEX 20KE ACEX Flex10K Mercury APEXII Embedded NIOS Processor Feb

4 Embedded MPU Black Box Instantiate Design Mega-Function Design Nios Soft core QuartusII SoPC NIOS System Builder Embedded Netlist file Mega-Wizard Altera Excalibur Nios AHDL VHDL Verilog HDL QuartusII SoPC NIOS System Builder (1) 16-Bit 32-Bit (2) Nios CPU Address BusSize (3) Internal Register File Size Register File Size Internal Register File ESB(Embedded System Block) (4) Internal Shifter Speed Multiply-Step Unit (5) Finish NIOS (Peripherals) NIOS NIOS NIOS Embedded NIOSProcessor / NIOS clk;irq_from_the_peripheral;data_to_cpu_from_the_peripheral;address_to_the_ peripheral; cpu_be_n_to_the_peripheral;cpu_read_n_to_the_peripheral;cpu_write_n_to_the _peripheral;data_from_cpu_to_the_peripheral;select_to_the_peripheral NIOS 4 Feb 2002

5 C C NEW S 16 (Peripherals) Add NewPerpheral to system Module Inside NIOS system module Embedded Processor NIOS (1)Memory Mapped Peripheral On-Chip/Off-Chip Port Data Bus WidthAddress WidthWait State IRQ (2) Memory-Interface On-Chip Dedicated Buses Off-Chip Shared Buses Data & Address Buses Width Read/Write Wait State Internal/Peripheral IRQ Alignment Base Address (3) UART (Serial Port ) Input Clock Baud Rate Parity BitData BitsStop Bits Alignment Base Address IRQ (4)ParallelI/O 1-32bit PinState(Input Only/Output Only/Tri-State) Edge Detection (Rising/Falling/Any Edge) Interrupt Source(Level/Edge) IRQ (5)Interval Timer 2 16Bit Registers Timer IRQ (6) On-Chip ROM Size Include User MIF AlignmentBase Address (7)On-Chip RAM Width Size (8)Generate Feb

6 NIOS EmbeddedProcessor Quartus Nios MPU Core Peripherals User NIOS System module "Add New Perpheral to system Module" "Outside NIOS system module" 6 Feb 2002

7 C C NEW S 16 (1) Outside Nios System Module User define Interface (2) Data Bus Type(separate or tri-state databus) (3) data bus address bus width (4)Setup time Hold time (5) system bus wait states peripheral drives wait signal (6) base address Generate NIOSSystem Feb

8 SoPC System Builder Nios soft core Netlist file Peripheral HDL source file simulation testbanch file C Header files Peripheral Drivers Custom Library ALTERA ALTERA Generates: Hardware:HDLSource& Netlist Software:CustomLibrary Simulation:Testbench Library source file Memory mapping fileheader file C NIOS C QuartusII C QuartusII C Gnupro Compiler tool Debug tool C Gnupro Bash Shell Srec2flash.Srec.flash External Memory.Mif (Memory Initialize file) Demo-BroadSerial PortCom1/Com2 Serial Port DownloadFPGA On-Chip RAM Nios FPGA 8 Feb 2002

9 C C NEW S 16 Gnupro Bash Shell Monitor Program (1)Nios-Run P Com1 T: Demo-Broad Com1 (2)Nios-Build user_program.c: user_program.c user_program.srec (3)Nios-Run User_Program.srec: User_Program.srec (4)Nios-Runt: Terminal Mode GERMs Bash Shell window GERMs Altera NRE NIOS ALTERA Excalibur steven@cic.edu.tw Feb

10 91.2 () Full-Custom IC Cell-Based ICRF/MM ICMixed-Signal IC IC Testing FPGA )!! US$1=NT$38 (... ). / license 909 Synopsys Altera Xilinx Synopsys Avant! HSPICETCADSynTest Synplify Pro Feb 2002

11 C C NEW S AnsoftCADENCE Debussy DiALOG Mentor SBTSPICE Tanner XilinxAltera Xilinx MAC address hostid (license file) / (license server) license.. Xilinx license Xilinx Synopsys Avant! HSPICE license Xilinx FPGA / license / Xilinx 1200 Foundation Elite/ISE 4.1i 1200 license / // / / 200 Foundation3.1i Xilinx 91 Xilinx Altera maggie@cic.edu.tw Feb

12 Workshop onmulti-projectchips Mixed-signal Analog IC Digital IC RF IC Silicon GaAs 91 GaAs 12 Feb 2002 :91/04/11 : / / : :00-09:30 09:00-09:30 09:30-10:10 Oral1(RF Scope) 09:30-10:10 Oral1(Digital Scope) 10:10-10:30 Break 10:10-10:30 Break 10:30-11:10 Oral2(RF Scope) 10:30-11:10 Oral2(Digital Scope) 11:10-11:50 Oral3(RF Scope) 11:10-11:50 Oral3(Digital Scope) 11:50-13:30 Lunch 11:50-13:30 Lunch 13:30-14:50 GaAs (1) 13:30-14:10 Oral1(Analog Scope) 14:10-14:50 Oral2(Analog Scope) 14:50-15:10 Break 14:50-15:10 Break 15:10-16:30 GaAs (2) 15:10-15:50 Oral3(Analog Scope) 15:50-16:30 Oral4(Analog Scope) 1. 10:30-11:30 ( / / )

13 C C NEW S 16 / Advanced Technology Consortium ADV System-on-Chip Consortium SOC Electronic Design Automation Consortium EDA Digital IP Consortium DIP Mixed Signal Consortium MSD Prototyping and Layout Consortium P&L top-down ADV VLSI ADV VLSI ADV ADV Feb

14 : IC / IP SOC Feb 2002

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untitled niosii H:\DB2005\project\niosDK\Example\NiosSmall QuartusII4.2 File -> New Project Wizard Diectory,Name,Top-Level Entity Add Files EDA Tools Setting Finish, OK H:\DB2005\project\niosDK\Example\NiosSmall