D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK =

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伟灰仰
5 years ago
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1 VHDL (Sequential Logic)

2 D-Type entity D_FF is D :in std_logic; CLK :in std_logic; Q :out std_logic); end D_FF; architecture a of D_FF is process(clk,d) if CLK'EVENT and CLK = '1' then Q <= D; 2

3 D-Type entity DFF_SR is nrst :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_SR; architecture a of DFF_SR is process(nrst,clk,d) if CLK'EVENT and CLK = '1' then if nrst = '0' then Q <= '0'; else Q <= D; 3

4 D-Type entity DFF_AR is nrst :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_AR; architecture a of DFF_AR is process(nrst,clk,d) if nrst = '0' then Q <= '0'; elsif CLK'EVENT and CLK = '1' then Q <= D; 4

5 D-Type entity DFF_PR is nrst :in std_logic; npreset :in std_logic; CLK :in std_logic; D :in std_logic; Q :out std_logic); end DFF_PR; architecture a of DFF_PR is process(nrst,npreset,clk,d) if nrst = '0' then Q <= '0'; elsif npreset = '0' then Q <= '1'; elsif CLK'EVENT and CLK = '1' then Q <= D; 5

6 RS-Type entity RS_FF is nrst :in std_logic; nset :in std_logic; Q :out std_logic; nq :out std_logic); end RS_FF; architecture a of RS_FF is signal Q_S: std_logic; signal nq_s: std_logic; Q_S <= nrst nand nq_s; nq_s <= nset nand Q_S; Q <= Q_S; nq <= nq_s; 6

7 (Negative Level) entity LATCH is nena :in std_logic; D :in std_logic; Q :out std_logic); end LATCH; architecture a of LATCH is signal Q_S: std_logic; process(nena,d) if nena = '0' then Q_S <= D; else Q_S <= Q_S; Q <= Q_S; 7

8 T- entity TFF is T :in std_logic; CLK :in std_logic; Q_O :out std_logic); end TFF; architecture a of TFF is signal Q: std_logic; process(clk,t) if CLK'EVENT and CLK = '1' then if T = '1' then Q <= not(q); else Q <= Q; Q_O <= Q; 8

9 2 entity DIV2 is CLK_IN :in std_logic; CLK_OUT :out std_logic); end DIV2; architecture a of DIV2 is signal CLK_2: std_logic; process(clk_in) if CLK_IN'EVENT and CLK_IN = '1' then CLK_2 <= not(clk_2); CLK_OUT <= CLK_2; 9

10 D- entity DFF_ena is D :in std_logic; CLK :in std_logic; Enable :in std_logic; Q :out std_logic); end DFF_ena; architecture a of DFF_ena is process(clk,d) if CLK'EVENT and CLK = '1' then if Enable = '1' then Q <= D; 10

11 entity SFT_PIPO is D_IN 0); CLK :in std_logic_vector(7 downto :in std_logic; :out std_logic_vector(7 downto D_OUT 0)); end SFT_PIPO; architecture a of SFT_PIPO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q <= D_IN; D_OUT <= Q; 11

12 entity SFT_PISO is D_IN :in std_logic_vector(7 downto 0); CLK :in std_logic; nload :in std_logic; D_OUT :out std_logic); end SFT_PISO; architecture a of SFT_PISO is signal Q: std_logic_vector(7 downto 0); process(nload,clk) if nload = '0' then Q <= D_IN; elsif CLK'EVENT and CLK = '1' then for I in 7 downto 1 loop Q(I-1) <= Q(I); end loop; process(nload,clk) if nload = '0' then D_OUT <= '0'; elsif CLK'EVENT and CLK = '1' then D_OUT <= Q(0); 12

13 / (Serial- In/Parallel-Out) entity SFT_SIPO is D_IN :in std_logic; CLK :in std_logic; D_OUT :out std_logic_vector(7 downto 0)); end SFT_SIPO; architecture a of SFT_SIPO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q(0) <= D_IN; for I in 1 to 7 loop Q(I) <= Q(I-1); end loop; D_OUT <= Q; 13

14 / (Serial- In/Serial-Out) entity SFT_SISO is D_IN :in std_logic; CLK :in std_logic; D_OUT :out std_logic); end SFT_SISO; architecture a of SFT_SISO is signal Q: std_logic_vector(7 downto 0); process(clk) if CLK'EVENT and CLK = '1' then Q(0) <= D_IN; for I in 1 to 7 loop Q(I) <= Q(I-1); end loop; D_OUT <= Q(7); 14

15 8 (Ripple Counter) entity rip_cnt8 is nclr :in std_logic; 0)); end rip_cnt8; architecture a of rip_cnt8 is component DIV2_AR CLK :in std_logic; Q_O :out std_logic_vector(7 downto CLK_IN :in std_logic; nclr :in std_logic; CLK_OUT :out std_logic); end component; signal Q: std_logic_vector(7 downto 0); FF1: DIV2_AR port map (CLK,nCLR,Q(0)); FF2_8: for I in 1 to 7 generate T1: DIV2_AR port map (Q(I-1),nCLR,Q(I)); end generate FF2_8; Q_O <= Q; 15

16 (Up Counter) use ieee.std_logic_unsigned.all; entity UPCNT8 is nclr :in std_logic; CLK :in std_logic; CO :out std_logic; Q_O :out std_logic_vector(7 downto 0)); end UPCNT8; architecture a of UPCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= " "; CO <= '0'; elsif CLK'EVENT and CLK = '1' then if Q = " " then CO <= '1'; else CO <= '0'; Q <= Q + '1'; Q_O <= Q; 16

17 (Up/Down Counter) use ieee.std_logic_unsigned.all; entity UPDNCNT8 is nclr :in std_logic; CLK :in std_logic; UP_DN :in std_logic; --'1':Up Counter;'0':Down Counter; Q_O :out std_logic_vector(7 downto 0)); end UPDNCNT8; architecture a of UPDNCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= " "; elsif CLK'EVENT and CLK = '1' then if UP_DN = '1' then Q <= Q + '1'; else Q <= Q - '1'; Q_O <= Q; 17

18 / (UD/Down Counter With Load) use ieee.std_logic_unsigned.all; entity UDLCNT8 is nclr :in std_logic; CLK :in std_logic; UP_DN :in std_logic; --'1':Up Counter;'0':Down Counter; nload :in std_logic; --Asychronous Load Data; D_IN : in std_logic_vector(7 downto 0); Q_O :out std_logic_vector(7 downto 0)); end UDLCNT8; architecture a of UDLCNT8 is signal Q: std_logic_vector(7 downto 0); process(nclr,clk) if nclr = '0' then Q <= " "; elsif nload = '0' then Q <= D_IN; elsif CLK'EVENT and CLK = '1' then if UP_DN = '1' then Q <= Q + '1'; else Q <= Q - '1'; Q_O <= Q; 18

19 (State Machine) (Finite State Machine FSM) 2 Moore Mealy Mealy (Glitch) 19

20 20

21 type STATE_TYPE is (State_A, State_B, ); signal Present_State: STATE_TYPE; signal Next_State: STATE_TYPE; 21

22 VHDL PROCESS PROCESS : PROCESS PROCESS : PROCESS PROCESS PROCESS PROCESS : PROCESS PROCESS PROCESS 22

23 Moore 23

24 Mealy 24

25 (State Encoding) One-Hot Gray S S S S

26 26

27 GEN 27

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29 29

B 6 A A N A S A +V B B B +V 2

B 6 A A N A S A +V B B B +V 2 V A A B B 3 C Vcc FT7 B B 1 C 1 V cc C 2 B 2 G G B 3 C 3V cc C B ND ND GND V A A B B C 1 C 3 C 2 C V cc V cc V 220Ωx B 1 B 2 B 3 B GND GND A B A B 1 1 0 0 0 2 0 1 0 0 3 0