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1 EDA VHDL

2 VHDL VHDL EDA VHDL FPGA 11 VHDL EDA 12 VHDL 13 VHDL 14 VHDL 12 VHDL 13 EDA / VHDL EDA VHDL : ( ) : : : : / : : : ISBN /TP 172 : : 25.00

3 VLSI 1 EDA Electronic Design Automation ASIC SOC System On a Chip EDA VLSI FPGA CPLD Xilinx Altera FPGA/CPLD FPGA GAL Lattice PLD/CPLD ISP CPLD 23% Cadence Data I/O Mentor Graphics OrCAD Synopsys Viewlogic EDA EDA CAD CAM CAT CAE EDA ESDA Electronic System Design Automation EDA EDA VHDL FPGA CPLD EDA VHDL IEEE EDA EDA EDA VHDL VHDL EDA ASIC IP Intelligence Property Core

4 EDA EDA VHDL VHDL VHDL EDA VHDL 1 VHDL 2 VHDL VHDL 3 VHDL 1 VHDL PC VHDL EDA VHDL / EDA VHDL VHDL / EDA span88@mail.hz.zj.cn / Hjwang@uestc.edu..cn

5 EDA VHDL VHDL EDA FPGA/CPLD VHDL VHDL VHDL VHDL VHDL ENTITY ARCHITECTURE BLOCK PROCESS (SUBPROGRAM) FUNCTION OVERLOADED FUNCTION PROCEDURE OVERLOADED PROCEDURE LIBRARY PACKAGE CONFIGURATION VHDL VHDL VHDL (VARIABLE) (SIGNAL) (CONSTANT) VHDL VHDL IEEE

6 VHDL VHDL IF CASE LOOP NEXT EXIT WAIT (RETURN) (NULL) (ATTRIBUTE) (TEXTIO) ASSERT REPORT VHDL

7 VHDL VHDL δ VHDL VHDL VHDL FSM FPGA

8 FIR FIR FIR FIR FIR IIR IIR IIR VHDL ispvhdl isplsi ispvhdl ispvhdl Altera MAX+plus II VHDL MAX+plus II Synplify Xilinx Foundation VHDL Foundation VHDL VHDL SRAM

9 RS PC FPGA VGA A/D D/A MCS-51 CPLD PS/ LED VHDL GW48 EDA FPGA CPLD

10 1 1 1 SSI MCU SSI MCU SSI FPGA/CPLD / EDA MCU MCU FPGA/CPLD MCU EDA FPGA/CPLD MCU MPU DSP A/D D/A RAM ROM / IP CPLD FPGA EDA 1.1 EDA 8255

11 2 VHDL PLD EDA TTL EDA EDA Electronic Design Automation 90 CAD CAM CAT CAE EDA EDA HDL EDA EDA EDA CPLD/FPGA EDA CPLD/FPGA EDA EDA PCB VHDL Verilog HDL ABEL-HDL EDA CPLD FPGA EDA EDA SOC

12 1 VHDL VHDL VHDL Very-High-Speed Integrated Circuit Hardware Description Language VHDL IEEE The Institute of Electrical and Electronics Engineers IEEE-1076 IEEE VHDL EDA VHDL VHDL VHDL 1993 IEEE VHDL VHDL VHDL IEEE VHDL Verilog IEEE EDA VHDL Verilog 1 VHDL VHDL VHDL VHDL ( ) VHDL VHDL h VHDL EDA VHDL VHDL FPGA CPLD h VHDL VHDL h VHDL VHDL

13 4 VHDL h VHDL EDA VHDL EDA VHDL h VHDL VHDL VHDL CPLD FPGA h VHDL 2 VHDL Verilog ABEL RTL VHDL RTL Verilog RTL RTL VHDL RTL Verilog RTL Verilog VHDL FPGA/CPLD ASIC VHDL Verilog ASIC VHDL Verilog VHDL Verilog Verilog VHDL Verilog VHDL VHDL Verilog VHDL VHDL VHDL Verilog Verilog VHDL Verilog EDA VHDL Verilog VHDL Verilog

14 1 EDA ABEL Verilog ABEL HDL ABEL Verilog Verilog EDA ABEL PLD ABEL-HDL HDL ABEL-HDL DOS ABEL3.0 GAL Lattice ispexpert DATAIO Synario Vantis Design-Direct Xilinx FOUNDATION WEBPACK EDA ABEL-HDL FPGA/CPLD ABEL-HDL ABEL-HDL VHDL Verilog-HDL VHDL Verilog-HDL ABEL-HDL DOS Windows PLD EDA ABEL-HDL ABEL-HDL EDA DATAIO Internet ABEL EDA TOP-TO-DOWN VHDL VHDL VHDL VHDL MCU RAM ROM FPGA ASIC EDA VHDL 1

15 6 VHDL 2 IP 3 4 EDA IP Core VHDL IP VHDL 1.4 VHDL EDA VHDL VHDL EDA 1-1 VHDL VHDL 1-1 VHDL VHDL EDA VHDL EDA IC FPGA CPLD 1-1 FPGA CPLD VHDL VHDL EDA VHDL EDA VHDL EDA / EDA

16 1 PROTEL VHDL VHDL EDA VHDL StateCAD Renoir Active-FSM VHDL VHDL VHDL DEA VHDL VHDL VHDL VHDL VHDL VHDL

17 8 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL EDIF/XNF VHDL VHDL VHDL VHDL 1-1 VHDL Netlist EDIF Xilinx XNF Xilinx FPGA/CPLD XNF VHDL VHDL VHDL VHDL EDIF/XNF FPGA CPLD VHDL VHDL VHDL / FPGA/CPLD / / FPGA CPLD 1-1 Hardware Debug VHDL VHDL VHDL VHDL VHDL VHDL

18 1 VHDL VHDL ASIC ASIC FPGA VHDL ASIC FPGA CPLD VHDL VHDL VHDL EDA CAD PROTEL PSPICE EWB POWERPCB EDA EDA EDA PROTEL PSPICE EWB POWERPCB HDL EDA FPGA/CPLD ASIC JEDEC FPGA/CPLD EDA Lattice PAC-DESIGNER EDA EDA FPGA/CPLD EEPROM PLCC TQFP PQFP BGA Lattice ISP In-System Programmability PLD

19 10 VHDL ISP 4 5 PLD ISP PC ISP ISP CPLD/FPGA ISP ISP EDA 1.6 FPGA/CPLD FPGA/CPLD MCU PC CPLD/FPGA FPGA/CPLD EDA FPGA/CPLD TI ASIC 80% IP CPLD/FPGA IP ASIC FPGA/CPLD VHDL ASIC 11 VHDL FPGA/CPLD 1.7 VHDL C VHDL VHDL VHDL

20 1 CPU CPU CPU CPU VHDL VHDL VHDL VHDL VHDL ADA ADA VHDL VHDL VHDL VHDL VHDL RTL VHDL CPU VHDL VHDL VHDL

21 12 VHDL 2 VHDL VHDL 2.1 VHDL a b s y y b s 0 y a s 1 VHDL 2-1 LIBRARY IEEE; IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS mux21 PORT ( a b : IN STD_LOGIC; PORT s : IN STD_LOGIC; y : OUT STD_LOGIC ); END ENTITY mux21; mux21 ARCHITECTURE one OF mux21 IS y <= a WHEN s = '0' ELSE b WHEN s = '1' ; END ARCHITECTURE one; 2 1 VHDL VHDL EDIF ALTERA EPM7128S 2-1 EPM7128S mux21

22 2 VHDL 13 HARDWARE DEBUG EDA MUX+PLUSII( 12 ) VHDL mux21 4 a b s y MUX+PLUSII 2-1 FPGA CPLD mux VHDL VHDL (1) (LIBRARY) IEEE STD_LOGIC_1164 VHDL VHDL (2) (ENTITY) mux21 mux21 a b s y PORT mux21 PORT IN a b a b OUT y a b s y IEEE STD_LOGIC_1164 STD_LOGIC (3) (ARCHITECTURE) mux21 <= y <= a a ( )y 2-1 END ENTITY mux21 END ARCHITECTURE one VHDL IEEE STD 1076_1993 VHDL 87 IEEE STD 1076_1987 END mux21 END one EDA VHDL VHDL'87 VHDL VHDL 87 VHDL VHDL IEEE

23 14 VHDL 2-1 VHDL VHDL VHDL 2-1 VHDL VHDL VHDL VHDL HDL 2 1 VHDL 2-2 D ENA ENA Q 2-2 VHDL 2-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Latch IS PORT D : IN STD_LOGIC; ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); 1 END ENTITY Latch ARCHITECTURE one OF Latch IS SIGNAL sig_save : STD_LOGIC; PROCESS (D, ENA) IF ENA = '1' THEN sig_save <= D ; END IF ; Q <= sig_save ; END PROCESS ; END ARCHITECTURE one; (1) SIGNAL SIGNAL sig_save

24 2 VHDL 15 D (2) PROCESS (D, ENA) END PROCESS D ENA (VHDL ) ENA D sig_save sig_save Q ENA sig_save Q IF_THEN VHDL IF sig_save <= D END IF IF_THEN PROCESS VHDL VHDL PROCESS(D ENA) (D ENA) D ENA ( ) ( ) VHDL VHDL VHDL ABEL COM REG 2.2 VHDL a b 2-3 so 1 co h_adder f_adder 3 u1 u2 u3 2-3 VHDL 2-4 VHDL EDA

25 16 VHDL LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 IS PORT (a,b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2 ARCHITECTURE fu1 OF or2 IS c <= a OR b ; END ARCHITECTURE fu1; -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT (a b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY h_adder ARCHITECTURE fh1 OF h_adder IS so <= (a OR b)and(a NAND b); co <= NOT( a NAND b); END ARCHITECTURE fh1; --1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT ( ain bin cin : IN STD_LOGIC; cout sum : OUT STD_LOGIC ); END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS COMPONENT h_adder PORT ( a b : IN STD_LOGIC; co so : OUT STD_LOGIC); END COMPONENT COMPONENT or2 PORT (a b : IN STD_LOGIC; c : OUT STD_LOGIC); END COMPONENT SIGNAL d e f : STD_LOGIC; u1 : h_adder PORT MAP( a =>ain b =>bin co=>d so =>e); u2 : h_adder PORT MAP( a =>e b =>cin co =>f so =>sum); u3 : or2 PORT MAP(a =>d b =>f c =>cout); END ARCHITECTURE fd1 ;, 2-3 EDA VHDL 2 f_adder VHDL or2.vhd h_adder.vhd f_adder.vhd 2-3 (1) -- VHDL -- (2) or2 or2 a b ( ) c ( )

26 2 VHDL 17 a b c (3) h_adder fh1 2-3 ( 2-1) VHDL NAND NOT OR AND (4) VHDL f_adder ain bin cin cout sum 1 fd1 COMPONENT COMPONENT or2 h_adder H_ADDER a B so co F_ADDER ain Bin cin Cout sum (5) fd1 COMPONENT END COMPONENT (Component Declaration) SIGNAL

27 18 VHDL d e f PORT MAP( ) (Component Instantiation) MAP u2 h_adder a b co so e cin f sum => (6) 2-3 f_adder IEEE IEEE.STD_LOGIC_1164.ALL VHDL VHDL VHDL 2-5 WORK VHDL VHDL ENTITY ARCHITECTURE CONFIGURATION 2-5 VHDL

28 3 VHDL 19 3 VHDL VHDL VHDL VHDL VHDL 2-5 VHDL VHDL ENTITY ARCHITECTURE VHDL VHDL VHDL LIBRARY PACKAGE VHDL 2-5 CONFIGURATION VHDL 3.1 ENTITY

29 20 VHDL VHDL 1. ENTITY IS [GENERIC ( ) ] [PORT ( ) ] END ENTITY ENTITY IS END ENTITY VHDL VHDL VHDL END ENTITY nand nand COMPONENT h_adder -- PORT ( a b : IN STD_LOGIC ; co so : OUT STD_LOGIC ); END COMPONENT;... u1 : h_adder PORT MAP ( a =>ain b =>bin co=>d so =>e) => h_adder 2-3 EDA VHDL MAX+PLUSII h_adder.vhd VHDL

30 3. GENERIC 3 VHDL 21 GENERIC GENERIC([ [ : ] { [ : ] } ) GENERIC PORT GENERIC INTEGER TIME VHDL ENTITY mcu1 IS GENERIC (addrwidth : INTEGER := 16); PORT( add_bus : OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0) );... GENERIC mcu1 add_bus add_bus 16 addrwidth INTEGER addrwidth 1 15 PORT (add_bus : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)); 3-2 addrwidth 3-3 2

31 22 VHDL ENTITY PGAND2 IS GENERIC ( trise : TIME := 1 ns; tfall : TIME := 1 ns ) ; PORT ( a1 : IN STD_LOGIC ; a0 : IN STD_LOGIC ; z0 : OUT STD_LOGIC ); END ENTITY PGAND2; 2 trise tfall 1ns n 3-2 n 3-5 GENERIC MAP ( ) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY andn IS GENERIC ( n : INTEGER ); PORT(a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); c : OUT STD_LOGIC); END; ARCHITECTURE behav OF andn IS PROCESS (a) VARIABLE int : STD_LOGIC; int := '1'; FOR i IN a'length - 1 DOWNTO 0 LOOP IF a(i)='0' THEN int := '0'; END IF; END LOOP; c <=int ; END PROCESS; END; 3-5 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY exn IS PORT(d1,d2,d3,d4,d5,d6,d7 : IN STD_LOGIC; q1,q2 : OUT STD_LOGIC); END; ARCHITECTURE exn_behav OF exn IS COMPONENT andn GENERIC ( n : INTEGER); PORT(a: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); c: OUT STD_LOGIC); END COMPONENT ; u1: andn GENERIC MAP (n =>2) PORT MAP (a(0)=>d1,a(1)=>d2,c=>q1);

32 3 VHDL u2: andn GENERIC MAP (n =>5) PORT MAP (a(0)=>d3,a(1)=>d4,a(2)=>d5, a(3)=>d6,a(4)=>d7, c=>q2); END; PORT PORT MODE TYPE LIBRARY USE PORT ( : { : } ) ; VHDL nand2 a c b nand LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nand2 IS PORT(a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END nand2 ; nand2 a b c IEEE 1076

33 24 VHDL hin IN Variable Signal hout OUT hinout INOUT INOUT IN OUT BUFFER 3-7 MCS51 P0 INOUT P0 hbuffer BUFFER ENTITY MCS51 IS PORT ( : P0 : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- / P2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8 RD WR : IN STD_LOGIC; END MCS51;... PROCESS( WR_ENABLE2 ) IF WR_ENABLE2'EVENT AND WR_ENABLE2 = '1' THEN LATCH_OUT2 <= P0; END IF; -- P0 END PROCESS; PROCESS( P2,LATCH_ADDRES,READY,RD ) IF (LATCH_ADDRES=" ") AND (P2=" ") AND (READY='1') AND (RD='0') THEN P0 <= LATCH_IN1 ; -- P0, P0 ELSE P0 <= "ZZZZZZZZ" ; END IF -- P0 END PROCESS;... BUFFER OUT, INOUT BUFFER BUFFER 3-8 SIGNAL 3-9

34 3 VHDL BUFFER 3-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY bfexp IS PORT( clk,rst,din : IN STD_LOGIC ; q1 : BUFFER STD_LOGIC ; q2 : OUT STD_LOGIC ) ; END bfexp ; ARCHITECTURE behav1 OF bfexp IS PROCESS(clk,rst) IF rst ='0' THEN q1 <= '0' ; q2 <= '0' ; ELSIF clk'event AND clk = '1' THEN q1 <= din ; -- din q1 q2 <= q1 ; -- q1, q2 END IF; END PROCESS; END; 3-9 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY bfexp IS PORT(clk,rst,din : IN STD_LOGIC ; q1 : OUT STD_LOGIC ; q2 : OUT STD_LOGIC ) ; END bfexp ; ARCHITECTURE behav1 OF bfexp IS SIGNAL qbuf : STD_LOGIC; -- qbuf PROCESS(clk,rst) IF rst ='0' THEN qbuf <= '0' ; q2 <= '0' ; ELSIF clk'event AND clk = '1' THEN qbuf <= din ; -- din qbuf q2 <= qbuf ; -- qbuf q2 END IF; q1 <= qbuf; -- qbuf q1, END PROCESS; END; IN OUT BUFFER TRI INOUT 25

35 26 VHDL BIDIR OUT IN OUT BUFFER INOUT BIT BIT_VECTOR BIT a0 a1 z0 STD_LOGIC IEEE STD_LOGIC_1164 BIT BIT_VECTOR 3-2 add_bus add_bus STD_LOGIC_VECTOR IEEE STD_LOGIC_ ARCHITECTURE 2-5 / h h h 2-3 CONFIGURATION

36 3 VHDL ARCHITECTURE OF IS [ ] [ ] END ARCHITECTURE ; ARCHITECTURE END ARCHITECTURE 2-2 Latch one sig_save STD_LOGIC (SIGNAL) (TYPE) (CONSTANT) (COMPONENT) (FUNCTION) (PROCEDURE) h h h

37 28 VHDL h h ARCHITECTURE BLOCK PROCESS PGAND2 behav a0 a1 z0

38 3 VHDL 3-10 ARCHITECTURE behav OF PGAND2 IS PROCESS (a1 a0) VARIABLE zdf : STD_LOGIC ; zdf := a1 AND a0 ; -- IF zdf ='1' THEN z0 <= TRANSPORT zdf AFTER trise ; ELSIF zdf ='0' THEN z0 <= TRANSPORT zdf AFTER tfall ; ELSE z0 <= TRANSPORT zdf ; END IF ; END PROCESS ; END ARCHITECTURE behav ; 29 VHDL AFTER tfall 3.3 BLOCK BLOCK PROTEL98 BLOCK BLOCK BLOCK VHDL BLOCK BLOCK BLOCK 1. BLOCK BLOCK BLOCK [ ]

39 30 VHDL END BLOCK BLOCK BLOCK END BLOCK PORT GENERIC PORT MAP GENERIC MAP BLOCK BLOCK BLOCK h USE h h h h h h BLOCK BLOCK 2. BLOCK BLOCK BLOCK BLOCK BLOCK BLOCK 3-11 BLOCK 3-12 BLOCK VHDL ENTITY gat IS GENERIC(l_time : TIME ; s_time : TIME ) ; -- PORT (b1, b2, b3 : INOUT BIT) ; -- END ENTITY gat ; ARCHITECTURE func OF gat IS SIGNAL a1 : BIT ; -- a1 Blk1 : BLOCK -- blk1 GENERIC (gb1, gb2 : Time) ; -- GENERIC MAP (gb1 => l_time,gb2 => s_time) ; --

40 3 VHDL 31 PORT (pb : IN BIT; pb2 : INOUT BIT ); -- PORT MAP (pb1 => b1, pb2 => a1 ) ; -- CONSTANT delay : Time := 1 ms ; -- SIGNAL s1 : BIT ; -- s1 <= pb1 AFTER delay ; pb2 <= s1 AFTER gb1, b1 AFTER gb2 ; END BLOCK blk1 ; END ARCHITECTURE func ; 3-11 BLOCK b1 : BLOCK SIGNAL s1: BIT ; S1 <= a AND b ; b2 : BLOCK SIGNAL s2: BIT ; s2 <= c AND d ; b3 : BLOCK Z <= s2 ; END BLOCK b3 ; END BLOCK b2 ; y <= s1 ; END BLOCK b1 ; BLOCK VHDL BLOCK a1 : out1 <= '1' after 3 ns ; blk1 : BLOCK A2 : out2 <= '1' AFTER 3 ns ; A3 : out3 <= '0' AFTER 2 ns ; END BLOCK blk1 ; 3-14 a1 : out1 <= '1' AFTER 3 ns ; a2 : out2 <= '1' AFTER 3 ns ; a3 : out3 <= '0' AFTER 2 ns ;

41 32 VHDL VHDL BLOCK GUARDED BLOCK BLOCK BLOCK VHDL COMPONENT INSTANTIATION 3.4 PROCESS PROCESS VHDL PROCESS PROCESS PROCESS C PASCAL VHDL PROCESS PROCESS PROCESS 1. PROCESS PROCESS [ ] PROCESS [ ( ) ] [IS] [ ] END PROCESS [ ] PROCESS PROCESS PROCESS BLOCK

42 3 VHDL WAIT Suspention PROCESS PROCESS PROCESS PROCESS END PROCESS [ ] [IS] 2. PROCESS PROCESS (1) (2) h SIGNAL h VARIABLE h PROCESS WAIT WAIT WAIT h h IF CASE LOOP NULL h NEXT EXIT (3) WAIT 3-15 p1 WAIT clock clock WAIT driver CASE 3-15 ARCHITECURE s_mode OF stat IS p1 PROCESS WAIT UNTIL clock ; IF (driver = '1' ) THEN CASE output IS WHEN s1 => output <= s2 ; -- clock 33

43 34 VHDL WHEN s2 => output <= s3 ; WHEN s3 => output <= s4 ; WHEN s4 => output <= s1 ; END CASE END IF END PROCESS p1 END ARCHITECURE s_mode ; IF clk clear stop cnt4 clk clear stop 3-16 SIGNAL cnt4 : INTEGER RANGE 0 TO 15 ; -- cnt4... PROCESS (clk, clear, stop) IF clear = '0' THEN cnt4 <= 0 ; ELSIF clk'event AND clk = '1' THEN -- IF stop = '0' THEN -- stop END IF ; END IF ; END PROCESS ; 3. cnt4 <= cnt4 + 1 ; -- VHDL VHLD 1 CPU 2 VHDL 3 (1) END PROCESS PROCESS (2) PROCESS CPU

44 3 VHDL CPU PROCESS PROCESS END PROCESS PROCESS VHDL δ 0 PROCESS (3) (4) WAIT WAIT WAIT (5) VHDL 93 (6) VHDL BLOCK (7) VHDL VHDL

45 36 VHDL 3.5 (SUBPROGRAM) VHDL VHDL VHDL 3 VHDL PROCEDURE FUNCTION 5 6 PC VHDL VHDL FUNCTION VHDL FUNCTION RETURN --

46 3 VHDL FUNCTION RETURN IS [ ] END FUNCTION FUNCTION VHDL CONSTANT SIGNAL 3-17 PACKAGE packexp IS -- FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR FUNCTION func1 ( a,b,c : REAL ) -- RETURN REAL FUNCTION "*" ( a,b : INTEGER ) -- RETURN INTEGER FUNCTION as2 (SIGNAL in1,in2 : REAL ) -- RETURN REAL END PACKAGE BODY packexp IS FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION END; -- PACKAGE BODY --

47 38 VHDL... USE WORK. packexp.all ENTITY axamp IS PORT(...); END; ARCHITECTURE bhv OF axamp IS... out1 <= max(dat1,dat2); -- PROCESS(dat3,dat4) out2 <= max(dat3,dat4); -- END PROCESS;... END; packexp 1 a b a b 2 a b c 3 "*" "+" SIGNAL in1 in2 REAL 2 END FUNCTION 3-17 max 3-18 PROCESS a a 3 a(0) a(1) a(2) sam m 3-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY func IS PORT a : IN STD_LOGIC_VECTOR (0 to 2 ) ; m : OUT STD_LOGIC_VECTOR (0 to 2 ) ;

48 3 VHDL END ENTITY func ARCHITECTURE demo OF func IS FUNCTION sam(x,y,z : STD_LOGIC) RETURN STD_LOGIC IS RETURN ( x AND y ) OR y ; END FUNCTION sam PROCESS ( a ) m(0) <= sam( a(0), a(1), a(2) ) ; m(1) <= sam( a(2), a(0), a(1) ) ; m(2) <= sam( a(1), a(2), a(0) ) ; END PROCESS ; END ARCHITECTURE demo ; MAX+PLUSII IF CASE RETURN 3-19 MAX+PLUSII 3-19 FUNCTION trans ( value : IN BIT_VECTOR (0 TO 1) ) ; RETURN BIT_VECTOR IS CASE value IS WHEN "0000" => RETURN "1100" ; WHEN "0101" => RETURN "0001" ; WHEN OTHERS => RETURN "1111" ; END CASE ; END FUNCTION trans ; IN ( 5 ) OVERLOADED FUNCTION VHDL 3-20 max 3-20 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; PACKAGE packexp IS -- FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR FUNCTION max( a,b IN BIT_VECTOR) --

49 40 VHDL RETURN BIT_VECTOR FUNCTION max( a,b IN INTEGER ) RETURN INTEGER END -- PACKAGE BODY packexp IS FUNCTION max( a,b IN STD_LOGIC_VECTOR) -- RETURN STD_LOGIC_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION FUNCTION max( a,b IN INTEGER) -- RETURN INTEGER IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION FUNCTION max( a,b IN BIT_VECTOR) -- RETURN BIT_VECTOR IS IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; -- FUNCTION END; -- PACKAGE BODY -- max LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE WORK.packexp.ALL ENTITY axamp IS PORT(a1,b1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); a2,b2 : IN BIT_VECTOR(4 DOWNTO 0); a3,b3 : IN INTEGER 0 TO 15; c1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); c2 : OUT BIT_VECTOR(4 DOWNTO 0); c3 : OUT INTEGER 0 TO 15); END; ARCHITECTURE bhv OF axamp IS c1 <= max(a1,b1); -- max( a,b IN STD_LOGIC_VECTOR) c2 <= max(a2,b2); -- max( a,b IN BIT_VECTOR) c3 <= max(a3,b3); -- max( a,b IN INTEGER) END;

50 3 VHDL VHDL VHDL IEEE STD_LOGIC_UNSIGNED "+" "-" "*" "=" ">=" "<=" ">" "<" "/=" "AND" "MOD" INTEGRE STD_LOGIC STD_LOGIC_VECTOR 3-21 Synopsys STD_LOGIC_UNSIGNED STD_LOGIC_UNSIGNED UNSIGNED IEEE.STD_LOGIC_ARITH MAXIUM 3-21 LIBRARY IEEE ; -- USE IEEE.std_logic_1164.all ; USE IEEE.std_logic_arith.all ; PACKAGE STD_LOGIC_UNSIGNED is function "+" (L : STD_LOGIC_VECTOR ; R : INTEGER) return STD_LOGIC_VECTOR ; function "+" (L : INTEGER; R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR ; function "+" (L : STD_LOGIC_VECTOR ; R : STD_LOGIC ) return STD_LOGIC_VECTOR ; function SHR (ARG : STD_LOGIC_VECTOR ; COUNT : STD_LOGIC_VECTOR ) return STD_LOGIC_VECTOR ;... end STD_LOGIC_UNSIGNED ; LIBRARY IEEE ; -- use IEEE.std_logic_1164.all ; use IEEE.std_logic_arith.all ; package body STD_LOGIC_UNSIGNED is function maximum (L, R : INTEGER) return INTEGER is begin if L > R then return L; else return R; end if; end; function "+" (L : STD_LOGIC_VECTOR ; R : INTEGER) return STD_LOGIC_VECTOR is Variable result : STD_LOGIC_VECTOR (L range) ; Begin result := UNSIGNED(L) + R ; 41

51 42 VHDL return std_logic_vector(result) ; end ;... end STD_LOGIC_UNSIGNED + USE STD_LOGIC_UNSIGNED STD_LOGIC_VECTOR STD_LOGIC 4 VHDL LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; -- ENTITY cnt4 IS PORT Clk : IN STD_LOGIC ; q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ); END cnt4; ARCHITECTURE one OF cnt4 IS PROCESS ( clk ) IF clk'event AND clk = '1' THEN IF q=15 THEN -- = q <= "0000" ; ELSE q <= q + 1 ; -- + END IF ; END IF ; END PROCESS ; END one ; q = 15 q 15 q<=q USE IEEE.STD_LOGIC_UNSIGNED.ALL

52 3 VHDL PROCEDURE VHDL PROCEDURE PROCEDURE PROCEDURE IS [ ] BIGIN END PROCEDURE IN OUT INOUT IN 3-23 PROCEDURE pro1 (VARIABLE a, b : INOUT REAL) ; PROCEDURE pro2 CONSTANT a1 : IN INTEGER VARIABLE b1 : OUT INTEGER ) ; PROCEDURE pro3 (SIGNAL sig : INOUT BIT) ; pro1 a b pro2 IN OUT pro3 sig INOUT BIT IN OUT INOUT IN INOUT OUT 2. WAIT WAIT

53 44 VHDL IN INOUT Wait 3-24 PROCEDURE prg1(variable value:inout BIT_VECTOR(0 TO 7)) IS CASE value IS WHEN "0000" => value: "0101" ; WHEN "0101" => value: "0000" ; WHEN OTHERS => value: "1111" ; END CASE ; END PROCEDURE prg1 ; value 3-25 PROCEDURE comp ( a, r : IN REAL; m : IN INTEGER ; v1, v2: OUT REAL) IS VARIABLE cnt : INTEGER ; v1 := 1.6 * a ; v2 := 1.0 ; Q1 : FOR cnt IN 1 TO m LOOP v2 := v2 * v1 ; EXIT Q1 WHEN v2 > v1; END LOOP Q1 ASSERT (v2 < v1 ) REPORT "OUT OF RANGE" SEVERITY ERROR ; END PROCEDURE comp ; v2 > v1 LOOP -- comp a r m v2 v1 comp LOOP v2 v2 r EXIT REPORT OVERLOADED PROCEDURE

54 3 VHDL 3-26 PROCEDURE calcu ( v1, v2 : IN REAL ; SIGNAL out1 : INOUT INTEGER) ; PROCEDURE calcu ( v1, v2 : IN INTEGER ; SIGNAL out1 : INOUT REAL) ;... calcu (20.15, 1.42, signl) ; -- calcu calcu ( sign2 ) -- calcu v1 v2 out1 INOUT v1 v2 out1 OUT INOUT LIBRARY VHDL VHDL VHDL VHDL USE USE VHDL IEEE IEEE IEEE IEEE 1076 Synopsys STD_LOGIC_UNSIGNED VHDL

55 46 VHDL WORK IEEE LIBRARY USE LIBRARY LIBRARY LIBRARY IEEE ; IEEE 1. VHDL h IEEE IEEE VHDL IEEE IEEE STD_LOGIC_1164 NUMERIC_BIT NUMERIC_STD STD_LOGIC_1164 IEEE IEEE Synopsys STD_LOGIC_ARITH STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED EDA Synopsys IEEE STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED IEEE IEEE VHDL STD_LOGIC_1164 VHDL h STD VHDL STANDARD TEXTIO / STD VHDL VHDL STD VHDL IEEE LIBRARY STD USE STD.STANDARD.ALL ; h WORK WORK VHDL WORK VHDL VHDL WORK PC VHDL

56 3 VHDL VHDL WORK VHDL VHDL h VITAL VITAL VHDL VHDL VITAL_TIMING VITAL_PRIMITIVES VITAL IEEE VHDL VITAL IEEE FPGA/CPLD ispexpert Compiler 12 VHDL VHDL FPGA/CPLD VITAL EDA FPGA/CPLD DATAIO GENERICS DATAIO Synopsys VHDL EDA WORK Synplicity Synplify ( 12 ) EDA 2 VHDL VHDL 3-22 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; IEEE STD_LOGIC_1164 STD_LOGIC_UNSIGNED VHDL USE LIBRARY USE 47

57 48 VHDL VHDL USE USE USE USE. USE..ALL USE USE USE USE IEEE.STD_LOGIC_1164.ALL ; IEEE STD_LOGIC_1164 VHDL ALL 3-27 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.STD_ULOGIC ; USE IEEE.STD_LOGIC_1164.RISING_EDGE ; STD_LOGIC_1164 RISING_EDGE STD_ULOGIC USE 3.7 PACKAGE VHDL VHDL VHDL h h VHDL 4

58 3 VHDL h VHDL h STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR PACKAGE IS -- END PACKAGE BODY IS -- END 3-21 STD_LOGIC_UNSIGNED 1. VHDL 3-28 PACKAGE pacl IS -- TYPE byte IS RANGE 0 TO 255 ; -- byte SUBTYPE nibble IS byte RANGE 0 TO 15 ; -- nibble CONSTANT byte_ff : byte := 255 ; -- byte_ff SIGNAL addend : nibble ; -- addend COMPONENT byte_adder -- PORT( a, b : IN byte ; c : OUT byte ; overflow : OUT BOOLEAN ) ; END COMPONENT ; FUNCTION my_function (a : IN byte) Return byte ; -- END pacl ; -- pacl byte nibble byte byte_ff nibble addend 49

59 50 VHDL USE LIBRARY WORK USE WORK.pacl.ALL ; ENTITY... ARCHITHCYURE WORK LIBRARY WORK USE 3-29 WORK 3-29 PACKAGE seven IS SUBTYPE segments is BIT_VECTOR(0 TO 6) ; TYPE bcd IS RANGE 0 TO 9 ; END seven ; USE WORK.seven.ALL ; ENTITY decoder IS PORT (input: bcd; drive : out segments) ; END decoder ; ARCHITECTURE simple OF decoder IS WITH input SELECT drive <= B" " WHEN 0, B" " WHEN 1, B" " WHEN 2, B" " WHEN 3, B" " WHEN 4, B" " WHEN 5, B" " WHEN 6, B" " WHEN 7, B" " WHEN 8, B" " WHEN 9, B" " WHEN OTHERS ; END simple ; 4 BCD 7 VHDL seven segments bcd 7 decoder WORK USE 2. USE 3-28

60 3 VHDL h STD_LOGIC_1164 STD_LOGIC_1164 IEEE IEEE VHDL 0 1 Z X STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR FPGA/CPLD h STD_LOGIC_ARITH STD_LOGIC_ARITH IEEE Synopsys STD_LOGIC_1164 UNSIGNED SIGNED SMALL_INT h STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED Synopsys IEEE INTEGER STD_LOGIC STD_LOGIC_VECTOR STD_LOGIC_VECTOR INTEGER STD_LOGIC_SIGNED STD_LOGIC_ARITH STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED IEEE VHDL VHDL h STANDARD TEXTIO STANDARD TEXTIO STD STANDARD STANDARD VHDL USE TEXTIO USE STD.TEXTIO.ALL TEXTIO TEXTIO VHDL CONFIGURATION

61 52 VHDL VHDL VHDL VHDL VHDL VHDL CONFIGURATION OF IS END 3-30 nand 3-30 LIBRARY IEEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY nand IS PORT (a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ) ; END ENTITY nand ; ARCHITECTURE one OF nand IS c <= NOT (a AND b) ; END ARCHITECTURE one ; ARCHITECTURE two OF nand IS c <= 1 WHEN (a = 0 )AND(b = 0 ) ELSE 1 WHEN (a = 0 )AND(b = 1 ) ELSE 1 WHEN (a = 1 )AND(b = 0 ) ELSE 0 WHEN (a = 1 )AND(b = 1 ) ELSE 0 ; END ARCHITECTURE two CONFIGURATION second OF nand IS FOR two END FOR END second ;

62 3 VHDL CONFIGURATION first OF nand IS FOR one END FOR END first ; second nand two first nand one 3-30 nand nand nand RS nand two nand 3-31 LIBRARY LEEE; USE LEEEE.STD_LOGIC_1164.ALL ; ENTITY rs1 IS PORT ( r : IN STD_LOGIC ; s : IN STD_LOGIC ; q : OUT STD_LOGIC ; qf : OUT STD_LOGIC ; END rs1 ; ARCHITECTURE rsf OF rs1 IS COMPONENT nand PORT ( a : IN STD_LOGIC ; b : IN STD_LOGIC ; c : OUT STD_LOGIC ; END COMPONENT ; U1: nand PORT MAP ( a => s, b => qf, c => q ) ; U2: nand PORT MAP ( a => q, b => r, c => qf ) ; END rsf ; CONFIGURATION sel OF rs1 IS FOR rsf FOR u1, u2 : nand USE ENTITY WORK.nand( two ) ; END FOR END FOR END sel ; WORK 3-1 ENTITY VHDL

63 54 VHDL 3-4 PROCESS PROCESS 3-5 VHDL LS373 D CLOCK OE Q ENTITY buf3s IS -- PORT (input : IN STD_LOGIC ; -- enable : IN STD_LOGIC ; -- output : OUT STD_LOGIC ) ; -- END buf3x ; 2 ENTITY mux21 IS PORT (in0, -- 0 in1, -- 1 sel : IN STD_LOGIC; -- output : OUT STD_LOGIC); -- END mux21 ; 3-9 VHDL 3-10 VHDL ENTITY dlatch IS PORT( d, cp : IN STD_LOGIC ; q, qn : BUFFER STD_LOGIC ) ; END dlatch ; ARCHITECTURE one OF dlatch IS SINGAL n1, n2 : STD_LOGIC ; n1<= (NOT d) NAND cp ; n2<= d NAND cp ;q <= qn NAND n1 ; qn <= q NAND n2 ; END one ; 3-11 VHDL ENTITY ENTITY SN74LS20 IS

64 3 VHDL PORT ( I1A, I1B, I1C, I1D : IN STD_LOIGC ; I2A, I2B, I2C, I2D : IN STD_LOIGC ; O1, O2 : OUT STD_LOGIC ) ; END SN74LS20 ; ARCHITECTURE struc OF SN74LS20 IS O1 <= NOT (I1A AND I1B AND I1C AND I1D) ; O2 <= NOT (I1A AND I1B AND I1C AND I1D) ; END struc ; 3-12 VHDL 3-13 BLOCK BLOCK

65 4 VHDL 55 4 VHDL VHDL VHDL VHDL VHDL VHDL VHDL (Data Objects Objects) (Variables) (Signals) (Constants) (Data Types Types) (Operands) (Operators) 4.1 VHDL VHDL VHDL VHDL (Literal) 1. h E2(=15600) 45_234_287 (= ) h _670_ _909(= ) E-2(=0.4499) h # # 0

66 56 VHDL... SIGNAL d1,d2,d3,d4,d5, : INTEGER RANGE 0 TO 255; d1 <= 110#170# ; d2 <= 16#FE# ; d3 <= 2#1111_1110#; -- ( 170) -- ( 254) -- ( 254) d4 <= 8#376# ; -- ( 254) d5 <= 16#E#E1 ; -- ( 2# # 224)... h (VHDL ) 60s (60 ) 100m (100 ) k ( ) 177A (177 ) 2 ASCII 'R' 'a' '*' 'Z' 'U' '0' '11' '-' 'L' TYPE STD_ULOGIC IS ( 'U' 'X' '0' '1' 'W' 'L' 'H' '-' ) (1) "ERROR" "Both S and Q equal to 1" "X" "BB$CC" (2) Bit "B" "O" "X" h B 0 1 Bit h O 3 (BIT) h X (0 F) 4 data1 <= B"1_1101_1110" data2 <= O"15" data3 <= X"AD0" data4 <= B"101_010_101_010" -- 12

67 data5 <= "101_010_101_010" data6 <= "0AD0" 4 VHDL -- X -- B 57 3 VHDL h 26 a z A Z 0 9 _ h h _ h VHDL 93 h \74LS373\ \Hello World\ h ( ) \IRDY#\ \C/BE\ \A or B\ h 1987 VHDL Decoder_1 FFT Sig_N Not_Ack State0 Idle _Decoder_1 -- 2FFT Sig_#N Not-Ack RyY_RST_ data BUS return # _ ( )

68 58 VHDL m 3 SIGNAL a b : BIT_VECTOR (0 TO 3) ; SIGNAL m : INTEGER RANGE 0 TO 3 ; SIGNAL y z : BIT ; y <= a(m) ; z <= b(3) ; ( ) ( ) TO DOWNTO TO (2 TO 8) DOWNTO (8 DOWNTO 2) SIGNAL a z : BIT_VECTOR (0 TO 7) ; SIGNAL b : STD_LOGIC_VECTOR (4 DOWNTO 0) ; SIGNAL c : STD_LOGIC_VECTOR (0 TO 4) ; SIGNAL e : STD_LOGIC_VECTOR (0 TO 3) ; SIGNAL d : STD_LOGIC ;... z(0 TO 3) <= a(4 TO 7) ; -- z 0 <=a(4) z 1 <=a(5)... z(4 TO 7) <= a(0 TO 3) ; b(2) <= '1'; b(3 DOWNTO 0) <= "1010"; -- b 3 <='1' b 2 <='0'... c(0 TO 3) <= "0110"; c(2) <= d ; c <= b ; -- c(0 TO 4)<=b(4 DOWNTO 0) c 0 <=b(4) c 1 <=b(3)... e <= c ; -- e <= c 0 TO 3 ; -- e <= c 1 TO 4 ; VHDL VHDL (Data Objects) (VARIABLE) (CONSTANT) (SIGNAL)

69 4 VHDL VHDL GND VCC VHDL VHDL VHDL ( VHDL ) VHDL VHDL FPGA/CPLD (VARIABLE) VHDL VHDL VARIABLE := VARIABLE a : INTEGER ; VARIABLE b, c : INTEGER := 2 ; VARIABLE d : STD_LOGIC ; a b c 2 d

70 60 VHDL := := VARIABLE x y : REAL ; VARIABLE a b : BIT_VECTOR( 0 TO 7 ) ; x := ; -- x y := 1.5+x ; -- y a := b ; a := " " ; -- a a (3 TO 6) := ( '1' '1' '0' '1') ; -- a (0 TO 5) := b (2 TO 7) ; a (7) := '0' ; a b 8 8 a (0) a (1) a (7) b (0) b (1) b (7) VHDL 93 SHARED VARIABLE fre: BOOLEAN := true VHDL (SIGNAL) VHDL ABEL REG NODE SIGNAL := VHDL

71 4 VHDL (Port) SIGNAL temp : STD_LOGIC := 0 ; SIGNAL flaga flagb : BIT ; SIGNAL data : STD_LOGIC_VECTOR(15 DOWNTO 0 ) ; SIGNAL a : INTEGER RANGE 0 TO 15; temp STD_LOGIC BIT flaga flagb STD_LOGIC_VECTOR 16 a 0 15 VHDL TYPE four IS ( 'X', '0', '1', 'Z' ) SIGNAL s1 : four SIGNAL s2 : four := 'X' SIGNAL s3 : four := '1' four TYPE four STD_LOGIC s1 VHDL LEFT most 'X' ( ) s2 'X' s3 '1' VHDL <= 61

72 62 VHDL ( ) <= ( 8 ) <= <= := := x <= 9 ; y <= x ; z <= x AFTER 5ns ; 5ns x z AFTER AFTER δ δ VHDL ( ) SIGNAL a b c y z: INTEGER... PROCESS (a b c) y <= a * b ; z <= c x ; y <= b END PROCESS ;... a b c y b y b ( ) 4-3 ARCHITECTURE fun1 OF adder_h IS

73 4 VHDL sum <= a XOR b ; carry <= a AND b ; END ARCHITECTURE fun1 63 a b sum carry (CONSTANT) CONSTANT := CONSTANT fbus : BIT_VECTOR := "010115" ;-- CONSTANT Vcc : REAL := 5.0 ; CONSTANT dely : TIME := 25ns ; VHDL (file) (Access) PACKAGE t IS CONSTANT rst : STD_LOGIC ; END PACKAGE t PACKAGE BODY t IS CONSTANT rst : STD_LOGIC := '0' ; END PACKAGE BODY t ; 4-4 rst

74 64 VHDL 4.3 VHDL 4.2 (TYPES) VHDL ( ) VHDL VHDL VHDL VHDL BIT VHDL 1. (Scalar Type) h h h h 2. (Composite Type) (Array) (Record) 3. (Access Type) 4. (Files Type) VHDL VHDL VHDL STANDARD STD_LOGIC_1164 VHDL VHDL

75 4 VHDL VHDL VHDL REAL TIME FILE ( ) VHDL VHDL VHDL STANDARD VHDL USE 1. (BOOLEAN) STANDARD TYPE BOOLEAN IS (FALSE TRUE) FALSE( ) TRUE( ) BOOLEAN a b IF (a>b) TRUE FALSE (BIT) 1 0 VHDL BIT STANDARD TYPE BIT IS ( '0', '1' ) 3 (BIT_VECTOR) BIT STANDARD : TYPE BIT_VECTOR IS ARRAY (Natural Range <> ) OF BIT ; SIGNAL a : BIT_VECTOR(7 TO 0) ; a 8 a(7) a(0) 4. (CHARACTER) 'A' 'B' 'b'

76 66 VHDL STANDARD TYPE CHARACTER IS ( NUL SOH STX ETX EOT ENQ ACK BEL, BS HT LF VT FF CR SO SI, DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FSP GSP RSP USP, ' ' '!' '"' '#' '$' '%' '&' ''', '(' ')' '*' '+' ',' '-' '.' '/', '0' '1' '2' '3' '4' '5' '6' '7', '8' '9' ':' ';' '<' '=' '>' '?', '@' 'A' 'B' 'C' 'D' 'E' 'F' 'G', 'H' 'I' 'J' 'K' 'L' 'M' 'N' 'O', 'P' 'Q' 'R' 'S' 'T' 'U' 'V' 'W', 'X' 'Y' 'Z' '[' '\' ']' '^' '_', '`' 'a' 'b' 'c' 'd' 'e' 'f' 'g', 'h' 'i' 'j' 'k' 'l' 'm' 'n' 'o', 'p' 'q' 'r' 's' 't' 'u' 'v' 'w', 'x' 'y' 'z' '{' ' ' '}' '~' DEL ) ; VHDL 5. (INTEGER) + * / VHDL VHDL INTEGER VHDL Integer VHDL RANGE VHDL SIGNAL typei : INTEGER RANGE 0 TO 15 ; typei typei E4

77 4 VHDL 16#D2# 8#720# 2# # (NATURAL) (POSITIVE) STANDARD SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER'HIGH ; SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER'HIGH ; 7. (REAL) VHDL 1.0E38 1.0E38 VHDL VHDL _ _3333 8#43.6#e E 4 8. (STRING) VARIABLE string_var : STRING (1 TO 7 ) ; string_var := "a b c d" 9. (TIME) VHDL 55 ms 20 ns STANDARD TYPE time IS RANGE TO units fs ; -- VHDL ps = 1000 fs ; -- ns = 1000 ps ; -- us = 1000 ns ; -- ms = 1000 us ; -- sec = 1000 ms ; --

78 68 VHDL min = 60 sec ; hr = 60 min ; end units ; 10. (SEVERITY LEVEL) VHDL NOTE( ) WARNING( ) ERROR( ) FAILURE( ) TYPE severity_level IS (note warning error failure) ; 11. (1) (2) REAL (3) Aceess (4) File RAM ROM IEEE IEEE STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR 1. STD_LOGIC IEEE STD_LOGIC_1164 STD_LOGIC TYPE STD_LOGIC IS 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' ) ; LIBRARY IEEE; USE IEEE.STD_LOIGC_1164.ALL;

79 4 VHDL STD_LOGIC BIT STD_LOGIC BIT 0 1 IEEE STD_LOGIC BIT STD_LOGIC STD_LOGIC_1164 STD_LOGIC AND NAND OR NOR XOR NOT BIT STD_LOGIC STD_LOGIC STD_LOGIC 0 1 Z VHDL 2. (STD_LOGIC_VECTOR) STD_LOGIC_VECTOR TYPE STD_LOGIC_VECTOR IS ARRAY ( NATURAL RANGE <> ) OF STD_LOGIC ; STD_LOGIC_VECTOR STD_LOGIC_1164 STD_LOGIC STD_LOGIC_VECTOR ARRAY 4-5 CPU TYPE t_data IS ARRAY(7 DOWNTO 0) OF STD_LOGIC; -- SIGNAL databus memory : t_data ; -- databus,memory CPU : PROCESS -- CPU VARIABLE rega : t_data ; -- rega... databus <= rega; -- 8 END PROCESS CPU -- CPU MEM : PROCESS -- RAM... databus <= memory ; END PROCESS MEM... STD_LOGIC_VECTOR 69

80 70 VHDL STD_LOGIC VHDL Synopsys IEEE STD_LOGIC_ARITH h (UNSIGNED) h (SIGNED) h (SMALL_INT) STD_LOGIC_ARITH TYPE UNSIGNED IS array (NATURAL range < >) OF STD_LOGIC ; TYPE SIGNED IS ARRAY (NATURAL range < >) OF STD_LOGIC ; SUBTYPE SMALL_INT IS INTEGER RANGE 0 TO 1 ; LIBRARY IEEE ; USE IEEE.STD_LOIGC_ARITH.ALL ; UNSIGNED SIGNED UNSIGNED SIGNED IEEE NUMERIC_STD NUMERIC_BIT UNSIGNED SIGNED NUMERIC_STD STD_LOGIC NUMERIC_BIT BIT STD_LOGIC_ARITH NUMBER_STD NUMERIC_BIT STANDARD STD_LOGIC_VECTOR UNSIGNED SIGNED 1. (UNSIGNED TYPE) UNSIGNED 8 UNSIGNED'("1000") UNSIGNED UNSIGNED VARIABLE var : UNSIGNED(0 TO 10) ;

81 SIGNAL sig : UNSIGNED(5 TO 0) ; 4 VHDL 71 var 11 var(0) var(10) sig 6 sig(5) 2. (SIGNED TYPE) SIGNED SIGNED'("0101") +5 5 SIGNED'("1011") 5 var SIGNED VARIABLE var SIGNED(0 TO 10) ; var 11 var(0) VHDL (Enumeration Types) (Interger Types) (Array Types) (Record Types) (Time Types) (Real Types) TYPE SUBTYPE 1. TYPE TYPE TYPE IS OF Type IS TYPE OF BIT STD_LOGIC INTEGER TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ; TYPE week IS (sun mon tue wed thu fri sat) ; TYPE byt IS STD_LOGIC(15 TO 0) ;--

82 72 VHDL st1 16 STD_LOGIC sun = 1010 ;,TYPE VHDL STD_LOGIC VHDL (SIGNAL VARIABLE CONSTANT) TYPE v1 8 byte TYPE byte IS ARRAY(7 DOWNTO 0) of BIT VARIABLE v1 : byte ; --v1 byte colour TYPE colour IS (Red Green Yellow Blou Violet);... a <= colour (Red) ; 2. SUBTYPE -- Red a SUBTYPE TYPE SUBTYPE SUBTYPE IS RANGE TYPE TYPE VHDL TYPE SUBTYPE digits IS INTEGER RANGE 0 to 9 ; INTEGER digits INTEGER 10 2 SUBTYPE SUBTYPE dig1 IS STD_LOGIC_VECTOR(7 DOWNTO 0) ; SUBTYPE dig3 IS ARRAY(7 DOWNTO 0) of STD_LOGIC;-- STANDARD (Natural type) (Positive type) INTEGER

83 4 VHDL VHDL VHDL TYPE m_state IS ( state1 state2 state3 state4 state5 ) ; SIGNAL present_state next_state : m_state ; present_state next_state m_state state1 state5 VHDL BIT (BOOLEAN) (CHARACTER) STD_LOGIC BIT TYPE my_logic IS ( 1 Z U 0 ) ; SIGNAL s1 : my_logic ; s1 <= Z ; TYPE STD_LOGIC IS ( U X 0 1 Z W L H - ) ; SIGNAL sig : STD_LOGIC ; sig <= Z ; ( ) state1 = 000 state2 = 001 state3 = 010 state4 = 011 state5 = 100 state1 < state2 < state3 < state4 < state5 9

84 74 VHDL VHDL VHDL h h VHDL RANGE TYPE percent IS RANGE 100 TO 100 ; TYPE num1 IS range 0 to TYPE num2 IS range 10 to TYPE num3 IS range -100 to SUBTYPE num4 IS num3 RANGE 0 to ( ) ) VHDL VHDL 0 TO DOWNTO 0 16 VHDL

85 4 VHDL TYPE IS ARRAY ( )OF 75 TYPE stb IS ARRAY (7 DOWNTO 0) of STD_LOGIC ; stb stb(7) stb(6) stb(0) TYPE x is (low high) ; TYPE data_bus IS ARRAY (0 TO 7 x) of BIT ; x data_bus 9 BIT TYPE IS ARRAY ( RANGE <>)OF <> <> < > 4-8 TYPE Bit_Vector IS Array (Natural Range <>)OF BIT VARIABLE va Bit_Vector (1 to 6) TYPE Real_Matrix IS ARRAY (POSITIVE RANGE <>) of RAEL ; VARIABLE Real_Matrix_Object : Real_Matrix (1 TO 8) ; TYPE Log_4_Vector IS ARRAY (NATURAL RANGE <>, POSITIVE RANGE<>) OF Log_4 ; VARIABLE L4_Object : Log_4_Vector (0 TO 7 1 TO 2) ; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

86 76 VHDL ENTITY regfile IS PORT ( q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); d : IN STD_LOGIC_VECTOR (7 DOWNTO 0); addr : IN STD_LOGIC_VECTOR (3 DOWNTO 0); we, clk : IN STD_LOGIC); END regfile; ARCHITECTURE behave OF regfile IS TYPE rf_type IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL rf : rf_type (15 DOWNTO 0); PROCESS (clk) IF RISING_EDGE(clk) THEN IF we = '1' THEN rf(conv_integer(addr)) <= d; END IF; END IF; END PROCESS; q <= rf(conv_integer(addr)); END behave; 8 RAM RAM RTL TYPE IS RECORD... : ; : ; END RECORD [ ]; 4-12 TYPE GlitchDataType IS RECORD -- GlitchDataType

87 4 VHDL 77 SchedTime : TIME ; -- SchedTime GlitchTime : TIME ; -- GlitchTime SchedValue : STD_LOGIC ; -- SchedValue CurrentValue : STD_LOGIC ; -- CurrentValue END RECORD ; OTHERS OTHERS TYPE RegName IS (AX BX CX DX) ; TYPE Operation IS RECORD Mnemonic : STRING (1 TO 10) ; OpCode : BIT_VECTOR(3 DOWNTO 0) ; Op1 Op2 Res : RegName ; END record ; VARIABLE Instr1 Instr2: Operation ;... Instr1 := ("ADD AX BX" "0001" AX BX AX) ; Instr2 := ("ADD AX BX" "0010" others => BX) ; VARIABLE Instr3 : Operation ; Instr3.Mnemonic := "MUL AX BX" ; Instr3.Op1 := AX ; Operation Mnemonic 4 OpCode Op1 Op2 Res Op1 Op2 Res Instr1 Operation "ADD AX BX" 4 "0001" AX BX AX BX AX AX Instr3.Mnemonic := "MUL AX BX" ; "MUL AX BX" Instr3 Mnemonic (. )

88 78 VHDL VHDL PACKAGE defs IS SUBTYPE short IS INTEGER RANGE 0 TO 15 ; END defs ; USE WORK.defs.ALL ; ENTITY cnt4 IS PORT (clk : IN BOOLEAN ; P : INOUT short) ; END ENTITY cnt4 ARCHITECTURE behv OF cnt4 IS PROCESS (clk) IF clk AND clk EVENT THEN P <= P + 1 ; END IF ; END PROCESS ; END behv ; defs short 0 15 P short + P 1 VHDL + PLD I/O P P PLD I/O RTL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY cnt4 IS

89 4 VHDL PORT (clk : IN STD_LOGIC ; p : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) ) END cnt4 LIBRARY dataio ; USE dataio.std_logic_ops.all ARCHITECTURE behv OF cnt4 IS PROCESS (clk) IF clk = 1 AND clk EVENT THEN p <= To_Vector(2,To_Integer(p)+1) ; END IF END PROCESS ; END behv ; 79 dataio DATAIO STD_LOGIC_ops To_Vector( NTEGER STD_LOGIC_VECTOR) To_Integer( STD_LOGIC_VECTOR INTEGER) + 1 STD_LOGIC_VECTOR EDA 4-14 VHDL VHDL 4-16 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY amp IS PORT ( a1 a2 : IN BIT_VECTOR(3 DOWNTO 0); c1 c2,c3 : IN STD_LOGIC_VECTOR (3 DOWNTO 0); b1 b2 b3 : INTEGER RANGE 0 TO 15; d1,d2,d3,d4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END amp;... d1 <= TO_STDLOGICVECTOR(a1 AND a2); --(1)... d2 < = CONV_STD_LOGIC_VECTOR(b1,4) WHEN CONV_INTEGER(b2)=9 else CONV_STD_LOGIC_VECTOR(b3,4); --(2)

90 80 VHDL... d3 < = c1 WHEN CONV_INTEGER(c2)= 8 ELSE c3; --(3)... d4 < = c1 WHEN c2 = 8 else c3; --(4), (1) IEEE.STD_LOGIC_1164, : FUNCTION TO_STDLOGICVECTOR( s : BIT_VECTOR) RETURN STD_LOGIC_VECTOR; STD_LOGIC_VECTOR IEEE.STD_LOGIC_UNSIGNED : FUNCTION CONV_INTEGER(arg: STD_LOGIC_VECTOR) RETURN INTEGER; FUNCTION CONV_STD_LOGIC_VECTOR(arg: INTEGER;size INTEGER) (2) RETURN STD_LOGIC_VECTOR 3 (4) STD_LOGIC_UNSIGNED "=" STD_LOGIC_VECTOR 4-17 CONV_INTEGER( ) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder3to8; ARCHITECTURE behave OF decoder3to8 IS PROCESS (input) output <= (OTHERS => '0'); output(conv_integer(input)) <= '1'; END PROCESS; END behave; 4-18 FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0' ) RETURN BIT ; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR ; FUNCTION To_bitvector ( s : std_ulogic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR ;

91 4 VHDL 81 To_bitvector FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0' ) RETURN BIT_VECTOR IS ALIAS sv : std_logic_vector(s'length-1 DOWNTO 0 ) IS s ; VARIABLE result : BIT_VECTOR(s'LENGTH-1 DOWNTO 0 ); FOR i IN result'range LOOP CASE sv(i) IS WHEN '0' 'L' => result(i) := '0'; WHEN '1' 'H' => result(i) := '1'; WHEN OTHERS => result(i) := xmap; END CASE ; END LOOP ; RETURN result ; END ; To_bitvector std_logic_vector BIT_VECTOR STANDARD STD_LOGIC_1164 Vector INTEGER EDA 2. VHDL ( ) ( ) h ( ) h h VARIABLE Data_Calc Param_Calc : INTEGER ;... Data_Calc := INTEGER(74.94 * REAL(Param_Calc) ) ;

92 82 VHDL 4.4 VHDL VHDL (Operands) (Operators) VHDL VHDL 4-1 (Logical Operator) (Relational Operator) (Arithmetic Operator) (Sign Operator) (Overloading Operator) AND OR NAND NOR XOR XNOR NOT BIT BOOLEAN STD_LOGIC_1164 STD_LOGIC AND OR NAND NOR XOR XNOR AND OR XOR A and B and C and D (A or B) xor C VHDL h h VHDL ( 4-1 ) BIT STD_LOGIC ABEL-HDL 4-2 ** ABS NOT NOT

93 4 VHDL VHDL + & * ( ) / ( ) MOD REM SLL BIT SRL BIT SLA BIT SRA BIT ROL BIT ROR BIT ** ABS = /= < > <= >= AND BIT BOOLEAN STD_LOGIC OR BIT BOOLEAN STD_LOGIC NAND BIT BOOLEAN STD_LOGIC NOR BIT BOOLEAN STD_LOGIC XOR BIT BOOLEAN STD_LOGIC XNOR BIT BOOLEAN STD_LOGIC NOT BIT BOOLEAN STD_LOGIC VHDL NOT ABS ** * / MOD REM +( ) ( ) + & SLL SLA SRL SRA ROL ROR = /= < <= > >= AND OR NAND NOR XOR XNOR VHDL AND( ) OR( ) NAND( ) NOR(

94 84 VHDL ) XOR( ) XNOR NOT( ) ( ) BIT BOOLEAN STD_LOGIC BIT_VECTOR STD_LOGIC_VECTOR 4-2 NOT 4-20 SIGNAL a b c : STD_LOGIC_VECTOR (3 DOWNTO 0) SIGNAL d e f g : STD_LOGIC_VECTOR (1 DOWNTO 0) SIGNAL h I j k : STD_LOGIC SIGNAL l m n o p : BOOLEAN... a<=b AND c ; -- b c a a b c -- 4 d<=e OR f OR g ; -- OR h<=(i NAND j)nand k -- NAND l<=(m XOR n)and(o XOR p); -- h<=i AND j AND k ; -- AND h<=i AND j OR k ; -- a<=b AND e ; -- b e h<=i OR l ; -- i STD_LOGIC l BOOLEAN 4-3 BIT 4-3 a b NOT a a AND b a OR b a XOR b a NAND b a NOR b a XNOR b TRUE 0 FALSE BOOLEAN ( STD_LOGIC_VECTOR) a b c d AND2 XOR OR2 e

95 4 VHDL a[0] output[0] b[0] a[1] output[1] 4-21 b[1] a[2] STD_LOGIC 4-22 output[2] b[2] a[3] output[3] STD_LOGIC_VECTOR 4-4 b[3] AND2 X LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY logical_ops_1 IS PORT (a b c d : IN STD_LOGIC ; E: OUT STD_LOGIC); END logical_ops_1 ; ARCHITECTURE example OF logical_ops_1 IS SIGNAL tmp: STD_LOGIC; e <= (a AND b) OR tmp; -- tmp <= c XOR d; -- END ARCHITECTURE example; 4-22 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY logical_ops_2 IS PORT ( a b : IN STD_LOGIC_VECTOR (0 TO 3) ; output : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END logical_ops_2 ; ARCHITECTURE example OF logical_ops_2 IS output <= a AND b ; END ARCHITECTURE example ; (BOOLEAN) TRUE FALSE VHDL 4-1 = ( ) /= ( ) > ( )

96 86 VHDL < ( ) >= ( ) <= ( ) VHDL VHDL a b (a= b) TRUE (a /= b) FALSE ( ) VHDL BOOLEAN TRUE TRUE < <= > >= VHDL '1' > '0' TRUE > FALSE a > b ( a=1 b=0) TO DOWNTO q (1011) (101011) (101011) 0 VHDL TRUE '1' = '1' "101" = "101" "1" > "011" "101" < "110" STD_LOGIC_ARITH UNSIGNED UNSIGNED UNSIGNED' "1" < UNSIGNED' "011" TRUE (= /=) 4-23 a[0] b[0] a[1] b[1] 4-24 a[2] b[2] 4 a[3] b[3] 4-23 = 4-24 >= XOR X 4 NOR a = b output

97 4 VHDL b[0] a[0] b[1] a[1] 87 b[2] a[2] b[3] a >= b output a[3] ENTITY relational_ops_1 IS PORT ( a b : IN BIT VECTOR (0 TO 3) ; m : OUT BOOLEAN) ; END relational_ops_1 ; ARCHITECTURE example OF relational_ops_1 IS output <= (a = b) ; END example ; 4-24 ENTITY relational_ops_2 IS PORT (a b : IN INTEGER RANGE 0 TO 3 ; m : OUT BOOLEAN) ; END relational_ops_2 ; ARCHITECTURE example OF relational_ops_2 IS output <= (a >= b) ; END example ;

98 88 VHDL (Adding operators) +( ) ( ) &( ) 2 (Multiplying operators) * / MOD REM 3 (Sign operators) +( ) ( ) 4 (Miscellaneous ** ABS 5 operators) (Shift operators) SLL SRL SLA SRA ROL ROR 1. VHDL VHDL 4 VHDL 4-25 VARIABLE a b c,d e,f : INTEGER RANGE 0 TO 255 ;... a := b + c ; d := e f ; PROCEDURE adding_e (a : IN INTEGER ; b : INOUT INTEGER ) IS... b := a + b ;... a[0] b[0] a[1] b[1] a[2] b[2] ( ) OR2 XOR AND4 XOR AND2 NOR NXOR NAND2 c[0] c[1] c[2]

99 4 VHDL PACKAGE example_arithmetic IS TYPE small_int IS RANGE 0 TO 7 ; END example_arithmetic ; USE WORK.example_arithmetic.ALL ; ENTITY arithmetic IS PORT (a b : IN SMALL_INT ; c : OUT SMALL_INT) ; END arithmetic ; ARCHITECTURE example OF arithmetic IS c <= a + b ; END example ; & VH & DL VHDL ;'0'&'1' SIGNAL a d : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL b c g : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL e : STD_LOGIC_VECTOR (2 DOWNTO 0) ; SIGNAL f h I : STD_LOGIC ;... a <= NOT b & NOT c ; -- 4 d <= NOT e & NOT f ; -- 4 g <= NOT h & i ; -- 2 a <= '1'&'0'&b(1)&e(2) ; -- 4 '0'&c <= e ; IF a & d = " " THEN... - IF 3. * ( ) / ( ) MOD( ) RED( ) VHDL ( )

100 90 VHDL + 1 ( 13 ) MOD RED 2 MOD RED 4-29 SIGNAL a b c d e f g h : INTEGER RANGE 0 TO 15 ; a <= b*4 ; -- a 15 c <= d/4 ; e <= f MOD 4 ; g <= h REM 4 ; 4-30 VARIABLE c : Real c:= * ( 234.4/43.89 ) ; -- c 0 15 (* / MOD REM) 2 2 ( ) MAX+plus II * / 2 x * 8 MAX+plus II LPM FUNDATION FPGA Express / MOD REM 2 * MAX+plus II MOD REM z := x*( y) 5. ** ABS VHDL (**) VHDL

101 SIGNAL a b : INTEGER RANGE 8 to 7 ; SIGNAL c : INTEGER RANGE 0 to 15 ; SIGNAL d : INTEGER RANGE 0 to 3 ; a <= ABS(b) ; c <= 2 ** d ; 4 VHDL 91 MAX+plus II ABS ** FUNDATION FPGA Express ** 2 6. (OTHERS => X ) SIGNAL d1,d2 e : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL f: STD_LOGIC_VECTOR(4 DOWNTO 0);... d1 < = (OTHERS = >'0'); d1 < = " ",,, (OTHERS => X ) OTHERS d2 < = (1 = >'1',4 = >'1', OTHERS = >'0'); d2 1 4 '1', '0' (OTHERS => X ) d2 : f < = (1 = > e(3),3 = > e(5), OTHERS = > e(1) ); ( a 5 ): f < = e(1) & e(5) & e(1) & e(3) & e(1) ; f < = f(4) & f(3) & f(2) & f(1) & f(0) ; (OTHERS => X) & 7. SLL SRL SLA SRA ROL ROR VHDL VHDL 93 BIT BOOLEAN EDA STD_LOGIC_VECTOR INTEGER INTEGER INTEGER SLL SRL SLL ROL

102 92 VHDL ROR SLA SRA VARIABLE shifta : STD_LOGIC_VECTOR(3 DOWNTO 0) := ('1','0','1','1'); shifta SLL 1 -- ('0' '1' '1' '0') -- 1 shifta SLL 3 -- ('1' '0' '0' '0') -- 3 shifta SLL 3 -- shifta SRL 3 shifta SRL 1 -- ('0' '1' '0' '1') shifta SRL 3 -- ('0' '0' '0' '1') shifta SRL 3 -- shifta SLL 3 shifta SLA 1 -- ('0' '1' '1' '1') shifta SLA 3 -- ('1' '1' '1' '1') shifta SLA 3 -- shifta SRA 3 shifta SRA 1 -- ('1' '1' '0' '1') shifta SRA 3 -- ('1' '1' '1' '1') shifta SRA 3 -- shifta SLA 3 shifta ROL 1 -- ('0' '1' '1' '1') shifta ROL 3 -- ('1' '1' '0' '1') shifta ROL 3 -- shifta ROR 3 shifta ROR 1 -- ('1' '1' '0' '1') shifta ROR 3 -- ('0' '1' '1' '1') shifta ROR 3 -- shifta ROL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY shift1 IS PORT ( a b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ; out1 out2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ) ; END shift1 ; ARCHITECTURE example OF shift1 IS out1 <= a SLL 2 ; out2 <= b ROL 2 END example ;

103 4 VHDL LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ; ENTITY shift1 IS PORT (a b : IN STD_LOGIC_VECTOR (7 DOWNTO 0 ) ; out1 out2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ) ; END shift1 ; ARCHITECTURE example OF shift1 IS out1 <= a(5 DOWNTO 0) & "00" ; out2 <= b(5 DOWNTO 0) & b(7 DOWNTO 6) END example; 4-35 SLL STD_LOGIC_UNSIGNED CONV_INTEGER LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS port ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0); output: OUT BIT_VECTOR (7 DOWNTO 0)); END decoder3to8; ARCHITECTURE behave OF decoder3to8 IS output <= " " SLL CONV_INTEGER(input); END behave; ( ) VHDL

104 94 VHDL STD_LOGIC_UNSIGNED Synopsys STD_LOGIC_ARITH STD_LOGIC_UNSIGNED STD_LOGIC_SIGNED SINGNED UNSIGNED STD_LOGIC INTEGER INTEGER STD_LOGIC STD_LOGIC_VECTOR VHDL 16 0FA 10 12F HC245 \74HC574\ CLR/RESET \IN 4/SCLK\ D (1) (2) (3) (4) + BIT BOOLEAN (5) VHDL (**) (6) = /= > < (7) AGE function CONV_INTEGER(ARG: AGE) return INTEGER; + SIGNAL a c : AGE;... c <= a + 20; A= [A15 A0] B=[B15 B0] D E F A=B D=1 A>B E=1 A<B F=1 4-6 VHDL

105 5 VHDL 95 5 VHDL (Sequential Statements) (Concurrent Statements) VHDL ( ) (Process) (Function) (Procedure) VHDL VHDL VHDL VHDL VHDL h h h h h h 5.1

106 96 5 VHDL VHDL <= = VHDL ( ) ( ) ( ) D VHDL ( 9 ) := <= SIGNAL s1,s2 : STD_LOGIC; SIGNAL svec : STD_LOGIC_VECTOR (0 TO 7);... PROCESS ( s1,s2 ) VARIABLE v1,v2 : STD_LOGIC

107 v1 := '1' ; v2 := '1' ; s1 <= '1' ; s2 <= '1' ; svec(0) <= v1; svec(1) <= v2; svec(2) <= s1; svec(3) <= s2; v1 := '0' ; v2 := '0' ; s2 <= '0' ; svec(4) <= v1; svec(5) <= v2; svec(6) <= s1; svec(7) <= s2; END PROCESS ; 97 5 VHDL -- v v s s v1 1 svec(0) -- v2 1 svec(1) -- s1 1 svec(2) -- s2 '0' svec(3) -- v v s2 -- '0' '1' -- v1 0 svec(4) -- v2 0 svec(5) -- s1 1 svec(6) -- s2 0 svec(7) VARIABLE a b STD_LOGIC ; SIGNAL c1 : STD_LOGIC_VECTOR (1 TO 4); a := '1' b := '0' c1 := "1100" a b c1 2. ( ) ( )

108 98 5 VHDL SIGNAL a b STD_LOGIC_VECTOR (0 TO 3); SIGNAL i INTEGER RANGE 0 TO 3 ; SIGNAL y z STD_LOGIC; a <= " 1010 " ; b <= " 1000 " ; a (I) <= y ; -- b (3) <= z ; ( 1 TO( DOWNTO) 2) TO DOWNTO VARIABLE a b STD_LOGIC_VECTOR (1 TO 4); a (1 TO 2) := "10" -- a(1) :='1' a(2) := '0' a (1 To 4) := " 1011" SIGNAL a, b, c, d STD_LOGIC SIGNAL s STD_LOGIC_VECTOR (1 TO 4);... VARIABLE e, f STD_LOGIC VARIABLE g STD_LOGIC_VECTOR (1 TO 2); VARIABLE h : STD_LOGIC_VECTOR (1 TO 4); s <= ('0' '1' '0' '0') (a, b, c, d) <= s ; (3=>e, 4=>f 2 =>g(1) 1=>g(2) ) := h -- a <= '0' b <= '1' c <= '0' d <= '0' g(2) = h(1) g(1) = h(2) e = h(3) f = h(4)

109 5 VHDL h IF h CASE h LOOP h NEXT h EXIT IF IF IF IF Then END IF IF Then ELSE END IF -- IF -- IF IF Then -- IF ELSIF Then... ELSE END IF IF BOOLEAN IF TRUE FALSE IF (TRUE) (THEN) END IF IF (FALSE) IF IF 5-6

110 k1 : IF (a>b) THEN output <= '1' ; END IF k1; 5 VHDL k1 (a>b) TRUE output 1 IF IF FALSE END IF ELSE IF IF IF FUNCTION and_func (x,y : IN BIT ) RETURN BIT IS IF x='1' AND y='1' THEN RETURN '1'; ELSE RETURN '0'; END IF END and_func ; IF BOOLEAN LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY control_stmts IS PORT (a, b, c: IN BOOLEAN; output: OUT BOOLEAN); END control_stmts; ARCHITECTURE example OF control_stmts IS PROCESS (a, b, c) VARIABLE n: BOOLEAN; IF a THEN n := b; ELSE n := c; END IF; output <= n; END PROCESS; END example; a

111 5 VHDL IF ELSIF ( ) c VHDL a 5-9 p1 p2 b output SIGNAL a, b, c, p1, p2, z : BIT ;... IF (p1 ='1') THEN z <= a ; -- (p1 ='1') ELSIF (p2 ='0') THEN z <= b ; -- (p1 ='0') AND (p2 ='0') ELSE z <= c ; -- (p1 ='0') AND (p2 ='1') END IF; IF IF-THEN-ELSIF LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY coder IS PORT ( din : IN STD_LOGIC_VECTOR(0 TO 7); output : OUT STD_LOGIC_VECTOR(0 TO 2) ); END coder; ARCHITECTURE behav OF coder IS SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0); PROCESS (din) IF (din(7)='0') THEN output <= "000" ; --(din(7)='0') ELSIF (din(6)='0') THEN output <= "100" ; --(din(7)='1')and(din(6)='0') ELSIF (din(5)='0') THEN

112 102 5 VHDL output <= "010" ; --(din(7)='1')and(din(6)='1')and(din(5)='0') ELSIF (din(4)='0') THEN output <= "110" ; ELSIF (din(3)='0') THEN output <= "001" ; ELSIF (din(2)='0') THEN output <= "101" ; ELSIF (din(1)='0') THEN output <= "011" ; ELSE output <= "111" ; END IF END PROCESS END behav; din0 din1 din2 din3 din4 din5 din6 din7 output0 output1 output2 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x VHDL 5-10 output <= "111" (in (7) ='1') AND (in (6) ='1') AND (in (5) ='1') AND (in (4) ='1') AND(in (3) ='1') AND (in (2) ='1') AND (in (1) ='1') AND (in (0) ='0' ) CASE CASE CASE CASE IS When => When =>... END CASE CASE

113 5 VHDL CASE ( => THEN ) [ ] h 4 h (2 TO 4) h h CASE (1) (2) CASE OTHERS OTHERS OTHERS STD_LOGIC STD_LOGIC_VECTOR 1 0 Z X (3) CASE (4) CASE CASE 5-11 CASE 4 1 VHDL 5-11 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux41 IS PORT (s1, s2 : IN STD_LOGIC; a, b, c, d : IN STD_LOGIC; z : OUT STD_LOGIC); END ENTITY mux41 ARCHITECTURE activ OF mux41 IS SIGNAL s : STD_LOGIC_VECTOR (1 DOWNTO 0); s <= s1 & s2 ; PROCESS (s, a, b, c, d) - s s1 s2 CASE s IS WHEN "00" => z<= a ; WHEN "01" => z<= b ; 103

114 104 5 VHDL WHEN "10" => z<= c ; WHEN "11" => z<= d ; WHEN OTHERS => z<= 'X' ;-- X END CASE END PROCESS End activ s1 s2 d c b a D C B A S1 S z 5-11 STD_LOGIC_VECTOR s VHDL STD_LOGIC 5-3 WHEN OTHERS => z<= 'X' X STD_LOGIC IF CASE LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux41 IS PORT (s4 s3, s2 s1 : IN STD_LOGIC; z4 z3, z2 z1 : OUT STD_LOGIC); END mux41 ARCHITECTURE activ OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; PROCESS (sel s4 s3 s2 s1 ) sel<= 0 ; -- IF (s1 ='1') THEN sel <= sel+1 ; ELSIF (s2 ='1') THEN sel <= sel+2 ; ELSIF (s3 ='1') THEN sel <= sel+4 ; ELSIF (s4 ='1') THEN sel <= sel+8 ; ELSE NULL; -- END IF ; z1<='0' ; z2<='0'; z3<='0'; z4<='0'; -- CASE sel IS WHEN 0 => z1<='1' ; -- sel=0 WHEN 1 3 => z2<='1' ; -- sel 1 3 WHEN 4 To 7 2 => z3<='1'; -- sel WHEN OTHERS => z4<='1' ; -- sel 8 15 END CASE

115 END PROCESS END activ 5 VHDL IF-THEN-ELSIF s4 s3 s2 s1 4 sel 5-13 CASE 5-13 SIGNAL value : INTEGER RANGE 0 TO 15; SIGNAL out1 : STD_LOGIC ;... CASE value IS -- WHEN END CASE... CASE value IS WHEN 0 => out1<= '1' ; -- value2 15 WHEN 1 => out1<= '0' ; END CASE... CASE value IS WHEN 0 TO 10 => out1<= '1'; WHEN 5 TO 15 => out1<= '0'; END CASE IF CASE CASE IF CASE CASE IF CASE IF IF-THEN-ELSLF ( ) CASE 5-14 VHDL opcode CASE IF-THEN 5-14 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY alu IS PORT( a, b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR (1 DOWNTO 0); result: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END alu; ARCHITECTURE behave OF alu IS CONSTANT plus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"00"; CONSTANT minus : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"01"; CONSTANT equal : STD_LOGIC_VECTOR (1 DOWNTO 0) := b"10";

116 106 5 VHDL CONSTANT not_equal: STD_LOGIC_VECTOR (1 DOWNTO 0) := b"11"; PROCESS (opcode,a,b) CASE opcode IS WHEN plus => result <= a + b; -- a b WHEN minus => result <= a - b; -- a b WHEN equal => -- a b IF (a = b) THEN result <= x"01"; ELSE result <= x"00"; END IF; WHEN not_equal => -- a b IF (a /= b) THEN result <= x"01"; ELSE result <= x"00"; END IF; END CASE; END PROCESS; END behave; LOOP LOOP LOOP (1) LOOP [ LOOP ] LOOP END LOOP [ LOOP ] ( EXIT ) LOOP L2 : LOOP a := a+1; EXIT L2 WHEN a >10 ; END LOOP L2; a 10 EXIT a>10 a := a+1 (2) FOR_LOOP [LOOP ] FOR IN LOOP END LOOP [LOOP ]

117 5 VHDL FOR LOOP LOOP LOOP LOOP VHDL 5-16 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY p_check IS PORT ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); y : OUT STD_LOGIC ); END p_check ARCHITECTURE opt OF p_check IS SIGNAL tmp STD_LOGIC PROCESS(a) tmp <='0'; FOR n IN 0 TO 7 LOOP tmp <= tmp XOR a(n); END LOOP ; y <= tmp; END PROCESS; END opt; 5-17 LOOP 5-17 SIGNAL a, b, c : STD_LOGIC_VECTOR (1 TO 3);... FOR n IN 1 To 3 LOOP a(n) <= b(n) AND c(n); END LOOP; a(1)<=b(1) AND c(1); a(2)<=b(2) AND c(2); a(3)<=b(3) AND c(3); LOOP LOOP (3) WHILE_LOOP 107

118 108 5 VHDL [ ] WHILE LOOP END LOOP [ ] FOR_LOOP WHILE_LOOP a=0 a>b TRUE FALSE END LOOP Shift1 : PROCESS (inputx) VARIABLE n : POSITIVE := 1; L1 : WHILE n<=8 LOOP -- <= outputx(n)<=inputx(n + 8) n := n+1; END LOOP L1; END PROCESS Shift1; a[0] a[1] a[2] a[3] out1[3] out1[2] out1[1] out1[0] WHILE_LOOP n 9 NEXT EXIT a[0] a[1] a[2] out1[2] out1[1] out1[0] ENTITY LOOP_stmt IS PORT (a: IN BIT_VECTOR (0 TO 3); out1: OUT BIT_VECTOR (0 TO 3)); END LOOP_stmt; ARCHITECTURE example OF LOOP_stmt IS PROCESS (a) VARIABLE b : BIT; b := '1';

119 5 VHDL FOR i IN 0 TO 3 LOOP b := a(3-i) AND b; out1(i) <= b; END LOOP; END PROCESS; END example; ENTITY while_stmt IS PORT (a: IN BIT_VECTOR (0 TO 3); out1: OUT BIT_VECTOR (0 TO 3)); END while_stmt; ARCHITECTURE example OF while_stmt IS PROCESS (a) VARIABLE b: BIT; VARIABLE i: INTEGER; i := 0; WHILE i < 4 LOOP b := a(3-i) AND b; out1(i) <= b; END LOOP; END PROCESS; END example; 5-20 WHILE_LOOP WHILE LOOP NEXT NEXT LOOP NEXT NEXT LOOP NEXT LOOP WHEN -- LOOP NEXT LOOP NEXT LOOP LOOP LOOP LOOP WHEN NEXT TRUE NEXT

120 110 5 VHDL LOOP NEXT WHEN LOOP L1 : FOR cnt_value IN 1 TO 8 LOOP s1 : a(cnt_value) := '0'; NEXT WHEN (b=c); s2 : a(cnt_value + 8 ):= '0'; END LOOP L1; 5-21 NEXT (b=c) TRUE NEXT L1 cnt_value 1 s1 s2 NEXT L_x : FOR cnt_value IN 1 TO 8 LOOP s1 : a(cnt_value):= '0'; k := 0; L_y : LOOP s2 : b(k) := '0'; NEXT L_x WHEN (e>f); s3 : b(k+8) := '0'; k := k+1; NEXT LOOP L_y ; NEXT LOOP L_x ; e>f TRUE NEXT L_x L_x cnt_value 1 s1 FALSE s3 k EXIT EXIT NEXT LOOP EXIT EXIT EXIT LOOP EXIT LOOP WHEN NEXT NEXT LOOP LOOP LOOP LOOP EXIT LOOP LOOP NEXT LOOP EXIT LOOP

121 5 VHDL 5-22 a b EXIT 5-23 SIGNAL a, b : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL a_less_then_b : Boolean;... a_less_then_b <= FALSE ; -- FOR i IN 1 DOWNTO 0 LOOP IF (a(i)='1' AND b(i)='0') THEN a_less_then_b <= FALSE ; -- a > b EXIT ; ELSIF (a(i)='0' AND b(i)='1') THEN a_less_then_b <= TRUE ; -- a < b EXIT; ELSE NULL; END IF; END LOOP; -- i=1 LOOP NULL ELSE a b 1 TRUE FALSE a b WAIT ( ) WAIT (Suspension) WAIT WAIT WAIT ON WAIT UNTIL -- WAIT FOR -- ( ) 5-24 WAIT 5-24 SIGNAL s1,s2 : STD_LOGIC;... PROCESS

122 WAIT ON s1,s2 END PROCESS 5 VHDL WAIT s1 s2 PROCESS VHDL WAIT WAIT (1) (2) WAIT 5-25 (a) (b) 5-25 (a) WAIT_UNTIL (b) WAIT_ON... LOOP Wait until enable ='1'; Wait on enable;... EXIT WHEN enable ='1'; END LOOP; 5-25 enable 1 enable 0 enable WAIT_UNTIL ( VHDL ) WAIT_UNTIL WAIT UNTIL =Value -- (1) WAIT UNTIL EVENT AND =Value; -- (2) WAIT UNTIL NOT STABLE AND =Value; -- (3) clock WAIT ( 5.7 ) WAIT UNTIL clock ='1'; WAIT UNTIL rising_edge(clock) ; WAIT UNTIL NOT clock STABLE AND clock ='1'; WAIT UNTIL clock ='1' AND clock EVENT; 5-26 a 4 4

123 PROCESS WAIT UNTIL clk ='1'; ave <= a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= ave + a; WAIT UNTIL clk ='1'; ave <= (ave + a)/4 ; END PROCESS ; 5 VHDL LOOP WAIT 5-27 PROCESS rst_loop : LOOP WAIT UNTIL clock ='1' AND clock EVENT; -- NEXT rst_loop WHEN (rst='1'); -- rst x <= a ; -- WAIT UNTIL clock ='1' AND clock EVENT; -- NEXT rst_loop When (rst='1'); -- rst y <= b ; -- END LOOP rst_loop ; END PROCESS; 5-27 rst WAIT DATA(0 TO 3) NEW_CORRECT_PARITY PARITY_OK 5-28 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY Pari IS PORT( CLOCK : IN STD_LOGIC; SET_PARITY : IN STD_LOGIC; NEW_CORRECT_PARITY : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR(0 TO 3); PARITY_OK : OUT BOOLEAN ); END Pari;

124 114 5 VHDL ARCHITECTURE behav OF Pari IS SIGNAL CORRECT_PARITY : STD_LOGIC; PROCESS(CLOCK) VARIABLE TEMP : STD_LOGIC; IF CLOCK EVENT AND CLOCK ='1' THEN IF SET_PARITY ='1' THEN First: CORRECT_PARITY <= NEW_CORRECT_PARITY; END IF; TEMP := '0'; FOR I IN DATA RANGE LOOP TEMP := TEMP XOR DATA(i); END LOOP; Second PARITY_OK <= (TEMP = CORRECT_PARITY); END IF; END PROCESS; END behav; RTL 5-28 NEW_CORRECT_PARITY SET_PARITY 5-7 WAIT D CORRECT_PARITY First PARITY_OK Second TEMP TEMP NEW_CORRECT_PARITY SET_PARITY D0 Q0 FD11 MUX21 A B O S DATA[0] DATA[3] DATA[1] DATA[2] CLOCK D0 Q0 FD11 PARITY_OK RTL 5-29 VHDL LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

125 115 5 VHDL ENTITY shifter IS PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); shift_left: IN STD_LOGIC; shift_right: IN STD_LOGIC; clk: IN STD_LOGIC; reset : IN STD_LOGIC; mode : IN STD_LOGIC_VECTOR (1 DOWNTO 0); qout : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) ); END shifter; ARCHITECTURE behave OF shifter IS SIGNAL enable: STD_LOGIC; PROCESS WAIT UNTIL (RISING_EDGE(clk) ); -- IF (reset = '1') THEN qout <= " "; ELSE CASE mode IS WHEN "01" => qout <= shift_right & qout(7 DOWNTO 1);-- WHEN "10" => qout <= qout(6 DOWNTO 0) & shift_left; -- WHEN "11" => qout <= data; -- WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END behave; WAIT 5.4 VHDL VHDL ( ) ( ) ( )

126 116 5 VHDL ( ) 1. [([ => ] { [ => ] }) ] (1) IN INOUT (2) (3) IN INOUT swap ( ) swap 5-30 PACKAGE data_types IS -- SUBTYPE data_element IS INTEGER RANGE 0 TO 3 -- TYPE data_array IS ARRAY (1 TO 3) OF data_element; END data_types USE WORK.data_types.ALL; -- data_types ENTITY sort IS PORT ( in_array : IN data_array ; out_array : OUT data_array); END sort; ARCHITECTURE exmp OF sort IS PROCESS (in_array) -- data_types PROCEDURE swap(data : INOUT data_array; -- swap data low high low, high : IN INTEGER ) IS VARIABLE temp : data_element ; -- IF (data(low) > data(high)) THEN --

127 117 5 VHDL temp := data(low) ; data(low) := data(high); data(high) := temp ; END IF END swap ; -- swap VARIABLE my_array : data_array ; -- my_array -- my_array := in_array ; -- swap(my_array, 1, 2); -- my_array 1 2 data low high swap(my_array, 2, 3); swap(my_array, 1, 2); out_array <= my_array ; END Process ; END exmp ; [4:5] in_array[2:7] [2:3] [2:7] [6:7] swap_temp4 < < [1:0] [4:5] 0 [1:0] [2:3] 1 [1:0] [6:7] 0 1 [1:0] [1:0] < [1:0] [1:0] 0 [1:0] 1 [1:0] [1:0] out_array_1[1:0] out_array[2:7] [2:3] 0 [1:0] [1:0] [1:0] 0 1 [1:0] out_array_2[1:0] [4:5] 1 [1:0] swap_data_3[1:0] [6:7] [1:0] 0 1 [1:0] RTL ENTITY sort4 is GENERIC (top : INTEGER :=3); PORT (a, b, c, d : IN BIT_VECTOR (0 TO top); ra, rb, rc, rd : OUT BIT_VECTOR (0 TO top)); END sort4; ARCHITECTURE muxes OF sort4 IS PROCEDURE sort2(x, y : INOUT BIT_VECTOR (0 TO top)) is VARIABLE tmp : BIT_VECTOR (0 TO top); IF x > y THEN tmp := x; x := y; y := tmp; END IF; END sort2; PROCESS (a, b, c, d)

128 118 5 VHDL VARIABLE va, vb, vc, vd : BIT_VECTOR(0 TO top); va := a; vb := b; vc := c; vd := d; sort2(va, vc); sort2(vb, vd); sort2(va, vb); sort2(vc, vd); sort2(vb, vc); ra <= va; rb <= vb; rc <= vc; rd <= vd; END PROCESS; END muxes; (RETURN) RETURN; RETURN END 5-31 RS REPORT 5-31 PROCEDURE rs (SIGNAL s, r : IN STD_LOGIC ; SIGNAL q, nq : INOUT STD_LOGIC) IS IF ( s ='1' AND r ='1') THEN REPORT "Forbidden state : s and r are quual to '1'"; RETURN ; ELSE q <= s AND nq AFTER 5 ns ; nq <= s AND q AFTER 5 ns ; END IF ; END PROCEDURE rs ; s r 1 IF RETURN

129 5 VHDL 5-32 opt opran opran a AND b a OR b 5-32 FUNCTION opt (a, b, opr :STD_LOGIC) RETURN STD_LOGIC IS IF (opr ='1') THEN RETURN (a AND b); ELSE RETURN (a OR b) ; END IF ; END FUNCTION opt ; opr a b rtn_valu 5-8 opt rtn_valu 5.6 (NULL) NULL NULL CASE NULL 5-33 CASE NULL 5-33 CASE Opcode IS WHEN "001" => tmp := rega AND regb ; WHEN "101" => tmp := rega OR regb ; WHEN "110" => tmp := NOT rega ; WHEN OTHERS => NULL ; END CASE ; CPU "001" "101" "110" CPU EDA MAXPLUS II NULL

130 120 5 VHDL NULL WHEN OTHERS => tmp := rega ; (ATTRIBUTE) VHDL VHDL h h h h h h VHDL ( ) VHDL ( ) 5-2 LEFT RIGHT HIGH LOW RANGE REVERS RANGE LENGTH EVENT STABLE ' EVENT clock EVENT clock δ clock IF BOOLEAN TRUE FALSE clock EVENT clock EVENT AND clock='1'

131 5 VHDL 5-2 LEFT[(n)] n RIGHT[(n)] n HIGH[(n)] n LOW[(n)] n LENGTH[(n)] ( ) n STRUCTURE[(n)] 'STURCTURE TRUE BEHAVIOR 'BEHAVIOR TRUE POS(value) value VAL(value) value SUCC(value) value PRED(value) value LEFTOF(value) value RIGHTOF(value) value EVENT TRUE FALSE ACTIVE TRUE FALSE LAST_EVENT LAST_VALUE LAST_ACTIVE DELAYED[(time)] STABLE[(time)] TRUE QUIET[(time)] TRUE TRANSACTION BIT ( 0 1 ) RANGE[(n)] n n REVERSE_RANGE[( n)] n n h 'LEFT 'RIGHT 'LENGTH 'LOW h 'POS 'VAL 'SUCC 'LEFTOF 'RIGHTOF h 'ACTIVE 'EVENT 'LAST_ACTIVE 'LAST_EVENT 'LAST_VALUE 121

132 122 5 VHDL h 'DELAYED 'STABLE 'QUIET 'TRANSACTION h 'RANGE 'REVERSE_RANGE clock clock TRUE δ clock 1 clock ='1' TRUE TRUE TRUE clock ='1' δ clock 0 clock PROCESS (clock) IF (clock EVENT AND clock ='1' ) THEN Q <= DATA ; END IF ; END PROCESS; 5-34 VHDL IF TRUE Q <= DATA Q clock (clock EVENT AND clock ='0') STABLE EVENT TRUE (NOT clock STABLE AND clock ='1') (clock EVENT AND clock ='1') NOT(clock STABLE AND clock ='1') VHDL BIT clock 1 0 clock EVENT AND clock ='1' clock STD_LOGIC (clock='1') = TRUE δ clock '0' RISING EDGE (clock) RISING EDGE ( ) VHDL IEEE

133 IF RISING EDGE (clock) THEN 5 VHDL WAIT UNTIL RISING EDGE (clock) 123 EVENT STABLE VHDL EVENT IF WAIT 2 'RANGE[(n)] 'REVERSE RANGE[(n)] 5-2 RANGE REVERSE RANGE SIGNAL range1 : IN STD LOGIC VECTOR (0 TO 7)... FOR i IN range1'range LOOP FOR LOOP FOR i IN 0 TO 7 LOOP range1 RANGE range1 REVERSE RANGE (7 DOWNTO 0) 3. VHDL LEFT RIGHT HIGH LOW PROCESS (clock, a, b); TYPE obj IS ARRAY (0 TO 15) OF BIT ; SIGNAL ele1, ele2, ele3, ele4: INTEGER ; ele1 <= obj RIGNT ; ele2 <= obj LEFT ; ele3 <= obj HIGH ; ele4 <= obj LOW ;... ele1 ele2 ele3 ele

134 124 5 VHDL 5-37 'LOW 'HIGH LIBRARY IEEE;--PARITY GENERATOR USE IEEE.STD_LOGIC_1164.ALL; ENTITY parity IS GENERIC (bus_size : INTEGER := 8 ); PORT (input_bus : IN STD_LOGIC_VECTOR(bus_size-1 DOWNTO 0); even_numbits, odd_numbits : OUT STD_LOGIC ) ; END parity ; ARCHITECTURE behave OF parity IS PROCESS (input_bus) VARIABLE temp: STD_LOGIC; temp := '0'; FOR i IN input_bus'low TO input_bus'high LOOP temp := temp XOR input_bus( i ) ; END LOOP ; odd_numbits <= temp ; even_numbits <= NOT temp; END PROCESS; END behave; 4 LENGTH TYPE arry1 ARRAY (0 TO 7) OF BIT VARIABLE wth: INTEGER;...

135 wth1: =arry1 LENGTH; -- wth1 = VHDL ATTRIBUTE : ; ATTRIBUTE OF : IS ; VHDL EDA Synplify synplify.attributes LIBRARY synplify; USE synplicity.attributes.all; DATA I/O VHDL pinnum 5-39 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cntbuf IS PORT( Dir: IN STD_LOGIC; Clk,Clr,OE: IN STD_LOGIC; A,B: INOUT STD_LOGIC_VECTOR (0 to 1); Q: INOUT STD_LOGIC_VECTOR (3 downto 0) ); ATTRIBUTE PINNUM : STRING; ATTRIBUTE PINNUM OF Clk: signal is "1"; ATTRIBUTE PINNUM OF Clr: signal is "2"; ATTRIBUTE PINNUM OF Dir: signal is "3"; ATTRIBUTE PINNUM OF OE: signal is "11"; ATTRIBUTE PINNUM OF A: signal is "13,12"; ATTRIBUTE PINNUM OF B: signal is "19,18"; ATTRIBUTE PINNUM OF Q: signal is "17,16,15,14"; END cntbuf; Synopsys FPGA Express synopsys.attributes VHDL (TEXTIO) VHDL IC VHDL

136 126 5 VHDL VHDL VHDL STD.TEXTIO STD.TEXTIO VHDL VHDL ModelSim STD.TEXTIO type LINE is access string; type TEXT is file of string; type SIDE is (right, left); subtype WIDTH is natural; file input : TEXT open read_mode is "STD_INPUT"; file output : TEXT open write_mode is "STD_OUTPUT"; STD.TEXTIO READ READLINE WRITE WRITELINE VHDL STD.TEXTIO component counter8 port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; D N: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end component;... file RESULTS: TEXT open WRITE_MODE is "results.txt";... procedure WRITE_RESULTS ( CLK : STD_LOGIC; RESET : STD_LOGIC; CE : STD_LOGIC; LOAD : STD_LOGIC; DIR : STD_LOGIC; DIN : INTEGER;

137 5 VHDL COUNT : INTEGER ) is variable V_OUT : LINE; begin -- write(v_out, now, right, 16, ps); write(v_out, CLK, right, 2); write(v_out, RESET, right, 2); write(v_out, CE, right, 2); write(v_out, LOAD, right, 2); write(v_out, DIR, right, 2); write(v_out, DIN, right, 257); -- write(v_out, COUNT, right, 257); writeline(results,v_out); end WRITE_RESULTS; VHDL WRITE_RESULTS results.txt ASSERT ASSERT( ) VHDL ASSERT TRUE FALSE ASSERT REPORT SEVERITY [SEVERITY_LEVEL] 5-41 ASSERT NOT (S= '1' AND R= '1') REPORT "Both values of signals S and R are equal to '1'" SEVERITY ERROR; SEVERITY SEVERITY_LEVEL SEVERITY_LEVEL NOTE WARNING ERROR FAILURE ASSERT

138 128 5 VHDL ASSERT REPORT REPORT ASSERT REPORT ; REPORT SEVERITY SEVERITY_LEVEL; 5-42 WHILE counter <= 100 LOOP IF counter > 50 THEN REPORT "the counter is over 50"; END IF;... END LOOP; VHDL 1993 REPORT ASSERT FALSE ASSERT 1987 REPORT (Resolution) 5-43 package RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT; subtype RESOLVED_BIT is RES_FUNC BIT; end; package body RES_PACK is function RES_FUNC(DATA: in BIT_VECTOR) return BIT is begin for I in DATA'range loop if DATA(I) = '0' then return '0'; end if; end loop; return '1'; end; end; USE work.res_pack.all; ENTITY WAND_VHDL is PORT(X, Y: in BIT; Z: out RESOLVED_BIT); END WAND_VHDL;

139 5 VHDL ARCHITECTURE WAND_VHDL OF WAND_VHDL IS begin Z <= X; Z <= Y; end WAND_VHDL; 129 VHDL VHDL 1 Signal A, EN : std_logic; Process (A, EN) Variable B : std_logic; Begin if EN = 1 then B <= A; end if; end process; 2 Architecture one of sample is variable a, b, c : integer; begin c <= a + b; end; 3 library ieee; use ieee.std_logic_1164.all; entity mux21 is port ( a, b : in std_logic; sel : in std_logic; c : out std_logic;); end sam2; architecture one of mux21 is begin if sel = '0' then c := a; else c := b; end if; end two; (1) (2)

140 130 5 VHDL (3) ASSERT (4) VHDL (5) (6) 5-4 CASE IF WAIT f_adder cin cout VHDL M1 M0 (M1 M0) (0 0) 19 (M1 M0) (0 1) 4 (M1 M0) (1 0) 10 (M1 M0) (1 1)

141 6 VHDL VHDL VHDL VHDL VHDL 6-1 h Concurrent Signal Assignments h (Process Statements) h (Block Statements)

142 132 VHDL h (Selected Signal Assignments h (Component Instantiations) h (Generate Statements) h (Concurrent Procedure Calls) ARCHITECTURE OF IS END ARCHITECTURE VHDL 6.1 VHDL VHDL VHDL VHDL

143 6 VHDL IF WAIT in1(3 DOWNTO 0) 1 out1(3 DOWNTO 0) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt10 IS PORT clr : IN STD_LOGIC; in1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); out1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END cnt10 ARCHITECTURE actv OF cnt10 IS PROCESS in1 clr IF (clr ='1' OR in1 = "1001") THEN out1 <= "0000" ; -- 9 out1 0 ELSE -- 1 out1 <= in1 + 1 ; END IF -- STD_LOGIC_UNSIGNED END PROCESS ; END actv ; 133 in1[0] in1[1] in1[2] in1[3] clr NOT AND4 OR2 ADDER ADDER41 A0 S0 A1 S1 A2 S2 A3 S3 B0 VCC S0=0 : => Z[3..0] = A[3..0) S0=1 : => Z[3..0] = B[3..0] 1 0 A0 A1 A2 A3 B0 B1 B2 B3 S0 Z0 Z1 Z2 Z3 MUX42 out1[0] out1[1] out1[2] out1[3] cnt ADDER 1 4 A(3 DOWNTO 0)+B0=S(3 DOWNTO 0) B0=1 MUX

144 134 VHDL WAIT LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cnt10 IS PORT ( clr : IN STD_LOGIC ; Clk : IN STD_LOGIC ; Cnt : Buffer STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END cnt10 ARCHITECTURE actv OF cnt10 IS PROCESS WAIT UNTIL clk'event AND clk = '1' ; -- clk IF ( clr ='1' OR cnt = 9 ) THEN cnt <= "0000" ; ELSE cnt <= cnt+ 1 ; END IF ; END PROCESS ; END actv ; D0 Q0 out1[0] clr NOT AND4 OR2 ADDER ADDER41 A0 S0 A1 S1 A2 S2 A3 S3 B0 VCC S0=0 : => Z[3..0] = A[3..0) S0=1 : => Z[3..0] = B[3..0] 1 0 A0 A1 A2 A3 B0 B1 B2 B3 S0 Z0 Z1 Z2 Z3 MUX42 FD11 D0 Q0 FD11 D0 Q0 FD11 D0 Q0 out1[1] out1[2] out1[3] clk FD cnt10 ( 4 D ) D 1

145 6 VHDL 4 4 D BUFFER b1 a1 6-3 inc 4 NOR2 clk rst rst NOT NAND2 s0 clk current_state current_state PACKAGE mtype IS TYPE state_t IS (s0, s1, s2, s3); -- END mtype; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE WORK.mtype.ALL; -- ENTITY s4_machine IS PORT(clk, inc, a1, b1 : IN STD_LOGIC ; rst : IN BOOLEAN ; out1: OUT STD_LOGIC) ; END ENTITY s4_machine; ARCHITECTURE activ OF s4_machine IS SIGNAL current_state, next_state: state_t ; sync: PROCESS(clk, rst) -- IF (rst) THEN -- current_state <= s0; ELSIF (clk EVENT AND clk ='1') THEN -- current_state <= next_state; END IF; END PROCESS sync; fsm: PROCESS(inc current_state, a1, b1) -- out1 <= a1; D_FF D D C C Q Q MUX21 S B A out1 NAND

146 136 VHDL next_state <= s0; IF (inc = '1') THEN CASE current_state IS WHEN s0 => next_state <= s1; WHEN s1 => next_state <= s2; out1 <= b1; WHEN s2 => next_state <= s3; WHEN s3 => NULL ; END CASE; END IF; END PROCESS fsm; END activ; a_out <= a WHEN (ena) ELSE 'Z' ; b_out <= b WHEN (enb) ELSE 'Z' ; c_out <= c WHEN (enc) ELSE 'Z' ; PRO1 PROCESS (a_out) bus_out <= a_out ; END PROCESS ; PRO2 PROCESS (b_out) bus_out <= b_out ; END PROCESS ; PRO3 PROCESS (c_out) bus_out <= c_out ; END PROCESS ; ena enb enc a b c 9 9- a_out OT11 b_out OT c_out OT11 bus_out

147 6 VHDL a y b c z d b1 : BLOCK SIGNAL s : BIT ; s <= a AND b ; b2 : BLOCK SIGNAL s : BIT ; s <= c AND d ; b3 : BLOCK z <= s ; END BLOCK b3 ; END BLOCK b2 ; y <= s ; END BLOCK b1; -- b1 -- b1 s -- b1 s -- b2 b1 -- b2 s -- b2 s -- s b2 -- s b

148 138 VHDL 6.3 h h h VHDL <= ARCHITECTURE curt OF bc1 IS SIGNAL s1 : STD_LOGIC ; output1 <= a AND b ; output2 <= c + d ; B1 : BLOCK SIGNAL e, f, g, h : STD_LOGIC ; g <= e OR f ; h <= e XOR f ; END BLOCK B1 s1 <= g ; END ARCHITECTURE curt 6.3.2

149 <= WHEN ELSE WHEN ELSE... 6 VHDL 139 IF = TRUE IF ELSE WHEN CASE z <= a WHEN p1 = '1' ELSE b WHEN p2 = '1' ELSE c ;... p1 p2 1 z a WITH SELECT <= WHEN WHEN... WHEN CASE CASE CASE WITH CASE

150 140 VHDL a b c data1 data2 dataout 6-8 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder IS PORT ( a b c : IN STD_LOGIC; data1 data2 : IN STD_LOGIC; dataout : OUT STD_LOGIC ); END decoder; ARCHITECTURE concunt OF decoder IS SIGNAL instruction : STD_LOGIC_VECTOR(2 DOWNTO 0) instruction <= c & b & a ; WITH instruction SELECT dataout <= data1 AND data2 WHEN "000" data1 OR data2 WHEN "001" data1 NAND data2 WHEN "010" data1 NOR data2 WHEN "011" data1 XOR data2 WHEN "100" data1 XNOR data2 WHEN "101" 'Z' WHEN OTHERS ; END concunt ; a b c data1 6-9 data DECODER WITH selt SELECT muxout <= a WHEN 0 1, b WHEN 2 TO 5, DECODER a b c d_out d1 d2 dataout

151 ... 6 VHDL c WHEN 6, d WHEN 7, 'Z' WHEN OTHERS ; PROCEDURE adder(signal a, b :IN STD_LOGIC ; -- adder SIGNAL sum : OUT STD_LOGIC );... adder(a1 b1 sum1) ; a1 b1 sum1 a b sum PROCESS( c1 c2) ; -- Adder(c1 c2 s1) ; -- c1 c2 s1 END PROCESS ; -- a b sum check 1 check error TRUE 6-11 PROCEDURE check(signal a : IN STD_LOGIC_VECTOR; -- SIGNAL error : OUT BOOLEAN ) IS -- VARIABLE found_one : BOOLEAN := FALSE ; -- FOR i IN a'range LOOP -- a IF a(i) = '1' THEN -- a '1' IF found_one THEN -- found_one TRUE '1' ERROR <= TRUE; -- '1' found_one TRUE

152 142 VHDL RETURN; -- END IF; Found_one := TRUE; -- a '1' End IF; End LOOP; -- a error <= NOT found_one; -- '1' error TRUE END PROCEDURE check CHBLK BLOCK SIGNAL s1: STD_LOGIC_VECTOR (0 TO 0); -- SIGNAL s2: STD_LOGIC_VECTOR (0 TO 1); SIGNAL s3: STD_LOGIC_VECTOR (0 TO 2); SIGNAL s4: STD_LOGIC_VECTOR (0 TO 3); SIGNAL e1, e2, e3, e4: Boolean; Check (s1, e1); -- s1 e1 Check (s2, e2); -- s2 e2 Check (s3, e3); -- s3 e3 Check (s4, e4); END BLOCK; s4 e4 s2[1] s2[0] s3[0] s3[2] s3[1] e2 e3 s4[0] s4[1] s4[2] s4[3] s1[0] e4 e1 6-8 CHBLK 6-8

153 6 VHDL VHDL VHDL FPGA Verilog IP FPGA IP COMPONENT IS GENERIC PORT END COMPONENT -- PORT MAP [ =>] PORT MAP

154 144 VHDL => PORT MAP PORT MAP 6-13/14 u1 a x 2 b 6-9 u2 3 c y 6-13 d ord LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY nd2 IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END nd2; ARCHITECTURE nd2behv OF nd2 IS y <= a NAND b; END nd2behv ; 6-14 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY ord41 IS PORT ( a1 b1 c1 d1 : IN STD_LOGIC; z1 : OUT STD_LOGIC ); END ord41; ARCHITECTURE ord41behv OF ord41 IS COMPONENT nd2 PORT ( a, b : IN STD_LOGIC ; c : OUT STD_LOGIC) ; END COMPONENT ; SIGNAL x, y : STD_LOGIC ; u1 : nd2 PORT MAP (a1, b1, x) ; -- u2 : nd2 PORT MAP (a => c1, c => y, b => d1); -- u3 : nd2 PORT MAP (x, y, c => z1) ; -- END ARCHITECTURE ord41behv u3 z

155 6 VHDL GENERIC map PORT MAP( ) PORT MAP( ) GENERIC 6-15 addern adders 6-10 addern addern 16 U1 U2 addern LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY addern IS PORT (a, b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END addern; ARCHITECTURE behave OF addern IS result <= a + b; END; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY adders IS GENERIC(msb_operand: INTEGER := 15; msb_sum: INTEGER :=15); PORT(b: IN STD_LOGIC_VECTOR (msb_operand DOWNTO 0); result: OUT STD_LOGIC_VECTOR (msb_sum DOWNTO 0)); END adders; ARCHITECTURE behave OF adders IS COMPONENT addern PORT ( a, b: IN STD_LOGIC_VECTOR; result: OUT STD_LOGIC_VECTOR); END COMPONENT; SIGNAL a: STD_LOGIC_VECTOR (msb_sum /2 DOWNTO 0);

156 146 VHDL SIGNAL twoa: STD_LOGIC_VECTOR (msb_operand DOWNTO 0); twoa <= a & a; U1: addern PORT MAP (a => twoa, b => b, result => result); U2: addern PORT MAP (a=>b(msb_operand downto msb_operand/2 +1), b=>b(msb_operand/2 downto 0), result => a); END behave; [ ] FOR IN GENERATE END GENERATE [ ] [ ] IF GENERATE Begin END GENERATE [ ] (1) FOR IF (2) (3) Copy

157 6 VHDL (4) FOR LOOP FOR LOOP 147 TO DOWNTO -- 1 TO DOWNTO VHDL ATTRIBUTE RANGE COMPONENT comp PORT (x : IN STD_LOGIC y : OUT STD_LOGIC ); END COMPONENT ; SIGNAL a, b : STD_LOGIC_VECTOR (0 TO 7)... gen : FOR i IN a RANGE GENERATE u1: comp PORT MAP (x => a(i) y => b(i) ) ; END GENERATE gen,... FOR_GENERATE 8 a[0] COMP INPUT OUTPUT b[0] a[1] a[7] COMP INPUT OUTPUT... COMP INPUT OUTPUT b[1] b[7] LS373/74HC D1 D8 Q1 Q8 OEN

158 148 VHDL OEN=1 Q8 Q1 OEN=0 Q8~Q1 G G=1 D8 D G= Latch latch.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SN74373 IS -- SN74373 PORT (D : IN STD_LOGIC_VECTOR( 8 DOWNTO 1 ); -- 8 OEN : IN STD_LOGIC; G : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(8 DOWNTO 1)); -- 8 END ENTITY SN74373; ARCHITECTURE one OF SN74373 IS COMPONENT Latch PORT ( D, ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT; SIGNAL sig_mid : STD_LOGIC_VECTOR( 8 DOWNTO 1 ); GeLatch : FOR inum IN 1 TO 8 GENERATE FOR_GENERATE Latchx : Latch PORT MAP(D(iNum),G,sig_mid(iNum)); -- END GENERATE; Q <= sig_mid WHEN OEN =0 ELSE -- "ZZZZZZZZ"; -- OEN=1 Q(8)~Q(1) END ARCHITECTURE one; ARCHITECTURE two OF SN74373 IS SIGNAL sigvec_save : STD_LOGIC_VECTOR(8 DOWNTO 1); PROCESS(D, OEN, G sigvec_save) IF OEN = '0' THEN Q <= sigvec_save; ELSE Q <= "ZZZZZZZZ"; END IF; IF G = '1' THEN Sigvec_save <= D; END IF; END PROCESS; END ARCHITECTURE two IF (1)

159 6 VHDL VHDL two ARCHITECTURE two ARCHITECTURE one 2-2 ENTITY Latch (2) COMPONENT 2-2 ENTITY Latch VHDL COMPONENT COMPONENT Latch Latch one COMPONENT VHDL VHDL Latch (3) FOR_GENERATE GeLatch inum 1~8 8 (4) Latchx : Latch PORT MAP ( D(iNum), G, sig_mid(inum) ); inum D2 D Q Latchx Latch D D(iNum) ENA G Q sig_mid(inum) inum 1~8 Latch 1~8 8 8 Latch D(1)~D(8) sig_mid(1) ~sig_mid(8) 8 Latch 6-17 one 6-12 D7 D D8 D FOR_GENERATE OEN D LATCH D Q ENA LATCH LATCH D Q ENA LATCH D Q ENA LATCH LATCH D1 D3 D4 D5 D6 G FOR_GENERATE 6-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff IS PORT ( d, clk_s : IN STD_LOGIC ; q : OUT STD_LOGIC ; ENA LATCH D Q ENA LATCH D ENA ENA ENA Q Q Q OT11 OT11 OT11 OT11 OT11 OT11 OT11 OT11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q SN74373

160 150 VHDL nq : OUT STD_LOGIC ); END ENTITY d_ff; ARCHITECTURE a_rs_ff OF d_ff IS bin_p_rs_ff : PROCESS(CLK_S) IF clk_s = '1' AND clk_s'event THEN q <= d ; nq <= NOT d; END IF; END PROCESS; END ARCHITECTURE a_rs_ff; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY cnt_bin_n is GENERIC (n : INTEGER := 4); PORT (q : OUT STD_LOGIC_VECTOR (0 TO n-1); in_1 : IN STD_LOGIC ); END ENTITY cnt_bin_n; ARCHITECTURE behv OF cnt_bin_n IS COMPONENT d_ff PORT(d, clk_s : IN STD_LOGIC; Q, NQ : OUT STD_LOGIC); END COMPONENT d_ff; SIGNAL s : STD_LOGIC_VECTOR(0 TO n); s(0) <= in_1; q_1 : FOR i IN 0 TO n-1 GENERATE dff : d_ff PORT MAP (s(i+1), s(i), q(i), s(i+1)); END GENERATE; END ARCHITECTURE behv; q0 q1 i=0 i=1 D0 Q0 D0 Q0 clk clk s(0) FD11 s(1) nq... qn-1 i=n-1 D0 Q0 clk FD11 FD11 s(2) s(n) nq nq 6-14 n IF_GENERATE IF_GENERATE FOR_GENERATE

161 6 VHDL 6-14 n n D n FOR_GENERATE IF_GENERATE 6-18 VHDL 6-1 CASE WITH_SELECT 6-2 WHEN_ELSE PROCESS a b c d IF a= '0' AND b='1' THEN next1 <= "1101" ELSIF a='0' THEN next1 <= d ELSIF b='1' THEN next1 <= c ELSE Next1 <= "1011" END IF END PROCESS 6-3 VHDL ARCHITECTURE one OF com1 VARIABLE a b c clock STD_LOGIC ; pro1 PROCESS IF NOT clock ' EVENT AND clock = '1' THEN x <= a xor b or c END IF; END PROCESS; END; 6-4 VHDL WITH_SELECT_WHEN STD_LOGIC_UNSIGNED VHDL (1) h_suber diff s_out sub_in (2) 6-1 (3) 1 8 ( x y - sun_in = diffr) 151

162 152 VHDL X y sub_in diffr sub_out D VHDL

163 7 VHDL VHDL VHDL VHDL RTL RTL VHDL 7.1 VHDL VHDL ABEL-HDL 7-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY cunter_up IS PORT( reset, clock : IN STD_LOGIC; counter : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END; ARCHITECTURE behv of cunter_up IS

164 154 VHDL SIGNAL cnt_ff: UNSIGNED(7 DOWNTO 0); PROCESS (clock,reset,cnt_ff) IF reset='1' THEN cnt_ff <= X"00" ; ELSIF (clock='1' AND clock'event) THEN cnt_ff <= cnt_ff + 1 ; END IF; END PROCESS; counter <= STD_LOGIC_VECTOR(cnt_ff); END ARCHITECTURE behv 7-2 MODULE counter_up Clock,reset, PIN ; Counter7..counter0 PIN ISTYPE 'COM' ; Cnt_ff7..cnt_ff0 NODE ISTYPE 'REG' ; Counter = [counter7..counter0]; Cnt = [cnt_ff7..cnt_ff0]; EQUATIONS Cnt.CLK = clock ; Cnt.AR = reset ; Cnt := cnt.fb + 1 ; Counter = cnt ; END counter_up ABEL-HDL 8 'REG' 8 'COM' cnt.clk = clcok CLK cnt 8 clock cnt.ar = reset reset cnt AR cnt := cnt.fb + 1.FB 1 cnt 7-2 PLD ABEL 7-1

165 7 VHDL ABEL- HDL ELSIF (clock ='1' AND clock EVENT) THEN VHDL VHDL 7-2 cnt.clk=clock ABEL-HDL VHDL VHDL VHDL VHDL VHDL VHDL Verilog-HDL RTL VHDL VHDL VHDL VHDL VHDL VHDL Cadence Synplicity Synopsys Viewlogic EDA VHDL RTL RTL RTL VHDL RTL

166 156 VHDL ENTITY \74LS18\ IS PORT( I0_A, I0_B, I1_A, I1_B, I2_A : IN STD_LOGIC; I2_B I3_A I3_B : IN STD_LOGIC; O_A : OUT STD_LOGIC; O_B : OUT STD_LOGIC ); END \74LS18\; ARCHITECTURE model OF \74LS18\ IS O_A <= NOT ( I0_A AND I1_A AND I2_A AND I3_A ) AFTER 55 ns ; O_B <= NOT ( I0_B AND I1_B AND I2_B AND I3_B ) AFTER 55 ns ; END model; 7.3 VHDL VHDL VHDL 7-4 ARCHITECTURE STRUCTURE OF COUNTER3 IS COMPONENT DFF PORT(CLK, DATA: IN BIT; Q: OUT BIT); END COMPONENT; COMPONENT AND2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT OR2 PORT(I1, I2: IN BIT; O: OUT BIT);

167 7 VHDL END COMPONENT; COMPONENT NAND2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT XNOR2 PORT(I1, I2: IN BIT; O: OUT BIT); END COMPONENT; COMPONENT INV PORT(I: IN BIT; O: OUT BIT); END COMPONENT; SIGNAL N1, N2, N3, N4, N5, N6, N7, N8, N9: BIT; u1: DFF PORT MAP(CLK, N1, N2); u2: DFF PORT MAP(CLK, N5, N3); u3: DFF PORT MAP(CLK, N9, N4); u4: INV PORT MAP(N2, N1); u5: OR2 PORT MAP(N3, N1, N6); u6: NAND2 PORT MAP(N1, N3, N7); u7: NAND2 PORT MAP(N6, N7, N5); u8: XNOR2 PORT MAP(N8, N4, N9); u9: NAND2 PORT MAP(N2, N3, N8); COUNT(0) <= N2; COUNT(1) <= N3; COUNT(2) <= N4; END STRUCTURE; 157 VHDL VHDL VHDL EDA EDA VHDL EDA EDA VHDL 7-1 VHDL 7-2 VHDL 7-3 VHDL

168 158 VHDL 8 Simulation VHDL VHDL EDA FPGA VHDL VHDL VHDL VHDL EDA SRAM FPGA VHDL VHDL VHDL VHDL VHDL EDA

169 8 159 VHDL VHDL VHDL VHDL VHDL VHDL (1) DEBUG ModelSim Active-VHDL VHDL (2) C VHDL VHDL VHDL VHDL VHDL VHDL Mentor Graphics Renoir Xilinx Foundation Series EDA VHDL VHDL VHDL VHDL VHDL

170 160 VHDL VHDL VHDL LIBRARY USE VHDL VHDL VHDL FPGA/CPLD PLD VHDL VHDL VHDL VHDL VHDL VHDL VHDL REPORT ASSERT VHDL EDA VHDL VHDL MAX+PLUSII SNF PC VHDL Model Technology ModelSim Aldec Active-VHDL ModelSim V-System/ Windows Windows 8-1 VHDL EDA MAX+PLUSII EPF10K10LC84 MAX+PLUSII SNF VHDL 8-2 EPF10K10LC VHDL 8-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and1 IS PORT(aaa,bbb : IN STD_LOGIC; ccc: OUT STD_LOGIC); END and1; ARCHITECTURE one OF and1 IS ccc <= aaa AND bbb; END;

171 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY TRIBUF_and1 IS GENERIC ( ttri: TIME := 1 ns; ttxz: TIME := 1 ns; ttzx: TIME := 1 ns); PORT ( in1 : IN std_logic; oe : IN std_logic; y : OUT std_logic); END TRIBUF_and1; ARCHITECTURE behavior OF TRIBUF_and1 IS PROCESS (in1, oe) IF oe'event THEN IF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttzx; END IF; ELSIF oe = '1' THEN y <= TRANSPORT in1 AFTER ttri; ELSIF oe = '0' THEN y <= TRANSPORT 'Z' AFTER ttxz; END IF; END PROCESS; END behavior; LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE work.tribuf_and1; ENTITY and1 IS PORT ( aaa : IN std_logic; bbb : IN std_logic; ccc : OUT std_logic); END and1; ARCHITECTURE EPF10K10LC84_a3 OF and1 IS SIGNAL gnd : std_logic; SIGNAL vcc : std_logic; SIGNAL n_8, n_9, n_10, n_11, n_12, a_a4_aout, n_14, n_15, n_16, n_17, n_18, n_20, n_22 : std_logic; COMPONENT TRIBUF_and1 GENERIC (ttri, ttxz, ttzx: TIME); PORT (in1, oe : IN std_logic; y : OUT std_logic); END COMPONENT;

172 162 VHDL gnd <= '0'; vcc <= '1'; PROCESS(aaa, bbb) ASSERT aaa /= 'X' OR Now = 0 ns REPORT "Unknown value on aaa" SEVERITY Warning; ASSERT bbb /= 'X' OR Now = 0 ns REPORT "Unknown value on bbb" SEVERITY Warning; END PROCESS; TRIBUF_2: TRIBUF_and1 GENERIC MAP (ttri => 2600 ps, ttxz => 4500 ps, ttzx => 4500 ps) PORT MAP (IN1 => n_8, OE => vcc, Y => ccc); DELAY_3: n_8 <= TRANSPORT n_9; XOR2_4: n_9 <= n_10 XOR n_14; OR1_5: n_10 <= n_11; AND1_6: n_11 <= n_12; DELAY_7: n_12 <= TRANSPORT a_a4_aout AFTER 2500 ps; AND1_8: n_14 <= gnd; DELAY_9: a_a4_aout <= TRANSPORT n_15 AFTER 500 ps; XOR2_10: n_15 <= n_16 XOR n_22; OR1_11: n_16 <= n_17; AND2_12: n_17 <= n_18 AND n_20; DELAY_13: n_18 <= TRANSPORT bbb AFTER 4800 ps; DELAY_14: n_20 <= TRANSPORT aaa AFTER 4300 ps; AND1_15: n_22 <= gnd; END EPF10K10LC84_a3; VHDL VHDL VHDL 8.2 VHDL VHDL FPGA/CPLD VHDL FPGA/CPLD FPGA/CPLD VHDL 8-2 VHDL

173 VHDL δ δ VHDL VHDL δ VHDL z <= x XOR y AFTER 5ns 5ns x XOR y 5ns x XOR y 5ns z x y z <= x XOR y x XOR y δ z FPGA/CPLD VHDL VHDL PCB ASIC z <= TRANSPORT x AFTER 10 ns; TRANSPORT

174 164 VHDL AFTER 8.3 d VHDL δ δ δ δ 8.4 VHDL TEXTIO VHDL 4 4 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER4 IS PORT ( a, b : IN INTEGER RANGE 0 TO 15; c : OUT INTEGER RANGE 0 TO 15 ); END ADDER4; ARCHITECTURE one OF ADDER4 IS c <= a + b; END one;

175 8 165 h VHDL ENTITY SIGGEN IS PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END; ARCHITECTURE Sim OF SIGGEN IS sig1 <= 10, 5 AFTER 200 ns, 8 AFTER 400 ns; sig2 <= 3, 4 AFTER 100 ns, 6 AFTER 300 ns; END; 8-2 ModelSim SIGGEN ADDER4 VHDL 8-2 SIGGEN ENTITY BENCH IS END; ARCHITECTURE one OF BENCH IS COMPONENT ADDER4 PORT ( a, b : integer range 0 to 15; c : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; COMPONENT SIGGEN PORT ( sig1 : OUT INTEGER RANGE 0 TO 15; sig2 : OUT INTEGER RANGE 0 TO 15 ); END COMPONENT; SIGNAL a, b, c : INTEGER RANGE 0 TO 15; U1 : ADDER4 PORT MAP (a, b, c); U2 : SIGGEN PORT MAP (sig1=>a, sig2=>b); END; a b c ModelSim 8-3 h

176 166 VHDL ModelSim force force force < > < > [< >][, < > < > ] [-repeat < >] force a 0 force b 0 0, BENCH 0 b force clk 0 0, 1 15 repeat 20 clk 20 ADDER4 ModelSim force a 10 0, 5 200, force b 3 0, 4 100, Run Run ModelSim 12 VHDL 8.5 VHDL VHDL Test Bench VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL Test Bench VHDL /

177 VHDL VHDL 8 Library IEEE; use IEEE.std_logic_1164.all; entity counter8 is port CLK CE LOAD DIR RESET: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 ); end counter8; architecture counter8_arch of counter8 is begin process (CLK, RESET) variable COUNTER: INTEGER range 0 to 255; begin if RESET='1' then COUNTER := 0; elsif CLK='1' and CLK'event then if LOAD='1' then COUNTER := DIN; Else if CE='1' then if DIR='1' then if COUNTER =255 then COUNTER := 0; Else COUNTER := COUNTER + 1; end if; else if COUNTER =0 then COUNTER := 255; Else COUNTER := COUNTER - 1; end if; end if; end if; end if; end if; COUNT <= COUNTER; end process; end counter8_arch; Entity testbench is end testbench; Architecture testbench_arch of testbench is File RESULTS: TEXT open WRITE_MODE is "results.txt"; Component counter8 port ( CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in INTEGER range 0 to 255; COUNT: out INTEGER range 0 to 255 );

178 168 VHDL end component; shared variable end_sim : BOOLEAN := false; signal CLK, RESET, CE, LOAD, DIR: STD_LOGIC; signal DIN: INTEGER range 0 to 255; signal COUNT: INTEGER range 0 to 255; procedure WRITE_RESULTS ( CLK CE LOAD LOAD RESET : STD_LOGIC; DIN COUNT : INTEGER ) is Variable V_OUT : LINE; Begin write(v_out, now, right, 16, ps); -- write(v_out, CLK, right, 2); write(v_out, RESET, right, 2); write(v_out, CE, right, 2); write(v_out, LOAD, right, 2); write(v_out, DIR, right, 2); write(v_out, DIN, right, 257); --write outputs write(v_out, COUNT, right, 257); writeline(results,v_out); end WRITE_RESULTS; begin UUT: COUNTER8 port map (CLK => CLK,RESET => RESET, CE => CE, LOAD => LOAD, DIR => DIR, DIN => DIN, COUNT => COUNT ); CLK_IN: process Begin if end_sim = false then CLK <= '0'; Wait for 15 ns; CLk <='1'; Wait for 15 ns; Else Wait; end if; end process; STIMULUS: process Begin RESET <= '1'; CE <= '1'; -- DIR <= '1'; -- DIN <= 250; -- LOAD <= '0'; -- wait for 15 ns; RESET <= '0'; wait for 1 us; CE <= '0'; -- wait for 200 ns; CE <= '1';

179 8 169 wait for 200 ns; DIR <= '0'; wait for 500 ns; LOAD<= '1'; wait for 60 ns; LOAD <= '0'; wait for 500 ns; DIN <= 60; DIR <= '1'; LOAD<= '1'; wait for 60 ns; LOAD<= '0'; wait for 1 us; CE <= '0'; wait for 500 ns; CE <= '1'; wait for 500 ns; end_sim :=true; wait; end process; WRITE_TO_FILE: WRITE_RESULTS(CLK,RESET,CE,LOAD,DIR,DIN,COUNT); End testbench_arch; Active-VHDL 8.6 VHDL VHDL VHDL PLI

180 170 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL 8051 PIC16C5X VHDL IP PCI C51 VHDL VHDL VHDL VHDL PSPICE VHDL PSPICE PSPICE VHDL VHDL VHDL VHDL Internet FSF VHDL δ 8-3 VHDL VHDL 8-4 VHDL 8-5 VHDL

181 VHDL Synthesis VHDL FPGA/CPLD ASIC EDA VHDL VHDL VHDL VHDL VHDL VHDL PLD 1 VHDL VHDL VHDL 9.1 VHDL EDA VHDL VHDL / /

182 172 VHDL VHDL VHDL Speed Area Density VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL EDA VHDL VHDL FPGA/CPLD EDA MAX+PLUSII HDL HDL / VHDL

183 9 VHDL VHDL VHDL VHDL VHDL VHDL IEEE EDA VHDL VHDL EDA EDA Synopsys Design Compiler FPGA Express FPGA CompilerII Synplicity Synplify Candence Synergy Mentor Graphics AutologicII DATA I/O Synario Viewlogic Workview Office Altera MAX+plusII VHDL FPGA Express Synopsys FPGA/CPLD VHDL/Verilog FPGA/CPLD FPGA/CPLD VHDL EDIF EDIF EDA PLD EDA EDIF 200 VHDL ADDER4.VHD FPGA Express isplsi1032 Export EDIF ADDER4.EDF Lattice ISPDS+ FPGA/CPLD EDIF EDA VHDL EDIF V CC GND MAX+plusII EDIF EDA Lattice ISPDS+ 5.0 Altera EDIF MAX+plusII Lattice MAX+plusII EDA EDIF Lattice EDA Altera FPGA Express Synplify EDIF Workview Office EDIF VHDL VHDL 173

184 174 VHDL 9.2 VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL 32 VHDL VHDL VHDL VHDL / CPLD FPGA VHDL EDA

185 VHDL VHDL 1 WAIT IF h h IF_THEN IF_THEN_ELSE h h IF IF h IF True h IF ELSE ELSIF (1) PROCESS (clk_a, clk_b) IF (clk_a'event AND clk_a ='1' ) THEN a <= b;

186 176 VHDL END IF; IF (clk_b'event AND clk_b ='1' ) THEN c <= b; END IF; END PROCESS; -- (2) 9-2 ELSE 9-2 PROCESS (clock) IF(clock'EVENT AND clock ='1') THEN sig <= b; ELSE sig <= c; -- END IF; END PROCESS; ELSE sig <= c; (3) IF PROCESS (clock) VARIABLE edge_var, any_var: BIT; IF (clock'event AND clock ='1') THEN edge_signal <= x; -- edge_var := y; -- any_var := edge_var; -- END IF; any_var := edge_var; -- END PROCESS; (4) IF NOT(clock'EVENT AND clock ='1') THEN... (5) 9-4 IF ELSE gate data 9-4 PROCESS (gate,data) IF (gate = '1') THEN q <= data; END IF; END PROCESS;

187 9 177 (6) FUNCTION my_func(data, gate : BIT) RETURN BIT IS VARIABLE s1: BIT; IF (gate = '1') THEN s1 := data; END IF; RETURN s1; END;... q <= my_func (data, gate);... (7) 9-6 I B A H LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( CLK,C,J,K : IN STD_LOGIC; A,H : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL I,B : STD_LOGIC; PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN B <= C; A <= B; H <= I; I <= J XOR K; END IF; END PROCESS ; END behav; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (CLK,C,J,K : IN STD_LOGIC; A,H : OUT STD_LOGIC ); END EXAP ;

188 178 VHDL ARCHITECTURE behav OF EXAP IS SIGNAL I,B : STD_LOGIC; PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN B <= C; I <= J XOR K; END IF; END PROCESS ; A <= B; H <= I; END behav; J K D I Q D H Q H J K D H Q H CLK C CLK D B Q D A Q A C D A Q A (8) x <= '1'; IF x='1' x LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk,a,b : IN STD_LOGIC; y : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL x : STD_LOGIC; PROCESS WAIT UNTIL CLK ='1' ; x <= '0'; y <= '0'; IF a = b THEN x <= '1';

189 179 9 END IF; IF x='1' THEN y <= '1' ; END IF ; END PROCESS ; END behav; 9-8 x x LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk,a,b : IN STD_LOGIC; y : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS PROCESS VARIABLE x : STD_LOGIC; WAIT UNTIL CLK ='1' ; x := '0'; y <= '0'; IF a = b THEN x := '1'; END IF; IF x='1' THEN y <= '1' ; END IF ; END PROCESS ; END behav; a a=b D Q D Q y a a=b D Q y b b CLK CLK

190 180 VHDL IF_THEN WAIT PROCESS (clk) IF clk='1' THEN y <= a; ELSE END IF; END PROCESS; -- VHDL y y ABEL-HDL ABEL-HDL ELSE PROCESS (clk) IF clk='1' THEN y <= a; ELSE y <= b; END IF; END PROCESS; IF IF CASE 9-11 PROCESS (clk) IF clk='1' THEN ELSE y <= a; END IF; END PROCESS; 9-12 PROCESS (clk) IF clk='0' THEN -- --

191 y <= a; END IF; END PROCESS; clk'event AND clk='1' 9-13 PROCESS (clk) IF clk'event AND clk='1' THEN y <= a; END IF; END PROCESS; 9-14 STD_LOGIC rising_edge( ) 9-14 SIGNAL clk STD-LOGIC... PROCESS (clk) IF rising_edge(clk) THEN y <= a; END IF; END PROCESS; WAIT 9-15 WAIT a y y 9-15 PROCESS WAIT UNTIL clk'event AND clk='1' y <= a; END PROCESS; VHDL WAIT WAIT 9-16 IF 9-16 PROCESS (clk, a, b) IF clk='1' THEN y <= a AND b; END IF; END PROCESS;

192 182 VHDL 9-17 IF 9-17 ARCHITECTURE dataflow OF latch IS PROCEDURE my_latch( SIGNAL clk,a,b : IN Boolean; SIGNAL y : OUT Boolean) IF clk='1' THEN y <= a AND b; END IF; END; Latch_1: my_latch (clock,input1,input2,outputa); Label_2: my_latch (clock,input1,input2,outputb); END dataflow; 9-18 Y 9-18 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( b, a : IN STD_LOGIC; clk : BOOLEAN; Y1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL Y : STD_LOGIC; Y <= a AND b WHEN clk ELSE Y; Y1 <= Y ; END behav; clk='1' AND clk 'EVENT ELSE 9-19

193 9 ARCHITECTURE concurrent OF my_register IS Y <= a AND b WHEN clk='1' AND clk'event; END concurrent; VHDL LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,d : IN STD_LOGIC; ena : IN BOOLEAN; -- ena q1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL q : STD_LOGIC; PROCESS(clk,ena) IF (clk='1' AND clk'event) AND ena THEN q <= d; END IF; q1 <= q ; END PROCESS; END behav; IF clk='1' AND clk'event THEN IF ena THEN -- ena

194 184 VHDL q <= d; END IF; END IF; PROCESS(clk) IF clk='1' AND clk'event THEN IF set='1' THEN y <= '1'; -- '1' TRUE ELSE y <= a AND b; END IF; END IF; END PROCESS; set/reset / reset='0' FALSE y TRUE/FALSE /

195 9 VHDL / / PLD BOOLEAN LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,reset : IN STD_LOGIC; a,b : IN BOOLEAN; Y1 OUT BOOLEAN ); END EXAP ; ARCHITECTURE behav OF EXAP IS SIGNAL Y : BOOLEAN; PROCESS (clk,reset) IF reset='1' THEN y <= FALSE; ELSIF clk='1' AND clk'event THEN y <= a AND b; END IF; END PROCESS; Y1 <= Y; END behav; VHDL PLD VHDL LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT (clk,reset,preset : IN STD_LOGIC; a,b : IN STD_LOGIC; Y1 : OUT STD_LOGIC ); END EXAP ; ARCHITECTURE behav OF EXAP IS

196 186 VHDL SIGNAL Y :STD_LOGIC; PROCESS (clk, reset, preset) IF reset='1' THEN y <='0'; -- 0 ELSIF preset='1' THEN y <='1'; ELSIF rising_edge(clk) THEN y <= a AND b; END IF; END PROCESS; Y1 <= Y; END behav; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT ( clock, reset : IN STD_LOGIC; and_b, or_b, nor_b : OUT STD_LOGIC ); END exmp; ARCHITECTURE rtl OF exmp IS PROCESS VARIABLE count : STD_LOGIC_VECTOR(2 DOWNTO 0); WAIT UNTIL clock'event AND clock ='1'; IF (reset = '1') THEN count := "000"; ELSE count := count + 1; END IF; and_b <= count(2) AND count(1) AND count(0); or_b <= count(2) OR count(1) OR count(0); nor_b <= count(2) XOR count(1) XOR count(0); END PROCESS; END rtl;

197 D 3 count count WAIT 187 D0 Q0 and_b clock FD11 D0 Q0 or_b D0 Q0 FD11 D0 Q0 FD11 D0 Q0 FD11 nor_b reset FD11 D0 Q0 FD11 B A S max WAIT IF 9-26 WAIT 9-26 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT( clock, reset : IN STD_LOGIC; and_b, or_b, xor_b : OUT STD_LOGIC); END exmp; ARCHITECTURE rtl OF exmp IS SIGNAL count : STD_LOGIC_VECTOR(2 DOWNTO 0); PROCESS -- WAIT UNTIL clock'event AND clock ='1'; IF (reset = '1') THEN Count <= "000"; ELSE Count <= count + 1; END IF; END PROCESS; PROCESS(count) --

198 188 VHDL and_b <= count(2) AND count(1) AND count(0); or_b <= count(2) OR count(1) OR count(0); xor_b <= count(2) XOR count(1) XOR count(0); END PROCESS; END rtl; D0 Q0 and_b I3 reset FD11 B A S D0 Q0 or_b D0 Q0 FD11 xor_b clock FD IF WAIT IF WAIT 9-27 cond a(0) a (1) a (2) a (4) 4 output cond a LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY exmp IS PORT ( clk : IN STD_LOGIC; cond : IN INTEGER RANGE 0 TO 3; a : IN STD_LOGIC_VECTOR(0 to 3); output : OUT STD_LOGIC); END exmp; ARCHITECTURE activ OF exmp IS SIGNAL s_cond : INTEGER RANGE 0 TO 3;

199 9 PROCESS WAIT UNTIL clk'event AND clk ='1'; s_cond <= cond; END PROCESS; PROCESS (a, s_cond) output <= a(s_cond); END PROCESS; END activ; p1 p2 temp temp l_b a p1 p2 D Q D Q q temp l_b LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.All; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY latch2 IS PORT(p1, p2, a : IN STD_LOGIC; q : OUT STD_LOGIC );

200 190 VHDL END latch2; ARCHITECTURE activ OF latch2 IS SIGNAL temp, l_b: STD_LOGIC; PROCESS(p1, a, l_b) IF (p1 = '1') THEN temp <= a AND l_b; -- END IF; END PROCESS; PROCESS(p2, temp) IF(p2 = '1') THEN l_b <= NOT temp; -- END IF; END PROCESS; q <= l_b; END activ; FPGA/CPLD CPU VHDL Lattice isplsi Xilinx FPGA Z IF (condition) THEN out_val <= in_val; ELSE out_val <= 'Z'; -- Z END IF;... Z Z RETURN out_val <= 'Z' AND in_val

201 IF in_val = 'Z' THEN IF FALSE THEN... 'Z' VHDL 'Z' VHDL 'Z' STD_LOGIC 'Z' s_a < = 'Z'; s_b < = 'z'; 'Z' IEEE STD_LOGIC IF IF OT11 8 IF IF 9-30 IF IF WHEN-ELSE LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

202 192 VHDL ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS PROCESS(enable,input3, input2, input1, input0 ) IF enable(3) = '1' THEN output <= input3 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(2) = '1' THEN output <= input2 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(1) = '1' THEN output <= input1 ; ELSE output <=(OTHERS => 'Z'); END IF ; IF enable(0) = '1' THEN output <= input0 ; ELSE output <=(OTHERS => 'Z'); END IF ; END PROCESS; END multiple_drivers; 9-31 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS output <= input3 WHEN enable(3) = '1' ELSE (OTHERS => 'Z'); output <= input2 WHEN enable(2) = '1' ELSE (OTHERS => 'Z'); output <= input1 WHEN enable(1) = '1' ELSE (OTHERS => 'Z'); output <= input0 WHEN enable(0) = '1' ELSE (OTHERS => 'Z'); END multiple_drivers; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tris IS port ( three_s,clk, input : IN STD_LOGIC; cnd : IN BOOLEAN ; output : OUT STD_LOGIC );

203 9 END tris ; ARCHITECTURE mul OF tris IS PROCESS(three_s,clk, input ) IF (three_s = '0') THEN output <= 'Z'; ELSIF (clk ='1' AND clk'event) THEN IF (cnd) THEN output <= input; END IF; END IF; END PROCESS; END mul; three_s temp LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch_3s IS PORT( clk, three_s, input : IN STD_LOGIC ; output : OUT STD_LOGIC; cnd : IN BOOLEAN ); END latch_3s; ARCHITECTURE activ OF latch_3s IS SIGNAL temp: STD_LOGIC; PROCESS(clk, cnd, input) IF (clk ='1' AND clk EVENT) THEN IF (cnd) THEN temp <= input; END IF;

204 194 VHDL END IF; END PROCESS; PROCESS(three_s, temp) IF (three_s = '0') THEN output <= 'Z'; ELSE output <= temp; END IF; END PROCESS; END ARCHITECTURE activ; 9-34 three_s cnd 9-17 input clk INOUT enable OT LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bidir IS PORT (input_val, enable, other_sig : IN STD_LOGIC; output_val : OUT STD_LOGIC; bidir_port : INOUT STD_LOGIC) ; END bidir ; ARCHITECTURE tri_state OF bidir IS bidir_port <= input_val WHEN enable = '1' ELSE 'Z'; output_val <= bidir_port XOR other_sig ; END tri_state; B A S MUX21 D Q D_FF I1 OT11 output VHDL

205 9 Area Optimize Or Density Optimize LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY SHARE IS PORT(A,B,C,D :IN STD_LOGIC_VECTOR (3 DOWNTO 0); SEL : IN STD_LOGIC ; OPUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SHARE ; ARCHITECTURE BEHAVE OF SHARE IS SIGNAL OUT1 : STD_LOGIC_VECTOR (3 DOWNTO 0); PROCESS (A,B,C,D,SEL) IF (SEL='1') THEN OUT1 <= A+B; ELSE OUT1 <= C+D ; END IF; OPUT <= OUT1; END PROCESS; END BEHAVE ; 9-36 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY SHARE IS PORT(A,B,C,D :IN STD_LOGIC_VECTOR (3 DOWNTO 0); SEL : IN STD_LOGIC ; OPUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END SHARE ; ARCHITECTURE BEHAVE OF SHARE IS SIGNAL OUT1,F,G : STD_LOGIC_VECTOR (3 DOWNTO 0); PROCESS (A,B,C,D,SEL) IF (SEL='1') THEN F <= A; G <=B; ELSE F <= C ;G <=D; END IF; OPUT <= F+G; END PROCESS; 195

206 196 VHDL END BEHAVE ; VHDL VHDL SEL SEL C[3:0] D[3:0] + 0 OPUT[3:0] C[3:0] A[3:0] 0 1 f[3:0] + OPUT[3:0] 1 A[3:0] B[3:0] + OPUT[3:0] D[3:0] B[3:0] 0 1 g[3:0] VHDL VHDL VHDL 9-4 FPGA CPLD VHDL LED ( ) A B C D E F RS T JK VHDL (1) [d7..d0] : 8 (2) dataout

207 (3) datain 9 (4) clock (5) clken (6) clr (7) s/l dataout(0)~ dataout(7) 0 dataout 7 dataout = dataout 7 Clken Clock Datai clr s/l n d0 d n dataout 0 dataout n 1 X X X X X 0 dataout n X 1 dataout n 1 1 X 0 X X dataout 0 dataout n X X X 1 X X X X 0 X X

208 198 VHDL 10 FSM VHDL VHDL CPU h VHDL h h VHDL h VHDL CPU CPU CPU h CPU CPU CPU CPU h CPU CPU CPU 2 ns CPU

209 10 FSM 199 ms 10.1 Mealy Moore VHDL 1 TYPE ARCHITECTURE ARCHITECTURE...IS TYPE states IS (st0, st1, st2, st3); -- SIGNAL current_state, next_state: states; ; 2 next_state current_state next_state 3 next_state next_state

210 200 4 VHDL REG COM 10-1 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT STD_LOGIC_VECTOR (0 TO 1) ); END s_machine; ARCHITECTURE behv OF s_machine IS TYPE states IS (st0, st1, st2, st3); -- states SIGNAL current_state, next_state: states; REG PROCESS (reset,clk) -- IF reset = '1' THEN current_state <= st0; -- ELSIF clk='1' AND clk'event THEN current_state <= next_state; -- END IF; END PROCESS; -- current_state COM COM PROCESS(current_state, state_inputs) -- CASE current_state IS -- WHEN st0 => comb_outputs <= "00"; -- "00" IF state_inputs = "00" THEN -- "00" next_state <= st0; -- REG st0 ELSE next_state <= st1; -- REG st1 END IF; WHEN st1 => comb_outputs <= "01";-- st1 "01" IF state_inputs = "00" THEN -- "00" next_state <= st1; -- REG st1 ELSE next_state <= st2; -- REG st2 END IF;

211 10 FSM 201 WHEN st2 => comb_outputs <= "10"; -- IF state_inputs = "11" THEN next_state <= st2; ELSE next_state <= st3; END IF; WHEN st3 => comb_outputs <= "11"; IF state_inputs = "11" THEN next_state <= st3; ELSE next_state <= st0; -- REG st0 END IF; END case; END PROCESS; -- next_state REG END behv; reset state_inputs clk PROCESS REG 10-2 AD574 comb_outputs REG REG st0 st1 st2 st3 state_inputs REG current_state COM current_state state_inputs REG FSM: next_state s_machine current_state PROCESS COM 10-1 s_machine 10-1 AD574 X comb_outputs CE CS RC K12/8 A0 0 X X X X X 1 X X X X X 1 8 state_inputs X

212 202 VHDL 10-1 current_state REG COM next_state COM REG 3 clk reset 10-1 current_state next_state VHDL 10-1 PROCESS REG CLK current_state next_state CS I.C. : AD574 A0 RC K12/8 STSTUS D[11:0] FSM: AD574 PROCESS COM LOCK PROCESS LATCH Q[11:0] 10-3 AD A/D AD574 AD LATCH 12 REGL COM AD574 6 LOCK st3 st LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT (D :IN STD_LOGIC_VECTOR(11 DOWNTO 0); --AD574 CLK,STATUS : IN STD_LOGIC; --CLK STATUS CS,A0,RC,K12/8 : OUT STD_LOGIC; --CS A0 12 A/D 12 --RC A/D K12/ Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));-- A/D END AD574; ARCHITECTURE behav OF AD574 IS TYPE states IS (st0, st1, st2, st3,st4,st5); -- SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0);--A/D

213 10 FSM 203 SIGNAL LOCK : STD_LOGIC; -- K12/8 <= '1'; COM: PROCESS(current_state,STATUS) -- CASE current_state IS WHEN st0 => CS<='1';A0<='0';RC<='0';LOCK<='0'; next_state <= st1;--ad574 st0 st1 WHEN st1=> CS<='0';A0<='0';RC<='0';LOCK<='0'; next_state <= st2; WHEN st2=> CS<='0';A0<='0';RC<='0';LOCK<='0'; IF (STATUS='1') THEN next_state <= st2; -- ELSE next_state <= st3; -- END IF ; WHEN st3=> CS<='0';A0<='0';RC<='1';LOCK<='0'; next_state <= st4; -- RC 12 WHEN st4=> CS<='0';A0<='0';RC<='1';LOCK<='1'; next_state <= st5; -- WHEN st5=> CS<='1';A0<='1';RC<='1';LOCK<='0'; next_state <= st0; -- AD574 WHEN OTHERS => next_state <= st0; -- END CASE ; END PROCESS COM ; REG PROCESS (CLK) IF ( CLK'EVENT AND CLK='1') THEN current_state <= next_state; -- CLK END IF; END PROCESS REG; -- current_state COM LATCH PROCESS (LOCK) -- LOCK 12 REGL IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ; Q <= REGL; -- REGL Q END behav; REG FUNC1 FUNC LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY system IS PORT (clock: IN STD_LOGIC; a: IN STD_LOGIC; d: OUT STD_LOGIC); END system; ARCHITECTURE moore OF system IS SIGNAL b, c: STD_LOGIC;

214 204 VHDL -- 1 FUNC1: PROCESS (a, c) b <= FUNC1(a, c); -- c END PROCESS; FUNC2: PROCESS (c) d <= FUNC2(c); END PROCESS; REG: PROCESS (clock) IF clock='1' AND clock'event THEN c <= b; -- b END IF; END PROCESS; END moore; D FUNC FUNC FSMs OE START ALE EOC RST PROCESS COM ADC ADC_NEXT_STATE ADC_CURRENT_STATE PROCESS REG AD_STATE PROCESS REG DATA_LOCK 8 DIN ENABLE CLK ADC_END ADC_DATA 8 ADDRES_CNT CLK PROCESS REG RAM_NEXT_STATE PROCESS COM 13 PROCESS REG WRIT_STATE RAM_CURRENT_STATE RAM_WRITE COUNTER CS ADDRESS RAM_DIN RD ADDA ADDRES_PLUS FPGA/CPLD

215 10 FSM 205 FUNC1 FUNC FPGA CPLD ADC0809 SRAM ( 10-5 ) 1 ADC0809 ADC AD_STATE DATA_LOCK ADC RST ST0 ENABLE 6264 A/D ST2 A/D START ST4 EOC 0 1 ST5 OE LOCK DATA_LOCK ADC_DATA ST7 A/D ADC_END 6264 AD_STATE 2 SRAM 6264 WRIT_STATE RAM_WRITE COUNTER WRIT_STATE AD_STATE WRIT_STATE ADC START_WRITE (ADDRES_CNT = " ") A/D ENABLE=0 RST ADDRES_CNT A/D ENABLE=1 WRITE1 A/D ADC_END=1 SRAM WRITE2 ADDRES_CNT 13 ADC_DATA ADC_DATA WRITE3 WR= A/D COUNTER RST WRITE_END A/D CLK A/D A/D ENABLE A/D ADC_END LOCK ADDRES_PLUS ADC WRIT_STATE DATA_LOCK COUNTER ISPEXPERT MAXPLUS-II EDA 10-4 LIBRARY IEEE;

216 206 VHDL USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SRAM IS PORT ( --ADC0809 DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,EOC: IN STD_LOGIC; --CLK EOC RST: IN STD_LOGIC; -- ALE: OUT STD_LOGIC; START: OUT STD_LOGIC; OE: OUT STD_LOGIC; ENABLE PIN 9 ADDA: OUT STD_LOGIC; SRAM 6264 CS: OUT STD_LOGIC; RD,WR: OUT STD_LOGIC; / RAM_DIN: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ADDRESS: OUT STD_LOGIC_VECTOR(12 DOWNTO 0));-- END SRAM ; ARCHITECTURE behav OF SRAM IS --A/D TYPE AD_STATES IS (ST0, ST1, ST2, ST3, ST4,ST5,ST6,ST7) ; TYPE WRIT_STATES IS (START_WRITE,WRITE1, WRITE2, WRITE3, WRITE_END); --SRAM SIGNAL RAM_CURRENT_STATE, RAM_NEXT_STATE: WRIT_STATES ; SIGNAL ADC_CURRENT_STATE, ADC_NEXT_STATE: AD_STATES ; SIGNAL ADC_END : STD_LOGIC; SIGNAL LOCK : STD_LOGIC; -- SIGNAL ENABLE : STD_LOGIC; -- A/D SIGNAL ADDRES_PLUS: STD_LOGIC; --SRAM 1 -- SIGNAL ADC_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0); --SRAM SIGNAL ADDRES_CNT: STD_LOGIC_VECTOR(12 DOWNTO 0); ADDA <= '1'; -- ADDA=1 ADDB=0 ADDC=0 A/D IN-1 RD <= '1'; -- SRAM,,RD -- ADC A/D ADC: PROCESS(ADC_CURRENT_STATE,EOC,ENABLE,RST) IF (RST='1') THEN ADC_NEXT_STATE <= ST0; -- ELSE CASE ADC_CURRENT_STATE IS WHEN ST0 => ALE<='0'; START<='0'; OE<='0'; LOCK<='0'; ADC_END<='0'; --A/D IF (ENABLE='1') THEN ADC_NEXT_STATE<=ST1;-- ELSE ADC_NEXT_STATE <= ST0; -- END IF; WHEN ST1 => ALE<='1'; START<='0'; OE<='0';

217 10 FSM 207 LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST2; -- WHEN ST2 => ALE<='1'; START<='1'; OE<='0'; LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST3; -- A/D START WHEN ST3 => ALE<='1'; START<='1'; OE<='0'; LOCK<='0'; ADC_END<='0'; -- IF (EOC='0') THEN ADC_NEXT_STATE <= ST4; ELSE ADC_NEXT_STATE <= ST3; -- END IF ; WHEN ST4 => ALE<='0'; START<='0'; OE<='0'; LOCK<='0'; ADC_END<='0'; IF (EOC='1') THEN ADC_NEXT_STATE<=ST5;-- ELSE ADC_NEXT_STATE <= st4; -- END IF ; WHEN ST5 => ALE<='0'; START<='1'; OE<='1'; LOCK<='0'; ADC_END<='0'; ADC_NEXT_STATE <= ST6; -- OE WHEN ST6 => ALE<='0'; START<='0'; OE<='1'; LOCK<='1'; ADC_END<='1'; ADC_NEXT_STATE <= ST7; -- WHEN ST7 => ALE<='0'; START<='0'; OE<='1'; LOCK<='1'; ADC_END<='1'; ADC_NEXT_STATE <= ST0; A/D WHEN OTHERS => ADC_NEXT_STATE<=ST0; -- END CASE ; END IF END PROCESS ADC ; AD_STATE: PROCESS (CLK) --A/D IF ( CLK'EVENT AND CLK='1') THEN ADC_CURRENT_STATE <= ADC_NEXT_STATE;-- END IF; END PROCESS AD_STATE ; -- current_state DATA_LOCK: PROCESS (LOCK) -- LOCK ADC_DATA IF LOCK='1' AND LOCK'EVENT THEN ADC_DATA <= DIN ; END IF; END PROCESS DATA_LOCK; -- SRAM WRIT_STATE: PROCESS (CLK,RST) -- SRAM IF RST='1' THEN RAM_CURRENT_STATE <= START_WRITE;-- ELSIF ( CLK'EVENT AND CLK='1') THEN RAM_CURRENT_STATE <= RAM_NEXT_STATE; -- END IF; END PROCESS WRIT_STATE ; RAM_WRITE:PROCESS(RAM_CURRENT_STATE,ADC_END, ADDRES_CNT, ADC_DATA) --SRAM

218 208 VHDL CASE RAM_CURRENT_STATE IS WHEN START_WRITE => CS<='1'; WR <='1';ADDRES_PLUS<='0' ; IF (ADDRES_CNT = " ") -- THEN ENABLE <='0'; --SRAM A/D RAM_NEXT_STATE <= START_WRITE ; ELSE ENABLE <='1'; --SRAM A/D RAM_NEXT_STATE <= WRITE1 ; END IF; WHEN WRITE1 => CS<='1'; WR <='1'; ENABLE <='1'; ADDRES_PLUS<='0' ; -- A/D IF (ADC_END='1') THEN RAM_NEXT_STATE <= WRITE2;-- ELSE RAM_NEXT_STATE <= WRITE1 ; -- A/D END IF ; WHEN WRITE2 => CS<='0'; WR <='1'; -- SRAM ENABLE <='0'; -- A/D ADDRES_PLUS<='0' ; ADDRESS<=ADDRES_CNT ; RAM_DIN <= ADC_DATA; -- 8 SRAM RAM_NEXT_STATE <= WRITE3; -- WHEN WRITE3 => CS<='0'; WR <='0'; -- ENABLE <='0'; -- A/D ADDRES_PLUS<='1'; RAM_NEXT_STATE <= WRITE_END; -- WHEN WRITE_END => CS<='1'; WR <='1'; ENABLE <='1'; -- A/D ADDRES_PLUS <='0'; -- 1 RAM_NEXT_STATE <= START_WRITE; -- WHEN OTHERS => RAM_NEXT_STATE <= START_WRITE; END CASE ; END PROCESS RAM_WRITE; COUNTER: PROCESS(ADDRES_PLUS, RST) -- 1 IF (RST='1') THEN ADDRES_CNT <= (OTHERS=>'0' ;-- ELSIF ( ADDRES_PLUS'EVENT AND ADDRES_PLUS='1') THEN ADDRES_CNT <= ADDRES_CNT + 1; END IF; END PROCESS COUNTER; END behav; 10-4 SRAM

219 10 FSM 209 IF-THEN-ELSE IF-THEN-ELSE IF clk='1' THEN y <= a; END IF; clk='0' Y ELSE IF clk='1' THEN y <= a; ELSE Y<=b END IF; ELSE IF current_state =st0 THEN a <= '1'; ELSIF current_state =st1 THEN b <= '1'; ELSE c <= '1'; --current_state =st2 END IF; st0 st2 st3 a b c st0 st2 st3 a b c st0 st1 st2 a b c 3 a <= '0'; b <= '0'; c <= '0'; IF current_state =st0 THEN a <= '1'; ELSIF current_state =st1 THEN b <= '1'; ELSE c <= '1'; END IF; VHDL VHDL

220 210 VHDL VHDL VHDL AD CS A0 RC LK1 LK2 STATE STATE STATUS=0 STATE2 STATE AD574 8 STATE LK1 8 STATE AD574 4 STATE LK AD STATE0 STATE LK1 LK LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK,STATUS : IN STD_LOGIC; CS,A0,RC,K128 : OUT STD_LOGIC; LK1 LK2 : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END AD574; ARCHITECTURE behav OF AD574 IS

221 10 FSM 211 SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT STATE0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ; CONSTANT STATE1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ; CONSTANT STATE2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ; CONSTANT STATE3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ; CONSTANT STATE4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01100" ; CONSTANT STATE5 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "01101" ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(2 DOWNTO 0 ); CONSTANT ST0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; CONSTANT ST1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001" ; CONSTANT ST2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010" ; CONSTANT ST3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011" ; CONSTANT ST4 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100" ; CONSTANT ST5 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101" ;... FPGA CS A0 RC LK1 LK STATE STATE STATE STATE STATE STATE SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(1 DOWNTO 0 ); CONSTANT ST0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT ST1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT ST2 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

222 212 VHDL CONSTANT ST3 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10" ;... 4 onehot encoding n n FPGA CPLD FPGA/CPLD VHDL st0 000 st1 001 st2 010 st3 011 st st5 101 st0 st1 st2 st3 st4 st5 undefined1 110 undefined TYPE states IS (st0, st1, st2, st3 undefined1 undefined2 undefined3 undefined4); SIGNAL current_state, next_state: states;...

223 10 FSM 213 COM PROCESS(current_state, state_inputs) -- CASE current_state IS WHEN OTHERS => next_state <= st0; END case; 10-8 OTHERS st n m = 2 n 1 '1' '0' 1 '1' '1' '1' alarm alarm <= (st0 AND (st1 OR st2 OR st3 OR st4 OR st5)) OR (st1 AND (st0 OR st2 OR st3 OR st4 OR st5)) OR (st2 AND (st0 OR st1 OR st3 OR st4 OR st5)) OR (st3 AND (st0 OR st1 OR st2 OR st4 OR st5)) OR (st4 AND (st0 OR st1 OR st2 OR st3 OR st5)) OR (st5 AND (st0 OR st1 OR st2 OR st3 OR st4)) ; 10-1 VHDL ( ) 1 0 I/O xi zo xi

224 214 VHDL zo a b output clk 5 S0 S1 S2 S3 S4 [b a]=0 clk 1 [b a]=1 clk 1 [b a]=2 0 [b a]=3 S0 1 (1) (2) VHDL (3) VHDL (4) VHDL SRAM VHDL a /="010" b='1' st0 a = "010" st1 lock <= '0' out1<="001" a='1' AND b='1' AND c='1' b='0' lock <='0' out1<="010" lock<='0' out1<="000" c='0' st2 st4 c='1' lock<='0' out1<="111" st3 lock<='1' out1<="100"

225 EDA FPGA/CPLD DSP FPGA VHDL FIR IIR 11.1 FPGA FFT DSP DSP FIR FIR 11-1 FPGA DSP FIR DSP 8 FIR FPGA MSPS ASIC FIR MIPS FIR FIR FPGA

226 216 VHDL FPGA 32 8 FIR FIR 2 FPGA Million Samples Per Second MSPS) 3 DSP FPGA DSP Million Instructions Per Second MIPS FPGA 8 8 FIR 104MSPS DSP 832MIPS DSP 100MIPS DSP DSP DSP FPGA FIR FIR FIR 50-MHz DSP 133-MHz CPU 50-MHz DSP 4 50-MHzCPU DSP EPF8820A-2 3/4 EPF81500A-2 3/5 ALTERA FPGA 8000 FPGA FPGA EPF81500A-2 DSP FPGA DSP 1/3 133-MHz CPU MHz DSP 2.8 FPGA EPF8820A FIR

227 FIR 217 FIR / H N 1 n= 0 ( z) = h( n) z n y N 1 ( n) h( m) x( n m) = m= 0 ( ) ( ) x n h n n x ( n) 1 z 1 z 1 z 1 z 1 z h ( 0) h ( 1) h ( 2) h ( 3) h ( 4) h ( N 2) h ( N 1) y( n) y( n) n ( ) 11-2 h n h n ( ) ( M n) h( n) h = = n,,, M M y M ( n) h( k) x( n k) = k =0

228 218 VHDL ( n) x 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z M 1 M M M = k M 2 h( k ) x( n k) + h x n + h( k) x( n k) = k = M 1 M 1 M M = k= k = h( k ) x( n k) + h x n + h( M k) x( n M + k) y M 1 2 M k = 0 2 M 2 ( n) h( k) [ x( n k) + x( n M + k) ] + h x n = M ( n) h ( 0) h ( 1) h ( 2) h ( 3) h ( M 2 1) h( M 2) y ( n) 11-3 x 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z 1 z y( n) h ( 0) h ( 1) h ( 2) h ( 3) h [( M 3) 2] h[ ( M 1) 2] 11-4 y ( M 1) 2 ( n) h( k )[ x( n k) + x( n M + k) ] = k= 0

229 11 H d ( e jω ) N 1 ( ) ( ) n= 0 jω H e = h n e ( ) jωn jω ( ) H e d jω H e n h d jω jωn ( n) H d ( e ) e dω 1 = 2 π π π d h d ( ) ( H e jω ) ( n) d h d ( h n) h( n) 219 ( h d n) ( ) n ω n h d ( ) h d ( n) h ( n) ω( n) h ( n) = d ω( n) = R ( n) N 1 2 n π 2 N 1 ( ω n) = 1 cos R ( n) ( ω n) = cos R ( n) N 2πn N 1 N 2πn 4ωn ω n = cos cos R N N 1 1 ( ) ( n) N

230 220 VHDL FIR 1 FIR , M M 11-3 FIR FIR FIR 11-5 FIR

231 FIR N 8 FIR N 8 8 FPGA 3 FPGA FIR N N N A B N Q N B = 1 2 i B( i) ( B i) B i i= N 1 N 1 i Q = A B = A 2 B i= 0 i ( i) = 2 A B( i) i= N ROM ROM 11-7 ( n i) h( i) Q i = x 11-7 FIR FIR

232 222 VHDL ROM N FIR FIR 11-8 FIR N N W y N 1 ( n) h( m) x( n m) = m= 0 y N 1 W 1 W 1 N = 1 i m= 0 i= 0 i= 0 m= 0 i i ( n) x( n m) 2 h( m) = 2 h( m) x( n m) W 1 N 1 i= 0 m= 0 i ( n) = 2 x( n m) h( m) y i W 1 i= 0 i ( ) ( ) i i x n m h m N 1 W ( ) i ( ) ( ) i 11-8 Q m h m x n m 1 W FIR N 1 m= 0

233 KHz 10KHz 11 FIR h(n) FIR 11-3 h n 1024 h(0) h(10) H FIR h(1) h(9) H h(1) h(9) H h(2) h(8) H h(3) h(7) bH h(4) h(6) c0h h(5) cdh FIR clk_regbt<=not clk and clk_en; -- clk_reg<=not clk and not clk_en; -- process(clk,res) begin if(res='1')then -- counter<=0; count_bt<=0; elsif(clk'event and clk='1')then -- if(counter<8)then -- 8 clk_en<='1'; -- counter<=counter+1; -- count_bt<=count_bt-1; -- else -- 9 ounter<=0; count_bt<=0; clk_en<='0'; end if; end if; end process; clk res counter count_bt counter 9 count_bt clk_regbt clk_reg clk_regbt clk_reg

234 224 VHDL clk res 8 count_bt clk_en clk_en clk_en clk_regbt clk_reg not clk clk clk_en process(clk_reg,clr,res) begin if(res='1' or clr='1')then -- for I in 0 to 10 loop reg_xn(i)<=" "; end loop; elsif(clk_reg'event and clk_reg='0')then -- for I in 10 to 1 loop reg_xn(i)<=reg_xn(i-1); end loop; reg_xn(0)<=data_xn; -- end if; end process; reg_xn 11 8 clk_reg x reg_xn(10)

235 11 reg_xn(0) data_xn clk_reg h(n) x(n) process(clk) begin if(clk'event and clk='0')then -- for I in 0 to 10 loop -- if (reg_hn(i)(count_bt)='1')then -- 1 add_xn(i)<=reg_xn(i); -- reg_xn(i) else -- 1 end if; end loop; end if; end process; add_xn(i)<=" "; -- " " clk clk_regbt clk_regbt clk clk clk_regbt 11-9 clk_regbt reg_hn add_xn reg_xn reg_hn h(n) add_xn h(n) x(n) count_bt reg_hn(i)(count_bt) reg_hn i+1 count_bt h(i) count_bt count_bt h(i) 8 x(i)

236 226 VHDL W 1 i= 0 i N 1 i = x( n m) h( m) i m= 0 Q 11-8 i Q i i 2 process(clk_regbt,clk_reg,clr,set) begin if(clr= 1 or set= 1 ) then -- sum <= (OTHERS =>'0'); data_yn <= (OTHERS =>'0'); elsif(clk_reg= 1 )then -- data_yn<=result(18 downto 11); -- sum<=(others =>'0'); -- elsif(clk_regbt='1')then sum91<=add_xn(0)+add_xn(1); sum92<=add_xn(2)+add_xn(3); sum93<=add_xn(4)+add_xn(5); sum94<=add_xn(6)+add_xn(7); sum101<=sum91+sum92; sum102<=sum93+sum94; sum11<=sum101+sum102; sum<=result+sum11; -- else result<=sum(17 downto 0)& 0 ; -- end if; end process; W 1 N 1 i= 0 m= 0 ( ) i 2 p m i ( p m) i ( ) ( ) i i x n m h m 8 FIR h n ( )

237 FIR 6 1 h( n) FPGA FPGA process(clk) begin if(clk event and clk= 1 )then if(pcount<pmax & 0 )then pcount:=pcount+ 1 ; if(pcount<pmax)then clkout<= 0 ; else clkout<= 1 ; end if; else pcount:=0; end if; end if; end process; pmax 1/2 clkout 1/2 clkout 50% 2 h( n) process(set,enter,mode) begin if(set<='1')then if(mode="00")then reg_hn(0)<=" "; reg_hn(10)<=" ";

238 228 VHDL reg_hn(9)<=" "; reg_hn(1)<=" "; reg_hn(2)<=" "; reg_hn(8)<=" "; reg_hn(3)<=" "; reg_hn(7)<=" "; reg_hn(4)<=" "; reg_hn(6)<=" "; reg_hn(5)<=" "; elsif(mode="01")then -- if(enter= 1 )then -- reg_hn(addr_hn)<=data_hn; -- h( n) end if; end if; end if; end process; ( ) h n reg_hn ( ) h n 0 mode="00" h n FIR ( ) 1 mode="01" addr_hn data_hn addr_hn addr_hn set EDA FIR A/D 8 A/D AD574 ADC0809 FIR FPGA EPF10K20-TC144 FIR A/D DAC FPGA FIR FIR

239 IIR 229 FIR IIR FPGA IIR FIR IIR IIR FIR IIR 5~10 IIR IIR IIR FPGA 1 IIR a + a z + a z ( z) = b0 z b1 z H II n X(n) Y(n) n IIR d( n) = X ( n) + b d( n 1) + b Y ( n) = d( n) a d( n 1) a 1 2 ( n 2) + d( n 2) a FPGA 2 ROM VHDL ROM IIR y n = a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn II {X n } Y N ai bi {X(N)} b 2 X(n) <1 X(n)

240 230 VHDL b 1 k k 0 x n = xn 2 x n K = 1 k X(N) b-k 0 5bit F k k k k k k k k k k F( xn, xn 1, xn 2, yn 1, yn 2 ) a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2 = b 1 k k k k k k y n = 2 F( xn, xn 1, xn 2, yn 1, yn 2 ) F( xn, xn 1, xn 2, yn 1, yn 2 ) k = 1 F 32 32*b ROM ROM xn SR1 SR2 k x n k xn 1 k xn 2 y n SR3 k yn 1 y k n 2 SR4 k x n k xn 1 ROM k xn 2 k yn 1 k yn 2 FPGA FIR ROM ROM ROM ROM 3 ROM ROM IIR y n = a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2

241 11 {X n } Y N ai bi {X(N)} b 2 X(n) <1 X(n) 231 b 1 k k 0 x n = xn 2 x n K = 1 k X(N) b-k 0 5bit F k k k k k k k k k k F( xn, xn 1, xn 2, yn 1, yn 2 ) a0xn + a1xn 1 + a2xn 2 + b0 yn 1 + b1 yn 2 = k k k k k k k k k k F( a0, a1, a2, b0, b1 ) xna0 + xn 1a1 + xn 2a2 + yn 1b0 + yn 2b1 = b 1 k k k k k k y n = 2 F( a0, a1, a2, b0, b1 ) F( a0, a1, a2, b0, b1 ) k = X(n) X(n-1) X(n-2) Y(n-2) Y(n-1) k a 0 X k a 1 X k a 2 X k b 1 X k b 0 X Y(n) a a1, a2, b0,, b F ( a, a, a, b, ) = b1

242 232 VHDL b 1 k k k k k k y n = 2 F( a0, a1, a2, b0, b1 ) k = 1 8 * X N FPGA A/D Y N X n-1 X n-2 X n X n-1 Y N ->Y(N-1),Y(N-1)->Y(N-2) 1 Y N <1 k k k k k =max{ F a, a, a, b, b )} ( k k k k k =min{ F a, a, a, b, b )} ( y n b α 1 K = 1 2 k β k = 1 k 2 = 1 y < α β y(n) <1 S n S > α β α = = β = = S = α β = Q5 2 VHDL CLR RES counter clk_en

243 11 count_bt Clk_en 8 process(clk,clr,res) begin if(clr='1' or res='1')then - counter<=0; count_bt<=0; elsif(clk'event and clk='1')then if(counter<8)then clk_en<='1'; counter<=counter+1; -- count_bt<=count_bt+7; -- 1 else counter<=0; count_bt<=0; clk_en<='0'; end if end if; end process; 8 *1 8 clr,res data_yn data_yntemp 8 process(clk_regbt,clk_reg,clr,res)--adder begin if(clr='1' or res='1') then - sum<= OTHERS =>'0' ; data_yn<= OTHERS =>'0' ; elsif(clk_reg='1')then data_yn<=result(14 downto 7); -- 8 data_yntemp<=result(14 downto 7); sum<= OTHERS =>'0' ; elsif(clk_regbt='1')then sum<=result+add_xn(0)+add_xn(1)+add_xn(2) -add_yn(0)-add_yn(1);-- else result<=sum(14 downto 0)&'0';-- 2 end if; end process; 8 * process(clk)-- get the addend begin if(clk'event and clk='0')then if (reg_an(0)(count_bt)='1')then add_xn(0)<=reg_xn(0); else add_xn(0)<=" "; end if; --a0 count_bt x(n) if (reg_an(1)(count_bt)='1')then add_xn(1)<=reg_xn(1); else add_xn(1)<=" "; 233

244 234 VHDL end if; if (reg_an(2)(count_bt)='1')then add_xn(2)<=reg_xn(2); else add_xn(2)<=" "; end if; if (reg_bn(0)(count_bt)='1')then add_yn(0)<=reg_yn(0); else add_yn(0)<=" "; end if; if (reg_bn(1)(count_bt)='1')then add_yn(1)<=reg_yn(1); else add_yn(1)<=" "; end if; end if; end process; A/D X N X n X n-1 X n-1 X n-2 Y N ->Y(N-1),Y(N-1)->Y(N-2). process(clk_en) begin if(clk_en'event and clk_en='0')then data_xn<=ad_data; end if; end process; process(clk_reg,clr,res) begin if(res='1' or clr='1')then - reg_xn(0)<=" "; reg_xn(1)<=" "; reg_xn(2)<=" "; reg_yn(0)<=" "; reg_yn(1)<=" "; elsif(clk_reg'event and clk_reg='0')then reg_xn(2)<=reg_xn(1); -- X(N-1)->X(N-2) reg_xn(1)<=reg_xn(0) --X(N)->Y(N-1); reg_xn(0)<=data_xn reg_yn(1)<=reg_yn(0); reg_yn(0)<=data_yntemp; end if; end process; end; 11-1 FPGA DSP 11-2 VHDL FIR

245 12 VHDL VHDL VHDL VHDL EDA VHDL / EDA VHDL EDA VHDL VHDL VHDL VHDL CPU VHDL VHDL ASIC FPGA CPLD VHDL EDA VHDL VHDL VHDL EDA IP FPGA/CPLD ASIC PLD 3 EDA PC FPGA CPLD ASIC EDA / 12.1 ispvhdl VHDL isplsi VHDL VHDL isplsi VHDL PC VHDL Model Technology ModelSim VHDL Verilog VHDL Synplicity Synplify VHDL Verilog Lattice ispexpert Compiler EDA

246 236 VHDL ` ispvhdl isplsi EDA ModelSim PE/Plus 4.7h Synplify VHDL VHDL Verilog UltraEdit ispexpert Compiler ispds EDA isplsi isplsi CPLD Lattice 1 5 isplsi isplsi 1K/2K/2KE/3K/5K/6K/8K isplsi 2KE/5K/8K V isplsi1k/e Lattice E 2 CMOS MHz ISP Daisy Chain Download isplsi2ke SupperFast 200MHz isplsi3k 125MHz 12-1 isplsi EDA isplsi5k SuperWide isplsi5kv Lattice 3.3V isp PLD PLD 125MHz JTAG I/O 5V 3.3V 2.5V isplsi8k SuperBig CPLD PLD ModelSim Synplify ispexpert Compiler ModelSim ispvhdl 1 ModelSim ModelSim Model Technology VHDL Verilog Model Technology Mentor Graphics ModelSim RTL Functional Gate-Level RTL VHDL VHDL

247 12 VHDL VHDL VHDL ModelSim VHDL IEEE IEEE ModelSim Verilog IEEE Open Verilog ModelSim SDF VITAL 2.2b VITAL 95 2 Synplify Synplify FPGA CPLD Synplicity Synplicity Cadence Synplify Verilog VHDL Synplify VHDL Verilog Synplify FSM Synplify HDL Synplify RTL Technology RTL Synplify VHDL RTL VHDL Synplify Actel Altera Lattice Lucent Philips QuickLogic Vantis(AMD) Xilinx Synplify VHDL Verilog ispexpert Compiler ispexpert Compiler Lattice Fitter EDA EDIF ispexpert Compiler Lattice isplsi1k/2k/3k/5k/6k VHDL Verilog EDIF ispexpert Compiler EDIF PLA LAF VHDL Viewlogic Synopsys Synplicity Aldec VeriBest OrCAD Cadence Mentor Graphics Exemplar Logic EDA Lattice isplsi2ke isplsi5kv isplsi8k ispvhdl 4 VHDL isplsi 4 VHDL 12-1

248 238 VHDL ` LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY Cnt4b IS PORT ( CLK : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15 ) ; END Cnt4b ; ARCHITECTURE one OF Cnt4b IS PROCESS ( CLK ) IF CLK'EVENT AND CLK = '1' THEN IF Q = 15 THEN Q <= 0 ; ELSE Q <= Q + 1 ; END IF; END IF ; END PROCESS ; END one ; DOS Windows D D D:\ISPEXAM 1 VHDL Cnt4b.vhd Windows 98 Synplicity Synplify Synplify Synplify File New HDL File File Save 12-2 ModelSim Directory D:\ISPEXAM Cnt4b.vhd Synplify VHDL Tools Syntax Check Synplify Cnt4b.vhd /

249 12 VHDL 2 ModelSim Cnt4b.vhd 239 Windows Model Tech ModelSim ModelSim (1) ModelSim File Directory 12-2 D:\ISPEXAM 12-3 WORK (2) Library New WORK WORK WORK 12-3 WORK WORK 3 WORK ( ) (3) File Compile VHDL 12-4 Cnt4b.vhd Compile Cnt4b.vhd Done Cnt4b WORK Cnt4b one WORK (4) File Simulate Simulate a Design 12-5 Entity VHDL

250 240 VHDL ` Cnt4b (5) View Wave Wave 12-6 (6) Signals Add to Waveform Signals in Region Cnt4b clk q 12-6 (7) Transcript ModelSim force clk 0 0, 1 50 repeat 100 Enter 100 ns 0 ns 0 50 ns ns (8) Wave Run Run 100 ns Run ModelSim 8 3 Synplify Cnt4b.vhd VHDL Synplify (1) Synplify File New Project OK Unsaved Project D:\ISPEXAM CNT4.prj File Save 12-7 D:\ISPEXAM 12-7 Work

251 12 VHDL CNT4.prj D:\ISPEXAM CNT4.prj D:\ISPEXAM\CNT4.prj CNT4.prj (2) D:\ISPEXAM\CNT4.prj ( 12-10) Add Add Source Files 12-8 Cnt4b.vhd ADD Cnt4b.vhd Source Work Cnt4b.vhd [VHDL] 241 Synplify VHDL ADD VHDL 12-8 Cnt4b.vhd (3) Change Change Target Set Device Options 12-9 Technology Lattice 12-9 isplsi OK Lattice isplsi 12-9 Altera FLEX10K EDIF / (4) Run Synplify Cnt4.prj Cnt4b.vhd D:\ISPEXAM Cnt4b.edf EDIF Done View Log

252 242 VHDL ` (5) HDL Analyst RTL View RTL VHDL HDL Analyst Technology View 4 ispexpert Compiler Cnt4b.edf Lattice ispexpert Compiler JED (1) Windows Lattice Semiconduct or ispexpert Compiler (2) Project New Create New Project RTL

253 ( 12-12) EDIF Reader Settings EDIF Reader 13 Vendor Synplicity Synplify EDIF OK EDF Project Update Cnt4b.laf (4) Assign Device 12 VHDL Synplify EDF Device Selection Settings 12- isplsi1032e- 70LJ84 OK (3) Create New Project D:\ISPEXAM Cnt4b.edf OK ispexpert Compiler Synplify Cnt4b.edf ispexpert Compiler Cnt4b.edf ispexpert Compiler 12-14

254 244 VHDL ` Lattice isplsi Synplify (5) Assign Pin Locations ispexpert Compiler Unassigned CLK Q(0)..Q(3) CLK I/O Pin Location Assignment Save Pin Assignments Q(2) I/O18(PIN 47) Q(3) I/O19(PIN 48).ppn Read Pin File 12-1 CLK I/O7 (PIN 33) Q(0) I/O16(PIN 45) Q(1) I/O17(PIN 46) 12-1 Unassigned Assigned Pins I/O GW48 NO PIO19 PIO CLK PIO7 8 1 PIO19 PIO16 PIO7 isp1032e 1 isplsi1032e PIO19 PIO16 PIO FLEX10K20 1 (6) ispexpert Compiler Assign Pin Locations Tools Compile Compile ispexpert Compiler Cnt4b.laf

255 12 VHDL Cnt4b.jed Cnt4b.jed isp1032e (7) Interfaces VHDL Writer ispds+ VHDL Cnt4b.vhd Cnt4b (8) ModelSim Cnt4b.vhd Cnt4b.vhd 5 Cnt4b.jed ispexpert Compiler Tools ispdcd LSC ISP Daisy Chain Download Cnt4b.jed isplsi1032e ISP Configuration Scan Board SCAN Lattice ISP E 1032E Browse Cnt4b.jed Command Run Operation Cnt4b PASS 1 6 VHDL Lattice Lattice ispexpert Compiler Macro Library Macro VHDL Lattice I/O 600 isplsi6000 RAM Lattice Lattice Synplify Lattice Lattice Lattice components LIBRARY LATTICE; USE LATTICE.COMPONENTS.ALL ; 245

256 246 VHDL ` Lattice ispexpert System manuals Lattice Synplify isplsi isplsi RTL Synplify VHDL RTL View Technology View VHDL 12.2 Altera MAX+plus II VHDL MAX+plus II EDA MAX+plus II VHDL Verilog EDIF MAX+plusII MAX+plusII EDIF VHDL Verilog MAX+plusII EDA Synopsys Cadence Synplicity Mentor Viewlogic Exemplar Model Technology MAX+plusII APEX20K Altera FPGA/CPLD 1 Cnt4.vhd 12-5 Cnt4.vhd 4 VHDL File New Text Editor file OK Untitled - Text Editor New 12-2 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY CNT4 IS PORT ( CLK : IN STD_LOGIC ; Q : BUFFER INTEGER RANGE 0 TO 15) ; END ; ARCHITECTURE one OF CNT4 IS PROCESS (CLK) IF CLK'EVENT AND CLK = '1' THEN Q <= Q + 1 ; END IF; END PROCESS ; END ;

257 12 VHDL File Save Directories D:\MAXVS\GUIDE File Name Cnt4.vhd OK D:\MAXVS\GUIDE MAX+plusII.VHD VHDL.TDF AHDL.V Verilog Cnt4 Cnt4 File Create Default Symbol MAX+plusII Cnt4 MAX+plusII Cnt4.vhd Cnt Cnt4.vhd 2 Decl7s.vhd Decl7s.vhd Decl7s.vhd 1. Cnt4.vhd Cnt4.vhd D:\MAXVS\GUIDE 12-3 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DecL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END ; ARCHITECTURE one OF DecL7S IS

258 248 VHDL ` PROCESS( A ) CASE A(3 DOWNTO 0) IS WHEN "0000" => LED7S <= " " ; -- X 3F 0 WHEN "0001" => LED7S <= " " ; -- X 06 1 WHEN "0010" => LED7S <= " " ; -- X 5B 2 WHEN "0011" => LED7S <= " " ; -- X 4F 3 WHEN "0100" => LED7S <= " " ; -- X 66 4 WHEN "0101" => LED7S <= " " ; -- X 6D 5 WHEN "0110" => LED7S <= " " ; -- X 7D 6 WHEN "0111" => LED7S <= " " ; -- X 07 7 WHEN "1000" => LED7S <= " " ; -- X 7F 8 WHEN "1001" => LED7S <= " " ; -- X 6F 9 WHEN "1010" => LED7S <= " " ; -- X WHEN "1011" => LED7S <= " " ; -- X 7C 11 WHEN "1100" => LED7S <= " " ; -- X WHEN "1101" => LED7S <= " " ; -- X 5E 13 WHEN "1110" => LED7S <= " " ; -- X WHEN "1111" => LED7S <= " " ; -- X WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; 3 TOP.GDF TOP.GDF 1 2 Cnt4.vhd Decl7s.vhd File New Graphic Editor File OK Graphic Editor Graphic Editor (1) Graphic Editor Enter Symbol Symbol Name VHDL 12-21

259 12 VHDL OK Symbol Files Cnt4 Decl7s Symbol Libraries d:\maxvs\guide VHDL VHDL VHDL OK Cnt4 Decl7s INPUT OUTPUT prim e:\maxplus2\max2lib\prim Symbol Files INPUT OUTPUT Symbol Name INPUT OUTPUT MAX+plusII INPUT OUTPUT (2) / / LED7S[7..0] 8 Options Line Style (3) / INPUT OUTPUT TOP.GDF CLK 8 LED7S[7..0] LED7S[7..0] VHDL LED7S7 LED7S0 LED7S7 AHDL VHDL LED7S File Save TOP.GDF 249

260 250 VHDL `, File Name 4 TOP.GDF CLK PIN 23 PIO13 8 TOP.GDF LED7S7 PIN 38 PIO23 D8 LED7S6 PIN 78 PIO46 g Project LED7S5 PIN 73 PIO45 f LED7S4 PIN 72 File Project Set Project to PIO44 e LED7S3 PIN 71 PIO43 d Current File LED7S2 PIN 70 PIO42 c TOP LED7S1 PIN 67 PIO41 b LED7S0 PIN 66 PIO40 a Assign Device Device Family FLEX10K Devices EPF10K10LC OK II MAX+plus Compiler START Assign Pin/Locatio n/chip Node Name Pin: Add LED7S[7..0] LED7S7 LED7S6 LED7S OK GW48 1 NO.6 CLK 8

261 12 VHDL LED7S7 D8 LED7S6 LED7S0 PIO46 PIO40 7, MAX+plus II Compiler VHDL Interfaces VHDL Netlist Reader Settings VHDL VHDL Assign Global Project Logic Synthesis Area Optimize Speed CPLD MAX Device Synthesis Options Define Synthesis Style Style Normal Minimization Full Slow Slew Rate I/O 7128S XOR Synthesis 251 OK Assign Global Project Device Options Security Bit Enable JTAG Suport JTAG OK Compiler Start Fitter rpt 5 TOP MAX+plusII File New New Waveform Editor file OK Node Enter Nodes from SNF List

262 252 VHDL ` => OK CLK 7 LED7S[7..0] Cnt4:1 Q File Save top.scf SNF CLK CLK Value CLK CLK OK OPTIONS Grid Size Simulator MAX+plusII 200ns Simulator Start errors 0 warnings

263 VHDL File End Time 5 s OK MAX+plusII Simulator Simulator End Time 5 s File Open Open Waveform Editor Files Files top.scf 0 1 X Z INV G 6 TOP MAX+plus II Programmer Programmer ( 12-30) FPGA GW48 1 FLEX10K 10K10 Configure 10K10 Configuration Complete F 7 VHDL GDF TOP

264 254 VHDL ` FPGA Configure CPLD EPM7128S Program Configure CLK 42 1/2 10K10 42 Clock1 Clock1 8Hz 4Hz 2Hz 1Hz File Open Open Graphic Editor top.gdf Assign Pin/Location/Pin CLK Pin 42 Change OK MAX+plusII Compiler Start MAX+plus II MAX+plusII FLEX ISP MAX ByteBlaster ByteBlaster Programmer Options Hardware Setup Hardware Type ByteBlaster OK MAX+plus II Synplify EDA VHDL Synopsys FPGA Express Synplicity Synplify VHDL MAX+plusII VHDL EDA VHDL IP EDA MAX+plus II Synplify Synplify VHDL MAX+plus II MAX+plusII TOP TOP Cnt4 Decl7s Cnt4 EDA Synplify 12-2

265 12 VHDL CNTS Synplify File New HDL File OK 12-1 CNTS Cnt4 d:\maxvs\guide CNTS.VHD File New Project OK Synplify-[Unsaved Project] File Save Save as CNTS.PRJ Add CNTS.VHD Add Change Target EPF10K10 OK Run EDIF CNTS.EDF Altera MAX+plus II CNTS.ACF d:\maxvs\guide Synplify Synplify.PRJ MAX+plus II File Project Name Hierarchies Project Name Show Only Tops of Files EDF CNTS.EDF VHDL EDF Interfaces CNTS.EDF File Create Default Symbol top.gdf cnts Cnt4 top.gdf MAX+plusII File Project Name top.gdf Compiler Compiler EPF10K10 Settings Interfaces EDIF Netlist Reader Vendor Synplicity Customize >> LMF #1 MAX+plus II8.0 OK Compiler Start Programmer 255 / 10K10 1 Synplify VHDL 2 MAX+plusII EDF Project File 3 MAX+plusII Interfaces EDIF Netlist Reader Settings EDA Synplicity 4 MAX+plusII 5 MAX+plusII 1 6 EDA

266 256 VHDL ` 12.4 Xilinx Foundation VHDL Foundation Series Xilinx EDA XC3000A/L XC3100A/L XC4000E/L/EX/XL/XV/XLA XC5200 XC9500 C9500XL Spartan SpartanXL Virtex Foundation Foundation Project Manager Xilinx Synopsys FPGA Express Foundation Series EDA Synopsys FPGA Express Foundation VHDL Verilog HDL IP JTAG CPLD FPGA Foundation Foundation Foundation HDL hhdl Flow h (1) Xilinx (2) Options Create Netlist 12-31

267 12 VHDL (3) Logic Simulator (4) Translate Map Place & Route Timing Configure (5) (6) HDL (7) HDL Foundation HDL HDL VHDL VHDL 4 ADDER4b Foundation 1 ADDER4b HDL ADDER4b D \XLINSAM Foundation Foundation Create a New Project OK

268 258 VHDL ` ADDER4b HDL OK File New Project New Project 2 HDL ADDER4b.VHD ADDER4b.VHD (1) HDL Foundation HDL HDL Editor Create Empty OK HDL 12-4 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_ARITH.ALL ; ENTITY ADDER4b IS PORT ( a, b : IN INTEGER RANGE 0 TO 15 ; c : OUT INTEGER RANGE 0 TO 31 ) ; END ADDER4b ; ARCHITECTURE one OF ADDER4b IS c <= a + b ; END one ; (2) 12-4 HDL VHDL File Save ADDER4b.VHD ADDER4b.VHD (3) Project Add to Project ADDER4b.VHD HDL Foundation ADDER4b.VHD HDL

269 12 VHDL VHDL HDL Add to Project VHDL Foundation ADDER4b.VHD Synthesis Check Syntax 3 ADDER4b.VHD ADDER4b (1) 259 Foundation Version Versions Version Version ver1 ver2 ver3 (2) ADDER4b / ADDER4b / Edit Synthesis/Implementation Constraints Speed Area Run Run Pad Loc P P5 5 FPGA 2 XCS10 XCS Global Buffer I/O CLK CLK DONT USE CLK Global Buffer DONT USE

270 260 VHDL ` ( ) Foundation Versions Ver1-SPARTAN- S05PC84-3 Edit Constraints OK Foundation 2. (1) Foundation (2) Signal Add Signals Singal Selection Add Waveform Viewer Ctrl Add Waveform Viewer 0 Close

271 12 VHDL Component Selection for Waveform Viewer A3, A0 B3, B0 C4, C0 A3, A0 A3 A2 A1 A0 Add Close (3) Waveform Edit Test Vector State Selection 12-3 Test Vector State Selection 12-3 Low High Unkn_X High_Z Del Bus Bus Bus State Test Vector State Selection High A3, A0 B3, B Bus

272 262 VHDL ` Bus (4) Simulation Step Tools 50ns ADDER4b (1) Foundation Options Options (2) Optional Targets Produce Timing Simulation Data Produce Configuration Data OK (3) / 12-42

273 12 VHDL Run Flow Engine Foundation Flow Engine 12-4 Running Completed Configure Completed Foundation ADDER4b 12-43

274 264 VHDL ` 7 Hardware Debugger Parallel GW48 1 Download Download Design 12-4 Xilinx CPLD Translate Map Xilinx FPGA XC95108 Place & Route 1 Timing Configure b 2 CPLD 8 XC9500 Project Manager Implementation Options Options XC9500 Edit Template ADDER4b Slew Rate TOP VHDL Cnt4.vhd Decl7s.vhd TOP.VHD