Word Pro - FPGA设计高级技巧（Xilinx篇）.lwp

Size: px

Start display at page:

Download "Word Pro - FPGA设计高级技巧（Xilinx篇）.lwp"

扶涤封
5 years ago
Views:

1 V1.0 FPGA 62 FPGA ( ) 2001/09/15 yyyy/mm/dd yyyy/mm/dd

2 FPGA 2001/09/

3 FPGA Coding Style FPGA VirtexII Coding Style FPGA ASIC Coding Style VirtexII CLB Slice LUT Shift Register LUT SRL MUXFX Carry Logic Arithmetic Logic Gates SOP FFX/FFY Memory Distributed RAM Block RAM IOB IOB Select I/O DCI Clock Resource Global Clock CLK MUX DCM LUT Block SelectRAM IF Case

4 FPGA if if if loop Pipelining fanout virtex virtex LUT IOB Distributed RAM Block SelectRAM SRL LFSR map FPGA Editor FloorPlanner TimingAnalyzer TIG False path Multi-Cycle-Path net MaxdelayMaxskew BUFGS Module Distributed RAM BlockRAM Distributed RAM

5 FPGA VirtexII RAM... 2 VirtexII BlockRAM... 3 Block RAM... 4 VirtexII... 5 VirtexII DCM Mux Mux VirtexII VirtexII CLB SLICE VirtexII Slice SRL VirtexIIMUXFX VirtexII VirtexII SOP FFX/FFY x1 RAM x1 RAM VirtexII Block RAM Write first Read first No Change Block RAM XC2V VirtexIIIOB VirtexII IOB DDR VirtexII IOB VirtexII Clock Pads VirtexII VirtexII

6 FPGA 30 VirtexIIBUFGMUX VirtexIIBUFG VirtexII BUFGCE VirtexII BUFGCE VirtexII 250 DCM VirtexII DCM Block Select RAM Read first mode Write first mode No-read-on-write mode if-else case critical critical Mealy VirtexE IOB IOB Distributed RAM LFSR VIRTEX

7 FPGA FPGA xilinx FPGA LUT FPGA FPGA : ASIC CLB DCI DCM DDR DLL FPGA GRM IOB LFSR LUT SOP SRL UCF Application Specific Integrated Circuit Configurable Logic Block Digitally Controlled Impedance Digital Clock Manager Double Data Rate Delay-Locked Loop Field Programmable Gate Array General Routing Matrix Input/Output Block Linear Feedbak Shift Register Look Up Table Sum of Product Shift Register LUT Custom Constraints File : VHDL / Virtex VerilogHDL FPGA UCF / Xilinx LFSR

8 xilinx gensim.pdf xilinx VirtexII_DesignConsid eration.pdf xilinx sp_block_mem.pdf xilinx lfsr.pdf xilinx ds031(virtexii).pdf VirtexII 1 HDL Hardware Description Language HDL FPGA FPGA ASIC FPGA FPGA RAM HDL FPGA FPGA 2 FPGA

9 FPGA 2.1 Synthesis Optimization ASIC Gate FPGA FPGA ASIC Gate Gate Code Style FPGA 161MUX 4000 case BUFT Buffer 5 CLBs 1 Mux

10 FPGA Mux 8 CLBs 2.2 DC Design Compiler FC2 FPGA Compiler II Synplify Leonardo Galileo DC ASIC FC2DCFPGA FC2 Leonardo FPGA Synplify Synplicity FPGA FPGA FPGA Leonardo DAFPGA ASIC Synplify FPGA Virtex Xilinx XST Synplicity Amplify 2.3 Coding Style FPGA Core FPGA FPGA ASIC FPGAXilinx 1. module 2. Critical path module 3. Critical path module module critial path module

11 4. Register Output module 5. modulesize 6. module verilog 3 FPGA VirtexII 20~30 FPGA shift register IOB register FPGA coregen module VirtexII FPGA FPGA Virtex Virtex xilinx 3.1 Coding Style FPGA Altera FPGA Xilinx FPGA FPGA CLB LE component LUT Altera FPGAFPGA 4 LUT LE CLBComponent FPGA components CLBCLB CLB FPGA

12 FPGA FPGA CLB Virtex LUT LUT FPGA ASIC ASIC FPGA Gage FPGA gate Coding Style ASICFPGA Coding Style FPGA Coding ASCI Coding Gate Array shandard cell Coding Gate Array 66M FPGA M FPGA Code Style ASIC ---- FPGA LUT FPGA 3.2 VirtexII VirtexII 1.5v FPGA 1 FPGA 40K xc2v40 10M xc2v M 840Mb/s I/O 2 19 single-ended IO 9 IO VirtexII XCITE 3 IOB DDR Double Data Rate 1108 sink current 2ma 24ma 4 RAM RAM18Kbit 400M b/s DDR-SDRAM 400Mb/s FCRAM RAM

FPGA 333Mb/sQDR-SRAM 600Mb/s Sigma RAM 5 18bit x 18 bit 6 7 DLL 12DCM 8 SRAM 9.15um 8 3.

13 FPGA 333Mb/sQDR-SRAM 600Mb/s Sigma RAM 5 18bit x 18 bit 6 7 DLL 12DCM 8 SRAM 9.15um VirtexII 16 3 VirtexII VirtexII Virtex VirtexE IOBs CLBs IOBCLB DCM DLL CLB Slice VirtexII CLBVirtex Family VirtexE Family CLB

14 FPGA 4 VirtexII CLB CLB 4 Slice 4Slice Slice GRM CLB 4slice 4Slice slice SHIFT Slice Slice 24 LUT GF2Storage element FFX FFY D Slice carry logic arithmetic logic gates multiplexers G4 G3 G2 G1 F4 F3 F2 F1 LUT G LUT F FFY FFX 5 SLICE

15 FPGA FPGA Slice FPGA VirtexII slice 6 VirtexII Slice VirtexII Slice LUT Slice 4 LUT FG Function Generator 4000 LUT RAM LUT 16X1RAM 4 GG1 G4 FF1 F4 RAM RAM 1 4 RAMROM LUT RAM Distributed RAM RAM WG

16 FPGA CLB LUT 4 LUT Shift Register LUT SRL LUT 16 LUT CLB4Slice SRL16 LUTMC15 Slice G MC15 DIF_MUXSHIFTIN F shiftin SHIFTOUT F MC15 slice 7 SRL SRL Shift Registers LUT MUXFX LUTVirtexII Slice MUXF7 MUXF5 MUXF8 MUXF5 Slice LUT F G 9 CLB 4 MUX MUXFX FX MUXF6 MUXFX MUXF6 MUXF7 MUXF8 FXINA FXINB MUXFX F6 F7F8 Slice MUX Slice MUXF5 X0Y0 X1Y0 Slice MUXFX MUXF6 F6 MUXF6 CLB Slice CLB Slice MUXF7 MUXF7 81MUX 19 MUX F6 X0Y1 Slice MUXFX MUXF7 CLB 39 81MUX

17 FPGA F7 CLB 4 Slice 161 MUX MUXF8 MUXF8 MUXF5 MUX Slice F7 X1Y1 Slice MUXFX MUXF8 F8 CLB 321MUX MUXFX CLB F8 Slice S3 F6 F5 Slice S2 F5 Slice S1 F5 F7 Slice S0 F5 F6 8 VirtexIIMUXFX Carry Logic Arithmetic Logic Gates Arithmetic Logic Gates XOR MULTIAND VirtexII Slice Slice VirtexII MUXCYXOR MUXCY

18 FPGA 9 3bit

19 FPGA 11 VirtexII CLB

20 FPGA 12 VirtexII SOP VirtexII Slice OR ORCY SOP Slice

21 FPGA 13 VirtexII SOP 4LUT4MUXCY 16 ORCY FFX/FFY VirtexII FFX FFY FFX/FFY 4attribute SRHIGH SRLOW INIT1INIT0 SR 01 configuration GSR 0 1 UCF 14 FFX/FFY DYG LUT YSlice VirtexII Slice 3.4 Memory Distributed RAM VirtexIILUT RAM RAM RAM R/W VirtexIICLB4Slice RAM

22 FPGA RAM RAM 1 VirtexII RAM X Lut 16 x x x x x x x 1 8 Distributed RAM 15 32x1 RAM

23 FPGA 16 16x1 RAM Block RAM VirtexII Block RAM Block 18k bit Block RAM4 6 VirtexII

24 FPGA 17 VirtexII Block RAM N CLB 4 2 VirtexII BlockRAM RAM18bit

25 FPGA 3 Block RAM Configuration Depth Data bits Parity bits 16K x 1 16Kb 1 0 8K x 2 8Kb 2 0 4K x 4 4Kb 4 0 2K x 9 2Kb 8 1 1K x 18 1Kb x VirtexII block RAM Write first new data is written and then appears on the RAM output Data_in RAM DO Data_out = Data_in 18 Write first Read first Previous data value is read from the WRITE address, then held on the output during the WRITE operation Data_in RAM DO DO = prior stored data 19 Read first NO CHANGE RAM output only changes when WE is inactive Data_in DI RAM DO DO (no change during Write 20 No Change Block RAM sp_block_mem.pdf 3.5 VirtexII 18bits x 18bits VirtexII Block RAM Block RAM

26 FPGA 21 Block RAM 22 XC2V

27 FPGA 4 VirtexII 4x4 signed 8x8 signed 12x12 signed 18x18 signed ~255 MHz ~210 MHz ~170 MHz ~140 MHz 3.6 IOB IOB I/Obuf DELAY I/O buf IOB 5I/O Buf buf IOBUF buf IBUFG buf IBUF buf OBUF buf OBUFT Virtex II IOB IOB DDR IO DCI IOB VirtexII IOB VirtexII IO IO 5IOB 4IOB 24 VirtexIIIOB VirtexIIIOB IOB I/Obuf DELAY DDR DDR MUX DDR DCM DDR IOB

28 FPGA 25 VirtexII IOB DDR 26 VirtexII IOB Select I/O VirtexII Select I/O VirtexII 8 banks banks VRNVRP IO

29 FPGA VirtexII 19 signal-ended IO --LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) --PCI-X at 133MHz, PCI (3.3V at 33MHz and 66MHz) --GTL, GTLP --HSTL (Class I, II, III, and IV) --SSTL (3.3V and 2.5V, Class I and II) --AGP-2X DCI --LVDS, BLVDS, ULVDS --LDT --LVPECL VirtexII DCI Digital Controlled Impedance IO 3.7 Clock Resource VirtexII 16 Virtex II Global Clock VirtexII MUX MUX VirtexII Clock Pads

30 FPGA MUX 28 VirtexII VirtexII 16 MUX 4 8 VirtexII 29 VirtexII CLK MUX VirtexII MUXBUFGMUX DCM BUFGMUX

31 FPGA 30 VirtexIIBUFGMUX BUFGMUX BUFG BUF 31 VirtexIIBUFG BUFGCE Enable Buf BUFGMUX MUX 32 VirtexII BUFGCE

32 FPGA 33 VirtexII BUFGCE DCM VirtexII Virtex DLL DCM Digital Clock Manager VirtexII 12DCM DCM CLB DCM V2250 8DCM DCM VirtexII 250 DCM VirtexII DCM

33 FPGA 5 VirtexII DCM VirtexII DCM 35 VirtexII DCM DCM DLL DLL Delay-Locked Loop DLL DCM 0 DPS Digital Phase Shifter DCM 4 DFS Digital Frequency Synthesizer DSS Digital Spread Spectrum

34 FPGA LUT LUT 16X1RAM 4 RAM 0 3 LUT F F= F4 F3 F2 F= F4 F3 F2 F1 F4 F3 F2 /F1 /. F4~ or 1110 F= 1 3F4 2 F4 1RAM LUT F2 0 RAM F4 F F LUT LUT LUT 3. LUT LUT FPGA LUT LUT ASIC

35 36 a LUT 2 LUT 2 LUT 3LUT LUT 2 b 2 a 2 LUT 2LUT 2 3 LUTLUT Block SelectRAM Block SelectRAM RAM RAM RAM FPGA

36 FPGA 37 Block Select RAM RAM RAM Block Memory VirtexII Block Memory Write First Read First No-read-on-write No Change DI WE MO D Q DOUT ADDR EN CLK EN CLK 38 Read first mode

37 FPGA DI WE MO 0 1 REG_D D Q DOUT ADDR EN CLK EN CLK 39 Write first mode DI WE MO D Q DOUT ADDR EN CLK EN CLK 40 No-read-on-write mode Distributed RAM Distributed RAM 4 LUT

38 FPGA VHDL verilog VerilogHDL VHDL VHDL -- A is the addend -- B is the augend -- C is the carry -- Cin is the carry in C0 <= (A0 and B0) or ((A0 or B0) and Cin); C1 <= (A1 and B1) or ((A1 or B1) and C0); -- Ps are propagate -- Gs are generate p0 <= a0 or b0; g0 <= a0 and b0; p1 <= a1 or b1; g1 <= a1 and b1; c0 <= g0 or (p0 and cin);

39 FPGA c1 <= g1 or (p1 and g0) or (p1 and p0 and cin); 42 Virtex FPGA FPGA Z <= A + B + C + D; 43 Z <= (A + B) + (C + D);

40 FPGA D A B C D A B C D 4.2 IF Case IF Case IF Case Case Case IF-Else IF-Else IF IF IF speed-critical paths Critical Signal IFCase IF-Then-Else 81 MUX6to1:process(sel,in) begin if(sel= "000") then out <= in(0); elseif(sel = "001") then out <= in(1); elseif(sel = "010") then out <= in(2); elseif(sel = "011") then out <= in(3); elseif(sel = "100") then else end if; end process; out <= in(4); out <= in(5);

FPGA 45 if-else Case 81 VHDL FPGA CLB 41 Virtex CLB 81 IF-Else CLB Case Case 81 MUX8to1 process( C, D, E, F, G, H, I, J, S ) begin case S is end case; end process; when 000 => Z <= C; when 001 => Z

41 FPGA 45 if-else Case 81 VHDL FPGA CLB 41 Virtex CLB 81 IF-Else CLB Case Case 81 MUX8to1 process( C, D, E, F, G, H, I, J, S ) begin case S is end case; end process; when 000 => Z <= C; when 001 => Z <= D; when 010 => Z <= E; when 011 => Z <= F; when 100 => Z <= G; when 101 => Z <= H; when 110 => Z <= I; when others => Z <= J; 46 case 4.3 FPGA critical path critical 2 if (clk'event and clk ='1') then

42 FPGA if (non_critical='1' and critical='1') then out1 <= in1; else out1 <= in2; end if; end if; 47 critical 2 critical critical signal out_temp : std_logic; process (non_critical, in1, in2) if (non_critical='1') then else end if; end process; process(clk) out_temp <= in1; out_temp <= in2; if (clk'event and clk ='1') then if (critical='1') then else end if; end if; end process; out1 <= out_temp; out1 <= in2;

43 FPGA 48 critical FPGA 4 LUT ASIC if if if If 1 then Do action1 Else if 2 then Do action2 Else if 3 then Do action if 3 If 3 then Do action3 Else if 1 then Do action1 Else if 2 then Do action2 4.4 if if if If 1 then

44 FPGA 1 Else if 2 then 0 Else if 3 then 1 Else if 4 then 0 if If 1 or 3 then 1 Else if 2 or 4 then if HDL HDL VHDL 4 if (...(siz = "0001")...) then count <= count + "0001"; else if (...((siz = "0010")...) then count <= count + "0010"; else if (...(siz = "0011")...) then count <= count + "0011"; else if (...(siz == "0000")...)then count <= count + "0100"; end if; 2 if (...(siz = "0000")...) then count <= count + "0100"; else if (...) then count <= count + siz; end if;

45 FPGA if (select = '1') then sum<=a +B; else sum<=c +D; end if; if (sel ='1') then else temp1 <=A; temp2 <=B; temp1 <=C; temp2 <=D; end if; sum <= temp1 + temp2; loop VHDL 4 req for i in 0 to 3 loop if (req(i)='1') then sum <= vsum + offset(i);

46 FPGA end if; end loop; req 51 4 for i in 0 to 3 loop if (req(i)='1') then offset_1 <= offset(i); end if; end loop; sum <= vsum + offset_1; VHDL a+b temp <= a + b; x <= temp; y <= temp + c;

47 FPGA FPGA CompilerII/FPGA Express 1. * + - > < >= <= 2. position sum1 <= A + B + C; sum2 <= D + A +B; sum3 <= E + (A +B); sum1sum3 (A +B), sum2 3. block process if (cond1 =..) then else end if ; S1 <= A +B ; if (cond2...) then else end if ; S2 <= E + F ; S3 <= G+ H ; S2 S3 S1 ASIC FPGA ASIC 4.6 Pipelining FPGA FPGA clock-to-out

48 FPGA process(clk, a, b, c) begin if(clk'event and clk = '1') then a_temp <= a; b_temp <= b; c_temp <= c; end if; end process; Process(clk, a_temp, b_temp, c_temp) begin if(clk'event and clk = '1') then out <= (a_temp * b_temp) + c_temp; end if; end process; 53 process(clk, a, b, c) begin if(clk'event and clk = '1') then a_temp <= a; b_temp <= b; c_temp1 <= c; end if; end process; process(clk, a_temp, b_temp, c_temp1) begin if(clk'event and clk = '1') then mult_temp <= a_temp * b_temp

49 FPGA end if; end process; c_temp2 <= c_temp1; process(clk, mult_temp, c_temp2) begin if(clk'event and clk = '1') then out <= mult_temp + c_temp2; end if; end process; Mealy Mealy 55 Mealy

50 FPGA Mealy Mealy VHDL 5 Mealy -- Example of a 5-state Mealy FSM library ieee; use ieee.std_logic_1164.all; entity mealy is port (clock, reset: in std_logic; data_out: out std_logic; data_in: in std_logic_vector (1 downto 0)); end mealy; architecture behave of mealy is type state_values is (st0, st1, st2, st3, st4); signal pres_state, next_state: state_values; begin -- FSM register statereg: process (clock, reset) begin if (reset = '0') then pres_state <= st0; elsif (clock'event and clock ='1') then pres_state <= next_state; end if; end process statereg; -- FSM combinational block fsm: process (pres_state, data_in) begin case pres_state is when st0 => case data_in is when "00" => next_state <= st0; when "01" => next_state <= st4; when "10" => next_state <= st1;

51 FPGA when "11" => next_state <= st2; when others => next_state <= (others <= 'x'); end case; when st1 => case data_in is when "00" => next_state <= st0; when "10" => next_state <= st2; when others => next_state <= st1; end case; when st2 => case data_in is when "00" => next_state <= st1; when "01" => next_state <= st1; when "10" => next_state <= st3; when "11" => next_state <= st3; when others => next_state <= (others <= 'x'); end case; when st3 => case data_in is when "01" => next_state <= st4; when "11" => next_state <= st4; when others => next_state <= st3; end case; when st4 => case data_in is when "11" => next_state <= st4; when others => next_state <= st0; end case; when others => next_state <= st0; end case; end process fsm; -- Mealy output definition using pres_state w/ data_in outputs: process (pres_state, data_in) begin case pres_state is when st0 =>

52 FPGA case data_in is end case; when st1 => data_out <= '0'; when st2 => case data_in is end case; when st3 => data_out <= '1'; when st4 => case data_in is end case; when "00" => data_out <= '0'; when others => data_out <= '1'; when "00" => data_out <= '0'; when "01" => data_out <= '0'; when others => data_out <= '1'; when "10" => data_out <= '1'; when "11" => data_out <= '1'; when others => data_out <= '0'; end case; end process outputs; end behave; when others => data_out <= '0'; 4.8 a b 56 a b c

53 fanout VHDL Tri_en FPGA

54 FPGA 59 buffer virtex CLB XC4000Spartan CLB 6 F GH 41 CLB CLB buffer BUFT BUFT 1 2 buffer 3 BUFTCLB CLB 4 one-hot 60 BUFT

55 61 xilinx CLB virtex virtex MUX CLB VirtexII CLB4slice 161 CLB CLB MUXF LUT LUT LUT LUT 4.12 IOB FPGA

56 FPGA 62 VirtexE IOB IOB IOB CLB 63 IOB FPGA Register Register FPGA 5663

57 FPGA 1. IOB register 2. FPGA Register Input DelayOutput Delay IOB D NODELAY UCF I/O Slew rate I/O IOB IOB IOB 1. IOB 2. IOB CLB IOB FPGA ASIC xlinx IOB Buffer IBUFG IOB Virtex II 4.13 Distributed RAM Distributed RAM Virtex Block RAM Distributed RAM Block RAM RAM Distributed RAM LUTRAM 64X32 RAMLUT 1 2 RAM Distributed RAM bits 1 Block RAM

58 FPGA +1 ADDR MCLK WE_CON DIN A Distributed DO RAM W_CLK WE DOUT 64 Distributed RAM 1 Distributed RAM RAM RAM LUT 16registers 4.14 Block SelectRAM Block SelectRAM RAM RAM Block SelectRAM FPGA FPGA ASIC 1. RAM ASICRAM ASIC 2. RAM ASIC 3. FPGA ASIC ASIC RAM RAM Block SelectRAM BlockRAM SelectRAM LUT RAM Block SelectRAM Distributed RAM 4.15 SRL LUT 16 LUT 4.16 LFSR

59 FPGA LFSR FIFO LFSR LFSR SRL 15bit LFSR SRL 16 SRL LFSR VIRTEX LFSR LFSR lfsr.pdf 5 Xilinx

60 TIG Multi-Cycle-Path ucf map Virtex FPGA map 100% slice LUT Regsiter LUTRegister LUT Register Block RAM Slice 5.2 FPGA Editor FPGA Editor FPGA Editor FPGA

61 FPGA FPGA Editor 5.3 FloorPlanner FloorPlanner place ucf mfp Place and Route LUT LUTplace module moduleplace place place place place 5.4 TimingAnalyzer TimingAnalyzer TimingAnalyzer TimingAnalyzer TimingAnalyzer FPGA Distributed RAM Pipeline 6.2 LUT TIG False path Multi-Cycle-Path TIGMulti-Cycle-Path

62 LUT net MaxdelayMaxskew BUFGS net BUFGS BUFGS copy fanout case if if LUT pipeline LUT MUX SRL Coregen ASIC ASIC Module LUT floorplanner LUT 6.3 FPGA

63 FPGA Distributed RAM BlockRAM LUTBLOCK RAM Distributed RAM BlockRAM Distributed RAM if case LUT IOB BlockRAM ASIC 2.3 Coding Style

a b c d e f g C2 C1 2

a b c d e f g C2 C1 2 IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3 BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4