Microsoft PowerPoint - STU_EC_Ch07.ppt

Size: px

Start display at page:

Download "Microsoft PowerPoint - STU_EC_Ch07.ppt"

谋样宁
4 years ago
Views:

1 樹德科技大學資訊工程系 Chapter 7: Flip-Flops and Related Devices Shi-Huang Chen Fall Outline Latches Edge-Triggered Flip-Flops Master-Slave Flip-Flops Flip-Flop Operating Characteristics Flip-Flop Applications One-Shots The 555 Timer 2 1

2 Latches A latch ( 閂 ) is a temporary storage device that has two stable states (bistable). It is a basic form of memory. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-high inputs; with NAND gates, it responds to active-low inputs. R S S NOR Active-HIGH Latch R NAND Active-LOW Latch 3 S-R (SET-RESET) Latch (1) The active-high S-R latch is in a stable (latched) condition when both inputs are LOW. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (0). To SET the latch ( = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. To RESET the latch ( = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. 0 R 10 Latch initially RESET 01 0 S 0 0 R S 01 Latch initially SET

3 S-R (SET-RESET) Latch (2) The active-low S-R latch is in a stable (latched) condition when both inputs are HIGH. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (1). To SET the latch ( = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid). 1 S 10 Latch initially RESET 01 1 R 1 S 1 R 01 Latch initially 10 SET 5 S-R (SET-RESET) Latch (3) The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition. 6 3

4 S-R (SET-RESET) Latch (4) 7 S-R (SET-RESET) Latch (5) (c) No-change condition (d) Invalid condition 8 4

5 S-R (SET-RESET) Latch (6) 9 S-R (SET-RESET) Latch (7) Logic symbols 10 5

6 The 74LS279 quad S-R latch 11 Application Example The S-R latch used to eliminate switch contact bounce. 12 6

7 A Gated S-R Latch A gated latch is a variation on the basic latch. The gated latch has an additional S input, called enable (EN) that must be HIGH in order for the latch to EN respond to the S and R inputs. Show the output with relation to the input signals. R Assume starts LOW. Keep in mind that S and R are only active when EN is HIGH. S R EN 13 A Gated D Latch (1) The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D D EN EN A simple rule for the D latch is: follows D when the Enable is active. 14 7

8 A Gated D Latch (2) D Determine the output for the D latch, given the inputs shown. EN D EN Notice that the Enable is not active during these times, so the output is latched. 15 The 74LS75 quad gated D latches 16 8

9 Flip-Flops (1) A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative. D D C C Dynamic input indicator (a) Positive edge-triggered (b) Negative edge-triggered 17 Flip-Flops (2) The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock; otherwise it is latched. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. Inputs Outputs D Comments SET RESET Inputs Outputs D Comments SET RESET (a) Positive-edge triggered (b) Negative-edge triggered 18 9

10 Flip-Flops (3) The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). J Inputs K Outputs Comments No change RESET SET Toggle 19 Flip-Flops (4) Determine the output for the J-K flip-flop, given the inputs shown. Notice that the outputs change on the leading edge of the clock. J K Set Toggle Set Latch J K 20 10

11 Flip-Flops (5) A D-flip-flop does not have a toggle mode like the J-K flipflop, but you can hardwire a toggle mode by connecting back to D as shown. This is useful in some counters as you will see in Chapter 8. For example, if is LOW, is HIGH and the flip-flop will toggle on the next clock edge. Because the flip-flop only changes on the active edge, the output will only change once for each clock pulse. D D flip-flop hardwired for a toggle mode 21 Flip-Flops (6) Synchronous inputs are transferred in the triggering edge of the clock (for example the D or J-K inputs). Most flipflops have other inputs that are asynchronous, meaning they affect the output independent of the clock. Two such inputs are normally labeled preset (PRE) and clear (CLR). These inputs are usually active LOW. A J-K flip flop with active LOW preset and CLR is shown. PRE J K CLR 22 11

12 Flip-Flops (7) PRE Determine the output for the J-K flip-flop, given the inputs shown. J K J Set Toggle Set Reset Toggle CLR Latch K PRE CLR Set Reset 23 Flip-Flops (8) Flip-flop Characteristics Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. 50% point on triggering edge 50% point 50% point on LOW-to- HIGH transition of 50% point on HIGH-to- LOW transition of t PLH t PHL The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications

13 Flip-Flops (9) Flip-flop Characteristics Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns. PRE 50% point CLR 50% point 50% point 50% point t PHL t PLH 25 Flip-Flops (10) Flip-flop Characteristics Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Setup time is the minimum time for the data to be present before the clock. D Set-up time, t s Hold time is the minimum time for the data to remain after the clock. D Hold time, t H 26 13

14 Flip-Flops (11) Flip-flop Characteristics Other specifications include maximum clock frequency, minimum pulse widths for various inputs, and power dissipation. The power dissipation is the product of the supply voltage and the average current required. A useful comparison between logic families is the speed-power product which uses two of the specifications discussed: the average propagation delay and the average power dissipation. The unit is energy. What is the speed-power product for 74AHC74A? Use the data from Table 7-5 to determine the answer. From Table 7-5, the average propagation delay is 4.6 ns. The quiescent power dissipated is 1.1 mw. Therefore, the speed-power product is 5.06 pj 27 Flip-Flop Applications (1) Example of flip-flops used in a basic register for parallel data storage For data storage applications, a group of flip-flops are connected to parallel data lines and clocked together. Data is stored until the next clock pulse

15 Flip-Flop Applications (2) The J-K flip-flop as a divide-by-2 device. is one-half the frequency of. Frequency Division 29 Flip-Flop Applications (3) Example of two J-K flip-flops used to divide the clock frequency by 4. A is one-half and B is one-fourth the frequency of. If = 100 MHz A = 50 MHz B = 25 MHz 30 15

16 Flip-Flop Applications (4) 31 Flip-Flop Applications (5) Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown 32 16

17 Flip-Flop Applications (6) 33 One-Shot (1) The one-shot or monostable multivibrator is a device with only one stable state. When triggered, it goes to its unstable state for a predetermined length of time, then returns to its stable state. +V For most one-shots, the length of time in the unstable state (t W ) is determined by an external RC circuit. R EXT Trigger C EXT CX RX/CX Trigger t W 34 17

18 One-Shot (2) Nonretriggerable one-shot action 35 One-Shot (3) Retriggerable one-shot action 36 18

The 555 Timer (1) The 555 timer can be configured in various ways, including as a one-shot. A basic one shot is shown. The pulse width is determined by R 1 C 1 and is approximately +V t W = 1.

19 The 555 Timer (1) The 555 timer can be configured in various ways, including as a one-shot. A basic one shot is shown. The pulse width is determined by R 1 C 1 and is approximately +V t W = 1.1R 1 C 1. CC (4) (8) R 1 (7) RESET DISCH V CC The trigger is a negative-going pulse. (6) (2) C 1 THRES OUT TRIG CONT GND (1) (3) (5) t W = 1.1R 1 C 1 37 The 555 Timer (2) Internal functional diagram of a 555 timer, pin numbers are in () 38 19

20 The 555 Timer (3) Determine the pulse width for the circuit shown. t W = 1.1R 1 C 1 = 1.1(10 kω)(2.2 μf) = 24.2 ms +V CC +15 V R 1 (4) (8) 10 kω (7) RESET DISCH V CC (6) THRES OUT (3) C μf (2) TRIG CONT GND (1) (5) t W = 1.1R 1 C 1 39 The 555 Timer (4) The 555 can be configured as a basic astable multivibrator with the circuit shown. In this circuit C 1 charges through R 1 and R 2 and discharges through only R 2. The output +V frequency is given by: CC f = 1.44 R R C ( + 2 ) The frequency and duty cycle are set by these components. ( R + R2 ) Duty Cycle = ( R + 2R ) % R 1 R 2 C 1 (4) (8) RESET (7) DISCH (6) THRES (2) TRIG GND V CC OUT CONT (3) (5) (1) 40 20

The 555 Timer (5) Given the components, you can read the frequency from the chart. Alternatively, you can use the chart to pick components for a desired frequency. 100 +V CC C 1 (μf) 10 1.0 0.1 0.

21 The 555 Timer (5) Given the components, you can read the frequency from the chart. Alternatively, you can use the chart to pick components for a desired frequency V CC C 1 (μf) MΩ 1 MΩ 10 kω 100 kω 1 kω R 1 R 2 C 1 (4) (8) RESET V CC (7) DISCH (6) THRES OUT (2) TRIG CONT GND (1) (3) (5) k 10k 100k f (Hz) 41 Example: Frequency and Duty Cycle f = ( R R ) C = = 5.64kHz (2.2kΩ + 9.4kΩ)0.022μF ( R1 + R2) Duty Cycle = 100% ( R + 2R ) 1 2.2kΩ + 4.7kΩ = 100% = 59.5% 2.2kΩ + 9.4kΩ

Microsoft PowerPoint - STU_EC_Ch08.ppt

Microsoft PowerPoint - STU_EC_Ch08.ppt 樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters