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2 EDA_VHDL / 1-1 QuartusII 1-2. QuartusII / 1-8. QuartusII QuartusII QuartusII VHDL A/D D/A A/D (CRC) FPGA ( ) FPGA PWM VGA VGA GW48PK2 VGA (DDS) ( ) PLL DDS 200MHz DAC PLL DDS ( ) A/D ( PLL, ) ( ) / ( ) FPGA isp ( ) PS/ PS/2 VGA FPGA_ _PC ( ) IP NCO IP FIR 2

3 1-42. IP FFT IP CSC VGA IP SignalTapII CPU 2-1 ALU 2-2 ALU FIFO / CPU PC AR CPU /89C51 FPGA SOPC/EDA I DSP Builder FIR 3-4 DSP Builder IIR 3-5 DSP Builder DDS 3-6 m RS 3-9 EDA 4-1 EDA PAC _Designer 4-2 isppac isppac GDM12864A 5-2 HS G A SOPC/EDA II 6-1 MATLAB/DSP Builder DSP Nis 6-3 SOPC GSM 6-6 SOPC 6-7 Nis Avaln Slave PWM 6-8 Nis Avaln Slave 6-9 Nis 3

4 6-10 Nis VGA 6-11 Nis 6-12 Nis 6-13 Nis FIFO 6-14 Nis FFT 6-15 DMA 6-16 SOPC 6-17 SOPC GPRS 6-18 SOPC GPS GW48 EDA/SOPC EDA/SOPC 1 GW48-PK2/PK3 GW48-CK GW48-SOPC EDA VHDL SOPC 5 EDA QuartusII FPGA VHDL EDA VHDL SOPC 6 QuartusII MATLAB DSP Builder SOPC Builder Mdelsim 7 Cyclne FPGA EP1C3 EP1C6 EP1C6 EP1C3 EP1C6 EP1C FPGA SOPC AD/DA USB20 ARM GPRS GPS 4

5 \Experiments\chapter4\Ep1c3_41_mux21A\ mux21a (1) Quartus VHDL (2) 1 Quartus (mux21a.vhd) 3-3 (3) 2 mux21a COMPONENT MUX21A PORT ( a b s : IN STD_LOGIC; y : OUT STD_LOGIC); END COMPONENT... u1 : MUX21A PORT MAP(a=>a2 b=>a3 s=>s0 y=>tmp); u2 : MUX21A PORT MAP(a=>a1 b=>tmp s=>s1 y=>uty); END ARCHITECTURE BHV ; 3-3 ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE ne OF mux21a IS PROCESS (a,b,s) IF s = '0' THEN y <= a ; ELSE y <= b ; END IF; END PROCESS; END ARCHITECTURE ne ; mux21a (4) 3 EP1C (PIO0 1) s0 2(PIO1 2) s1 a3 a2 a1 clck5( 16) clck0( 93) clck2( 17) uty spker( 129) clck0 256Hz clck5 1024Hz clck2 8Hz 1 2 s0 s1 5

6 (5) (6) 1 Quartus 3.3 (7) QuartusII (1) Quartus VHDL (2) ( 3-6) 3-6 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF1 IS PORT (CLK : IN STD_LOGIC ; D : IN STD_LOGIC ; Q : OUT STD_LOGIC ); END ; ARCHITECTURE bhv OF DFF1 IS SIGNAL Q1 : STD_LOGIC ; -- PROCESS (CLK,Q1) IF CLK'EVENT AND CLK = '1' THEN Q1 <= D ; END IF; END PROCESS ; Q <= Q1 ; END bhv; (3) 2( 3-14) PROCESS (CLK D) IF CLK = '1' -- THEN Q <= D ; END IF; END PROCESS ; (4) Cin Cut 2 3 FPGA GW48 EDA Cin D1 Cut clck0 8 8 / 0 / / (5) \Experiments\chapter4\Ep1c3_43_cnt10\ cnt10 (1) VHDL 6

7 (2) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS PROCESS(CLK, RST, EN) VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0); IF RST = '1' THEN CQI := (OTHERS =>'0') ; -- ELSIF CLK'EVENT AND CLK='1' THEN -- IF EN = '1' THEN -- IF CQI < 9 THEN CQI := CQI + 1; --, 9 ELSE CQI := (OTHERS =>'0'); -- 9 END IF; END IF; END IF; IF CQI = 9 THEN COUT <= '1'; -- 9 ELSE COUT <= '0'; END IF; CQ <= CQI; -- END PROCESS; END behav; (3) 1 Quartus 3-22 (4) (5) 3 SignalTap II 4.3 (6) 4 SignalTap II EPCS1 POF ByteBlasterII AS EPCS1 (7) 4 SignalTap II clck0=12mhz CLK 256Hz 16384Hz 6MHz (8) 3-22 CQI CQ <= CQ + 1 (9) \Experiments\chapter5\Ep1c3_51_DECL7S\ DECL7S (1) 7 VHDL CASE (2) 7 IC BCD FPGA/CPLD LED7S LED7S g f e d c b a h 5-18 LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) (7 DOWNTO 0) (3) QuartusII

8 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DECL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) ; END ; ARCHITECTURE ne OF DECL7S IS PROCESS( A ) CASE A IS WHEN "0000" => LED7S <= " " ; WHEN "0001" => LED7S <= " " ; WHEN "0010" => LED7S <= " " ; WHEN "0011" => LED7S <= " " ; WHEN "0100" => LED7S <= " " ; WHEN "0101" => LED7S <= " " ; WHEN "0110" => LED7S <= " " ; WHEN "0111" => LED7S <= " " ; WHEN "1000" => LED7S <= " " ; WHEN "1001" => LED7S <= " " ; WHEN "1010" => LED7S <= " " ; WHEN "1011" => LED7S <= " " ; WHEN "1100" => LED7S <= " " ; WHEN "1101" => LED7S <= " " ; WHEN "1110" => LED7S <= " " ; WHEN "1111" => LED7S <= " " ; WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ; (4) 2 GW (PIO46-PIO40) (5) VHDL CNT4B DECL7S tmp 4 led ( 2 1 ) clck0 (6) \Experiments\chapter5\Ep1c3_52_SCAN\ SCAN_LED (1) 8

9 (2) h g f e d c b a h 8 8 k1 k2 k8 k3 k k1 k2 k clk SG 7 g f e d c b a 7 BT k1 k2 k8 CNT8 3 P2 P P1 8 CNT8 "001" K2 A 3 P3 " " 3 CNT BDF LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SCAN_LED IS PORT ( CLK : IN STD_LOGIC; SG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- BT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-- END; ARCHITECTURE ne OF SCAN_LED IS SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL A : INTEGER RANGE 0 TO 15; P1 PROCESS( CNT8 ) CASE CNT8 IS WHEN "000" => BT <= " " ; A <= 1 ; WHEN "001" => BT <= " " ; A <= 3 ; WHEN "010" => BT <= " " ; A <= 5 ; WHEN "011" => BT <= " " ; A <= 7 ; WHEN "100" => BT <= " " ; A <= 9 ; WHEN "101" => BT <= " " ; A <= 11 ; WHEN "110" => BT <= " " ; A <= 13 ; WHEN "111" => BT <= " " ; A <= 15 ; WHEN OTHERS => NULL ; END CASE ; END PROCESS P1; P2 PROCESS(CLK) IF CLK'EVENT AND CLK = '1' THEN CNT8 <= CNT8 + 1; END IF; END PROCESS P2 ; P3 PROCESS( A ) - CASE A IS WHEN 0 => SG <= " "; WHEN 1 => SG <= " "; WHEN 2 => SG <= " "; WHEN 3 => SG <= " "; WHEN 4 => SG <= " "; WHEN 5 => SG <= " "; WHEN 6 => SG <= " "; WHEN 7 => SG <= " "; WHEN 8 => SG <= " "; WHEN 9 => SG <= " "; WHEN 10 => SG <= " "; WHEN 11 => SG <= " "; WHEN 12 => SG <= " "; WHEN 13 => SG <= " "; WHEN 14 => SG <= " "; WHEN 15 => SG <= " "; WHEN OTHERS => NULL ; 9

10 END CASE ; END PROCESS P3; END; (3) SG 8 PIO49 PIO48 PIO42 BT 8 PIO34 PIO35 PIO41 12 GW48EDA CLK clck Hz (4) P A/D 1-6. \Experiments\chapter5\Ep1c3_53_DVF\ DVF (1) (2) 5-20 (3) P_REG P_DIV RTL 100.0µs 200.0µs 300.0µs 400.0µs 5-21 D FOUT (CLK =50ns) (4) CLK D 5-21 (5) / 1 8 D(PIO7-PIO0) CLK clck Hz ( ) FOUT (SPKER) 2/ 1 (6) PWM (7) (8) 5-20 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DVF IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT : OUT STD_LOGIC ); END; ARCHITECTURE ne OF DVF IS SIGNAL FULL : STD_LOGIC; P_REG: PROCESS(CLK) VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0); IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = " " THEN CNT8 := D; -- CNT8 D CNT8 FULL <= '1'; -- FULL ELSE CNT8 := CNT8 + 1; --1 FULL <= '0'; -- FULL END IF; END IF; 10

11 END PROCESS P_REG ; P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; IF FULL'EVENT AND FULL = '1' THEN CNT2 := NOT CNT2; -- FULL D IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF; END PROCESS P_DIV ; END; CPU (1) Quartus 8 EDA (2) cut cin (3) (PIO0/1/2) ain bin cin D2 D1(PIO9/8) sum cut (4) /5 D8 cut (5) 8 (1) 74 8 (2) (3) F_IN clck0 CLK clck2 clck2 = 8Hz CNT_EN 1 8 (4) \Experiments\chapter7\Ep1c3_71_SINGT\ SINGT 1 QuartusII LPM_ROM FPGA Quartus II Cyclne SignalTap II FPGA ROM 11

12 EPCS1 7-4 LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SINGT IS PORT ( CLK : IN STD_LOGIC; -- DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );--8 END; ARCHITECTURE DACC OF SINGT IS COMPONENT data_rm -- LPM_ROM data_rm.vhd PORT(address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);--6 inclck : IN STD_LOGIC ;-- q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; SIGNAL Q1 : STD_LOGIC_VECTOR (5 DOWNTO 0); -- PROCESS(CLK ) --LPM_ROM IF CLK'EVENT AND CLK = '1' THEN Q1<=Q1+1; --Q1 END IF; END PROCESS; u1 : data_rm PORT MAP(address=>Q1, q => DOUT,inclck=>CLK);-- END; D/A DAC0832 1µs ILE 5V WR1 WR2 1 2 XFER VREF10V 10V RFB IOUT1/IOUT2 D/A AGND/DGND GW48 N.5 DAC D[7..0] FPGA PIO EP1C3T CLK clck0 93 1µs DAC0832 +/ 12V GW48 +/-12V SINGT.sf FPGA GW48 GND AOUT GW ROM D/A 3 ROM 3-1 SINGT.VHD FPGA 2 ROM 5 ROM ROM LPM_ROM LPM_ROM FPGA EAB ESB CLK f 0 64 D/A f f = f 0 /

13 3 4 5 ROM ROM C DSP Builder/MATLAB SignalTapII 9 EPCS4/EPCS1 10 RTL 3-35 singt RTL ROM 8 8 MIF C 3 LPM RAM FPGA RAM GW48 FPGA D/A \Experiments\chapter7\Ep1c3_72_FREQTEST\ FREQTEST (1) 8 16 (2) FTCTRL

14 FTCTRL CNT_EN 1 32 COUNTER32B 7-34 ENABL CNT_EN LOAD 1 REG32B RST_CNT 1 (3) FIN clck0 4Hz 256HZ 3Hz...50MHz 1HZ CLK1HZ clck2 ( 1Hz) 8 16 (4) (5) 3 LPM (6) 4 PLL LPM 50MHz 20MHz PLL PLL CLK pin16 clck5 pin17 clck2 16MHz 50MHz Clck2 (7) 7-7 LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS PORT (CLKK : IN STD_LOGIC; -- 1Hz CNT_EN : OUT STD_LOGIC; -- RST_CNT : OUT STD_LOGIC; -- Lad : OUT STD_LOGIC ); -- END FTCTRL; ARCHITECTURE behav OF FTCTRL IS SIGNAL Div2CLK : STD_LOGIC; PROCESS( CLKK ) IF CLKK'EVENT AND CLKK = '1' THEN -- 1Hz 2 Div2CLK <= NOT Div2CLK; END IF; END PROCESS; PROCESS (CLKK, Div2CLK) IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';-- ELSE RST_CNT <= '0'; END IF; END PROCESS; Lad <= NOT Div2CLK; CNT_EN <= Div2CLK; END behav; 7-8 LIBRARY IEEE; --32 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS PORT ( LK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END REG32B; ARCHITECTURE behav OF REG32B IS PROCESS(LK, DIN) IF LK'EVENT AND LK = '1' THEN DOUT <= DIN; END IF; END PROCESS; 14

15 END behav; 7-9 LIBRARY IEEE; --32 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B IS PORT (FIN : IN STD_LOGIC; -- CLR : IN STD_LOGIC; -- ENABL : IN STD_LOGIC; -- DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); -- END COUNTER32B; ARCHITECTURE behav OF COUNTER32B IS SIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0); PROCESS(FIN, CLR, ENABL) IF CLR = '1' THEN CQI <= (OTHERS=>'0'); -- ELSIF FIN'EVENT AND FIN = '1' THEN IF ENABL = '1' THEN CQI <= CQI + 1; END IF; END IF; END PROCESS; DOUT <= CQI; END behav; 7-10 LIBRARY IEEE; -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS PORT ( CLK1HZ : IN STD_LOGIC; FSIN : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END FREQTEST; ARCHITECTURE struc OF FREQTEST IS COMPONENT FTCTRL PORT (CLKK : IN STD_LOGIC; -- 1Hz CNT_EN : OUT STD_LOGIC; -- RST_CNT : OUT STD_LOGIC; -- Lad : OUT STD_LOGIC ); -- END COMPONENT; COMPONENT COUNTER32B PORT (FIN : IN STD_LOGIC; -- CLR : IN STD_LOGIC; -- ENABL : IN STD_LOGIC; -- DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); -- END COMPONENT; COMPONENT REG32B PORT ( LK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; SIGNAL TSTEN1 : STD_LOGIC; SIGNAL CLR_CNT1 : STD_LOGIC; SIGNAL Lad1 : STD_LOGIC; SIGNAL DTO1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0); U1 : FTCTRL PORT MAP(CLKK =>CLK1HZ,CNT_EN=>TSTEN1, RST_CNT =>CLR_CNT1,Lad =>Lad1); U2 : REG32B PORT MAP( LK => Lad1, DIN=>DTO1, DOUT => DOUT); 15

16 U3 : COUNTER32B PORT MAP( FIN => FSIN, CLR => CLR_CNT1, ENABL => TSTEN1, DOUT=>DTO1 ); END struc; 7-33 FTCTRL 7-34 \Experiments\chapter8\Ep1c3_81_SCHK\ SCHK (1) (2) ( ) A B (3) 1 QuartusII 8-11 N (PIO11) CLR 6(PIO9) CLK DIN PIO10( ) AB PIO39 PIO36( 6) ( 6 B ) 6(CLK) 8 8 ( 2/1 D8 D0) B A B (4) ( 8 4/ 3 ) (5) VHDL ( ) (6) 8-11 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SCHK IS PORT(DIN CLK CLR : IN STD_LOGIC; -- / / 16

17 AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); -- END SCHK; ARCHITECTURE behav OF SCHK IS SIGNAL Q : INTEGER RANGE 0 TO 8 ; SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0); --8 ( =E5H) D <= " " ; --8 PROCESS( CLK, CLR ) IF CLR = '1' THEN Q <= 0 ; ELSIF CLK'EVENT AND CLK='1' THEN -- CASE Q IS WHEN 0=> IF DIN = D(7) THEN Q <= 1 ; ELSE Q <= 0 ; END IF ; WHEN 1=> IF DIN = D(6) THEN Q <= 2 ; ELSE Q <= 0 ; END IF ; WHEN 2=> IF DIN = D(5) THEN Q <= 3 ; ELSE Q <= 0 ; END IF ; WHEN 3=> IF DIN = D(4) THEN Q <= 4 ; ELSE Q <= 0 ; END IF ; WHEN 4=> IF DIN = D(3) THEN Q <= 5 ; ELSE Q <= 0 ; END IF ; WHEN 5=> IF DIN = D(2) THEN Q <= 6 ; ELSE Q <= 0 ; END IF ; WHEN 6=> IF DIN = D(1) THEN Q <= 7 ; ELSE Q <= 0 ; END IF ; WHEN 7=> IF DIN = D(0) THEN Q <= 8 ; ELSE Q <= 0 ; END IF ; WHEN OTHERS => Q <= 0 ; END CASE ; END IF ; END PROCESS ; PROCESS( Q ) -- IF Q = 8 THEN AB <= "1010" ; -- A ELSE AB <= "1011" ; -- B END IF ; END PROCESS ; END behav ; \Experiments\chapter8\Ep1c3_82_ADCINT\ ADCINT (1) A/D ADC0809 (2) ADC ( 8-2) ADC0809 CMOS 8 A/D µs 8 5V 8-3 START ALE 3 (ADDC ADDB ADDA) ( IN1 IN2 ) 3 ALE EOC 100µs EOC EOC OE 8 ADC LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK : IN STD_LOGIC; -- EOC : IN STD_LOGIC; -- ALE : OUT STD_LOGIC; --8 START : OUT STD_LOGIC; -- OE : OUT STD_LOGIC; -- 3 ADDA : OUT STD_LOGIC; -- LOCK0 : OUT STD_LOGIC; -- Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8 END ADCINT; ARCHITECTURE behav OF ADCINT IS TYPE states IS (st0, st1, st2, st3,st4) ; -- SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; -- ADDA <= '1';-- ADDA<='0' IN0 ADDA<='1'IN1 Q <= REGL; LOCK0 <= LOCK ; 17

18 COM: PROCESS(current_state,EOC) -- CASE current_state IS WHEN st0=>ale<='0';start<='0';lock<='0';oe<='0'; next_state <= st1; WHEN st1=>ale<='1';start<='1';lock<='0';oe<='0'; next_state <= st2; -- WHEN st2=> ALE<='0';START<='0';LOCK<='0';OE<='0'; IF (EOC='1') THEN next_state <= st3; --EOC=1 ELSE next_state <= st2; END IF ; -- WHEN st3=> ALE<='0';START<='0';LOCK<='0';OE<='1'; next_state <= st4;-- OE, WHEN st4=> ALE<='0';START<='0';LOCK<='1';OE<='1'; next_state <= st0; WHEN OTHERS => next_state <= st0; END CASE ; END PROCESS COM ; REG: PROCESS (CLK) IF (CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF; END PROCESS REG ; -- current_state :REG LATCH1: PROCESS (LOCK) -- LOCK IF LOCK='1' AND LOCK'EVENT THEN END PROCESS LATCH1 ; END behav; REGL <= D ; END IF; 8-3 ADC0809 (3) QuartusII ADC0809 N.5 ADC0809 CLK 750kHz START PIO34 OE ENABLE PIO35 EOC PIO8 ALE PIO33 CLK clck0 ADDA PIO32(ADDB ADDC GND) ADC PIO23 PIO16 Q 8/ 7(PIO47 PIO40) GW48 EDA FPGA 0809 GW48-CK A/D ADC0809 ADCINT.sf FPGA clck0 12MHz 6MHz 65536Hz GW48 ADC ADDA <= '1' AIN IN1 8 7 ADC FPGA (4) 8-2 (5) \Experiments\chapter8\Ep1c3_83_RSVSCP\ RESV (1) LPM RAM VHDL A/D D/A FPGA HDL (2) 7.2 FPGA ( ) 1 RAM RAM FPGA 18

19 1 2 FPGA EAB/ESB Altera FPGA EAB 3 EAB FIFO FIFO A/D A/D ADCINT ADCINT 0809 VHDL CNT10B 8-12 CNT10B RAM 9 CLK0 WE WE= 1 CLK0=LOCK0 LOCK LOCK0 RAM inclck=clkout=lock0 LOCK RAM RAM8B WE= 0 RAM CLKOUT=CLK0=CLK= 65536Hz CLK RAM RAM Q[7..0] DAC RAM8B LPM_RAM 8 9 WREN (3) 1 ADDA= IN1 Cyclne QuartusII RAM/ROM RAM (4) START ADCINT START 8-15 ADC0809 RSV.bdf (5) ADCINT 8-2 WE 1 CLK clck0 64Hz N.5 +/-12V WE= 1 1 ADDA <= '1' AIN1 RAM 1 WE= 0 clck Hz RAM QuartusII RAM RAM (6) 4 ADDA <= '0' AIN0 AIN0 +/-12V GW48 JL11 L_F JP18 INPUT 64Hz JP17 OUTPUT JL10 AIN0 64Hz 0809 IN0 8-2/12 ADDA <= '0' JP18 WAVE OUT 4V CLK=64 RAM clck Hz 1 RAM 19

20 (7) 5 RAM RAM CNT10B RAM D/A (8) D/A X Y D/A RAM 8-12 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10B IS PORT (LOCK0,CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; WE : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); CLKOUT : OUT STD_LOGIC ); END CNT10B; ARCHITECTURE behav OF CNT10B IS SIGNAL CQI : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK0 : STD_LOGIC; CLK0 <= LOCK0 WHEN WE='1' ELSE CLK; PROCESS(CLK0,CLR,CQI) IF CLR = '1' THEN CQI <= " "; ELSIF CLK0'EVENT AND CLK0 = '1' THEN CQI <= CQI + 1; END IF; END PROCESS; DOUT <= CQI; CLKOUT <= CLK0; END behav; \Experiments\chapter8\Ep1c3_84_DAC2ADC\ DAC2ADC (1) (2) 8-16 LM311 DAC A/D vi LM311 + FPGA DAC0832 LM311 - vc vc<vi LM vc>vi LM311 LM FPGA 0832 vi vi (3) FPGA N.5 CLK clck0 CLR 1 DD[7..0] PIO31-PIO24 LM311 PIO37 DISPDATA[7..0] 8 7 (PIO47-PIO40) FPGA +/-12V clck Hz GW48 EDA FPGA PIO37 LM311 N LM311 3 AIN0 LM311 2 AIN0 AIN1 AIN1 AIN0 AIN0 JL10 AIN0 AIN1 CLR 8-16 D/A A/D 20

21 8-13 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DAC2ADC IS PORT ( CLK : IN STD_LOGIC; -- LM311 : IN STD_LOGIC; --LM311 PIO37 FPGA CLR : IN STD_LOGIC; -- DD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; DISPDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );-- END; ARCHITECTURE DACC OF DAC2ADC IS SIGNAL CQI : STD_LOGIC_VECTOR(7 DOWNTO 0) ; DD <= CQI ; PROCESS(CLK, CLR, LM311) IF CLR = '1' THEN CQI <= " "; ELSIF CLK'EVENT AND CLK = '1' THEN IF LM311 = '1' THEN CQI <= CQI + 1; END IF;-- END IF; -- CQI END PROCESS; DISPDATA <= CQI WHEN LM311='0' ELSE " " ;-- CQI END; (3) A/D \Experiments\chapter9\Ep1c3_91_MULTI8X8\ MULTI8X8 (1) 8 (2) ( 9FH FDH ) START 16 A[7..0] SREG8B CLK 8 SREG8B 1 1 ANDARITH 8 B[7..0] 8 16 REG16B REG16B 1 ANDARITH 1 ABIN '1' DOUT DIN ABIN '0' DOUT LCs FH FDH 1 ( REG16B ) 4F80H 8 9D23H 9-34 VHDL 9-11 LIBRARY IEEE; -- 8 USE IEEE.STD_LOGIC_1164.ALL; ENTITY SREG8B IS PORT ( CLK, LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SREG8B; ARCHITECTURE behav OF SREG8B IS SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); PROCESS (CLK, LOAD) 21

22 IF CLK'EVENT AND CLK = '1' THEN IF LOAD = '1' THEN REG8 <= DIN; ELSE REG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1); END IF; END IF; END PROCESS; QB <= REG8(0); -- END behav; 9-12 LIBRARY IEEE; --8 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8B IS PORT ( CIN : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END ADDER8B; ARCHITECTURE behav OF ADDER8B IS SIGNAL SINT, AA,BB : STD_LOGIC_VECTOR(8 DOWNTO 0); AA<='0'&A; BB<='0'&B; SINT<=AA+BB+CIN;S<=SINT(7 DOWNTO 0); COUT<=SINT(8); END behav; 9-13 LIBRARY IEEE; --1 USE IEEE.STD_LOGIC_1164.ALL; ENTITY ANDARITH IS -- PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ANDARITH; ARCHITECTURE behav OF ANDARITH IS PROCESS(ABIN, DIN) FOR I IN 0 TO 7 LOOP DOUT(I) <= DIN(I) AND ABIN; END LOOP; END PROCESS; END behav; 9-14 LIBRARY IEEE; --16 / USE IEEE.STD_LOGIC_1164.ALL; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG16B IS PORT (CLK, CLR : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END REG16B; ARCHITECTURE behav OF REG16B IS SIGNAL R16S : STD_LOGIC_VECTOR(15 DOWNTO 0); PROCESS(CLK, CLR) IF CLR='1' THEN R16S<=" ";-- 8 ELSIF CLK'EVENT AND CLK='1' THEN R16S(6 DOWNTO 0) <=R16S(7 DOWNTO 1);-- 8 R16S(15 DOWNTO 7) <= D; -- 8 END IF; END PROCESS; Q <= R16S; END behav; 9-15 END behav; LIBRARY IEEE; 22

23 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ARICTL IS PORT (CLK, START : IN STD_LOGIC; CLKOUT,RSTALL : OUT STD_LOGIC ); END ARICTL; ARCHITECTURE behav OF ARICTL IS SIGNAL CNT4B : STD_LOGIC_VECTOR(3 DOWNTO 0); PROCESS(CLK, START) RSTALL <= START; IF START = '1' THEN CNT4B <= "0000"; ELSIF CLK'EVENT AND CLK ='1' THEN IF CNT4B < 8 THEN CNT4B <= CNT4B + 1; END IF; END IF; END PROCESS; PROCESS(CLK, CNT4B, START) IF START = '0' THEN IF CNT4B < 8 THEN CLKOUT <= CLK; ELSE CLKOUT <= '0'; END IF; ELSE CLKOUT <= CLK; END IF; END PROCESS; END behav; 9-16 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_lgic_unsigned.all; ENTITY MULTI8X8 IS -- 8 PORT ( CLKK,START : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END MULTI8X8; ARCHITECTURE struc OF MULTI8X8 IS COMPONENT ARICTL PORT ( CLK, START : IN STD_LOGIC; CLKOUT, RSTALL : OUT STD_LOGIC ); END COMPONENT; COMPONENT ANDARITH PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER8B PORT (CIN : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT SREG8B PORT ( CLK, LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG16B PORT ( CLK, CLR : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; SIGNAL GNDINT, INTCLK, RSTALL, NEWSTART, QB : STD_LOGIC; SIGNAL ANDSD : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DTBIN : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL DTBOUT : STD_LOGIC_VECTOR(15 DOWNTO 0); DOUT <= DTBOUT; GNDINT <= '0'; PROCESS(CLKK,START) IF START='1' THEN NEWSTART<='1'; ELSIF CLKK='0' THEN NEWSTART<='0'; END IF; 23

24 END PROCESS; U1 : ARICTL PORT MAP(CLK=>CLKK,START=>NEWSTART, CLKOUT=>INTCLK, RSTALL=>RSTALL); U2 : SREG8B PORT MAP(CLK=>INTCLK, LOAD=>RSTALL, DIN=>B, QB=>QB ); U3 : ANDARITH PORT MAP(ABIN => QB, DIN => A,DOUT => ANDSD); U4 : ADDER8B PORT MAP(CIN => GNDINT, A=>DTBOUT(15 DOWNTO 8), B=>ANDSD, S => DTBIN(7 DOWNTO 0), COUT => DTBIN(8) ); U5 : REG16B PORT MAP(CLK=>INTCLK, CLR=>RSTALL, D=>DTBIN, Q=>DTBOUT ); END struc; (3) 1 VHDL QuartusII 87H F5H (4) 2 N CLK 7 START START 0 (5) 3 clck0 clck0/ 0 CLK (6) 4 8X8 16 LPM (1) (2) N N N 1 (3) 1 4 ( 9-17 ) CASE

25 9-17 stemp <= a XOR b; PROCESS(stemp) CASE stemp IS WHEN "0000" => c <= "100"; --4 WHEN "0001" "0010" "0100" "1000" => c <= "011"; --3 WHEN "0011" "0101" "1001" "0110" "1010" "1100" => c <= "010"; --2 WHEN "0111" "1011" "1101" "1110" => c <= "001"; --1 WHEN "1111" => c <= "000"; -- 0; WHEN OTHERS => c <= "000"; END CASE; END PROCESS; (4) QuartusII (5) QuartusII (6) (7) clck (8) (1) VHDL LFSR FPGA LFSR (2) LFSR Linear Feedback Shift Register CRC PN 9-36 LFSR LFSR xr xr 9-36 X 3 +X 2 +X 0 (3) 9-36 LFSR X 4 +X 3 +X 0 EP1C3T144 QuartusII GW48 EDA (4) 1 LFSR LFSR 9-36 LFSR 9-37 LFSR (5) LFSR CRC ( xr xr ) 25

26 (6) QuartusII \Experiments\chapter10\Ep1c3_10_1_SONGER\ SONGER (1) 5-3 (2) ( 10-3 ) TONETABA.VHD NOTETABS.VHD SPEAKER.VHD 10-3 Synplify CPU MCU EDA 10-3 U1 U2 U SPEAKERA 5-3 clk 12MHz SPEAKERA SPKOUT D 1/2 SPEAKERA clk 11 Tne[10..0] SPKOUT Tne[10..0] SPKOUT TONETABA Tne[10..0]=1036"3" TONETABA SPEAKERA SPEAKER TONETABA 13 NOTETABS clk 4Hz 13 TONETABA 4 Index[3..0] Index[3..0] 16 TONETABA Index[3..0] TneIndex[3..0] NOTETABS 3 NOTETABS ROM 4Hz NOTETABS VHDL SPEAKERA 1 NOTETABS 4Hz ROM ROM TneIndex[3..0] TONETABA (3) NteTabs ROM music ROM ROM ROM (4) 2 VHDL QuartusII (5) 3 CLK12MHz clck9 12MHz clck9 12MHz CLK8Hz clck2 4Hz SPKOUT Speaker CODE1 5 HIGH1 D5 26

27 SOF NO.1 (6) NOTETABA (7) 5 ROM (8) 6 NO.3 (9) 1 LFSR ( ) LFSR (10) DelaySpkS (11) 3 (12) 4 VHDL VHDL : LIBRARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; ENTITY Snger IS PORT ( CLK12MHZ : IN STD_LOGIC; -- CLK8HZ : IN STD_LOGIC; -- CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);-- HIGH1 : OUT STD_LOGIC; -- 8 SPKOUT : OUT STD_LOGIC );-- END; ARCHITECTURE ne OF Snger IS COMPONENT NteTabs PORT ( clk : IN STD_LOGIC; TneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; COMPONENT TneTaba PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tne : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONENT; COMPONENT Speakera PORT ( clk : IN STD_LOGIC; Tne : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END COMPONENT; SIGNAL Tne : STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL TneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0); u1 : NteTabs PORT MAP (clk=>clk8hz, TneIndex=>TneIndex); u2 : TneTaba PORT MAP (Index=>TneIndex,Tne=>Tne,CODE=>CODE1,HIGH=>HIGH1); u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tne=>Tne, SpkS=>SPKOUT ); END; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Speakera IS PORT ( clk : IN STD_LOGIC; Tne : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END; ARCHITECTURE ne OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC; DivideCLK : PROCESS(clk) VARIABLE Cunt4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; PreCLK <= '0'; -- CLK 16 PreCLK CLK 16 IF Cunt4>11 THEN PreCLK <= '1'; Cunt4 := "0000"; 27

28 ELSIF clk'event AND clk = '1' THEN Cunt4 := Cunt4 + 1; END IF; END PROCESS; GenSpkS : PROCESS(PreCLK, Tne)-- 11 VARIABLE Cunt11 : STD_LOGIC_VECTOR (10 DOWNTO 0); IF PreCLK'EVENT AND PreCLK = '1' THEN IF Cunt11 = 16#7FF# THEN Cunt11 := Tne ; FullSpkS <= '1'; ELSE Cunt11 := Cunt11 + 1; FullSpkS <= '0'; END IF; END IF; END PROCESS; DelaySpkS : PROCESS(FullSpkS)-- 2 VARIABLE Cunt2 : STD_LOGIC; IF FullSpkS'EVENT AND FullSpkS = '1' THEN Cunt2 := NOT Cunt2; IF Cunt2 = '1' THEN SpkS <= '1'; ELSE SpkS <= '0'; END IF; END IF; END PROCESS; END; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TneTaba IS PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tne : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END; ARCHITECTURE ne OF TneTaba IS Search : PROCESS(Index) CASE Index IS -- WHEN "0000" => Tne<=" " ; CODE<="0000"; HIGH <='0'; WHEN "0001" => Tne<=" " ; CODE<="0001"; HIGH <='0';-- 773; WHEN "0010" => Tne<=" " ; CODE<="0010"; HIGH <='0';-- 912; WHEN "0011" => Tne<=" " ; CODE<="0011"; HIGH <='0';--1036; WHEN "0101" => Tne<=" " ; CODE<="0101"; HIGH <='0';--1197; WHEN "0110" => Tne<=" " ; CODE<="0110"; HIGH <='0';--1290; WHEN "0111" => Tne<=" " ; CODE<="0111"; HIGH <='0';--1372; WHEN "1000" => Tne<=" " ; CODE<="0001"; HIGH <='1';--1410; WHEN "1001" => Tne<=" " ; CODE<="0010"; HIGH <='1';--1480; WHEN "1010" => Tne<=" " ; CODE<="0011"; HIGH <='1';--1542; WHEN "1100" => Tne<=" " ; CODE<="0101"; HIGH <='1';--1622; WHEN "1101" => Tne<=" " ; CODE<="0110"; HIGH <='1';--1668; WHEN "1111" => Tne<=" " ; CODE<="0001"; HIGH <='1';--1728; WHEN OTHERS => NULL; END CASE; END PROCESS; END; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY NteTabs IS PORT ( clk : IN STD_LOGIC; TneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END; ARCHITECTURE ne OF NteTabs IS COMPONENT MUSIC -- ROM PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclck : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END COMPONENT; SIGNAL Cunter : STD_LOGIC_VECTOR (7 DOWNTO 0); CNT8 : PROCESS(clk, Cunter) 28

29 IF Cunter=138 THEN Cunter <= " "; ELSIF (clk'event AND clk = '1') THEN Cunter <= Cunter+1; END IF; END PROCESS; u1 : MUSIC PORT MAP(address=>Cunter, q=>tneindex, inclck=>clk); END; WIDTH = 4 ; -- DEPTH = 256 ; ADDRESS_RADIX = DEC ; DATA_RADIX = DEC ; CONTENT -- 00: 3 ; 01: 3 ; 02: 3 ; 03: 3; 04: 5; 05: 5; 06: 5;07: 6; 08: 8; 09: 8; 10: 8 ; 11: 9 ; 12: 6 ; 13: 8; 14: 5; 15: 5; 16: 12;17: 12;18: 12; 19:15; 20:13 ; 21:12 ; 22:10 ; 23:12; 24: 9; 25: 9; 26: 9; 27: 9; 28: 9; 29: 9; 30: 9 ; 31: 0 ; 32: 9 ; 33: 9; 34: 9; 35:10; 36: 7; 37: 7; 38: 6; 39: 6; 40: 5 ; 41: 5 ; 42: 5 ; 43: 6; 44: 8; 45: 8; 46: 9; 47: 9; 48: 3; 49: 3; 50: 8 ; 51: 8 ; 52: 6 ; 53: 5; 54: 6; 55: 8; 56: 5; 57: 5; 58: 5; 59: 5; 60: 5 ; 61: 5 ; 62: 5 ; 63: 5; 64:10; 65:10; 66:10; 67:12; 68: 7; 69: 7; 70: 9 ; 71: 9 ; 72: 6 ; 73: 8; 74: 5; 75: 5; 76: 5; 77: 5; 78: 5; 79: 5; 80: 3 ; 81: 5 ; 82: 3 ; 83: 3; 84: 5; 85: 6; 86: 7; 87: 9; 88: 6; 89: 6; 90: 6 ; 91: 6 ; 92: 6 ; 93: 6; 94: 5; 95: 6; 96: 8; 97: 8; 98: 8; 99: 9; 100:12 ;101:12 ;102:12 ;103:10;104: 9;105: 9;106:10;107: 9;108: 8;109: 8; 110: 6 ;111: 5 ;112: 3 ;113: 3;114: 3;115: 3;116: 8;117: 8;118: 8;119: 8; 120: 6 ;121: 8 ;122: 6 ;123: 5;124: 3;125: 5;126: 6;127: 8;128: 5;129: 5; 130: 5 ;131: 5 ;132: 5 ;133: 5;134: 5;135: 5;136: 0;137: 0;138: 0; END ; \Experiments\chapter10\Ep1c3_10_2_TENNIS\ TENNIS 8 VHDL tennis MAX+PLUSII ball clk bard 1 cu4 cu10 mway sund (1) 1 VHDL 8-35 NO.3 bain bbin 8 1 clr 0 7 clk clck2 4Hz suclk clck5 1024Hz ballut[7..0] 8 D1 D2.. D8 cuntbh[3..0] cuntbl[3..0] 7 6 cuntah[3..0] cuntal[3..0] 3 2 lamp 7 clck2 speaker (2) 2 NO.3 clck5 1024Hz clck1 4Hz 8 1 3/2 7/6 (3) 3 VHDL : 8-35 LIBRARY IEEE; -- use ieee.std_lgic_1164.all; entity TENNIS is prt(bain,bbin,clr,clk,suclk:in std_lgic; ballut:ut std_lgic_vectr(7 dwnt 0); cuntah,cuntal,cuntbh,cuntbl:ut std_lgic_vectr(3 dwnt 0); lamp,speaker:ut std_lgic); end; architecture ful f TENNIS is cmpnent sund 29

30 prt (clk,sig,en:in std_lgic; sut:ut std_lgic); end cmpnent; cmpnent ballctrl prt(clr,bain,bbin,serclka,serclkb,clk:in std_lgic; bdut,serve,serclk,ballclr,ballen:ut std_lgic); end cmpnent; cmpnent ball prt(clk,clr,way,en:in std_lgic; ballut:ut std_lgic_vectr(7 dwnt 0)); end cmpnent; cmpnent bard prt (ball,net,bclk,serve:in std_lgic; cuclk,serclk:ut std_lgic); end cmpnent; cmpnent cu10 prt(clk,clr:in std_lgic; cut:ut std_lgic; qut:ut std_lgic_vectr(3 dwnt 0)); end cmpnent; cmpnent cu4 prt(clk,clr:in std_lgic; cut:ut std_lgic; qut:ut std_lgic_vectr(3 dwnt 0)); end cmpnent; cmpnent mway prt(servea,serveb:in std_lgic; way:ut std_lgic); end cmpnent; signal net,cuclkah,cuclkal,cuclkbh,cuclkbl,cah,cbh:std_lgic; signal serve,serclka,serclkb,serclk,ballclr,bdut,way,ballen:std_lgic; signal bbll:std_lgic_vectr( 7 dwnt 0); begin net<=bbll(4); ballut<=bbll; lamp<=clk; uah:cu4 prt map (cuclkah,clr,cah,cuntah); ual:cu10 prt map (cuclkal,clr,cuclkah,cuntal); ubh:cu4 prt map (cuclkbh,clr,cbh,cuntbh); ubl:cu10 prt map (cuclkbl,clr,cuclkbh,cuntbl); ubda:bard prt map (bbll(0),net,bain,serve,cuclkal,serclka); ubdb:bard prt map (bbll(7),net,bbin,serve,cuclkbl,serclkb); ucpu:ballctrl prt map (clr,bain,bbin,serclka,serclkb,clk,bdut,serve,serclk,ballclr,ballen); uway:mway prt map (serclka,serclkb,way); uball: ball prt map (clk,ballclr,way,ballen,bbll); usund:sund prt map(suclk,ballen,bdut,speaker); end; 8-36 library ieee; use ieee.std_lgic_1164.all; entity sund is prt (clk:in std_lgic;-- sig:in std_lgic;-- en:in std_lgic;-- sut:ut std_lgic);-- end sund; architecture ful f sund is begin sut<=clk and (nt sig) and en;-- end; 8-37 library ieee; -- use ieee.std_lgic_1164.all; entity ballctrl is prt(clr:in std_lgic;-- bain:in std_lgic;-- bbin:in std_lgic;-- serclka:in std_lgic;-- serclkb:in std_lgic;-- 30

31 clk:in std_lgic;-- bdut:ut std_lgic;-- serve:ut std_lgic;-- serclk:ut std_lgic;-- ballclr:ut std_lgic;-- ballen:ut std_lgic);-- end ballctrl; architecture ful f ballctrl is signal bd:std_lgic; signal ser:std_lgic; begin bd<=bain r bbin; ser<=serclka r serclkb; serclk<=ser;-- bdut<=bd;-- prcess(clr,clk,bd) begin if(clr='1' ) then -- serve<='1'; -- ballclr<='1'; -- else -- if(bd='1')then -- ballclr<='1'; -- if(ser='1') then-- ballen<='1';-- serve<='0'; -- else ballen<='0'; serve<='1'; -- end if; else ballclr<='0'; -- end if; end if; end prcess; end; library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity ball is prt(clk:in std_lgic;-- clr:in std_lgic;-- way:in std_lgic;-- en:in std_lgic;-- ballut:ut std_lgic_vectr(7 dwnt 0));-- end ball; architecture ful f ball is signal lamp:std_lgic_vectr(9 dwnt 0); begin prcess(clk,clr,en) begin if(clr='1') then lamp<=" "; -- elsif en='0' then elsif (clk'event and clk='1') then-- if(way='1') then lamp(9 dwnt 1)<=lamp(8 dwnt 0);lamp(0)<='0';-- else lamp(8 dwnt 0)<=lamp(9 dwnt 1); lamp(9)<='0';-- end if; end if; ballut<=lamp(8 dwnt 1); end prcess; end; library ieee; use ieee.std_lgic_1164.all; entity bard is prt (ball:in std_lgic;-- net:in std_lgic;-- cunclk serclk 31

32 bclk:in std_lgic;-- serve:in std_lgic;-- cuclk:ut std_lgic; serclk:ut std_lgic);end bard; architecture ful f bard is begin prcess(bclk,net) begin if(net='1')then serclk<='0'; cuclk<='0'; -- cunclk serclk elsif(bclk'event and bclk='1')then -- if(serve='1')then serclk<='1'; else -- if(ball='1') then serclk<='1';--, else serclk<='0'; cuclk<='1'; end if; end if; end if; end prcess; end; library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity cu10 is prt(clk,clr:in std_lgic; cut:ut std_lgic; qut:ut std_lgic_vectr(3 dwnt 0)); end cu10; architecture ful f cu10 is signal qqut:std_lgic_vectr(3 dwnt 0); begin prcess(clr,clk) begin if(clr='1') then qqut<="0000"; cut<='0'; elsif(clk'event and clk='1') then if(qqut>"1000")then qqut<="0000"; cut<='1'; else qqut<=qqut+'1'; cut<='0'; end if; end if; qut<=qqut; end prcess; end; library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity cu4 is prt(clk,clr:in std_lgic; cut:ut std_lgic; qut:ut std_lgic_vectr(3 dwnt 0)); end cu4; architecture ful f cu4 is signal qqut:std_lgic_vectr(3 dwnt 0); begin prcess(clr,clk) begin if(clr='1') then qqut<="0000"; cut<='0'; elsif(clk'event and clk='1') then if(qqut>"0010")then qqut<="0000"; cut<='1'; else qqut<=qqut+'1'; cut<='0'; end if; end if; qut<=qqut; end prcess; end; library ieee; use ieee.std_lgic_1164.all; entity mway is prt(servea:in std_lgic;-- serveb:in std_lgic;-- 32

33 way:ut std_lgic);-- end mway; architecture ful f mway is begin prcess(servea,serveb) begin if(servea='1') then way<='1';-- elsif(serveb='1') then way<='0';-- end if; end prcess; end; (1) CRC FPGA (2) CRC Cyclic Redundancy Check CRC CRC k r CRC r CRC k r+1 (r CRC ) 2 CRC CRC r CRC 12 5 CRC CRC ( ) CRC ( ) CRC 11-5 CRC sdata 12 datald sdata errr datafini rdata ( ) 12 clk datacrc 5 CRC 17 CRC hsend hrecv CRC X 5 +X 4 +X CRC LIBRARY ieee; USE ieee.std_lgic_1164.all; USE ieee.std_lgic_unsigned.all; USE ieee.std_lgic_arith.all; ENTITY crcm IS PORT (clk, hrecv datald : IN std_lgic; sdata : IN std_lgic_vectr(11 DOWNTO 0); datacrc : OUT std_lgic_vectr(16 DOWNTO 0); datacrci : IN std_lgic_vectr(16 DOWNTO 0); rdata : OUT std_lgic_vectr(11 DOWNTO 0); datafini : OUT std_lgic; ERROR0, hsend : OUT std_lgic); END crcm; ARCHITECTURE cmm OF crcm IS CONSTANT multi_cef : std_lgic_vectr(5 DOWNTO 0) := "110101"; --, MSB '1' SIGNAL cnt,rcnt : std_lgic_vectr(4 DOWNTO 0); SIGNAL dtemp,sdatam,rdtemp : std_lgic_vectr(11 DOWNTO 0); SIGNAL rdatacrc: std_lgic_vectr(16 DOWNTO 0); SIGNAL st,rt : std_lgic; 33

34 PROCESS(clk) VARIABLE crcvar : std_lgic_vectr(5 DOWNTO 0); IF(clk'event AND clk = '1') THEN IF(st = '0' AND datald = '1') THEN dtemp <= sdata; sdatam <= sdata; cnt <= (OTHERS => '0'); hsend <= '0'; st <= '1'; ELSIF(st = '1' AND cnt < 7) THEN cnt <= cnt + 1; IF(dtemp(11) = '1') THEN crcvar := dtemp(11 DOWNTO 6) XOR multi_cef; dtemp <= crcvar(4 DOWNTO 0) & dtemp(5 DOWNTO 0) & '0'; ELSE dtemp <= dtemp(10 DOWNTO 0) & '0'; END IF; ELSIF(st='1' AND cnt=7) THEN datacrc<=sdatam & dtemp(11 DOWNTO 7); hsend <= '1'; cnt <= cnt + 1; ELSIF(st='1' AND cnt=8) THEN hsend<= '0'; st<='0'; END IF; END IF; END PROCESS; PROCESS(hrecv,clk) VARIABLE rcrcvar : std_lgic_vectr(5 DOWNTO 0); IF(clk'event AND clk = '1') THEN IF(rt = '0' AND hrecv = '1') THEN rdtemp <= datacrci(16 DOWNTO 5); rdatacrc <= datacrci; rcnt <= (OTHERS => '0'); ERROR0 <= '0'; rt <= '1'; ELSIF(rt= '1' AND rcnt < 7) THEN datafini <= '0'; rcnt <= rcnt + 1; rcrcvar := rdtemp(11 DOWNTO 6) XOR multi_cef; IF(rdtemp(11) = '1') THEN rdtemp <= rcrcvar(4 DOWNTO 0) & rdtemp(5 DOWNTO 0) & '0'; ELSE rdtemp <= rdtemp(10 DOWNTO 0) & '0'; END IF; ELSIF(rt = '1' AND rcnt = 7) THEN datafini <= '1'; rdata <= rdatacrc(16 DOWNTO 5); rt <= '0'; IF(rdatacrc(4 DOWNTO 0) /= rdtemp(11 DOWNTO 7)) THEN ERROR0 <= '1'; END IF; END IF; END IF; END PROCESS; END cmm; (3) 1 (4) 2 crcm CRC CRC EDA (5) 1 st rt ( reset ) (6) 2 CRC ( LFSR) (7) 3 8 CRC clk (8) CRC \Experiments\chapter12_A\Ep1c3_12_1_2_MOTO\ step_a (1) FPGA (2) Ap Bp Cp Dp Y0 Y1 Y2 Y3 PIO65 PIO64 PIO63 PIO62 GW48 EP1C CLK0 clck0 4Hz CLK5 clck Hz S PIO6 7 1/ / 18 / U_D PIO7 8 (JM0) N.5, Quartus step_1c3 step_a.sf EP1C3 87 (3) PWM FPGA 34

35 ( QuartusII EAB ROM3 ) 2 FPGA (4) 3 (5) 4 (6) 5 / PWM PWM \Experiments\chapter12_A\Ep1c3_12_1_2_MOTO\ step_a (1) PWM FPGA PWM (2) MA2 MA1 Z F EP1C3 PIO60 61 MA-CNT PIO66 CNTT18 JM1 JM2 CLK5 clck Hz CLK0 clck0 4Hz 1Hz 35

36 1 PIO0 Z_F 2 PIO1 D_STP N.5, Quartus step_1c3 step_a.sf EP1C3 (3) 2 (4) 3 FPGA (5) FPGA F PWM cntut Z PWM cntut \Experiments\chapter12_A\Ep1c3_12_3_VGA\ COLOR (1) VGA (2) VGA R G B 36

37 PIO60 PIO61 PIO HS VS PIO64 PIO CLK clck9 12MHz MD PIO0 5 1 P1 VGA 5 COLOR.SOF 1GW48 TO_MCU (3) 2 VGA (4) 3 VGA (5) 4 VGA 12-7 LIBRARY IEEE; -- VGA USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COLOR IS PORT ( CLK, MD : IN STD_LOGIC; HS, VS, R, G, B : OUT STD_LOGIC ); -- / END COLOR; ARCHITECTURE behav OF COLOR IS SIGNAL HS1,VS1,FCLK,CCLK : STD_LOGIC; SIGNAL MMD : STD_LOGIC_VECTOR(1 DOWNTO 0);-- SIGNAL FS : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL CC : STD_LOGIC_VECTOR(4 DOWNTO 0); -- / SIGNAL LL : STD_LOGIC_VECTOR(8 DOWNTO 0); -- / SIGNAL GRBX : STD_LOGIC_VECTOR(3 DOWNTO 1);-- X SIGNAL GRBY : STD_LOGIC_VECTOR(3 DOWNTO 1);-- Y SIGNAL GRBP : STD_LOGIC_VECTOR(3 DOWNTO 1); SIGNAL GRB : STD_LOGIC_VECTOR(3 DOWNTO 1); GRB(2) <= (GRBP(2) XOR MD) AND HS1 AND VS1; GRB(3) <= (GRBP(3) XOR MD) AND HS1 AND VS1; GRB(1) <= (GRBP(1) XOR MD) AND HS1 AND VS1; PROCESS( MD ) IF MD'EVENT AND MD = '0' THEN IF MMD = "10" THEN MMD <= "00"; ELSE MMD <= MMD + 1; END IF; -- END IF; END PROCESS; PROCESS( MMD ) IF MMD = "00" THEN GRBP <= GRBX; -- ELSIF MMD = "01" THEN GRBP <= GRBY; -- ELSIF MMD = "10" THEN GRBP <= GRBX XOR GRBY; -- ELSE GRBP <= "000"; END IF; END PROCESS; PROCESS( CLK ) IF CLK'EVENT AND CLK = '1' THEN -- 12MHz 13 IF FS = 12 THEN FS <= "0000"; ELSE FS <= (FS + 1); END IF; END IF; END PROCESS; FCLK <= FS(3); CCLK <= CC(4); PROCESS( FCLK ) IF FCLK'EVENT AND FCLK = '1' THEN IF CC = 29 THEN CC <= "00000"; ELSE CC <= CC + 1; END IF; END IF; END PROCESS; PROCESS( CCLK ) IF CCLK'EVENT AND CCLK = '0' THEN IF LL = 481 THEN LL <= " "; ELSE LL <= LL + 1; END IF; END IF; 37

38 END PROCESS; PROCESS( CC,LL ) IF CC > 23 THEN HS1 <= '0'; -- ELSE HS1 <= '1'; END IF; IF LL > 479 THEN VS1 <= '0'; -- ELSE VS1 <= '1'; END IF; END PROCESS; PROCESS(CC, LL) IF CC < 3 THEN GRBX <= "111"; -- ELSIF CC < 6 THEN GRBX <= "110"; ELSIF CC < 9 THEN GRBX <= "101"; ELSIF CC < 12 THEN GRBX <= "100"; ELSIF CC < 15 THEN GRBX <= "011"; ELSIF CC < 18 THEN GRBX <= "010"; ELSIF CC < 21 THEN GRBX <= "001"; ELSE GRBX <= "000"; END IF; IF LL < 60 THEN GRBY <= "111"; -- ELSIF LL < 120 THEN GRBY <= "110"; ELSIF LL < 180 THEN GRBY <= "101"; ELSIF LL < 240 THEN GRBY <= "100"; ELSIF LL < 300 THEN GRBY <= "011"; ELSIF LL < 360 THEN GRBY <= "010"; ELSIF LL < 420 THEN GRBY <= "001"; ELSE GRBY <= "000"; END IF; END PROCESS; HS <= HS1 ; VS <= VS1 ;R <= GRB(2) ;G <= GRB(3) ; B <= GRB(1); END behav; \Experiments\chapter12_A\Ep1c3_12_4_VGAP8\ VGAROM (1) VGA 12-8 imgrm ROM (2) / clk50mhz clck0 50MHz EDA VGA (3) 3 (4) 4 ROM FPGA ROM imgrm NO.5 ROM 27C020/27C040 FPGA./VGA88/vgarm.sf./VGAbb/vgarm.sf clck0 50MHz GW48 EDA ROM EDA TO_MCU 5 1 ROM 1 \Experiments\VGA_example\hb1\ vgainterface VGA_QH_HB1 vgainterface SOF GW48EDA FPGA EP1C3 clck0 50MHz Clck2 4Hz VGA 5 1 VGA 2 \Experiments\VGA_example\hb2\ vgainterface VGA_QH_HB2 vgainterface SOF GW48EDA FPGA EP1C3 VGA 3 \Experiments\VGA_example\MAO\ vgainterface 38

39 VGA_QH_MAO vgainterface SOF GW48EDA FPGA EP1C3 VGA 4 \Experiments\VGA_example\MAO1\ vgainterface VGA_QH_MAO vgainterface SOF GW48EDA FPGA EP1C3 VGA 5 PS/2 VGA \Experiments\VGA_example\VGA_CLOCK\ digital_clck VGA PS/2 PS/2 VGA_clck clck-digital SOF GW48EDA FPGA EP1C3 clck2 VGA S 0 Q A shift Enter Q \Experiments\chapter12_C\Ep1c3_13_9_DDS\ DDS/ PLL (1) EDA FPGA (2) 1 12 DDS DDS FWORD PWORD GW48 ADDA 10 D/A ADDA PA FPGA EP1C3 ADDA B A/D 16 +/-12V clck0 12MHz 50MHz A/D 2 1 (3) GW48 2 (4) 3(sin) (cs) (5) 4 FSK (6) CLK 200MHz H DDS LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS IS -- PORT ( CLK : IN STD_LOGIC; -- clck0 Pin93 DACLK : OUT STD_LOGIC; -- DACLK D/A Pin130 FWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- Pin FOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); Pin END; ARCHITECTURE ne OF DDS IS COMPONENT REG32B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG10B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; 39

40 COMPONENT ADDER32B PORT ( A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER10B PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT SIN_ROM PORT ( address : IN STD_LOGIC_VECTOR(9 DOWNTO 0); inclck : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; SIGNAL F32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL D32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL DIN32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL P10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL LIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL PWORD : STD_LOGIC_VECTOR(7 DOWNTO 0); DACLK<=CLK; F32B(27 DOWNTO 20)<=FWORD ; F32B(31 DOWNTO 28)<="0000"; P10B( 1 DOWNTO 0)<="00" ; F32B(19 DOWNTO 0)<=" " ; P10B( 9 DOWNTO 2)<=PWORD ; PWORD <=" "; u1 : ADDER32B PORT MAP( A=>F32B,B=>D32B, S=>DIN32B ); u2 : REG32B PORT MAP( DOUT=>D32B,DIN=> DIN32B, LOAD=>CLK ); u3 : SIN_ROM PORT MAP( address=>sin10b, q=>fout, inclck=>clk ); u4 : ADDER10B PORT MAP( A=>P10B,B=>D32B(31 DOWNTO 22),S=>LIN10B ); u5 : REG10B PORT MAP( DOUT=>SIN10B,DIN=>LIN10B, LOAD=>CLK ); END; \Experiments\chapter12_C\GW_PLL\ GW_PLL (1) Cyclne 2 PLL LPM PLL 1 QuartusII Tls MegaWizard Plug-In Manager Create a new custm I/O ALTPLL Cyclne VHDL d:\sin_gnt\pll50.vhd Next MHz 16MHz inclk0 50MHz 16MHz Next 7-30 Next 7-30 PLL PLL pllena areset lcked Next

41 7-31 4Next PLL EDA VHDL 7 PLL MHz LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY GW_PLL IS PORT (CLK0 : IN STD_LOGIC; FOUT0 : OUT STD_LOGIC ); END GW_PLL; ARCHITECTURE behav OF GW_PLL IS COMPONENT PLL50 PORT(inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END COMPONENT; 41

42 u1 : PLL50 PORT MAP(inclk0=>CLK0,c0=>FOUT0); END behav; PLL \Experiments\chapter12_C\Ep1c3_13_9_DDS_PLL\ DDS/ PLL (1) Cyclne 2 PLL LPM PLL50 DDS LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS IS -- PORT ( CLK2 : IN STD_LOGIC; DACLK : OUT STD_LOGIC; FWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END; ARCHITECTURE ne OF DDS IS COMPONENT REG32B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG10B 42

43 PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER32B PORT ( A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER10B PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT SIN_ROM PORT ( address : IN STD_LOGIC_VECTOR(9 DOWNTO 0); inclck : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT PLL50 PORT(inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END COMPONENT; SIGNAL F32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL D32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL DIN32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL P10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL LIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL PWORD : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CLK : STD_LOGIC; DACLK<=CLK; F32B(27 DOWNTO 20)<=FWORD ; F32B(31 DOWNTO 28)<="0000"; P10B( 1 DOWNTO 0)<="00" ; F32B(19 DOWNTO 0)<=" " ; P10B( 9 DOWNTO 2)<=PWORD ; PWORD <=" "; u1 : ADDER32B PORT MAP( A=>F32B,B=>D32B, S=>DIN32B ); u2 : REG32B PORT MAP( DOUT=>D32B,DIN=> DIN32B, LOAD=>CLK ); u3 : SIN_ROM PORT MAP( address=>sin10b, q=>fout, inclck=>clk ); u4 : ADDER10B PORT MAP( A=>P10B,B=>D32B(31 DOWNTO 22),S=>LIN10B ); u5 : REG10B PORT MAP( DOUT=>SIN10B,DIN=>LIN10B, LOAD=>CLK ); u6 : PLL50 PORT MAP(inclk0=>CLK2,c0=>CLK); END; PLL 1-28 PLL 20MHz 40MHz 80MHz 120MHz 190MHz 200MHz DDS DAC 200MHz GWAC3 FPGA I/O 100 DAC 190MHz \Experiments\chapter12_C\Ep1c3_13_10_PHAS\ DDS_VHDL \Experiments\chapter12_C\Ep1c3_13_10_PHAS_PLL\ DDS_VHDL 1 GW PWORD 2 1 FWORD 3-1 DDS_VHDL.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS_VHDL IS -- PORT ( CLK2 : IN STD_LOGIC; CLK_DA : OUT STD_LOGIC; FWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 43

44 PWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); POUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END; ARCHITECTURE ne OF DDS_VHDL IS COMPONENT PLL20 PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG32B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG10B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER32B PORT ( A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER10B PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT SIN_ROM PORT ( address : IN STD_LOGIC_VECTOR(9 DOWNTO 0); inclck : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; SIGNAL CLK : STD_LOGIC; SIGNAL F32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL D32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL DIN32B : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL P10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL LIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL DOUT : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL DIN: STD_LOGIC_VECTOR(7 DOWNTO 0); F32B(27 DOWNTO 20)<=FWORD ; F32B(31 DOWNTO 28)<="0000"; F32B(19 DOWNTO 0)<=" " ; P10B( 9 DOWNTO 2)<=PWORD ; P10B( 1 DOWNTO 0)<="00" ; CLK_DA <= CLK; u1 : ADDER32B PORT MAP( A=>F32B,B=>D32B, S=>DIN32B ); u2 : REG32B PORT MAP( DOUT=>D32B,DIN=> DIN32B, LOAD=>CLK ); u3 : SIN_ROM PORT MAP( address=>sin10b, q=>fout, inclck=>clk ); u4 : ADDER10B PORT MAP( A=>P10B,B=>D32B(31 DOWNTO 22),S=>LIN10B ); u5 : REG10B PORT MAP( DOUT=>SIN10B,DIN=>LIN10B, LOAD=>CLK ); u6 : SIN_ROM PORT MAP( address=>d32b(31 DOWNTO 22), q=>pout, inclck=>clk ); u7 : PLL20 PORT MAP( inclk0=>clk2,c0=>clk); END; 1 2 ROM 3 ROM 4 Zm Fit in Windw

45 DDS 9 RTL 10 GW48 N.1 CLK Clck2 50MHz 16 D/A CLK_DA pin130 8 FWORD[7..0] 2 1 PIO7 PIO PWORD[7..0] 4 3 PIO15 PIO D/A FOUT[9..0] FPGA PA pin POUT[9..0] FPGA PB pin FPGA ROM 45

46 12 EPCS SignalTap II MIF 1024 GW48 1 CLK clck0 12MHz 4 3 PWORD 2 1 FWORD PLLL A/D MHz 7 \Experiments\chapter12_B\Ep1c3_13_5_RSV\ RESERV \Experiments\chapter12_C\Ep1c3_13_5_RSV_PLL\ RESERV (1) FPGA ADC (2) LPM_RAM 16 PLL 45MHz ADC DAC +/-12V Y1 X GWADDA D/A PA GWADDA ADC AIN JP17 OUTPUTJP18 INPUT HZ JL11 3 H_FJP15 WAVE OUT 4V N.5 1 Y1 X GWADDA PA X Y2 Y GWADDA PB Y EP1C3_13_5_RSV_PLL RESERV (3) SignalTapII ADIN 5510 Q1 RAM q DPRAM 46

47 RAM 11-4 RAM LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY RESERV IS PORT(CLK2, KEY1 : IN STD_LOGIC;--CLK2 pin17 KEY1 pin1 CLKAD,CLKDA : OUT STD_LOGIC; --CLKAD pin91 ADC CLKDA pin130 DAC TRAG, DOUT : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ADIN : IN STD_LOGIC_VECTOR (7 DOWNTO 0) ); END; ARCHITECTURE DACC OF RESERV IS COMPONENT DPRAM PORT ( address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); inclck, wren : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END COMPONENT; COMPONENT PLL50 PORT(inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END COMPONENT; SIGNAL CLK : STD_LOGIC; SIGNAL Q1 : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL MD0,DIN : STD_LOGIC_VECTOR (7 DOWNTO 0); CLKDA<=CLK;CLKAD<=CLK; PROCESS(CLK) IF rising_edge(clk) THEN Q1 <= Q1 + 1; END IF; END PROCESS; prcess(clk, ADIN) begin if rising_edge(clk) then DIN <= ADIN ; end if; end prcess; DOUT(9 DOWNTO 2)<=MD0; TRAG<=Q1; DOUT(1 DOWNTO 0) <= "00"; u1 : DPRAM PORT MAP(data=>DIN, wren=>key1, address=>q1, q=>md0, inclck=>clk); u2 : PLL50 PORT MAP(inclk0=>CLK2,c0=>CLK); END; SignalTapII \Experiments\chapter12_C\Ep1c3_13_7_SPCTR\ ADSUART (1) (2) 1 RS232 GW48 PC 1 COM1 GW48 TO FPGA FPGA PC RS232 clck0 12MHz SPECTREM ADSUART.SOF FPGA 5 1 2READMEFASetup.exe ADDA AIN 1-31 FreqAna 12-26/7 47

48 GW48 TO MCU \Experiments\chapter12_B\Ep1c3_13_8_GW48\ ETESTER \Experiments\chapter12_B\Ep1c3_13_8_GWDVPB\ ETESTER LIBRARY IEEE; --FPGA USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY etester IS PORT (BCLK : IN STD_LOGIC; -- clck2 50MHZ TCLK : IN STD_LOGIC; -- CLR : IN STD_LOGIC; -- CL : IN STD_LOGIC; -- SPUL CL -- SPUL CL --CL CL SPUL : IN STD_LOGIC; -- START : OUT STD_LOGIC;-- EEND : OUT STD_LOGIC; -- SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8 END etester; ARCHITECTURE behav OF etester IS SIGNAL BZQ : STD_LOGIC_VECTOR(31 DOWNTO 0); -- SIGNAL TSQ : STD_LOGIC_VECTOR(31 DOWNTO 0); -- SIGNAL ENA : STD_LOGIC; -- SIGNAL MA, CLK1, CLK2, CLK3 : STD_LOGIC; SIGNAL Q1, Q2, Q3 BENA, PUL : STD_LOGIC; SIGNAL SS : STD_LOGIC_VECTOR(1 DOWNTO 0); START <= ENA ; DATA <= BZQ(7 DOWNTO 0) WHEN SEL="000" ELSE -- 8 BZQ(15 DOWNTO 8) WHEN SEL="001" ELSE BZQ(23 DOWNTO 16) WHEN SEL="010" ELSE BZQ(31 DOWNTO 24) WHEN SEL="011" ELSE -- 8 TSQ(7 DOWNTO 0) WHEN SEL="100" ELSE -- 8 TSQ(15 DOWNTO 8) WHEN SEL="101" ELSE TSQ(23 DOWNTO 16) WHEN SEL="110" ELSE TSQ(31 DOWNTO 24) WHEN SEL="111" ELSE -- 8 TSQ(31 DOWNTO 24) ; BZH : PROCESS(BCLK, CLR) -- IF CLR = '1' THEN BZQ <= ( OTHERS=>'0' ) ; ELSIF BCLK'EVENT AND BCLK = '1' THEN IF BENA = '1' THEN BZQ <= BZQ + 1; END IF; END IF; END PROCESS; TF : PROCESS(TCLK, CLR, ENA) -- IF CLR = '1' THEN TSQ <= ( OTHERS=>'0' ); ELSIF TCLK'EVENT AND TCLK = '1' THEN IF ENA = '1' THEN TSQ <= TSQ + 1; END IF; END IF; END PROCESS; PROCESS(TCLK,CLR) IF CLR = '1' THEN ENA <= '0' ; ELSIF TCLK'EVENT AND TCLK='1' THEN ENA <= CL ; END IF; END PROCESS; MA<=(TCLK AND CL) OR NOT(TCLK OR CL) ; -- CLK1<=NOT MA ; CLK2<=MA AND Q1 ; CLK3<=NOT CLK2; SS<=Q2 & Q3 ; DD1: PROCESS(CLK1,CLR) IF CLR = '1' THEN Q1 <= '0' ; ELSIF CLK1'EVENT AND CLK1 = '1' THEN Q1 <= '1' ; END IF; END PROCESS; DD2: PROCESS(CLK2,CLR) 48

49 IF CLR = '1' THEN Q2 <= '0' ; ELSIF CLK2'EVENT AND CLK2 = '1' THEN Q2 <= '1' ; END IF; END PROCESS; DD3: PROCESS(CLK3,CLR) IF CLR = '1' THEN Q3 <= '0' ; ELSIF CLK3'EVENT AND CLK3 = '1' THEN Q3 <= '1' ; END IF; END PROCESS; PUL<='1' WHEN SS="10" ELSE -- SS= 10 PUL '0' ; -- EEND<='1' WHEN SS="11" ELSE --EEND '0' ; -- BENA<=ENA WHEN SPUL='1' ELSE-- SPUL 1 PUL WHEN SPUL='0' ELSE-- SPUL 0 PUL ; END behav; 12 (1) FPGA GW GW48 (2) FPGA (3) (4) 4 PLL LPM 50MHz 100MHz PLL PLL CL 2 VHDL 2-1 FPGA. 3 etester.vhd, 4 12 TCLK BCLK 500ns DATA 5 TCLK START EEND 6 12 TCLK BCLK 500ns DATA 2-4 TCLK 7 GW48 EDA FPGA FPGA EP1C3 5 etester.vhd 1 BCLK clck9 12MHz 2 TCLK clck Hz 3 CLR CL SPUL START EEND DATA7 DATA6 DATA0 2 1 FPGA 6 DATA SEL2 SEL1 SEL VHDL GW48 FPGA 9 8 FPGA GWDVPB EP1C3 GWDVP-B GWDVP-B 10 1 FPGA FPGA.\gwdvpb\gwdvp_asm\gwdvp3.asm 89S51 isp 10 GW48 ByteblasterMV JP6 5V GWDVP-B 49

50 89S51 isp GW48 GWDVP-B 2-1A 11 EP1C3 GWDVP-B 10 GW48 GWDVP-B EP1C FPGA PIO16 GW48 GWDVP-B 12 1 GW48-PK2 JP6 +5V JP5 Qthers ByterBlsterMV 10 ByterBlsterMV MCU Dwnlad Prt 2 89S51/52 3 WAVE 4\Experiments\ispMCU_DwnLad\ ispmcu_dwnlad.exe isp K = N1/ N1+N2 N1 N2 2-8 TPAS.GDF ETESTER TCLK EPD ETESTER 2-10 PA PB EPD PB PA EPD PB PA PB PA EPD 360 Ο Ο = K* 360 = N1/ N1+N2 360 Ο 1 GWDVPB PIO16 PIO

51 GW48 4V GW48 GWDVPB PIO16/PIO TPAS.gdf 2-9 epd 2-10 EPD \Experiments\chapter12_C\Ep1c3_13_11_PS2KEY\ \Experiments\chapter12_C\Ep1c3_13_12_VGAGAME\ GW48 PS2 GW48 clck9 50MHz VGA GW48 VGA ENBL TOP.SOF FPGA VGA VGA \Experiments\chapter12_C\Ep1c3_13_7A_FTEST\ 1 GW48 RS232 GW48 PC 1 COM SENDFREOK FREQTEST.SOF FPGA 4 GW48 TO MCU FPGA AT89C51 5 P27 GND 51

52 6 CLOCK2 1Hz 7 CLOCK0 1HZ 50MHz CLOCK5/6/7 CLOCK Hz 8 CLOCK0 9 MCUCOM SEREALCOM.EXE 1 COM1 OK 10 RECEIVE FPGA 11 SEND 35 SEND GW48 FPGA 8/7 \Experiments\chapter12_B\Ep1c3_LOGIC_SYNSZ\ RAM DPRAM CLK clck0 12MHz 50MHz PLL KEY1 1 pin1 5 TRAG 9..0 ADDA DAC PB X Y1 X GWADDA PB DOUT 9..0 ADDA DAC PA Y 10 Y2 Y GWADDA PA FPGA DAC LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY RESERV IS PORT ( CLK KEY1 : IN STD_LOGIC; TRAG : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); DATAIN : IN STD_LOGIC_VECTOR (9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END; ARCHITECTURE DACC OF RESERV IS COMPONENT DPRAM PORT (address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); inclck : IN STD_LOGIC ; utclck : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (9 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT; SIGNAL SCANCNT : STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL Q1 : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL MD : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL CNT : STD_LOGIC; PROCESS(CLK) IF CLK'EVENT AND CLK = '1' THEN Q1 <= Q1 + 1; END IF; END PROCESS; PROCESS(Q1) IF Q1 = " " THEN CNT <= '1' ; ELSE CNT <= '0' ; END IF ; END PROCESS; PROCESS(CNT) IF CNT'EVENT AND CNT = '1' THEN IF SCANCNT < "0110" THEN SCANCNT <= SCANCNT + 1; ELSE SCANCNT<="0000" ; END IF; END IF ; 52

53 END PROCESS; PROCESS(SCANCNT,MD) CASE SCANCNT IS WHEN "0000" => IF MD(0)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0001" => IF MD(1)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0010" => IF MD(2)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0011" => IF MD(3)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0100" => IF MD(4)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0101" => IF MD(5)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN "0110" => IF MD(6)='1' THEN DOUT <= " " ; ELSE DOUT <= " " ; END IF; WHEN OTHERS => DOUT <= " " ; END CASE; END PROCESS; TRAG <= Q1 ; u1 : DPRAM PORT MAP(data=>DATAIN,wren=> KEY1, address=>q1, q => MD, inclck=>clk,utclck=>clk ); END; NCO IP NCO_v2.2.1 NCO1.vhd

54 NCO1.vhd GW48 10 DAC 10 NCO 2 1 NCO 1 FSK 2 PSK 3 DDS NCO FIR SOPC 6-5 FIR Hamming 10 GW48 ADC DAC FIR_Cmpiler_v3.2.0 FIR32.vhd 54

55 Hamming FIR Hamming 10 GW48 ADC DAC FFTv2.1.1 FFT1.vhd CSC VGA CSC_v2.2.0 CSC1.vhd

56 CSC_v2.2.0 CSC1.vhd SignalTapII SignalTapII 56

57 SignalTapII SignalTapII \Experiments\USB1C3\ USB245 EP1C3 \Experiments\USB1C6\ USB245 EP1C6/12 USB USB USB SOF Cyclne FPGA / 1 USB PC 2/ 1 6/ 5 PC USB

58 USB USB USB1C3 USB1C6TestSft USBDEMO.exe,

59 EEPROM USB EEPROM /5 712 FPGA VHDL CPU /CMPUT_EXPMT/EXPERIMENTS/EXPMT2 / 2-1.PPT /CMPUT_EXPMT/Experiments/Expmt2 / DEMO_2_1_alu ALU 2-1 ALU181 74LS181 VHDL 8 ALU 8 A[7..0] B[7..0] S[3..0] 16 S[3..0] 4 2 LPM_COUNTER Sclk 2-1 M=0 M=1 C N F[7..0]C O 8 IN[7..0] ALU ALU181 M=H M=L S3 S2 S1 S0 Cn=L Cn=H B F = A F = A F = A 1 F = A + F = A + B F ( A+ B) F = AB F = A + B F A + B F = F = 1 2 F = 0 = 1 = F = AB F = A AB F = A AB F = B F = ( A+ B) A B F = ( A+ B) A B F = A B F = A B F = A B F = AB F = A + B F = ( A + B) F = A + B F = A AB F = A AB F = A B F = A B F = A B F = B F = A + B AB F = ( A + B) AB F = AB F = AB F = AB F = 1 * F = A A F = A A F = A + B F = A + B A F = A + B A F = A + B F = A + B A F = A + B A F = A F = A F = A 1 1 *, ALU Quartus II Text Editr ALU181.VHD VHDL ALU181.VHD 59

60 2 2-1 Quartus II 3 Prgramming ALU.sf GW48 FPGA 4 NO.0 ALU 2-1 A[7..0] B[7..0] S[3..0] M Cy ALU / A[7..0] H 4/3 55H B[7..0] AAH 2/1 AAH H AAH 2-1 ALU181 VHDL 2 8 M=0 6 ~ S[3..0]=9 8 9 ALU 7 cn=0 7/6/5=0FF 55H+AAH=0FFH 7 cn=1 7/6/5=100 55H+AAH+1=100H 2-1 ALU 2-2 A[7..0] B[7..0] F[7..0] SW_B S3 S2 S1 S0 M BUS A[7..0] B[7..0] (4) ALU181 ALU DRl=A[7..0] DR2=B[7..0] ( ) ( ) ( 0) (4) S3 S2 S1 S0 M DR1=A[7..0] DR2=B[7..0] 2-3 S3 S2 S1 S0 A[7..0] B[7..0] M=0 M=1 cn=0 cn= A A 5 5 F= F= F= A A 5 5 F= F= F= 60

61 A A 5 5 F= F= F= A A 5 5 F= F= F= F F 0 1 F= F= F= F F 0 1 F= F= F= F F 0 1 F= F= F= F F 0 1 F= F= F= F F F F F= F= F= F F F F F= F= F= F F F F F= F= F= F F F F F= F= F= F= F= F= F= F= F= F= F= F= F= F= F= S3 S2S1S0 M Cn DR1 DR2 Cn4 66 FF DR 1 DR 2 DR 1 DR 1 DR 2 DR 1 1 DR DR DR 1 + DR 2 DR 1 DR 2 1 ALU ? ALU 1 VHDL 74373B LPM_COUNTER 3 VHDL ALU 4 VHDL 8 alu AND OR XOR NOT 5 VHDL 16 ALU 8 ALU 6 ALU181 /CMPUT_EXPMT/EXPERIMENTS/EXPMT2 / 2-2.PPT /CMPUT_EXPMT/Experiments/Expmt2 / DEMO_2_2_ALUc ALU181 D T 4 CN T 4 5 CN CN c 1 2-2A B 5 T4 7 CN =0 8 M 3 A0_B1 = ( ) 2 1 9DH 4/3 9D 61

62 2 3=0 2 1 E5H M 0 ALU 6 5 9DH+E5H=82H CN 1( ALU ) 5 T4 D =83H 4 8=1 5 T AC5E9 H+ BD5AF8H = S3 S2 S1 S0 A[7..0] B[7..0] 2-2A ALU 2-5 M=0 M=1 cn=0 cn= ? B ALU 62

63 /CMPUT_EXPMT/EXPERIMENTS/EXPMT2 / 2-3.PPT /CMPUT_EXPMT/Experiments/Expmt2 / DEMO_2_3_shifter SHEFT VHDL / / LED CLK S 0 S 1 M CLK M M=1 8 C0 7 S 0~3 6 LED8 D[7..0] QB[7..0] 6 5 CN7 1 0 Cnfigure 1SHEFT.bdf D[7..0] BH D[7..0] QB[7..0] 6 (S1,S0)=3 8 M=0 S&M=6 8 5 CLK (S1,S0)=2 S&M=4 8 5 CLK QB[7..0] 6 5 6BH B5H DAH 5 8 M=1 C M S1 S0 1 2? G S1 S0 M

64 VHDL 1SHEFT.VHD CNT2.VHD /CMPUT_EXPMT/EXPERIMENTS/EXPMT3 / 3-3.PPT /CMPUT_EXPMT/Experiments/Expmt3 / DEMO_3_3_FIFO 1 FPGA lpm_fif 2 FPGA lpm_fif lpm_fif 3 lpm_fif FIFO FIFO First In First Out FIFO CPU FIFO FPGA EAB lpm_fif lpm_fif lpm_fif 1 lpm_fif FIFO 2 GW-48 NO / WR CLK 4/3 2/1 FIFO 1 LPM-FIFO D8-D FIFO 64

65 fif2.bdf fif2.sf FPGA NO.0 1 LPM-FIFO 2 FIFO 1 FPGA EAB LPM-FIFO 2 lpm_fif FPGA EAB 3 lpm_fif CPU lpm_fif full empty usedw[7..0]d 4 LPM-FIFO 5 LPM-FIFO 1 FPGA FPGA / RAM 5 CPU /CMPUT_EXPMT/EXPERIMENTS/EXPMT4 / 4-1.PPT /CMPUT_EXPMT/Experiments/Expmt4 / DEMO_4_1_S_T D 4 T 1 ~T 4 CLK1 clck0 1Hz~12MHz RST1 T1 1 T2 T3 T4 0 RST1 T1~T4 CLK1 EXEC T1~T4 CLK1 RST T4.bdf T4.SOF 1 Clck0 4Hz 8 RST T1 T2 T3 T RST1 65

66 T1 T2 T3 T4 RST T5.bdf T5.SOF 1 Clck0 4Hz 1Hz-50MH 8 RST T1 T2 T3 T / S0 S0=0 S0= TS5.bdf TS5.SOF 1 Clck0 4Hz 8 RST1 7 S T1 T2 T3 T /

67 (1) (2) (3) / (4) (1) (2) (3) 1 2 /3 VHDL / /CMPUT_EXPMT/EXPERIMENTS/EXPMT4 / 4-2.PPT /CMPUT_EXPMT/Experiments/Expmt4 / DEMO_4_2_PC_AR PC CPU PC PC T4 1 LDPC LDPC data[ ] aclr 0 aclr AR SRAM 273 PC FPGA BUSMUX LDAR sel LDAR LDAR

68 NO.0 PC_unit.bdf pc_unit.sf B[7..0] D1~D8 2/1 CLR 5 2 (0 1 0) LDAR 6 =0 BUSMUX PC LDAR=1 BUSMUX B[7..0] LDPC 7 PC LDPC=1 B[7..0] PC LDPC=0 PC T4 T4 8 PC CLK 8 2 B[7..0] LDPC=0 1 LDPC= /1 A5 5 PC 0(0 1 0) 2 8 8/7 AR PC A5 PC 8 AR 8/7 A5 4 6=0 PC 2/ (0 1 0) LDPC 86 PC 5 8 AR (1) (2) (3) PC AR /CMPUT_EXPMT/EXPERIMENTS/EXPMT4 / 4-3.PPT /CMPUT_EXPMT/Experiments/Expmt4 / DEMO_4_3_uC FPGA LPM_ROM T2 ua T4 1 1 se5_1.sf N.1 / I[7..2] 2 FC FZ 2 3 P[4..1] ; 3 4 SWA SWB 4 8 T SE[6..1] FC FZ I[7..2] SE[6..1] I[7..2]SE[6..1] P[4..1] I[7..2] SE[6..1] SWA SWB SE[6..1] 68

69 se6_1.sf N.1 / D d[6..1] ; D 1 S[6..1] 3 7 D 4 8 CLK D q[6..1] d[6..1] q[6..1]/ s[6..1]q[6..1] 3 ldr0_2.sf ldr0_2.gdf N.5 I[3..0] LDRI RD_B RS_B RJ_B LDR0~LDR2 R0_B~R2_B (1) (2) (3) 1 FC FZ S[6..1] / 2 P[4..1] S[6..1] 2 SWA SWB S[6..1]

70 LPM_ROM /CMPUT_EXPMT/EXPERIMENTS/EXPMT6 / 6-1.PPT /CMPUT_EXPMT/Experiments/Expmt6 / DEMO_6_1_CPU 1 CPU OP-CODE rs rd IN ADD STA OUT JMP 4 OP-CODE rs rd Rs rd 00 R0 01 R1 10 R2 IN ADD addr STA addr OUT addr JMP addr Addr 0 0H 1 0H 2 0H 3 0H 4 0H INPUTR0 R0+[addr] IN 8 XX H addr RAM 70

71 1, KRD CLR SWA SWB 0 0 RAM 2, KWE CLR SWA SWB 0 1 RAM 3RP CLR SWA SWB SWB SWA S3 S2 S1 S0 M Cn WE A9 A8 A B C ua5 ua4 ua3 ua2 ua1 ua0 6-2 A B C LDRi RS-B P LDDR LDDR LDIR P LOAD ALU-B LDAR LDAR PC-B LDPC 24 (1) ua5 ua0 (2) S3 S2 Sl S0 ALU (3) M ALU M 0 M l (4) Cn Cn 0 ALU Cn 1 (5)WE RAM /CE 0 WE 0 WE 1 (6) A9 A8 CS0 CS1 CS2 SW_B RAM LED (7) A (8) B (9) C P(1)~P(4) LDPC 6-2 P(1) KRD KWE RP

72 P(1) IR7-IR4 5 5 P(4) 6-2 SWB SWA S3 S2 S1 S0 M CN WE A9 A8 A B C UA5 UA E D C E B A A E 0 0 D E D E D E D 8 E E D E00F A E D E D A A D IR P(1) T4 : LCD CPU B100_C.sf LCD CPU LCD IN INPUT DR1 DR1 OUT OUTPUT DR2 DR2 ALU PC BUS AR R0 R0 RAM / R1 R1 IR R2 R2 MC 72

73 1 1 IN 00 IN R0 2 ADD [0AH] 100A R0 RAM 0AH 34H 3 STA [0BH] 200B R0 RAM 0BH 4 OUT[0BH] 300B RAM 0BH OUT 5 JMP [12H] H LPM_ROM ROM_11.mif( demd_cpu5 ) b100_c.bdf b100_c.bdf b100_c.sf bus_c.sf clck0 1.5MHz 6-3 b100_c.bdf 2 ( b100_c.bdf ) 1 KWE KRD A 20 0B CPU RAM LPM_RAM_DQ 6-2 SWB SWA RST 8 = >1->0 IN=35 PC=00MC= BUS=35 35 RAM=35 LPM_RAM 7 2 C4 RAM PC 1 1 RAM 2 RAM LPM_RAM 8=0 PC SWB SWA RST 8 = LPM_RAM 6-1 CPU MIC PC AR IN BUS RAM DR0 DR1 LPM_RAM LPM_RAM 1 QuartusII b100_c.bdf b100_c.bdf LPM_RAM_DQ 73

74 LPM_FILE./5_ram.mif 5_ram.mif 5_ram.mif 2 LPM_RAM 3 RST 8 =1 SWB SWA FPGA 6-2 (, DR1 DR0, DR2 DR1) 4 3 SWB SWA=1,1 6-1 RP H RP 1123 MC= IN=56H PC=00 AR=00 PC 1 PC=01 MC=00ED82 IN= LED3 1 LED MC=00C RAM 00 BUS BUS IR= MC= IN IN R0=56; A RAM 0B

75 EAB CPU CPU CPU CLK1=1.5MHz 64 Pre.. STEP data[1] ALU data[2] RAM P[10] AR P[12] IR QuartusII 4 5 LPM_RAM 6 7 LPM_ROM 7 ALU DR1 PC IR AR BUS 6-2 INPUT

76 ALU VHDL GW48 2 VHDL PC 3 VHDL AR 4 VHDL IR 5 CPU VHDL 6 IN ADD STA OUT JMP SUB ADDC AND OR XOR 10 mif LPM_ROM 3 CPU 7 ALU181.VHD B100_C.SOF 0 8 in[7..0] 2 1 SWB SWA >KRD 01 >KWR 11 >RP RST1 > CPU, 8 STEP > 7 Clck0 1.5MHz CPU LCD CPU CPU 1 d0_[7..0] PC AR DR1 DR2 R0 CO T4..T1 ua bus[7..0] 6-6 CPU 1 DR1 DR2 DR0/DR1 6-1 (1) ua5 ua0 (2) IR7 IR5 IR7 IR6 IR5 76

77 (3) CLK1 6~12MHz (4) T1~T4 (5) s3 s2 sl s0 ALU (6) M ALU M 0 M l (7) cn cn 0 ALU cn 1 (8)SWE (9)SRD (10) RST1 0 (11)LDAR AR RAM (12) /CE RAM /CE 0 LPM_RAM (13) WE RAM /CE 0 WE 0 WE 1 (14)BUS(7..0) (15) LDPC PC (16) LOAD LOAD 0 PC( ) LOAD 1 PC (17) ALU_B BUS (18) PC_B BUS (19) R0_B R4 BUS (20) SW_B 2 1 (21) LDR0 DR0 (22) LDR1 DR1 (23) LDIR ( ) IR (25) P(1) P(1) (26) ua ua 0 (27) STEP 2 STEP ( ) Tl T2 T3 T4 FPGA 8051 M CPU RAM 3 4K ROM 4 ROM 89C51 1 M8051 EDIF 1 M POUT0[7..0] POUT1[7..0] POUT2[7..0] POUT3[7..0] M8051 P0 P1 P2 P PIN0[7..0] PIN1[7..0] PIN2[7..0] PIN3[7..0] M8051 P0 P1 P2 P CLK 3MHz--50MHz RST RST=1 RST=0 1 1 MaxplusII mcu8051.edf File Prject Name,.\demg_8051\m8051_1\mcu8051.edf mcu8051.edf (string. /asm/test0.hex ) ROM ASM test0.asm hex test0.hex test0.asm 9-3 M8051 4KB 2 1 P2 PIN /1 P3 PIN /3 P0 POUT0 8 6/5 P1 POUT1 8 8/7 CLK clck9 12MHz 3 mcu8051.sf HEX mcu8051.edf 77

78 5 m M M M M clck.asm mcu8051.edf 2 78

79 1 MaxplusII m8051_test.edf File Prject Name,.\demg_8051\m8051_2\m8051_test.edf 9-2 m8051_test.edf 1 (string. /asm/clck.hex ) 9-4 clck.hex clck.asm ASM CLK 12MHz 2 clck.asm LEDP[7..0] 7 LEDS[5..0] 6 key1 key2 key3 3 5 m8051_test.sf CLK clck9 12MHz RST 8 CPU key1 key2 key , GW48 8 SOPC/EDA I / library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity adder is prt(clck : in std_lgic; r1x : in std_lgic_vectr(15 dwnt 0); r2x : in std_lgic_vectr(15 dwnt 0); r3x : in std_lgic_vectr(15 dwnt 0); r4x : in std_lgic_vectr(15 dwnt 0); y : ut std_lgic_vectr(15 dwnt 0) ); end; 79

80 architecture rtl f adder is signal tmp:std_lgic_vectr(15 dwnt 0); begin prcess(clck) begin if rising_edge(clck) then tmp <= (r1x + r2x) + (r3x + r4x); end if; end prcess; y <= tmp; end; library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity mult is prt ( clck : in std_lgic; a_in : in std_lgic_vectr( 7 dwnt 0); b_in : in std_lgic_vectr( 7 dwnt 0); a_ut : ut std_lgic_vectr( 7 dwnt 0); b_ut : ut std_lgic_vectr( 7 dwnt 0); r : ut std_lgic_vectr(15 dwnt 0) ); end; architecture rtl f mult is signal tmp_a, tmp_b: std_lgic_vectr(7 dwnt 0); begin prcess(clck) begin if rising_edge(clck) then tmp_a <= a_in; tmp_b <= b_in; r <= tmp_a * tmp_b; end if; end prcess; a_ut <= tmp_a; b_ut <= tmp_b; end; library ieee; use ieee.std_lgic_1164.all; entity filter is prt ( clck : in std_lgic; din0x : in std_lgic_vectr( 7 dwnt 0); cef0x : in std_lgic_vectr( 7 dwnt 0); din4x : ut std_lgic_vectr( 7 dwnt 0); cef4x : ut std_lgic_vectr( 7 dwnt 0); result : ut std_lgic_vectr(15 dwnt 0) ); end; architecture rtl f filter is cmpnent mult prt ( clck : in std_lgic; a_in : in std_lgic_vectr( 7 dwnt 0); b_in : in std_lgic_vectr( 7 dwnt 0); a_ut : ut std_lgic_vectr( 7 dwnt 0); b_ut : ut std_lgic_vectr( 7 dwnt 0); r : ut std_lgic_vectr(15 dwnt 0) ); end cmpnent; cmpnent adder prt ( clck : in std_lgic; r1x : in std_lgic_vectr(15 dwnt 0); r2x : in std_lgic_vectr(15 dwnt 0); r3x : in std_lgic_vectr(15 dwnt 0); r4x : in std_lgic_vectr(15 dwnt 0); y : ut std_lgic_vectr(15 dwnt 0) ); end cmpnent; signal cef1x,cef2x,cef3x,din1x,din2x,din3x:std_lgic_vectr(7 dwnt 0); signal r0x,r1x,r2x,r3x: std_lgic_vectr(15 dwnt 0); begin mult_i0:mult prt map(clck,din0x,cef0x,din1x,cef1x,r0x); mult_i1:mult prt map(clck,din1x,cef1x,din2x,cef2x,r1x); mult_i2:mult prt map(clck,din2x,cef2x,din3x,cef3x,r2x); 80

81 mult_i3:mult prt map(clck,din3x,cef3x,din4x,cef4x,r3x); adder_i:adder prt map(clck,r0x,r1x,r2x,r3x,result); end; library ieee; use ieee.std_lgic_1164.all; use ieee.std_lgic_unsigned.all; entity largefilter is prt ( clck : in std_lgic; din0x : in std_lgic_vectr( 7 dwnt 0); cef0x : in std_lgic_vectr( 7 dwnt 0); result : ut std_lgic_vectr(15 dwnt 0) ); end; architecture str f largefilter is cmpnent filter prt ( clck : in std_lgic; din0x : in std_lgic_vectr( 7 dwnt 0); cef0x : in std_lgic_vectr( 7 dwnt 0); din4x : ut std_lgic_vectr( 7 dwnt 0); cef4x : ut std_lgic_vectr( 7 dwnt 0); result : ut std_lgic_vectr(15 dwnt 0) ); end cmpnent; signal cef4x,din4x,cef8x,din8x,cef12x,din12x,cef16x,din16x:std_lgic_vectr(7 dwnt 0); signal r0x,r4x,r8x,r12x :std_lgic_vectr(15 dwnt 0); begin filter_i0:filter prt map(clck,din0x,cef0x,din4x,cef4x,r0x); filter_i1:filter prt map(clck,din4x,cef4x,din8x,cef8x,r4x); filter_i2:filter prt map(clck,din8x,cef8x,din12x,cef12x,r8x); filter_i3:filter prt map(clck,din12x,cef12x,din16x,cef16x,r12x); prcess(clck) begin if rising_edge(clck) then result <= r0x + r4x + r8x + r12x; end if; end prcess; end; / 4 1 Matlab/Simulink DSP Builder QuartusII FIR FIR FIR

82 h( n) = C q ( h(0) x( n) + h(1) x( n 1) + h(2) x( n 2) + h(3) x( n 3) + h(4) x( n 4) + h(5) x( n 5)) h(0) = 25, h(1) = 93, h(2) = 212, h(3) = 212, h(4) = 93, h(5) = 25 = 0.04 C q Simulink I I Fs 48kHz Fc 10.8kHz FIR FIR 2 FIR h ( 0) = h(5) = 25, h(1) = h(4) = 93, h(2) = h(3) = 212 h( n) = Cq[ h(0)( x( n) + x( n 5)) + h(1)( x( n 1) + x( n 4)) + h(2)( x( n 2) + x( n 3))] FIR 7 6 DSP Builder Shift Taps Multiply Add FIR Shift Taps Multiply Add 2 5 FIR FIR Cmpiler IP Cre 32 FIR 9 8 DSP Builder : \DSPBuilder\designexamples\Fir32\ 32 FIR AltrFir32.mdl 20MHz MHz 5651 Simulink 10 1 Matlab/Simulink DSP Builder QuartusII IIR I IIR IIR IIR H z 1+ z + 0.3z 0.5z + 0.1z + 0.5z z z ( z) = DSP Builder IIR

83 1 Matlab/Simulink DSP Builder QuartusII DDS FSK PSK DDS Matlab FPGA GW48 Cyclne FPGA 10 D/A SignalTapII 6-68 Pwrd Fwrd 8 D/A 10 TRAGut 10 SINLUT Fwrd Pwrd Clck0 8 0 TRAGut ddsut 10 D/A GW48 D/A DDS 5 4 DDS AM FPGA 50MHz 1.5MHz 50Hz 8kHz 30% FSK 7 6 DDS 2ASK 6-68 DDS 8 7 DDS 2PSK TRAGut ROM SINLUT1 Pwrd 8 0 GW48 1 2/ 1 8 4/ 3 8 clck0 50MHz 12MHz 10 D/A 9 8QAM DDS 16QAM FIR IIR FFT DDS IP Cre Altera DDS IP Cre NCO Cmpiler 83

84 NCO Cmpiler 2FSK DDS Delay SINLUT 16 delay Fwrd QAM

85 m DSP Builder m Linear Feedback Shift Registers LFSR n i F( x) = C i x 6-27 i= 0 n n n = 5 m 5 LFSR 5 2 x + x m m x + x + 1 DSP Builder 6-54 DSP Builder XOR mut 6-54 DSP Builder 0 m m 1 m m 85

86 6-55 m 6-56 m Simulink m DSP Builder n { x i } 1 i n x i +1-1 n = R( j) i= j 1 x x i x+ j n, = 0, ± 1, 0, j = 0 0 < j < n j n j = 0 j R( j) ± 1 +1,+1,+1,-1,-1,+1, j = 0 R( j) = 7 i= 1 2 x i = 7 j = 1 R( j) = 1 j = 3,5, 7 R( j) = 0 j = 2,4, 6 R( j) = 1 86

87 Simulink DSP Builder 7 +1,+1,+1,-1,-1,+1,-1 MDL 6-57 Shift Taps bxp1m bxn1m x i x i + j 7 Pipeline Cmparatr Cnstant Cnstant bxp1m bxn1m + 1* x i + j 1* x i + j Simulink Frm Wrkspace1 Matlab bxp1m bxn1m 87

88 ARQ FEC HEC RS RS Reed Slmn BCH RS ( n, k) RS k m k m t RS n = 2 1 k n k = 2t 2t 1 m RS Altera RS IP Cre RS Cmpiler RS RS Cmpiler QuartusII DSP Builder RS IP Cre 2 5 QPSK RS QPSK 3 1 Matlab/Simulink DSP Builder QuartusII a(t) b(t) DDS I(t) Q(t) I 0 ( t) = a( t)csω t ( t) = b( t)sinω t Q X 0 ( t) = I( t) + Q( t) = a( t)csω 0t + b( t) sinω t X(t) I(t) Q(t) X(t) I(t) Q(t) a(t) b(t) 2 X(t) a(t) b(t) 6-72 X(t) = X ( t)csω 0t = a( t)cs ω 0 t + b( t)sinω 0 t csω t = a( t) + a( t)cs2ω 0t + b( t)sin 2ω 0t v A v B = X ( t)sinω 0t = b( t)sin ω 0 t + a( t)sinω 0 t csω 0 t = b( t) a( t)cs2ω 0t + a( t)sin 2ω 0t FIR (1/2)a(t) (1/2)b(t) K K K v C = a( t) v D = b( t) 2 2 DDS csω sinω t I(t) Q(t) t

89 a(t) b(t) FIR 16 FIR IP Cyclne FPGA EDA isppac isppac GW48 isppac PAC _Designer ISPPAC PAC _Designer isppac10 isppac80 isppac30 isppac20 16MB RAM 10MB 1 PAC _Designer F PAC_Designer D PAC-Designer D 10MB PAC_Designer F ISPPAC SETUP.EXE Next Yes Name Cmpany Next Brwse Path Drives Directries 89

90 OK YNext Finish crack license.dat D PAC-Designer ( ) PAC_Designer PAC_Designer PAC_Designer isppac80 5 Windws Lattice SemicnductrPAC_Designe PAC_Designe FileNew 9-1 isppac80 OK 9-2 isppac isppac CtgA unknwn [ ] Cpy Filter Cnfiguratin isppac80 Chebyshev KHz dB KHz. OK

91 Optins Simulatr Tls Run Simulatr 9-5 Edit Security isppac80 Tls Read IDCODE isppac80 Dwnlad isppac80 POWER POINT PAC 9 PAC_Designer isppac10 Windws Lattice SemicnductrPAC_Designe PAC_Designe FileNew 9-1 isppac10 OK 9-6 PAC 9 V = k V + k V k 1 9 OUT IN1 1 IN1 2 IN 2 V V 2 IN IA1 IN1 OK IA1 1 9 OK Optins 9-7 Simulatr 9-8 Tls Run Simulatr isppac10 Tls Dwnlad 9 91

92 isppac10

93 isppac10/20 isppac ISP PAC (PACblck) (IA1 IA2) (OA1) ( ) dB-10~ pF~62pF 128 PAC isppac isppac10 1 OUT2+ 2 Vut+ - Vut- 2 OUT2-2 Vut+ - Vut- 3 IN2+ 2 Vin+ - Vin- 4 IN2-2 Vin+ - Vin- 5 TDI TCK 6 TRST 7 VS 5 8 TDO TCK 9 TCK 10 TMS 11 IN4-4 Vin+ - Vin- 93

94 12 INT+ 4 Vin+ - Vin- 13 OUT4-4 Vut+ - Vut- 14 OUT4+ 4 Vut+ - Vut- 15 OUT3+ 3 Vut+ - Vut- 16 OUT3-3 Vut+ - Vut- 17 IN3+ 3 Vin+ - Vin- 18 IN3-3 Vin+ - Vin- 19 CMVin VREFut 2.5V 20 CAL 21 GND 22 VREFut 0.1uF 23 TEST 24 TEST 25 IN1-1 Vin+ - Vin- 26 IN1+ 1 Vin+ - Vin- 27 OUT1-1 Vut+ - Vut- 28 OUT1+ 1 Vut+ - Vut- 94

95 95

96 DDRAM CS1=1 CS2=1 Y= DB0 DB0 DB0 DB0 DB0 DB0 DB0 DB0 DB0 DB0 X=0 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 96

97 DB0 DB7 X=7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 DB0 DB7 97

98 98

99 99

100 100

101

102 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 AC6 AC5 AC4 AC3 AC2 C1 AC0 2

103 3

104 5-3 G A 4

105 5

106 SOPC/EDA II InCunt SinLUT SinLUT 8 Delay Prduct SinCtrl SinCtrl 1 SinCtrl Prduct SinOut D/A 1 1 Matlab Matlab Cmmand Windw Wrkspace Cmmand Histry Matlab Matlab wrk 2. simulink mdl simulink File 4-6 New mdel simulink 3 SignalCmpilder simulink Altera DSP BuilderDSP Builder DSP builder Blck AltLab AltLab SignalCmpilder SignalCmpilder 4-7 simulink Blck 4 Increment Decrement 4-2 Increment Decrement Increment Decrement 4-8 DSP Builder Arithmetic Arithmetic Increment Decrement SignalCmpilder Increment Decrement 4-1 DSP Builder 5. IncCunt Increment Decrement Increment Decrement 6

107 IncCunt IncCunt IncCunt IncCunt IncCunt Blck Parameters IncCunt 4-9 Increment Decrement signed Integer 6 IncCunt Directin Increment Use Cntrl Inputs simulink Clck Phase Selectin 1 Increment Decrement 3-10OK DSP Builder Help SinLUT Altera DSP Builder Gate LUT 4-10 SinLUT SinLUT Blck Parameters SinLUT, 4-11 Output[number f bits] 8 LUT Address Width 6 MATLAB Array sin sin sin([ : : ]) SinLUT π *sin[0:2*pi/2^6]:2*pi pi Use LPM QuartusII RAM EAB ESB M4K SinLUT RAM ROM LCs SinLUT Delay simulink Altera DSP Builder Strage Delay Delay Clck Phase Selectin SinCtrl simulink Altera DSP Builder Bus Manipulatin AltBus AltBus SinCtrl SinCtrl 1 SinCtrl SinCtrl Bus Type Single Bit Nde Type Input Prt Prduct Altera DSP Builder Arithmentic Prduct 4-14 Prduct Delay SinLUT SinCtrl SinCtrl SinLUT Prduct Prduct 4-14 Use Dedicated Circuitry FPGA 10 SinOut Altera DSP Builder Bus Manipulatin AltBus 4-15 AltBus SinOut SinOut 8 FPGA 8 D/A SinOut SinOut Bus Type Signed Integer Nde Type Output Prt Apply number f bits SinOut 4-2 DSP Builder DSP Builder SignalCmpiler File Save 7

108 Sinut sinut.mdl SignalCmpiler 4-5 simulink 4-7 SignalCmpiler IncCunt 4-10 LUT 4-11 SinLUT 4-12 Delay 8

109 2 Simulink DSP Builder simulink 1 Step SinCtrl Simulink simulink Surces Surces Step sinut step SinCtrl Altera DSP Builder SignalCmpiler VHDL Simulink Step 2 simulink simulink Sinks Scpe 3-17 sinut Scpe Scpe Scpe Parameters Scpe 3-19 Scpe Gerneral Data Histry Gerneral Number f axes 2 OK Scpe SinCtrl Scpe 4-21 VHDL AltBus 4-13 SinCtrl 3-18 Prduct SinOut 4-16 Step 4-17 Scpe 4-18 Scpe 4-19 Scpe sinut sinut SinCtrl Step sinut Step SinCtrl Step step timeinitial value Final value Sample time step time 50 Initial value 0 Final Value 1 Sample time 1 Interpret vectr parameters as 1-D Enable zercrssing dectectin sinut 4-21 Simulatin Simulatin parameters 4-22 sinut Simulatin Parameters : sinut 4-20 Step 4-21 sinut 9

110 5 Slver Wrkspace I/O Diagnstics Advanced Real-Time Wrkshp Slver sinut Start time 0.0 Stp time 500OK sinut 4-22 simulink 4-23 simulink Start 5sinut SimulatinStart 4-31 Scpe scpe 4-24 SinOut sinut scpe D/A SinCtrl sinut SinOut SinCtrl SinCtrl 1 SinOut SinCtrl 0 0 Scpe Autscale 6 D/A D/A LUT 127*sin[0:2*pi/2^6]:2*pi SignalCmpiler Simulink DSP Builder FPGA VHDL 1 sinut signalcmpiler 4-33 Analyze SignalCmpiler sinut Matlab 2 Signal Cmpiler 4-34 Signal Cmpiler Prject Setting OptinsHardware Cmpilatin Messages SignalCmpiler Device Stratix Cyclne Device QuartusII 4-33 SignalCmpiler 4-34 SignalCmpiler 4-36 MDL t VHDL 10

111 3 MDL VHDLDevice Synthesis Hardware Cmpilatin 4-34 Cnvert MDL t VHDL MDL VHDL SynthesisQuartusII Quartus 1 simulink *.mdl VHDL Messages Generated tp level sinut.vhd files sinut.vhd 4-34 sinut VHDL sinut.vhd e:/myprj/sinwave 4 Synthesis QuartusII QuartusII 5 QuartusII 3 QuartusII pf sf 4-36 FPGA 4-36 Reprt File sinut sinut_dspbuilder_reprt.html 4 QuartusII SignalCmpiler MATLAB QuartusII sinut_quartus.tcl 1 QuartusII File Open Prject sinut DSP Builder QuartusII sinut.quartus SignalCmpiler QuartusII QuartusII QuartusII QuartusII QuartusII 3 EP1C6Q240C8 Start Cmpilatin 3 Prcessing Start Simulatin Prcessing Simulatin Reprt 4-46 MATLAB SignalCmpiler P sinut QuartusII 5 QuartusII 3 Pin sinut sinut.vhd EP1C6Q240C8 D/A 8 SinOuts 7 dwnt 0 PIO31-PIO clck clck sclrp isinctrls FPGA 5 clck Hz +/-12V D/A SinCtrl SignalTapII Simulink sinut.mdl 1 SinCtrl SinOut 2 sinut.mdl VHDL QuartusII 1 Nis Nis SOPC CPU CPU PCB Nis CPU IP SOPC Builder 11

112 SOPC Nis Nis CPU SOPC Builder QuartusII Nis CPU Altera IP Cre Nis IP Cre VHDL Verilg Nis SOPC Builder SDK Nis CPU SDK SOPC Builder SDK NIOS C C++ Nis 2 Nis Nis SOPC Nis 1 SOPC QuartusII Prject 3 New Prject Wizard :d:\myprj nis_dvp Cyclne EP1C6Q240C8 QuartusII SOPC SOPC SOPC Builder QuartusII Tls SOPC Builder QuartusII SOPC SOPC Builder 5-2 SOPC Builder SOPC Builder Creat New System 5-2 SOPC SOPC Builder HDL SOPC nis32 VHDL OK SOPC Builder 5-3 SOPC Builder Nis SOPC Builder SOPC Builder Cyclne 50MHz 5-1 Nis 5-2 SOPC 12

113 FPGA 5-3 SOPC Builder 5-4 SOPC 2 SOPC SOPC FPGA 5-4 FPGA FPGA Nis CPU Cre SOPC Builder FPGA 5-4 SOPC Nis FPGA Nis CPU Nis Bt ROM UART RS232 Avln PIO Nis FPGA RS232 SRAM Flash ROM 3 Nis CPU Cre CPU SOPC Builder Avaln Mdules Nis Prcessrr Add New Nis Prcessr Nis ( 5-5) Nis CPU Nis CPU Nis CPU CPU Nis-32 Cnfiguratin Optin Standard Debug/Average LE usage Cnfiguratin OptinsEnable Advanced Cnfiguratin Cntrls CPU Next Debug Enable Nis OCI Debug mdule Finish Nis CPU Cre SOPC Builder nis_0 CPU Cre SOPC Nis Avaln Master CPU nis_0 nis_0 Rename cpu 4 bt_mnitr_rm CPU Bt ROM SOPC Bt ROM Bt ROM GERMS Mnitr Nis CPU Memry On-Chip Memry 5-7 Memry Type ROM read-nly Data Width bits Size 2KB Next Bt ROM ( 5-8) GERMS Mnitr GERMS Mnitr Nis bt_rm UART UART SOPC Nis Cmmunicatin UART RS232 series prt Finish uart Nis

114 5-7 Bt ROM 5-8 Bt ROM 5 Timer Others Interval Timer SOPC Finish Timer Buttn PIO PIO PIO I/O Others PIO 4 4 Input Next ( 5-10) IRQ 5-11 Finish buttn_pi 7 Led PIO LED PIO Others PIO 8 8 LED Output Finish led_pi 8 PIO 7 PIO Others PIO Output Finish seven_seg_pi 5-9 Timer 5-10 Buttn PIO 5-11 Buttn PIO 9 Avaln Nis CPU SRAM Flash Avaln Bridge Avaln Tri-State Bridge 5-13 Finish tri_state 10 SRAM FPGA SRAM GW48-SOPC Cypress Tw Cy7c1041 SRAM Finish sram1 11 Flash GW48-SOPC Avaln General Flash Flash ROM Attributes Timing nis Flash Finish general_flash Nis 12 Flash ROM Flash Flash 0x

115 5-16 general_flash1 BASE 0x general_flash1 Lck Base Address general_flash System Aut-Assign Base Addresses seven_seg_pi 5-13 Avalne tri bus 5-16 Nis 5-17 Flash ROM

116 Next 5-20 Reset Lcatin bt rm Vectr Table sram System Bt ID ID Next 5-22 SDK VHDL Generate SOPC Builder Nis SOPC cpu_sdk SOPC QuartusII HDL SOPC ID 4 Nis 5-22 Nis Nis Exit Nis File New 5-24 Blck Diagram/Schematic File 5-25 Insert Symbl Nis 5-26 Prject nis32 OK Nis 5-27 nis_dvp Prject Fcus t Current Entity / / 100 nis_practice_mdelm0a Nis

117 M0A Nis Nis 5-26 Nis 5-27 Nis 5-28 Nis 5-29 Nis FPGA 17

118 1 SOPC QuartusII Nis SOPC SOF JTAG FPGA GW48-SOPC 5 Nis SDK shell 5-32 Windws Altera Nis3.02 Nis SDK Shell, 5-33 nr -t -r FPGA Nis RS232 8 Nis 5-33 nis ID FPGA Nis Nis SDK shell src 5-34 d/nis_practice_mdel/cpu_sdk/src nb -d hell_wrld.c C hell_wrld.c nd hell_wrld.srec Nis C SDK shell 5-32 Nis SDK shell 5-33 Nis SDK shell 5-34 nb -d hell_wrld.c

119 Nis

120 uart_isr_test uart_isr_test ATT1T2T3T4< > AT ASCII 4 AT AT?< > AT AT? 1 ATOK< > ATOK 2 ATT1T2T3T4< > AT ASCII 4 AT MC35i GSM SMS 2 SOPC GSM MC35i GSM SMS 8-14 AT Cmmand Set 3 GSM AT AT Cmmand Nis MC35i AT<CR> MC35i <CR> \r 0x0d MC35i Nis OK<CR><LF><CR><LF> MC35i Nis MC35i ATE0<CR> MC35i Nis OK<CR><LF><CR><LF> Nis MC35i AT+CMGF=1 Text MC35i Nis OK<CR><LF><CR><LF> Nis MC35i AT+CMGW= <CR> MC35i Nis <CR><LF>> MC35i Nis MC35i Abcd1234<Ctrl+Z> Ctrl+Z MC35i Nis OK<CR><LF><CR><LF> Nis MC35i AT+CMGL= REC UNREAD <CR> SIM MC35i Nis Nis MC35i AT+CMGR=<INDEX><CR> <INDEX> MC35i Nis +CMGR:<stat>,<a>,[<alpha>],<scts> [,<ta>,<f>,<pid>,<dcs>,<sca>,<tsca>,<length>]<cr ><LF><data> OK<CR><LF><CR><LF> <data> 4 Nis PIO Nis 20

121 SIEMENS MC35i GPRS/GSM RXD TXD CTS RTS UART SIM Nis System Cyclne 1C SMS 1 Nis 2 Nis LED LCD LCD s0 s1 s0 s1 main() /* LCD */ /* ex_09_03_1.c */ 21

122 #include <excalibur.h> // static np_pi *pi = na_buttn_pi; // static np_timer *timer = na_timer1; // cnst lng ntimerperid = nasys_clck_freq / 100; // 10 static lng ntimercunt = 0; // 0.01 cnst lng MAX_COUNT = 3600 * 24 * 100; // 0.01 static int nbuttns = 0x000F; // static char strtime[16]; // // vid buttn_isr(int cntext); // vid timer_isr(int cntext); // vid start_timer(vid); // vid pause_timer(vid); // vid shw_time(vid); // // main int main(vid) { // LCD nr_pi_lcdinit(na_lcd_pi); // GW_SOPC // nr_installuserisr(na_buttn_pi_irq, buttn_isr, (lng)pi); pi->np_piinterruptmask = 0x000F; // 0.01 timer->np_timerperidh = ntimerperid >> 16; timer->np_timerperidl = ntimerperid & 0xffff; // nr_installuserisr(na_timer1_irq, timer_isr, (lng)timer); // timer->np_timercntrl = np_timercntrl_cnt_mask; // timer->np_timercntrl = np_timercntrl_it_mask; // start_timer(); // ESC while (nr_rxchar()!= 27) { }; // pause_timer(); // printf("\nexit ex09_03_01.\004\n"); nr_jumptreset(); } // start_timer vid start_timer(vid) { // stp start 1 timer->np_timercntrl &= ~np_timercntrl_stp_mask; timer->np_timercntrl = np_timercntrl_start_mask; } // pause_timer vid pause_timer(vid) { // start stp 1 timer->np_timercntrl &= ~np_timercntrl_start_mask; timer->np_timercntrl = np_timercntrl_stp_mask; } // shw_time LCD vid shw_time(vid) { int i; sprintf(strtime, "%02d:%02d:%02d.%02d", (ntimercunt / ) % 24, (ntimercunt / 6000) % 60, 22

123 (ntimercunt / 100) % 60, ntimercunt % 100); // LCD nr_pi_lcdwritescreen(strtime); // GW_SOPC // fr (i = 0; i < 16; ++i) printf("\b"); printf("%s", strtime); } // buttn_isr vid buttn_isr(int cntext) { // if (nbuttns!= pi->np_pidata & 0x000F) { // SW0 if (~(pi->np_pidata) & 0x0001) { pause_timer(); ntimercunt = 0; // shw_time(); } // SW1 if (~(pi->np_pidata) & 0x0002) { // if (timer->np_timercntrl & np_timercntrl_stp_mask) start_timer(); else pause_timer(); } // nbuttns nbuttns = pi->np_pidata & 0x000F; // nr_delay(10); } } // timer_isr vid timer_isr(int cntext) { np_timer *timert = (np_timer *)cntext; // // ntimercunt++; // if ( ntimercunt >= MAX_COUNT ) { // ntimercunt = 0; pause_timer(); } // shw_time(); // timert->np_timerstatus = 0; } s2 s3 s2 s3 LCD LED 99 5 Nis VHDL Nis standard_32 Nis

124 1 Avaln Slave PWM 2 Avaln Avaln Slave SOPC 3 Avaln PWM SOPC Builder Nis PWM 4 PWM Avaln Slave PWM PWM Avaln 1 Avaln 2 Avaln Avaln Slave SOPC Builder Avaln SOPC Builder Nis GW-SOPC GW-SOPC LED a b LED D1 D8 D8 D7 c. 3 D1 D2 D3 D4 d LED D5 1 e. 3 GW-SOPC seg_shw_bcd VGA VGA VGA 24

125 DMA 3 VGA draw_pixel draw_asc draw_hz draw_str 4 a uart_isr_test -equ equ =56 b. PS/2 VHDL PS/2 NIOS a 11-2 VGA -clr -clr< > VGA -equ -equ < equ12+34 > -h -h< > -equ < > -equ -equ h < > VGA Nis FIFO MATLAB Nis FFT SOPC SOPC 6-17 SOPC GPRS 25

126 GW48 EDA/SOPC ( ) a GW48 b FPGA FPGA FPGA I/O I/O c PIO60 PIO62 PIO64 PIO66 PIO CON1 PIO61 PIO63 PIO65 PIO67 PIO77 TCK +12V TDO -12V TMS SEL0 nsta SEL1 TDI 1.8V PIO0 3.3V 2.5V PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO7 PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO16 PIO17 PIO18 PIO19 PIO20 PIO21 PIO22 PIO23 PIO24 PIO25 GND VCC PIO68 PIO70 PIO72 PIO74 PIO78 CON2 PIO69 PIO71 PIO73 PIO75 PIO79 VCC GND CLOCK9 CLOCK5 SPEAKER CLOCK2 CLOCK0 PIO48 PIO46 PIO44 PIO42 PIO40 PIO38 PIO36 PIO34 PIO32 PIO30 PIO28 PIO26 PIO49 PIO47 PIO45 PIO43 PIO41 PIO39 PIO37 PIO35 PIO33 PIO31 PIO29 PIO TCK TDO TMS nsta TDI DCLK CONF_DONE nconfig DATA0 ASDO ByteBlast(MV) ByteBlast II ByteBlasterMV Cyclne 10 ByteBlasterMV 10 GWDVP-B ByteBlasterMV CPLD/FPGA isp 89S51 1 ByteBlasterII Cyclne AS EPCS4 EPCS1 (5) CPLD/FPGA 5V 3.3V 2.5V 1.8V 1.5V 1 GW48-PK2 Cyclne 26 GND SEL0 SEL1 GND VCCIO nce ncso GND