EDAKONXIN.PDF

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2 - 1 - ispexpert/synario EDA/VHDL GWDD6-C

3 a b GW48-CK GW48-CK EDA EDA README.TXT c d e f DAC0832 -/+12V 1-2

4 - 1 - BL7 BL7 BL6 GWDVP GW48 J3A J3B FPGA/CPLD 1 5V FPGA CPLD 2 5V FPGA/CPLD EP1K30/50/100 EPF10K30E 2.5V ByteBlasterMV (4) FPGA/CPLD GW48 5V JV2 2.5V 1.8V BL1 BL2 BL3 BL4 BL5 isplsi isplsi BL7

5 J4 50M J FUSE +5V GND D8 D7 D6 D5 D4 D3 D2 D1 S1 C38 K1 J1 JMCU JS6 J6 JVCC VGA B2 PS/2 B8 VGA B3 2 1 RS-232 J3B JVCC 3.3V(VCCIO) 5V VCC 5V VCC EP1K30/50/100 EPF10K30E/50E JVCC VCCIO JV2 J V 5V VCC ByteBlaster ByteBlasterMV SWG9 B4 J8 JV2 RS-232 JS5 2 CON2 J7 EDA CPLD/FPGA 1 CON1 KONXIN ASIC J2 SW10 SW9 Clock0 JSL AD1674/AD574 ADC0809 J11 A/D TLC549 DAC0832 A/D JP1A JP1B JP1C A/D ADCC IN0 AIN0 JP2 IN1 AIN1 D9 D10 D11 D12 D13 D14 D15 D16 ADC08031 AOUT D/A VR1 DACC A/D CXX 24CXX TLC TLV1572 JTL -12V GND +12V EEP ROM JAV D/A A/D A GW48-CK

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7 - 4 - ~ ~ 1-1 GW48-C AD574/1674 ~~~ ~ ~ ~ ~

8 - 5 - ~ ~ 5 PIO11~PIO8 PIO15~PIO12

9 - 6 - HEX PIO2 PIO3 PIO4 PIO5 PIO7 PIO6 D1 D2 D3 D4 D5 D6 D7 D8 D16 D15 D14 D13 D12 D NO.0 SPEAKER FPGA/CPLD PIO15-PIO12 PIO11-PIO8 PIO7--PIO2 HEX PIO47-PIO44 PIO43-PIO40 PIO39-PIO36 PIO35-PIO32 PIO31-PIO28 PIO27-PIO24 PIO23-PIO20 PIO19-PIO16

10 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 D8 D7 D6 D5 D4 D3 D2 D1 FPGA/CPLD PIO15 PIO14 PIO13 PIO12 PIO11 PIO10 PIO9 PIO8 PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 D9 D16 D15 D14 D13 D12 D11 D10 PIO0 SPEAKER NO.3

11 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 D8 D7 D6 PIO15 PIO14 PIO13 D5 PIO12 D4 PIO11 D3 PIO10 D2 PIO9 D1 PIO8 D16 D15 D14 D13 D12 D11 D10 D9 SPEAKER FPGA/CPLD PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO NO.5

12 PIO19-PIO16 PIO23-PIO20 PIO27-PIO24 PIO31-PIO28 PIO35-PIO32 PIO39-PIO36 D8 PIO47 D7 PIO46 D6 PIO45 D5 PIO44 D16 D15 D14 D13 D12 D11 D9 D4 PIO43 D3 PIO42 D2 PIO41 D1 PIO40 SPEAKER FPGA/CPLD PIO47-PIO40 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO NO.7

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14 D8 D7 D6 D5 D4 D3 D2 D1 D16 D15 D14 D13 D12 D11 D10 D9 ADEN ADEOC COMP DAWR COMM JP2(5/6) JP EU1 (24) (23) C ADC0809 PIO35 PIO8 FPGA/CPLD PIO23 PIO22 PIO21 PIO20 PIO19 PIO18 PIO17 PIO16 PIO8 msb lsb2-8 EOC ADD-A ADD-B ADD-C ALE ENABLE START PIO39-PIO36 PIO43-PIO40 PIO47-PIO44 PIO37 PIO38 DA0--+5 DA PIO C30 PIO33 PIO35 PIO34 750KHZA CLOCK 750KHZA 10 IN-0 IN-1 ref(+) ref(-) V 2 FIT AIN0 AIN1 0 VCC 10K VR1 NO.5A SPEAKER JP2(1/2,3/4) PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0

15 J PIO46 5 PS/2 PIO45 1 FPGA/CPLD 3 D8 D7 D6 D5 D4 D3 D2 D1 PC D16 D15 D14 D13 D12 D11 D10 D9 PIO39-PIO36 PIO43-PIO40 PIO47-PIO MHZA B4 PIO11 PIO12 PIO13 PIO14 RS EU3 SPEAKER GND P35 P34 P33 P32 X1 X2 P31 P30 RST P37 P10 P11 P12 P13 P14 P15 P16 P17 VCC PIO15 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO VCC AT89C2051 NO.5B PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO

16 D8 PIO15 D7 PIO14 D6 PIO13 D5 PIO12 D16 D15 D14 D13 D12 D11 D D4 PIO11 4 D3 PIO10 3 D2 PIO9 2 D1 PIO8 1 D9 FPGA/CPLD PIO19-PIO16 PIO23-PIO20 PIO35-PIO32 PIO43-PIO40 PIO47-PIO44 PIO15-PIO8 PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 PIO38 PIO24 PIO25 PIO26 PIO27 PIO28 PIO29 PIO30 PIO31 PIO37 COMM DA DA0--+5 JP2 JP2(9,10) DAC0832 EU2 D0 D1 D2 D3 D4 D5 D6 D7 DAWR WR FB 9 IOUT1 11 IOUT2 12 /CS WR2 XFER A GND D GND +5 VCC VREF 8 VCC 20 NO.5C 10K 102 FIT 5.1K 5.1K 7 TL082/2 R72 5.1K pFC TL082/1 3 LM COMP JP2(COMP) +5 AOUT AIN0 10K VCC

17 DACC 1K REFS 1K REFS NO.5D PIO34 PIO27 SDA SCL TEST NC NC NC PIO19 PIO17 PIO34 PIO27 GND NC NC DOUT DIN SK CS 24CXX 93CXX VCC VCC GND VCC VCC TLC549 VCC PIO30 PIO PIO28 CS DOUT CK VCC GND REF- AIN REF+ JSL PIO26 PIO24 PIO25 PIO31 VCC LOAD DACD DACC DACB DACA LDAC CLK DATA REFD REFC REFB REFA TLC5620 GND VCC REFSS VCC REFS JTL JAV PIO19 PIO18 TLV1572 PIO17 SCLK VCC FS DO AIN GND VREF PIO34 CS VCC REFSS REFIN CLK VCC PIO17 PIO34 PIO VIN- VIN+ CS DOUT GND ADC08031 VCC ADCC D1 PIO8 D2 D3 D4 D5 D6 D7 D8 PIO9 PIO10 PIO11 PIO12 PIO15 PIO14 PIO13 SPEAKER FPGA/CPLD D16 D15 D14 D13 D12 D11 D10 D9 PIO47-PIO44 PIO43-PIO40 PIO39-PIO36 PIO35-PIO32 PIO31-PIO28 PIO27-PIO24 PIO23-PIO20 PIO19-PIO16 PIO15-PIO8 PIO0 PIO1 PIO2 PIO3 PIO4 PIO5 PIO6 PIO

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19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

20 ~ ~ ~

21 JP1B GWDVP GWDVP 1 FPGA/CPLD ROM/RAM A/D DMA P3.0 P RS232 A/D D/A 3 ROM/RAM GWDVP 4053 DMA ROM/RAM FPGA/CPLD 27C512 27E512 27C256 27C128 27C64 28C64 28E FPGA/CPLD GWDVP 48

22 GWDVP FPGA/CPLD 1 isplsi1032 isplsi1048 isplsi3256 EPM7128S EPF10K10 EPF10K20 EPF10K30 EPF6016 XCS10 XC95108 FPGA/CPLD FPGA/CPLD GW48-CK EDA GW48-CK GWDVP GWDVP FPGA/CPLD GW48-CK 10 GWDVP FPGA/CPLD 12MHz 50MHz FPGA/CPLD 5 A/D ADC0832 ROM/RAM 8 6 D/A AD574 AD674 AD V +10V V 1 /10uS LM FPGA/CPLD 7 EEPROM 93C46 8 GWDVP GWDVP GWDVP PCB GWDVP1.PCB/S01 1 GWDVP GW48-CK 1 GW48-CK 10 2 GWDVP GW48-CK FPGA/CPLD GW48-CK GWDVP FPGA/CPLD GWDVP 3 GWDVP FPGA/CPLD GW48-CK 3 GW48-CK GWDVP 2 GWDVP GWDVP PCB DOS3.1 PROTEL GWDVP1.PCB GWDVP1.S01 C39=560P GWDVP EPROM 27C512 ALE 30 GWDVP ALE FPGA/CPLD CLOCK5 6 7 GWDVP CON2 CK3 GWDVP GWDVP.ASM BCD 2 2 BCD 60H GWDVP1.ASM

23 1 DIRR0 2 KKEYI P1 8 ACC ACC P1 ACC=3 P1.3 3 NL0 4 PROSD P3.5 1Hz 500KHz 7 Hz 5 DIVD1 2N 2 1N 30H 31H N=3 6 4AH 4BH 4CH 4DH 4EH 4FH 3 5DH 5EH 5FH 4DH 4EH 4FH 6 ADDMB 7 N M MULNM 8 2 BCD HEXBCD2 9 MULT3 10 N BCD M 2 BCDHEX1 11 ADDS1 12 SQR1 13 EEPROM93C46 SEPRD 00H-3FH 20H EABLE 22H LCALL SEPRD 16 21H 14 EEPROM93C46 LCALL 8 XXH H 21H 20H LCALL SEPWR LCALL DISLE 3 IC AD574J IC5 S10 10V 40PIN 7 DIP IC IC81 IC IC AD CK3 NC2 JK1 JK0 NC1 JK2 JK3 IC5 12 PT DISPLAY 4 POWER GND +5V -12V +12V 12V A/D RS1 D/A +5V VCC GWDVP V

24 V -12V +12V A/D D/A HC164 74LS HC164 8 DATA P3.0 CLOCK P3.1 DIRR0 GWDVP H 15H 14H 13H 12H 11H 10H 17H 18H 0AH 1 0AH 1 10H P1 P1 8 P1 P EEPROM 93C46 P3.2 93C46 GWDVP.ASM 8 NC2 JK1 JK0 NC1 JK3 JK2 NC2 JK1 JK0 NC1 JK3 JK2 JK3 FPGA\CPLD 8 IC10 D/A IC2 IC3 IC2 0V ~ -10V FPGA/CPLD ROM/RAM ROM 9 GWDVP FPGA/CPLD PIO8-PIO P2 AD574 8 P3.4 P3.4 PIO8-PIO15 P2.0-P2.7 P3.4 PIO8-PIO15 AD574 8 DB0- DB7 P3.4 FPGA/CPLD CLOCK3 FPGA/CPLD 10 AD574 A/D 3296 AD574 VHDL 13 LM V +10V 93C46 P3.0 P3.1 KEY1 AT89C51 KEY2 GWDVP 50MHz 12MHZ KEY3 CON1 KEY4 KEY5 CD4053 CD4053 FPGA/CPLD CD4053 KEY6 27C512/62256 AD574J KEY7 CON2 KEY8 GWDVP DAC0832 DAC D1 D2 D3 D4 D5 D6 D7 D8 CD4051 CD4052

25 IC15 P P3.3 3 CK B A P3.3 A B P3.3 P3.5-6V +6V A MDU2 IC15 AD574 10V S10 B 10V AD574 C D MDU1 D E 2 50MHz 11 FPGA/CPLD 12MHz CLOCK1 CK CK1 12MHz CLOCK0 50MHz CLOCK2 CLOCK4 12MHz CK3 ALE CLOCK5 FPGA/CPLD MOVX 12 1 P3.5 CLOCK8 CLOCK OUTPUT GND 14 1 GWDVP1.ASM ASM51B.EXE GWDVP1.OBJ AT89C51/52 GWDVP1\ISPAD1\SINAD ispexpert COPY ispexpert JED GW48-CK isplsj1032e GWDVP 2 2 P 3 2 Good bad 93C46 93C AD Hz PDF ABEL-HDL ABEL-HDL ABEL-HDL ASCII

26 A z A Z 0 9 Space (). [ ] ABEL-HDL 32 ^B1011 (= ^D11) ^O17 (= ^D15) ^D9038 (= ^D9038) ^HF0D5 (= ^D61653) ASCII in 'a' in ^h61 in 'abc' in ^h ABEL-HDL.C. ( ).K. ( ) ABEL 5-1.X..Z..P..F..D. (H-L ) ASCII.U. (L-H ) 5-1 \ \ 'It\'s an example' 'It's an esample ' * 31 * * out, OUT, out ( ) INPUT1 input1 _OUT CLK clock_d. ABEL-HDL ( SYNARIO ABEL-WIN EDITOR ), ABEL-HDL ABEL DVCE DEVICE P16V8C ; DECLARE DVCE TO BE 16V8 DVCE DEVICE P16V8C ; // DECLARE DVCE TO BE 16V8 // ( SYNARIO ABEL-WIN EDITOR

27 ) ABEL-HDL 1 :, A&B, A#B,!A, A$B!, A!$B : -A A-B A+B * A*B / A/B A%B << A<<B A B >> A>>B A B : =, =!=,!= >=, >=, >, < <=, <= (=1) (=0) (2= =3)=0 ; (3<5)=0 ; , := := F := D&F F F D A:= D$(B= =C) B=C A =!D B C A=D = = 2*4/3 & c = a & b & c & d, out := in := ABEL-HDL when then else when (select = = 0) then out = in0 ; when (select= =1) then out = in1 out = a # b # c out = a out = b out = c

28 IN [A B C D E F] ABEL IN [1 0 0] IN 5 [A1, A2, A3] = 2 A1=0 A2=1 A3=0 A B := { } {THIS IS A BLOCK} {A = B#C D = [0,1]+[1,0] A = B $ C } WHEN (M == S) THEN OT1 := IN1 ; ELSE WHEN (M==T) THEN OT1 := IN2; WHEN (M == S) THEN OT2 := 1 ; ELSE WHEN (M==T) THEN OT3 := 1 ; WHEN (M == S) THEN {OT1 := IN1 ; OT2 := 1 ;} ELSE WHEN (M == T) THEN {OT1 := IN2 ; OT3 := 1 ;} : IF (HOLD) THEN S1 WITH O1 := O1.FB ; O2 := O2.FB ; ENDWITH ELSE S2 ; IF (HOLD) THEN S1 WITH {O1 := O1.FB ; O2 := O2.FB ;} ELSE S2 ; : IF (H &!RST) THEN S1 ; IF (H & ERR) THEN S2 ; IF (!H ) THEN S3 ; : [c d] = ^B01 [c d]= ^B1 IF (H ) THEN { IF (!RST) THEN S1 ; IF (ERR) THEN S2 ;} ELSE S3 ABEL-HDL ABEL ABEL OUT [Y0 Y1 Y2 Y3] OUT = [Y0..Y3] ; AA = [0, C1, C2, Q15.. Q0] ABEL-HDL ABEL

29 ABEL-HDL ABEL ABEL // Title ABEL3.0 Declarations // module mux1 flag ' -r3 ' title ' 12to4 multiplexer ' U1 device 'P16V8C' ; a0..a3 b0..b3 s1 s0 pin y0..y3 c0 c1 c2 c3 pin H=[ ] L=[ ] X=[.x..x..x..x.] sel=[s1 s0] y=[y3..y0] a=[a3..a0] b=[b3..b0] c=[c3..c0] equations when (sel= =0 ) then y = a when (sel= =1) then y = b ; when (sel= =2) then y = c when (sel= =3) then y = c ; end mux1 test_vectors ([sel a b c ] > y ) [0 1 X X ] > 1 ; [0 10 H L ] > 10 ; [0 5 H L] > 5 ; [1 H 3 H] > 3 ; A B C module mux12to4 mux12ot4 module module END 2 flag ' -r3 ' -r3 flag -r t -r ispexpert/synario ABEL-WIN SYNARIO 3 Title ' 12to4 multipexer ' title Module module_name Flag MacroDefinitions // DeviceDefinitions // PinandnodeAssignments // ArrtibuteDeclaration // ConstantDeclaretion // BooleanEquations Truthtables StateDiagrams // // // FuseDeclarations // TestVectors Endm name // //

30 U1 device ' P16R8C ' ; U1 P16V8C device U1. JED. device device ABEL.jed EXPERT/SYNARIO ABEL-WIN 5 a0..a3 b0..b3 s1 s0 pin y0..y3 c0 c1 c2 c3 pin pin [! ] [,[! ] ]... pin [ = ' ' ] [ [ = ' ']... [ ] '! ' istype ISTYPE istype [ ] istype '[ ] ' pos reg_d D neg reg_t T eqn reg_jk jk com reg_jkd JK/D reg feed-reg feed-or pin share pos neg reg neg reg_ ( ) latch feed-pin feed-reg feed-or pin eqn fuse 6 H = [ ] L = [ ] X = [.x..x..x..x.] sel = [s1 s0] y = [y3..y0] a = [a3..a0] b = [b3..b0] c = [c3..c0] 7 equations equations EQUATIONS TRUTH_TABLES FUSES STATE_DIAGRAMS XOR_FACTORS test_vectors ( [ sel a b c ] y ) [ 0 1 X X ] 1 [ 0 10 H L ] 0 [ 0 5 H L ] 5 [ 3 H H 0 ] 0

31 8-28 -, ispexpert\synario 9 end mux1 module

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33 TRUTH_TABEL [ IN ]( ) TRUTH_TABEL [ IN ]( : ) TRUTH_TABEL [ IN ]( : ) > 4 :> [ ]

34 CASE ENDCASE WITH_ENDWITH CASE ^H01 CASE ^ CASE ^ CASE CASE in = =0 : 1 in = = 1 : 2 in= = 2 : 3 in= = 3 : 0

35 ES fuses fuses fuses [ IN ] fuses fuses [ ] ' V 4/0 ' fuses [ ] ' 1999 ' ES GAL16V8 ES GAL20V8 ES GAL

36 with_endwith with( ) [ ] endwith with_endwith CASE A B GOTO 4 WITH OUT_1 1 OUT_2 0 ENDWITH A B 4 OUT_1 1 OUT_2 0

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39 S / PDF ispexpert PDF EDA ispexpert, isplsi Expert WINDOWS98 ispexpert ) 10-1E

40 - 37-2) USER OK D USER D:\ISPDEMO\ WORK 3) COUNT10.SYN New.syn Unitiled ispxxxx 4) Untitled Title COUNT PROJECT( ) OK EDA isplsi1032e Choose Device ( 10-3E) EDA ABEL-HDL 10-2E EXPERT

41 - 38-2) + - 3) Sheet Add New Block Symbol New Block Symbol ( 10-6) Block Name CNT10, Tab Input Pins ( ) EN CLR CLK Tab Output Pins CAO Q3 Q2 Q1 Q0 Run ) Add Wire /

42 - 39-5) Add Symbol..., ( 10-7) 1 MISC 2 3 GATES.LIB 4 6 IOPADS.LIB 5 MUXES.LIB REGS.LIB 7 [Local] IOPADS.LIB G_INPUT G_INPUT CLK G_OUTPUT ( 10-7) EN CLR Edit Delete Edit Undo Move Ctrl R Edit Move 6) Add Net Name Net Name-Enter Name = VCC VCC EN EN GND CLR CLR CLR EN( ) CLR( ) 7) Add Net Name CK CLK IOPAD G_INPUT COUT QQ3 QQ2 QQ1 QQ0 8) Add Marker Input CK ( ) Mark MAR... Output Marker 10-8 File Save 10-8

43 - 40-9) (Attributes) Lock Pad ( G_INPUT G_OUPUT ) Marker Marker ISP ISP Pad ror Report 11) Add Symbol... MISC Dataio Add Text Text-Enter Text = AO, C. Synario/Expert Project Navigato Options All Schematic INI editor Controls Sheet Sizes Sheet D Word Edit Copy Image ( ) Windows Word ABEL-HDL COUNT10.SCH CNT10? CNT10 ABEL-HDL 1) CNT New Source ABEL-HDL Module OK New ABEL-HDL Source Module CNT10 File CNT10 OK CNT10 Module ABEL 2) Text Editor ABEL 10 (ABEL )

44 MODULE CNT10 EN CLK CLR PIN // EN CLR. CAO PIN ISTYPE COM // Q3.. Q0 PIN ISTYPE REG //. COUNT = [Q3..Q0] // ---DECLARATIONS EQUATIONS COUNT.CLK = CLK // CAO = Q0 &!Q1 &!Q2 & Q3 // WHEN (COUNT >= 9 ) THEN COUNT : = 0 ELSE COUNT : = COUNT.FB + 1 END ABEL-HDL *.abl File Insert Insert File *.abl ABEL isplsi1032e-70lj84 MODULE CNT10 EN CLK CLR PIN // EN CLR. CAO PIN 34 ISTYPE COM ; // Q3..Q0 PIN ISTYPE REG //. COUNT = [Q3..Q0] // ---DECLARATIONS EQUATIONS COUNT.CLK = CLK // CAO = Q0 &!Q1 &!Q2 & Q3 // WHEN (COUNT >= 9 ) THEN COUNT : = 0 ELSE COUNT : = COUNT.FB + 1 END 3) COUNT := (COUNT.FB + 1)&(COUNT < 9 ) CAO =...!CAO=...? ) (Simulation Test Vectors) ( 10-10) ( isplsi1032e-70lj84) Source New New Source ABEL Test Vectors OK New File COUNT OK 2) 10-11S SYNARIO

45 File Save File Exit 3) MODULE CNT10 A ABEL-HDL *.abl CK COUT QQ3..QQ0 PIN ; OUT1 = [COUT QQ3..QQ0] ; B TEST_VECTORS ( CK > [ OUT1]) Marker Net 36 {.C. > [.X.] ; } C END D.X..C F *.abv 1 Net Name Marker 2 4) ( ABEL ) Processes for Current Source Compile 5) count(count.sch) Processes for Current Source Reduce Schematic Logic 10-12S SYNARIO

46 - 43-6) CNT10.ABL cnt10(cnt10.abl) Reduce Logic cnt10.abl 7) Expert 8)

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48 Design 1) Fit PLD automake.log Warnings Log warnings 4) ispds+ Fitter Report warnings ISP EDA EDA EDA EDA EDA CPLD FPGA 1 EDA ISP EDA 2 isp Download System LSC ISP Daisy Chain Download Version ISP JED 3 Configuration Scan Board( ) Scan

49 ISP Browse ( 10-19) JED count10.jed OK( ) Command Run Operation ( ) JED ISP PASS EDA EDA GW48 isplsi1032e GW48 GW Project Navigator count.sch CNT10 isp1032e GW48 NO E IO GW48 PIO 1032E IO GW48 PIO CK QQ0 QQ1 QQ2 QQ3 COUT 33(IO7 80(IO44) 81(IO45) 82(IO46) 83(IO47) 34(IO8) 2 Fit Design ( Fit Design Properties Defaults) 3 GW48 5 GW48 NO.5 8 ISP1032 IO7 1032E (BCD ) D1 9 ( ) 4 cnt10.abl XCOPY ISPDEMO ISPLSI 1 GW48 EDA \ 2 3 WINDOWS EXPERT 4 DOWNLOAD JED GW48 5 GW48 6 EXPERT GW48 XCOPY 11-1

50 EDA ISPLSI1032E P 13-1 P E XCS05 3 P51 29 PIO ISPDEMO ABCD NO.6 7 ( ) 5 a b c y z a b 8 D15 NO a b c d e f g C ^HB MODULE ABCCNT CLK PIN; G, F, E, D, C, B, A PIN ISTYPE 'REG' ; EQUATIONS COUNT.CLK = CLK ; STATE_DIAGRAM [ G, F, E, D, C, B, A ] STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; STATE ^B : GOTO ^B ; END MODULE ADD6 A4..A1, B4..B1, C0 PIN; C1, S4..S1 PIN ISTYPE 'COM '; AA = [ 0,A4..A1] ; BB = [ 0,B4..B1] ;

51 CC = [ 0, 0, 0, 0, 0 ] ; SS = [C1, S4..S1] ; EQUATIONS SS = AA + BB + CC ; END ISPDEMO ADDC NO.1 NO A B CC1 D8 8 CC0 CC0= SHIFT P41 A8 P40 A7 P39 A6 P38 A5 P37 A4 QQ P36 A3 P35 A2 P34 A1 CLK LOAD I_40 I_39 I_43 EN CCLK CLOK EAL I_37 SHIFTL Q16 Q15 8 Q14 P33 P32 B8 B7 Q13 Q12 P31 B6 Q11 P30 B5 Q10 P29 B4 Q9 P28 B3 Q8 P27 B2 Q7 P26 B1 Q6 CLK LOAD Q5 Q4 Q3 Q2 Q1 I_42 CLK0 4 ENABLE 49 6 CLOKK 16 ANDL AND BB16 BB15 BB14 BB13 BB12 BB11 BB10 BB9 O16 O15 O14 O13 O12 O11 O10 O9 O8 BB8 O7 BB7 O6 BB6 O5 BB5 O4 BB4 O3 BB3 O2 BB2 O1 BB1 I_38 ADD A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 B16 S16 S15 S14 S13 S12 S11 S10 S9 S8 B15 S7 B14 S6 B13 S5 B12 S4 B11 S3 B10 S2 B9 S1 B8 B7 B6 B5 B4 B3 B2 B1 I_ LATCH16 D16 D15 D14 Q16 Q15 D13 Q14 D12 Q13 D11 Q12 D10 Q11 D9 Q10 D8 Q9 D7 Q8 D6 Q7 D5 Q6 D4 Q5 D3 Q4 D2 Q3 D1 Q2 CLK Q1 CLR I_3 P60 P59 P58 P57 P56 P55 P54 P53 P52 P51 P50 P49 P48 P47 P46 P45 16 NO ISPDEMO MULTI NO ( 2 1) ( 4 3) 3 ISP1031E CLK0(PIN 6) 1HZ 16HZ 16384HZ 4 8

52 ABEL Moore 11-4 A B 11-4 MODULE CHK title 'SERIAL NUMBER CHECKER' DIN,CLK,CLR,D7..D0 PIN ; Q3,Q2,Q1,Q0 NODE ISTYPE 'REG'; AB3..AB0 PIN ISTYPE 'COM' ; SS = [Q3,Q2,Q1,Q0] ; AB = [AB3..AB0] ; EQUATIONS SS.CLK = CLK ; SS.CLR= CLR ; STATE_DIAGRAM SS STATE 0 : AB=^HB ; IF (DIN == D7) THEN 1 ELSE 0 ; STATE 1 : AB=^HB ; IF (DIN == D6) THEN 2 ELSE 0 ; STATE 2 : AB=^HB ; IF (DIN == D5) THEN 3 ELSE 0 ; STATE 3 : AB=^HB ; IF (DIN == D4) THEN 4 ELSE 0 ; STATE 4 : AB=^HB ; IF (DIN == D3) THEN 5 ELSE 0 ; STATE 5 : AB=^HB ; IF (DIN == D2) THEN 6 ELSE 0 ; STATE 6 : AB=^HB ; IF (DIN == D1) THEN 7 ELSE 0 ; STATE 7 : AB=^HB ; IF (DIN == D0) THEN 8 ELSE 0 ; STATE 8 : AB=^HA ; IF (DIN == 0) THEN 9 ELSE 0 ; STATE 9 : AB=^HA ; GOTO 0 ; STATE 10 : AB=^HB ; GOTO 0 ; STATE 11 : AB=^HB ; GOTO 0 ; STATE 12 : AB=^HB ; GOTO 0 ; STATE 13 : AB=^HB ; GOTO 0 ; STATE 14 : AB=^HB ; GOTO 0 ; STATE 15 : AB=^HB ; GOTO 0 ; END ISPDEMO SCHEK1 NO a

53 B 4 6(CLK) B A a 8 LD D 11-5a CNT MODULE CNT10 CLK1, LD, D7..D0 PIN; CAO PIN ISTYPE 'COM'; Q7..Q0 NODE ISTYPE 'REG'; COUNT = [ Q7..Q0 ] ; DD = [ D7..D0 ] ; EQUATIONS COUNT.CLK = CLK1 ; COUNT := (COUNT.FB + 1) &!LD # LD & DD ; CAO = (COUNT == ^HFF) ; END ISPDEMO DIVF2 NO ( 2 1) ( 4 3) F=12MHZ 6MHZ 3MHZ CLK9(12) 32(68) 50 5 CLK9 3MHZ : 11-5b A CLK CAO HALFFOUT B CLK HALF FOUT C HALF 1 HALF D FOUT D C HALF HALF FOUT E 11-5b : 11-6 MODULE CNT10 CLK1, LD, D7..D0 PIN; CAO, HALF PIN ISTYPE 'COM'; Q7..Q0 NODE ISTYPE 'REG'; COUNT = [Q7..Q0] ; DD = [D7..D0] ; EQUATIONS COUNT.CLK = CLK1 ; COUNT := (COUNT.FB + 1) &!LD # LD & DD ; CAO = (COUNT == ^HFF) ; HALF = ( COUNT == [1, D7, D6, D5, D4, D3, D2,D1] ) ; END

54 EDA/VHDL 2.1 VHDL a b s 2-1 LIBRARY IEEE; y IEEE USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS mux21 PORT ( a b : IN STD_LOGIC; s 0 y a s 1 PORT s : IN STD_LOGIC; y b y : OUT STD_LOGIC ); END ENTITY mux21; mux21 ARCHITECTURE one OF mux21 IS VHDL, BEGIN 2 1 y <= a WHEN s = '0' ELSE b WHEN s = '1' ; END ARCHITECTURE one; mux21 VHDL VHDL EDIF ALTERA EPM7128S 2-1 EPM7128S HARDWARE DEBUG EDA MUX+PLUSII( 12 ) VHDL mux21 4 a b s y MUX+PLUSII 2-1 FPGA CPLD mux VHDL VHDL (1) (LIBRARY) IEEE STD_LOGIC_1164 VHDL VHDL (2) (ENTITY) mux21 mux21 a b s y PORT mux21 PORT IN a b

55 a b OUT y a b s y IEEE STD_LOGIC_1164 STD_LOGIC (3) (ARCHITECTURE) LIBRARY IEEE ; mux21 USE IEEE.STD_LOGIC_1164.ALL; ENTITY or22 IS PORT (a,b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or22 ARCHITECTURE fu1 OF or22 IS BEGIN c <= a OR b ; END ARCHITECTURE fu1; <= -- LIBRARY IEEE; y USE IEEE.STD_LOGIC_1164.ALL; <= a a ( ENTITY h_adder IS PORT (a b : IN STD_LOGIC; )y co, so : OUT STD_LOGIC); 2-1 END ENTITY h_adder ARCHITECTURE fh1 OF h_adder IS END ENTITY BEGIN mux21 END ARCHITECTURE so <= (a OR b)and(a NAND b); co <= NOT( a NAND b); one VHDL END ARCHITECTURE fh1; IEEE STD 1076_ LIBRARY IEEE; VHDL 87 IEEE USE IEEE.STD_LOGIC_1164.ALL; STD 1076_1987 ENTITY f_adder IS PORT (ain bin cin : IN STD_LOGIC; END mux21 cout sum : OUT STD_LOGIC ); END one END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS EDA VHDL COMPONENT h_adder VHDL'87 PORT ( a b : IN STD_LOGIC; VHDL co so : OUT STD_LOGIC); END COMPONENT VHDL 87 COMPONENT or22 PORT (a b : IN STD_LOGIC; 2-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Latch IS PORT D : IN STD_LOGIC; ENA : IN STD_LOGIC; Q : OUT STD_LOGIC ); END ENTITY Latch ARCHITECTURE one OF Latch IS SIGNAL sig_save : STD_LOGIC; BEGIN PROCESS (D, ENA) BEGIN IF ENA = '1' THEN sig_save <= D ; END IF ; Q <= sig_save ; END PROCESS ; END ARCHITECTURE one; c : OUT STD_LOGIC); END COMPONENT SIGNAL d e f : STD_LOGIC; BEGIN u1 : h_adder PORT MAP( a =>ain b =>bin co=>d so =>e); u2 : h_adder PORT MAP( a =>e b =>cin co =>f so =>sum); u3 : or22 PORT MAP(a =>d b =>f c =>cout); END ARCHITECTURE fd1 ; VHDL VHDL IEEE 2-1 VHDL

56 VHDL VHDL 2-1 VHDL VHDL VHDL VHDL HDL 2 1 VHDL 2-2 D ENA ENA Q 2-2 VHDL (1) SIGNAL SIGNAL sig_save D (2) PROCESS (D, ENA) END PROCESS D ENA (VHDL ) ENA D sig_save sig_save Q ENA sig_save Q IF_THEN VHDL IF sig_save <= D END IF IF_THEN PROCESS VHDL VHDL PROCESS(D ENA) (D ENA) D ENA ( ) ( ) VHDL VHDL VHDL ABEL COM REG

57 a b 2.2 VHDL so co h_adder f_adder 3 u1 u2 u3 2-3 VHDL 2-4 VHDL EDA, 2-3 EDA VHDL 2 f_adder VHDL or2.vhd h_adder.vhd f_adder.vhd 2-3 (1) -- VHDL -- (2) or2 or2 a b ( ) c ( ) a b c (3) h_adder fh1 2-3 ( 2-1) VHDL NAND NOT OR AND (4) VHDL f_adder ain bin cin cout sum 1 fd1 COMPONENT COMPONENT or2 h_adder 2-4

58 (5) fd1 COMPONENT END COMPONENT (Component Declaration) SIGNAL d e f PORT MAP( ) (Component Instantiation) MAP u2 h_adder a b co so e cin f sum => (6) 2-3 f_adder IEEE IEEE.STD_LOGIC_1164.ALL VHDL VHDL 2-1 H_ADDER a b so co VHDL WORK VHDL File D: ADDER 2 MAX+PLUSII File New OK File Type Graphic editor 3 Enter Symbol Symbol Libraries d: maxplu2 Symbol Files and2 or2 NAND2 not Enter Symbol Enter Symbol Symbol Name input OK 5 4 output PIN-NAME New a

59 b co so As 7 File Save D adder.gdf 8 MAX+PLUSΠ Compiler Compiler 1 File Project Name Cnt4.vhd Project Name D: File adder.gdf 2 Assign --> Device Cnt4.vhd Flex10k 12-3 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; EPF10KLC84-3 ENTITY DecL7S IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; OK END ; Compiler ARCHITECTURE one OF DecL7S IS BEGIN Start PROCESS( A ) BEGIN CASE A(3 DOWNTO 0) IS WHEN "0000" => LED7S <= " " ; -- X 3F 0 WHEN "0001" => LED7S <= " " ; -- X 06 1 Processing WHEN "0010" => LED7S <= " " ; -- X 5B 2 WHEN "0011" => LED7S <= " " ; -- X 4F 3 Fitter Settings WHEN "0100" => LED7S <= " " ; -- X 66 4 Use WHEN "0101" => LED7S <= " " ; -- X 6D 5 WHEN "0110" => LED7S <= " " ; -- X 7D 6 Quartus Fitter... WHEN "0111" => LED7S <= " " ; -- X 07 7 OK Start WHEN "1000" => LED7S <= " " ; -- X 7F 8 WHEN "1001" => LED7S <= " " ; -- X 6F 9 WHEN "1010" => LED7S <= " " ; -- X WHEN "1011" => LED7S <= " " ; -- X 7C 11 WHEN "1100" => LED7S <= " " ; -- X WHEN "1101" => LED7S <= " " ; -- X 5E 13 WHEN "1110" => LED7S <= " " ; -- X WHEN "1111" => LED7S <= " " ; -- X WHEN OTHERS => NULL ; END CASE ; END PROCESS ; END ;

60 Assign Pin / Location LIBRARY IEEE ; / Chip Node Name USE IEEE.STD_LOGIC_1164.ALL ; ENTITY CNT4 IS a Pin Type PORT ( CLK : IN STD_LOGIC ; Input a Q : BUFFER INTEGER RANGE 0 TO 15); END ; PIN ARCHITECTURE one OF CNT4 IS BEGIN 5 Add PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK = '1' b co so THEN Q <= Q + 1 ; END IF; OK 4 END PROCESS ; END ; EDA 10 NO Start 13 1 File New Waveform Editor file OK 2 Node Enter Nodes from SMF List a b co so OK 3 b 1 a OK 4 File Save adder.scf D: 5 MAX+PLUSΠ Simulator Start 14 Options 1 " MAX+PLUSΠ " Programmer OK b Hardware Setup 2 Configure Programmer ByteBlaster (MV) 3 NO.5 1 a 2 co D1 so D2 Altera MAX+plus II VHDL MAX+plus II EDA MAX+plus II VHDL Verilog EDIF MAX+plusII MAX+plusII EDIF VHDL Verilog MAX+plusII EDA Synopsys Cadence Synplicity Mentor Viewlogic Exemplar Model Technology MAX+plusII APEX20K Altera FPGA/CPLD

61 Cnt4.vhd 12-5 Cnt4.vhd 4 VHDL File New Text Editor file OK Untitled - Text Editor File Save Directories D:\MAXVS\GUIDE Verilog Cnt4 Cnt4 File Create Default Symbol MAX+plusII Cnt4 MAX+plusII 12-2 CLK PIN 23 PIO13 8 LED7S7 PIN 38 PIO23 D8 LED7S6 PIN 78 PIO46 g LED7S5 PIN 73 PIO45 f LED7S4 PIN 72 PIO44 e LED7S3 PIN 71 PIO43 d LED7S2 PIN 70 PIO42 c LED7S1 PIN 67 PIO41 b LED7S0 PIN 66 PIO40 a File Name Cnt4.vhd OK D:\MAXVS\GUIDE MAX+plusII.VHD VHDL.TDF AHDL.V 12-23

62 Cnt4.vhd Cnt Decl7s.vhd Decl7s.vhd Decl7s.vhd 1. Cnt4.vhd D:\MAXVS\GUIDE 3 TOP.GDF TOP.GDF 1 2 Cnt4.vhd Decl7s.vhd File New Graphic Editor File OK Graphic Editor Graphic Editor (1) Graphic Editor Enter Symbol Symbol Name VHDL OK Symbol Files Cnt4 Decl7s Symbol Libraries d:\maxvs\guide VHDL VHDL VHDL OK

63 Cnt4 Decl7s INPUT OUTPUT prim e:\maxplus2\max2lib\prim Symbol Files INPUT OUTPUT Symbol Name INPUT OUTPUT MAX+plusII INPUT OUTPUT (2) / / LED7S[7..0] 8 Options Line Style (3) / INPUT OUTPUT TOP.GDF CLK LED7S[7..0] LED7S[7..0] VHDL LED7S7 LED7S0 LED7S7 AHDL VHDL LED7S File Save TOP.GDF, File Name 4 TOP.GDF TOP.GDF Project File Project Set Project to Current

64 File TOP Assign Device Device Family FLEX10K Devices EPF10K10LC OK MAX+plus II Compiler START Assign Pin/Location/Chip Node Name Pin: Add LED7S[7..0] LED7S7 LED7S6 LED7S OK GW48 1 NO.6 CLK 8 LED7S7 D8 LED7S6 LED7S0 PIO46 PIO40 7,MAX+plus II Compiler VHDL Interfaces VHDL Netlist Reader Settings VHDL VHDL Assign Global Project Logic Synthesis Area TOP Optimize Speed CPLD MAX Device Synthesis Options Define Synthesis Style Style Normal Minimization Full Slow Slew Rate

65 S XOR Synthesis OK Assign Global Project Device Options Security Bit Enable JTAG Suport JTAG OK Compiler Start Fitter rpt 5 TOP MAX+plusII File New New Waveform Editor file OK Node Enter Nodes from SNF List => OK CLK 7 LED7S[7..0] Cnt4:1 Q File Save top.scf SNF CLK CLK Value CLK CLK OK OPTIONS Grid Size Simulator MAX+plusII 200ns Simulator Start errors 0 warnings File End Time 5 s OK MAX+plusII Simulator Simulator End Time 5 s

66 File Open Open Waveform Editor Files Files top.scf 0 1 X Z INV G 6 TOP ADDER4B.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; MAX+plus USE IEEE.STD_LOGIC_UNSIGNED.ALL; II ENTITY ADDER4B IS Programmer PORT ( CIN : IN STD_LOGIC ; A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Programmer S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; ( 12-30) COUT : OUT STD_LOGIC ); END ADDER4B ; FPGA ARCHITECTURE behav OF ADDER4B IS SIGNAL SINT : STD_LOGIC_VECTOR(4 DOWNTO 0) ; SIGNAL AA,BB : STD_LOGIC_VECTOR(4 DOWNTO 0) ; BEGIN AA<='0'&A ; GW48 BB<='0'&B ; SINT <= AA + BB + CIN ; 1 S <= SINT(3 DOWNTO 0) ; COUT <= SINT(4) ; END behav ; FLEX10K 10K10 Configure 10K10 Configuration Complete F 7 VHDL GDF FPGA Configure CPLD EPM7128S Program Configure CLK 42 1/2 10K10 42 Clock1 Clock1 8Hz 4Hz 2Hz 1Hz File Open Open Graphic Editor top.gdf Assign Pin/Location/Pin CLK Pin 42 Change OK MAX+plusII Compiler Start

67 OK ADDER8B.vhd MAX+plus II LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY ADDER8B IS MAX+plusII PORT ( CIN : IN STD_LOGIC ; A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; B : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; COUT : OUT STD_LOGIC ); END ADDER8B ; FLEX ISP MAX ARCHITECTURE struc OF ADDER8B IS COMPONENT ADDER4B -- ADDER4B ByteBlaster PORT ( CIN : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; ByteBlaster S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; COUT : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL CARRY_OUT: STD_LOGIC;-- 4 BEGIN U1 : ADDER4B-- 4 U1 PORT MAP(CIN=>CIN, A=>A(3 DOWNTO 0), Programmer B=>B(3 DOWNTO 0),S=>S(3 DOWNTO 0), Options COUT=>CARRY_OUT ) ; Hardware U2 : ADDER4B -- 4 U2 PORT MAP(CIN=>CARRY_OUT, A=>A(7 DOWNTO 4), Setup Hardware B=>B(7 DOWNTO 4),S=>S(7 DOWNTO 4),COUT=>COUT); Type END struc ; ByteBlaster CPLD VHDL 4 8 GW48-CK NO.1 1 A[7..0] PIO7 PIO0; B[7..0] PIO15 PIO8; S[7..0] PIO23 PIO16

68 A B PIO39 D8 8 CIN PIO49 VHDL GW48-CK EDA VHDL Hjwang@uestc.edu..cn H O CIN A[7..0] B[7..0] A[7..0] B[7..0] A[3..0] B[3..0] A[7..4] B[7..4] CIN A[3..0] B[3..0] CIN A[3..0] B[3..0] ADDER4B S[3..0] COUT ADDER4B S[3..0] COUT S[3..0] S[7..4] S[7..0] S[7..0] COUT VCCINT GNDINT MSEL0 MSEL1 TDO 45/CLKUSR /RDYnBSY INIT_DONE GNDINT VCCINT TMS ntrst nstatus /DATA1 5/DATA2 4/DATA3 3/DATA4 2/DATA5 1/DATA6 0/DATA7 VCCINT DEV_CLRn IN1 GCLCK1 IN4 DEV_OE GNDINT 49/nRS 48/nWS 47/CS 46/nCS TCK CONF_DONE nceo DATA0 DCLK nce TDI ALTERA FLEX EPF10K10LC84 84-PIN PLCC VCCINT nconfig VCCINT GNDINT IN2 GCLK2 IN3 VCCINT GNDINT ALTERA EPF10K10-PC84

69 RDYnBSY ALTERA 144-PIN TQFP 77 EPF10K30A INPUT3"CLOCK2" INPUT GCLOCK2 60 "CLOCK1" "CLOCK8" INPUT1 INPUT2 GCLOCK1 "CLOK0" "CLOCK10" "CLOCK7" "CLOCK6" VCCIO GNDIO VCCIO GNDINT GNDINT VCCINT VCCINT GNDIO VCCIO GNDIO "CLOCK5" "CLOCK4" "CLOCK3" "CLOCK9" "SPKER" EPF10K20 Total User GNDIO GNDIO GNDIO GNDIO GNDINT GNDINT GNDINT VCCIO VCCIO VCCIO VCCIO VCCINT VCCINT VCCINT VCCINT DEV_OE DEV_CLRn TMS DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 TDI nrs nws CS ncs DATA7 DATA6 nce DCLK nconfig nstatus MSEL1 MSEL0 GNDINT GNDIO INIT_DONE CLKUSR VCCINT VCCIO TDO nceo CONF_DONE TCK EP1K30/50 GND VCC /GTS1 /GTS2 /GCK1 /GCK2 /GSR VCC VCC GND TDO TCK TMS TDI XC9536PC44 XILINX GND GCK3 LATTICE 44-PIN PLCC isplsi2032/e PLSI1016/E isplsi1016/e SDI/IN0 ISPEN VCC Y GND SDO/IN SCLK/Y2 VCC Y1/RESET MODE/IN IN3 GND

70 ATMEL 84-PIN PLCC ATF1508AS EPM7160S EPM7128S EPM7096S EPM7064S ALTERA TDO IO TCK TMS TDI Note: Pin 6,39,46 and 79 are no-connect pins IN4/OE2/GCLK2 IN3/GCLRn IN2/OE1 IN1/GCLK1 VCCIO VCCIO VCCIO VCCINT VCCIO VCCIO VCCIO VCCINT on EPM7096S and EPM7160S GND GND GND GND GND GND GND GND /GCK3 9 8/GCK2 7/GCK /GTS /GTS1 59/GSR XC95108PC84 XC9572PC84 84-PIN PLCC XILINX GND VCCINT GND GND VCCINT GND GND GND VCCIO VCCIO VCCINT TMS TDO TDI TCK GWDD6-C

71 V GWDD6-C GWDD6C 10 GWDD6C +5V 3 GWL VHDL IN7 Y0 VCC GND ISPEN RESET SDI/IN IN6 GND IN5 LATTICE isplsi1032/e PLSI1032/E 84-PIN PLCC MODE/IN1 GND SDO/IN IN4 Y1 VCC GND Y2 Y3 IN3/SCLK

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