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1 論 FPGA FPGA External Step Motor Control Module 立老林年

3 立老論 VHDL VHDL 了論老了度老立老不老都度行流 VHDL 年來論了不識念

4 VHDL IEEE IEEE 年度 VHDL 不 FPGACPLD 了路利廉 FPGA 立利 VHDL ( MAXPLUS) 路 ( 利 PROTEL99SE ) 利歩

5 Abstract After IEEE enact IEEE 1076VHDL redact again at 1993The program language of VHDL can use at FPGA and CPLD chips which are different company produced this is his advantagein order to design a function formidable control circuit in a short period of timewe develop a tiny independent system with the application of low cost filed programmable gate arrays (FPGA) It is suitable for mass production, owning to the saving of software and applying of low cost FPGA This monograph is based on VHDL editing by MAXPLUSand the FPGA External Step Motor Control Module is boarding by PROTEL99SE To achieve the human-computer interface module of keyboardseven segment and step motor are interconnected

programmable gate arrays (FPGA) It is suitable for mass production, owning to the saving of software and applying of low cost FPGA This monograph is based on VHDL editing by

6 錄...i......ii.. iii 錄.. iv 錄......vi 錄.....vii FPGA 論 VHDL 路..2 VHDL 料 VHDL VHDL VHDL 路 ENTITYARCHITECTURE VHDL 料 OBJECT 連 VHDL MAX+PLUS

..4 2.2 ENTITYARCHITECTURE.5 2.3 VHDL 料 OBJECT.10 2.4 17 2.4.1.17 2.4.2 連.

7 流歩 PCB 路 Protel 99 SE 42 FPGA FPGA FPGA FPGA Scan generator 路路 FPGA 論來 68 參..69 錄..70

2.1 Scan generator...47 4.2.2 路.48 4.2.3 路.52 4.3 FPGA.54 4.3.1.54 4.3.2 57 論.

8 錄 LED 路流 (a) 歩 (b) 歩 (c) 歩 PORT 34 4 邏路 PORT 2 路邏 FPGA FPGA 路 FPGA 流...56

2-2 PORT 34 4 邏.. 49 4.2-3 路.... 50 4.2-4 PORT 2 路邏.

9 錄六

10 1.1 省略數 IC FPGA 數邏列了路路不行路更便來了 FPGA 1.2 FPGA 論力來路 (EDA)(CAD) 數路路了類更數歷切來數路離度邏 (Gate-Level) 流行 (HDL) 流路零來來力來數路理路列來 FPGA CPLD 量

11 都行不 IC 路 CPLD FPGA 都行路载說都行理年來 IC CPLD/FPGA 量數邏量 CPLD/FPGA 流量力 ASIC 來 CP 利來更 CPLD/FPGA 降 CPLD/FPGA ASIC 流都 STANDARD CELL FULLY CUSTOM ASIC 不數都 FPGA ActelAltera Xilinx Altera 1.3 VHDL 路 VHDL VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION LANGUAGE 便數路 TTL CMOS 數路不 VHDL 路不邏不路零數路 VHDL 數路 VHDL 路念數 IBM PC

12 VHDL 路省浪路更不 TTL CMOS 數路路例理不路理 VHDL VHDL 路理便了路理 VHDL 路路 ASIC FPGA VHDL IBM PC IEEE STD1076 IEEE STD1176 VHDL 路類 TTL 路路料路 ASIC 零 FPGA VHDL VHDL VHDL 數 TTL CMOS 來不更 RTLREGISTER TRANSFERLEVEL 數 REGISTER TRANSFERLEVEL 路年來路路更率更路

類 TTL 路路料路 ASIC 零 FPGA VHDL VHDL VHDL 數 TTL CMOS 來不更

13 VHDL 料 2.1 VHDL 2.1.1VHDL : 來行來理益路類 VHDL TOP-DOWN 數路數數數立立行 VHDL 路列. ASIC 路路 VHDL. 靈 VHDL 路行來更易率降便利 VHDL 更流 3. 不 VHDL 不來不路 4. 不來行不路更類邏 VHDL 路 VHDL 路了來路行 VHDL 路路路路

14 更 (Entity) 路 Entity VHDL 留 (Architecture) 路路論路來連 VHDL 路 Symbols (Package) 料了落裡 VHDL PACKAGE C (Attribute) 來料 2.2 ENTITYARCHITECTURE 1.VHDL STRUCTURE ARCHITECTURE VHDL 利料路不 VHDL 路路 WIRE

15 ENTITY IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END ; ARCHITECTURE STRUCT OF IS SIGNAL : STD_LOGIC; COMPONENT 1 PORT(X,Y:IN STD_LOGIC; END COMPONENT; Z:OUT STD_LOGIC) COMPONENT 2 PORT(J,K:IN STD_LOGIC; END COMPONENT; W:OUT STD_LOGIC)

PORT(X,Y:IN STD_LOGIC; END COMPONENT; Z:OUT STD_LOGIC)

16 路 BEGIN U0: 0 PORT MAP( ); U1: 1 PORT MAP( ); END STRUCT; COMPONENT 列 COMPONENT 連 U0U1INSTANTIATION 2. 行 BEHAVIOR ARCHITECTURE 類行利流 PROCESS 行行 CONCURRENT 行流 PROCESS 行流 PROCESSSEQUENTIAL 行流 PROCESSSIGNAL 來連流 PROCESS SEQUENTIAL 流 COMBINATION 流流流勵流 ENTITY IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END ;

行 BEHAVIOR ARCHITECTURE 類行利流 PROCESS 行行 CONCURRENT 行流 PROCESS 行流

17 ; ARCHITECTURE BEHAVIOR OF IS SIGNAL :STD_LOGIC; 行路 BEGIN PROCESS_1:PROCESS; BEGIN END PROCESS_1; PROCESS_2:PROCESS; BEGIN END PROCESS_2; END BEHAVIOR;

18 3. 料流 DATAFLOW ARCHITECTURE 料流邏邏利邏 ENTITY IS GENERIC(M:TIME:=3.ONS);---- SIGNAL :STD_LOGIC; 料流路 BEGIN C<=(A OR B) AFTER M; END DATAFLOW;

19 2.3 VHDL 料 OBJECT VHDL 料類烈路例數 VARIABL 路路 NET 路路類路路料理 VHDL 數 variablesignal 數 constant port 參數 loop varisblegenerics 都 type 1. 數 variablesingal 數流流立更流路理來路不來路列兩例料數異數數數不數數數料例 singal outputabstd_logic process(input,clk) begin if(clk event and clk= 1 ) then output <= b; b<=a a<=input;

數 variablesingal 數流流立更流路理來路不來路列兩例料數異數數數不數數數料例 singal

20 end if; end process; 例 a b input a a b b output 流 process 了兩 clk 例 a b 數路不 clk 例 signal output processs(input,clk) variable a,b:std_logic; begin if(clk event and clk= 1 )then a:=input; b:=a; output<=b; end if; end processs; 數 process process 立更若數來更列例 signal output process(input,clk) variable a,b:std_logic; begin if(clk event and clk= 1 )then output <= b;

a:=input; b:=a; output<=b; end if; end processs; 數 process process 立更若數來更列例 signal

21 b:=a; a:=input; end if; end process; 2. 數 constant 數不 constant A:std_logic_vector(0 to 7):="ZZZZZZZZ"; 3.PORT PORT PORT ENTITY port 類 1. IN 說路來 2. OUT 說路 3. INOUT 說路 INOUT INOUT Buffer 不 4. Buffer 不 INOUT ENTITY ADDER IS

22 PORT(INPUT: IN STD_LOGIC_VECTOR (0 TO 7); OUTPUT:OUT STD_LOGIC_VECTOR(0 TO 7); END ADDER; 4.GENERIC GENERIC 例 Generic( 參數 string 參數 integer) Generic Map( 參數參數, 參數參數 ) 說兩不 ENTITY ADDER IS GENERIC(SIZE:INTEGER:=8); PORT(INPUT:IN STD_LOGIC_VECTOR(0 TO 7); OUTPUT:OUT STD_LOGIC_VECTOR(0 TO 7); END ADDER; 5. 參數 loop variable 參數 loop variable 不 LOOP 1 FOR 數 in 數 to 數 LOOP END LOOP 例 FOR I in 0 to 3 LOOP

23 END LOOP 說 I 0 行 I 行 I 3 2 FOR 數 in 數 downto 數 LOOP END LOOP 例 FOR K in 10 downto 0 LOOP END LOOP 說 K 10 行 K 1 行 K 0 WHILE LOOP END LOOP 說 While Loop 行 FOR I IN 0 TO 5 LOOP A(I)<=B(I);

24 END LOOP LOOP 參數 I 行 6 六路 6.IF IF IF 1 IF THEN END IF 說立行 2 IF THEN A ELSE B END IF 說立 A 行行 B 3 IF 1 THEN A ELSEIF 2 B ELSEIF 3 C

25 ELSE D END IF 說 1 立行 A 2 立行 B 類 7.WAIT WAIT 1 WAIT FOR 度說來度行不 MAX+PLUS10.1 不 2 WAIT ON 列說 PROCESS 來列便行 PROCESS 3 WAIT UNTIL 說立行 PROCESS 4 WAIT 說

26 PROCESS 來 PROCESS 行 3 8. 零 (Package) 零數料零路不裡不了 2.4 路連若數路說連來路流路若路路路不易行 component port( 1 1 料料 2 料 )

27 end component; architecture of is begin end ; VHDL 來行行了數料不便讀連行路連狀行句兩 port map( 1 1, 2 2,

28 ) 說不狀 port map( 1, 2,) 說 1 連 2 連類來路流路來例路 A BCF G 路 B D E 路 C E H A B C F G D E E H

29 2.5 VHDL MAX+PLUS :Altera MAX+PLUS Max+Plus II 10.0 BASELINE ; 連錄錄句說都 (third party) Max+Plus II 邏路不 :File -> Project -> Name

30 VHDL :File -> New -> Text Editor

31 -> ->

32 -> 路 :MAX+plusII -> Floorplan Editor

33 : FPGA : <>

34 programmer

35 POF

36 Program --->

37 來說利 LED 列 IC 7447/7448 便數不都若更數 IC 更路路率利理來念度 1/16 留度便立了了利了理利留理度度了不省了 IC 量更省不率更率兩 LED 路

38 3.1-1 LED 路 1~9 數 abcdefgp 不 1 LED 六六六 NUM a b c d e f g

40 FPGA 六 sel0 sel1 sel2 sel3 sel4 sel5 FPGA IC 說見數見類類 ()()() 論類不立兩論列列 4 行 16 I/O 路省量立來路列行 INT

41 來列例行 1 列 1 行 1111 了 1110 INT 0 了 1 利 INT 來立列利理來流了念利 VHDL 來 4 4 數數數數 0 理不理流率數數流

42 3-2.3 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY KEYBOARD IS PORT( CLK:IN STD_LOGIC; AI:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); P:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); SP:OUT STD_LOGIC); END KEYBOARD; ARCHITECTURE KEY OF KEYBOARD IS SIGNAL F:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL F_HZ:STD_LOGIC; SIGNAL OSC:STD_LOGIC; SIGNAL OSC1:STD_LOGIC; SIGNAL C:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CODE:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL BCD:STD_LOGIC_VECTOR(23 DOWNTO 0); SIGNAL SUM:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; SIGNAL SPO:STD_LOGIC;

43 BEGIN P(5 DOWNTO 0)<=F(5 DOWNTO 0); CO(3 DOWNTO 0)<=C(3 DOWNTO 0); A(3 DOWNTO 0)<=AI(3 DOWNTO 0); SP<=SPO; ---- PROCESS(OSC) VARIABLE D_FF:STD_LOGIC_VECTOR(20 DOWNTO 0); BEGIN WAIT UNTIL CLK='1'; IF(D_FF(20 DOWNTO 0)>=2E6) THEN D_FF(20 DOWNTO 0):=" "; ELSE D_FF(20 DOWNTO 0):=D_FF+1; END IF; F_HZ<=NOT D_FF(6); OSC<=NOT D_FF(10); OSC1<=NOT D_FF(18); END PROCESS; ---- PROCESS(F_HZ,OSC,OSC1) VARIABLE B:STD_LOGIC; VARIABLE INT:STD_LOGIC; VARIABLE DATA:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE ST:STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE SEQ:STD_LOGIC_VECTOR(1 DOWNTO 0); VARIABLE SOUND:STD_LOGIC_VECTOR(1 DOWNTO 0);

44 BEGIN ---- IF(F_HZ='1' AND F_HZ'EVENT) THEN IF ST(2 DOWNTO 0)="110"THEN ST(2 DOWNTO 0):="000"; ELSE ST(2 DOWNTO 0):=ST(2 DOWNTO 0)+1; END IF; END IF; -- 列 -- IF(OSC='1' AND OSC'EVENT) THEN IF A="1111"THEN IF SEQ="11"THEN SEQ:="00"; ELSE SEQ:=SEQ+1; END IF; ELSE SEQ:=SEQ; END IF; IF(SEQ="00") THEN C(3 DOWNTO 0)<="1110"; ELSIF SEQ="01"THEN C(3 DOWNTO 0)<="1101"; ELSIF SEQ="10"THEN C(3 DOWNTO 0)<="1011"; ELSIF SEQ="11"THEN C(3 DOWNTO 0)<="0111"; END IF; END IF; IF A="1111"THEN INT:='0'; ELSE INT:='1'; END IF; -- 數 -- IF(OSC1'EVENT AND OSC1='1') THEN

45 B:=(INT AND (B AND INT)); ---- IF(B='1' AND DATA(3 DOWNTO 0)="1011") THEN BCD(23 DOWNTO 0)<=("0000" & BCD(23 DOWNTO 4));B:='0'; ---- ELSIF B='1' AND DATA(3 DOWNTO 0)="1111" THEN BCD(23 DOWNTO 0)<=" ";B:='0'; ---- ELSIF B='1' THEN BCD(23 DOWNTO 0)<=BCD(19 DOWNTO 0) & DATA(3 DOWNTO 0);B:='0'; -- 理 -- ELSIF INT='0' THEN BCD(23 DOWNTO 0)<=BCD(23 DOWNTO 0);B:='1'; END IF; END IF; -- 行列 -- SUM(1 DOWNTO 0)<=SEQ; SUM(4 DOWNTO 2)<=CODE; -- 料 -- CASE ST IS WHEN"000"=> D(3 DOWNTO 0)<=BCD(3 DOWNTO 0);F(5 DOWNTO 0)<="111110"; WHEN"001"=> D(3 DOWNTO 0)<=BCD(7 DOWNTO 4);F(5 DOWNTO 0)<="111101"; WHEN"010"=> D(3 DOWNTO 0)<=BCD(11 DOWNTO 8);F(5 DOWNTO 0)<="111011";

46 WHEN"011"=> D(3 DOWNTO 0)<=BCD(15 DOWNTO 12);F(5 DOWNTO 0)<="110111"; WHEN"100"=> D(3 DOWNTO 0)<=BCD(19 DOWNTO 16);F(5 DOWNTO 0)<="101111"; WHEN"101"=> D(3 DOWNTO 0)<=BCD(23 DOWNTO 20);F(5 DOWNTO 0)<="011111"; WHEN OTHERS=> D(3 DOWNTO 0)<="1100";F(5 DOWNTO 0)<="111111"; END CASE; -- 行 -- CASE A(3 DOWNTO 0) IS WHEN"1110"=>CODE<="100"; WHEN"1101"=>CODE<="101"; WHEN"1011"=>CODE<="110"; WHEN"0111"=>CODE<="111"; WHEN OTHERS=>CODE<="000"; END CASE; -- 行列 -- CASE SUM(4 DOWNTO 0) IS WHEN"10000"=>DATA:="0001";--0 WHEN"10001"=>DATA:="0101";--1 WHEN"10010"=>DATA:="1001";--2 WHEN"10011"=>DATA:="1100";--3 WHEN"10100"=>DATA:="0010";--4 WHEN"10101"=>DATA:="0110";--5 WHEN"10110"=>DATA:="0000";--6

47 WHEN"10111"=>DATA:="1101";--7 WHEN"11000"=>DATA:="0011";--8 WHEN"11001"=>DATA:="0111";--9 WHEN"11010"=>DATA:="1010";--A WHEN"11011"=>DATA:="1110";--B WHEN"11100"=>DATA:="0100";--C WHEN"11101"=>DATA:="1000";--D WHEN"11110"=>DATA:="1011";--E--- WHEN"11111"=>DATA:="1111";--F--- WHEN OTHERS=>DATA:=DATA; END CASE; ---- CASE D IS WHEN"0000"=>S<=" ";--0 WHEN"0001"=>S<=" ";--1 WHEN"0010"=>S<=" ";--2 WHEN"0011"=>S<=" ";--3 WHEN"0100"=>S<=" ";--4 WHEN"0101"=>S<=" ";--5 WHEN"0110"=>S<=" ";--6 WHEN"0111"=>S<=" ";--7 WHEN"1000"=>S<=" ";--8 WHEN"1001"=>S<=" ";--9 WHEN"1010"=>S<=" ";--a WHEN"1011"=>S<=" ";--b WHEN"1100"=>S<=" ";--c

48 WHEN"1101"=>S<=" ";--D WHEN"1110"=>S<=" ";--E WHEN"1111"=>S<=" ";--F WHEN OTHERS=>S<="ZZZZZZZ"; END CASE; END PROCESS; END KEY; 3-3 歩歩 (Step Motor) 利數數度數度精精來路易 2 數易精 3 度數 4 率 5 度量不累 6 易連 PCPLCFPGA 7 力 8 領力

49 3.3.3 度度 = 360 / 數數歩列 (1) 1 度 0 度 90 度 180 度 270 度流 3.3 (a) 若歩 A B A B (2) 2 度 45 度 135 度 225 度 270 度 2 流切不 A A B B 3.3 (b) 2 若 B B 2 不易歩量 2 (3) 1-2 度度說 1 2 行度 1 2 說精度

50 A B A B 3.3(a) A B A B 3.3(b)

51 A B A B 3.3(c) 3.3 歩 3.4 PCB 路 Protel 99 SE Protel PCB 99 Advanced PCB 料 100X100 路度 0.001mil 35 六 37 PCB 零料料 1 PCB 零 PCB 零數零切切不累 AUTO PLACE( 零 ) 零零零滑

52 列零零立零數 UNDO REDO 路精靈零精靈零淚更更路路行 Windows MDI 行路 - 路路 - 路狀列列 HPGL DMPL Windows

53 Protel 98 SE 流邏路 4X4 邏路路

54 ( 洞 ) Protel 精 PCB 路度拉都 PCB

55 FPGA 4.1 FPGA FPGA FPGA 歩來 0 9 數串數例 1000 來來便數 FPGA 1K IDE MAX+PLUS 10.0 Protel 99 SE

56 4.2 FPGA Scan generator FPGA CLK 利路 10MHz 數 KHz 10MHz Delay 利 10MHz 1KHz 1KHz 數 999 1Hz 10MHz 1KHz 1Hz 率利來例率 500Hz 率 10MHz 率 500Hz 利率來數 K 率 500Hz

57 FPGA 參 FPGA - 參數 742(2e6) 率 13.4KHz 路 FPGA 數狀 FPGA 數 FPGA 了六六數 ~ 了念省不率更率 4 4 FPGA 1K PORT 34 4 邏 4.2-3

58 邏

59 了路路流 FPGA FPGA VHDL 路立來度離說了路路 FPGA 來了離路路路理流 FPGA +5V 流路 +5V 流兩流連亮度不流流流立率來 4.XXX 零路 ICFT 5754SLA N3055 率 1N4002 來 5V 流 0.2A 精度 1.8 Deg/Step 2 路 FPGA 1K PORT 2 路邏路

60 路邏

61 4.2.3 路 FPGA 路 Protel 99 SE 來 FPGA 路路了路參路 4 4 路 FPGA 連路精度力路 FPGA 兩路 1 2 FPGA

62 FPGA 路

63 4.3 FPGA FPGA 1K ALTERA Corporation ALTERA FLEX 1K FPGA EP1K100QC208-1 利 FPGA FPGA 1K I/O CLK S1 112 S2 113 S3 114 S4 115 S5 116 S6 119 S7 120 S8 121 P0 122

64 P1 125 P2 126 P3 127 P4 128 P5 131 AI0 136 AI1 139 AI2 140 AI3 141 CO0 142 CO1 143 CO2 144 CO3 147 CLK COIL 0 58 COIL 1 60 COIL 2 61 COIL FPGA 流

65 率數數數數 FPGA 流

66 4.3.2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MUSIC_BOX IS PORT( CLK,DIRECTION,PHASE:IN STD_LOGIC:='0'; AI:IN STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); P:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); SP:OUT STD_LOGIC; COIL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END MUSIC_BOX; ARCHITECTURE ACTION OF MUSIC_BOX IS SIGNAL F:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL F_HZ:STD_LOGIC; SIGNAL OSC:STD_LOGIC; SIGNAL OSC1:STD_LOGIC; SIGNAL CLK_SCAN: STD_LOGIC; SIGNAL CLK2: STD_LOGIC; SIGNAL C:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CODE:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL BCD:STD_LOGIC_VECTOR(23 DOWNTO 0);

67 SIGNAL SUM:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; SIGNAL SPO:STD_LOGIC; SIGNAL IND_COIL: STD_LOGIC_VECTOR(3 DOWNTO 0):="0001"; SIGNAL SW:STD_LOGIC; SIGNAL KEY:STD_LOGIC; SIGNAL HZ:STD_LOGIC; SIGNAL COUNT:STD_LOGIC_VECTOR(23 DOWNTO 0); SIGNAL AC:STD_LOGIC; BEGIN COIL<= NOT IND_COIL; P(5 DOWNTO 0)<=F(5 DOWNTO 0); CO(3 DOWNTO 0)<=C(3 DOWNTO 0); A(3 DOWNTO 0)<=AI(3 DOWNTO 0); SP<=SPO; ---- PROCESS(OSC) VARIABLE D_FF:STD_LOGIC_VECTOR(20 DOWNTO 0); VARIABLE DELAY:STD_LOGIC_VECTOR(23 DOWNTO 0); BEGIN WAIT UNTIL CLK='1'; IF(D_FF(20 DOWNTO 0)>=2E6) THEN D_FF(20 DOWNTO 0):=" "; ELSE D_FF(20 DOWNTO 0):=D_FF+1; END IF; F_HZ<=NOT D_FF(6);

68 OSC<=NOT D_FF(10); OSC1<=NOT D_FF(18); CLK2<= NOT D_FF(20); IF DELAY>= THEN DELAY:=" ";HZ<=NOT HZ; ELSE DELAY:=DELAY+1; END IF; END PROCESS; ---- PROCESS(F_HZ,OSC,OSC1,HZ) VARIABLE B:STD_LOGIC; VARIABLE INT:STD_LOGIC; VARIABLE DATA:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE ST:STD_LOGIC_VECTOR(2 DOWNTO 0); VARIABLE SEQ:STD_LOGIC_VECTOR(1 DOWNTO 0); VARIABLE SOUND:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN ---- IF(F_HZ='1' AND F_HZ'EVENT) THEN IF ST(2 DOWNTO 0)="110"THEN ST(2 DOWNTO 0):="000"; ELSE ST(2 DOWNTO 0):=ST(2 DOWNTO 0)+1; END IF; END IF; -- 列 -- IF(OSC='1' AND OSC'EVENT) THEN

69 IF A="1111"THEN IF SEQ="11"THEN SEQ:="00"; ELSE SEQ:=SEQ+1; END IF; ELSE SEQ:=SEQ; END IF; IF(SEQ="00") THEN C(3 DOWNTO 0)<="1110"; ELSIF SEQ="01"THEN C(3 DOWNTO 0)<="1101"; ELSIF SEQ="10"THEN C(3 DOWNTO 0)<="1011"; ELSIF SEQ="11"THEN C(3 DOWNTO 0)<="0111"; END IF; END IF; IF A="1111"THEN INT:='0'; ELSE INT:='1'; END IF; -- 數 -- IF(OSC1'EVENT AND OSC1='1') THEN B:=(INT AND (B AND INT)); --KEY LOCK-- IF B='1' AND DATA(3 DOWNTO 0)="1010" THEN BCD<=BCD;B:='0';SW<=NOT SW; ---- ELSIF(SW='0' AND B='1' AND DATA(3 DOWNTO 0)="1110") THEN ---- BCD(23 DOWNTO 0)<=("0000" & BCD(23 DOWNTO 4));B:='0'; ELSIF B='1' AND DATA(3 DOWNTO 0)="1111" THEN

70 BCD(23 DOWNTO 0)<=" ";B:='0';SW<='0'; ELSIF BCD=0 AND KEY='1' THEN SW<='0';BCD<=BCD;KEY<='0';IND_COIL<="1111";AC<='0'; ELSIF SW='1' AND KEY='1' AND DATA(3 DOWNTO 0)/="1111" THEN BCD<=COUNT; ELSIF SW='1' AND DATA(3 DOWNTO 0)="1111" THEN SW<='0';BCD(23 DOWNTO 0)<=" ";KEY<='0'; ---- ELSIF SW='0' AND B='1' AND DATA(3 DOWNTO 0)="1011" AND BCD/=0 THEN B:='0';SW<='1';KEY<='1'; ELSIF SW='0' AND B='1' AND DATA(3 DOWNTO 0)="1011" AND BCD=0 THEN SW<='0';BCD<=BCD;KEY<='0';B:='0'; ---- ELSIF SW='0' AND B='1' THEN BCD(23 DOWNTO 0)<=BCD(19 DOWNTO 0) & DATA(3 DOWNTO 0);B:='0'; ELSIF INT='0' THEN BCD(23 DOWNTO 0)<=BCD(23 DOWNTO 0);B:='1'; END IF; ---- IF SW='1' AND DATA(3 DOWNTO 0)="1100" THEN AC<='1'; IF((IND_COIL="0001")OR(IND_COIL="0000")) THEN IND_COIL<="1100"; ELSE IND_COIL<=(IND_COIL(0)& IND_COIL(3 DOWNTO 1)); END IF; ELSIF SW='1' AND DATA(3 DOWNTO 0)="1101" THEN

71 AC<='1'; IF((IND_COIL="0001")OR(IND_COIL="0000")) THEN IND_COIL<="0011"; ELSE IND_COIL<=(IND_COIL(2 DOWNTO 0)& IND_COIL(3)); END IF; END IF; END IF; -- 行列 -- SUM(1 DOWNTO 0)<=SEQ; SUM(4 DOWNTO 2)<=CODE; -- 數 -- IF SW='0' THEN COUNT<=BCD; ELSE IF(HZ='1' AND HZ'EVENT)THEN IF AC='1' AND KEY='1' AND COUNT/=0 THEN ---- IF COUNT(3 DOWNTO 0)=0 AND COUNT(23 DOWNTO 4)>=1 THEN COUNT(3 DOWNTO 0)<="1001"; ELSE COUNT(3 DOWNTO 0)<=COUNT(3 DOWNTO 0)-1; END IF; ---- IF COUNT(7 DOWNTO 4)=0 AND COUNT(23 DOWNTO 8)>=1 AND COUNT(3 DOWNTO 0)=0 THEN COUNT(7 DOWNTO 4)<="1001"; ELSIF COUNT(3 DOWNTO 0)=0 AND COUNT(23 DOWNTO 4)>=1 THEN COUNT(7 DOWNTO 4)<=COUNT(7 DOWNTO 4)-1;

72 END IF; ---- IF COUNT(11 DOWNTO 8)=0 AND COUNT(23 DOWNTO 12)>=1 AND COUNT(7 DOWNTO 0)=0 THEN COUNT(11 DOWNTO 8)<="1001"; ELSIF COUNT(7 DOWNTO 0)=0 AND COUNT(23 DOWNTO 8)>=1 THEN COUNT(11 DOWNTO 8)<=COUNT(11 DOWNTO 8)-1; END IF; ---- IF COUNT(15 DOWNTO 12)=0 AND COUNT(23 DOWNTO 16)>=1 AND COUNT(11 DOWNTO 0)=0 THEN COUNT(15 DOWNTO 12)<="1001"; ELSIF COUNT(11 DOWNTO 8)=0 AND COUNT(23 DOWNTO 12)>=1 AND COUNT(7 DOWNTO 0)=0 THEN COUNT(15 DOWNTO 12)<=COUNT(15 DOWNTO 12)-1; END IF; ---- IF COUNT(19 DOWNTO 16)=0 AND COUNT(23 DOWNTO 20)>=1 AND COUNT(15 DOWNTO 0)=0 THEN COUNT(19 DOWNTO 16)<="1001"; ELSIF COUNT(15 DOWNTO 12)=0 AND COUNT(23 DOWNTO 16)>=1 ANDCOUNT(11 DOWNTO 0)=0 THEN COUNT(19 DOWNTO 16)<=COUNT(19 DOWNTO 16)-1; END IF; ---- IF COUNT(23 DOWNTO 20)=0 THEN

73 COUNT(23 DOWNTO 20)<="0000"; ELSIF COUNT(19 DOWNTO 16)=0 AND COUNT(23 DOWNTO 20)>=1 AND COUNT(15 DOWNTO 0)=0 THEN COUNT(23 DOWNTO 20)<=COUNT(23 DOWNTO 20)-1; END IF; END IF; END IF; END IF; -- 料 -- CASE ST IS WHEN"000"=> D(3 DOWNTO 0)<=BCD(3 DOWNTO 0);F(5 DOWNTO 0)<="111110"; WHEN"001"=> D(3 DOWNTO 0)<=BCD(7 DOWNTO 4);F(5 DOWNTO 0)<="111101"; WHEN"010"=> D(3 DOWNTO 0)<=BCD(11 DOWNTO 8);F(5 DOWNTO 0)<="111011"; WHEN"011"=> D(3 DOWNTO 0)<=BCD(15 DOWNTO 12);F(5 DOWNTO 0)<="110111"; WHEN"100"=> D(3 DOWNTO 0)<=BCD(19 DOWNTO 16);F(5 DOWNTO 0)<="101111"; WHEN"101"=> D(3 DOWNTO 0)<=BCD(23 DOWNTO 20);F(5 DOWNTO 0)<="011111"; WHEN OTHERS=> D(3 DOWNTO 0)<="1100";F(5 DOWNTO 0)<="111111"; END CASE; -- 行 --

74 CASE A(3 DOWNTO 0) IS WHEN"1110"=>CODE<="100"; WHEN"1101"=>CODE<="101"; WHEN"1011"=>CODE<="110"; WHEN"0111"=>CODE<="111"; WHEN OTHERS=>CODE<="000"; END CASE; -- 行列 -- CASE SUM(4 DOWNTO 0) IS WHEN"10000"=>DATA:="0001";--0 WHEN"10001"=>DATA:="0101";--1 WHEN"10010"=>DATA:="1001";--2 WHEN"10011"=>DATA:="1100";--3 WHEN"10100"=>DATA:="0010";--4 WHEN"10101"=>DATA:="0110";--5 WHEN"10110"=>DATA:="0000";--6 WHEN"10111"=>DATA:="1101";--7 WHEN"11000"=>DATA:="0011";--8 WHEN"11001"=>DATA:="0111";--9 WHEN"11010"=>DATA:="1010";--A WHEN"11011"=>DATA:="1110";--B WHEN"11100"=>DATA:="0100";--C WHEN"11101"=>DATA:="1000";--D WHEN"11110"=>DATA:="1011";--E--- WHEN"11111"=>DATA:="1111";--F--- WHEN OTHERS=>DATA:=DATA;

75 END CASE; ---- CASE D IS WHEN"0000"=>S<=" ";--0 WHEN"0001"=>S<=" ";--1 WHEN"0010"=>S<=" ";--2 WHEN"0011"=>S<=" ";--3 WHEN"0100"=>S<=" ";--4 WHEN"0101"=>S<=" ";--5 WHEN"0110"=>S<=" ";--6 WHEN"0111"=>S<=" ";--7 WHEN"1000"=>S<=" ";--8 WHEN"1001"=>S<=" ";--9 WHEN"1010"=>S<=" ";--a WHEN"1011"=>S<=" ";--b WHEN"1100"=>S<=" ";--c WHEN"1101"=>S<=" ";--D WHEN"1110"=>S<=" ";--E WHEN"1111"=>S<=" ";--F WHEN OTHERS=>S<="ZZZZZZZ"; END CASE; END PROCESS; END ACTION;

76 論 5.1 年來識都來年裡料論都 VHDL 說理都不 VHDL 都了 VHDL 率路來都不念來便了 8051 理來 4 4 來不不六來立數來六了讀理論不 VHDL MAXPLUS FPGA

77 行路 PROTEL 路路 PCB 來路 PCB 了例度洞都論路來 5.2 來來例 FPGA FPGA 省省更 LCD 狀六數數 LCD 利

78 參逸數路林林良路林益麟論論李林論論復沈數邏祿

79 錄錄 FPGA 路

80 錄 FPGA 路

81 錄 FPGA PCB 數量 24 2 connector connector 1 seven segment 6 PC N N OSC 10MHZ 2 330Ω 8 100Ω 8 10KΩ 4 4PIN 16 5V 1 JUMPER 1

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