kl5a_qv_n12m-gs_ _0900

Transcription

1 KL Intel Huron River Platform with iscrete GFX 0 FN / THERML EM0- RIII-SOIMM PG RIII-SOIMM PG Speaker PG Mic in (External MI) PG Head-Phone out ual hannel R 00/0/.V ST - H ST - -ROM US est Port 0 PG UIO OE L Int. MI PG PG PG PG R SYSTEM MEMORY PG ~ ST 0M ST 0M ST 0M IH PU Sandyridge 0. rpg FI MI ougarpoint 0. PG ~ FI PH MI MIX PI-E Graphics Interfaces PI-E US.0 PI-Express Port Mini PI-E ard (WLN/ Wimax) PGE PG ~ NM-GS INT_RT nvii INT_HMI INT_LVS Port LN Realtek (0/00&G co-lay) RTLE-V-GR PGE p MHz MHz HMI ON PG 0 RT PG L ONN PG Port US.0 VL0 PGE REGULTOR (R).VSUS, 0.VSMR_VTERM,.V.V_GPU,.V_PU REGULTOR.0V_VTT,.V / VPU, VPU, V PU ore VG ore iscrete PG PG PG PG.KHz LP Port Port Port US.0 Ports X luetooth Mini PI-E ard PG PG PG Port ard Reader RTS PGE Port PG 0 Port US PG 0 E IT -IN- ard Reader ONN PG PGE PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom LOK IGRM ate: Friday, October, 00 Sheet of

2 0 PGE ESRIPTION LOK IGRM Sandy ridge (PU) ougarpoint (PH) R IMM--RVS(.0H) 0 HMI ONN RT ONN K/, T/P Table of ontents Front Page R IMM-0-RVS(.0H) NM (GPU) L ONN LN(RTLE-V-GR) L/MI/LINE-OUT ST H/EST/-ROM ard Reader (RTS) US.0*/WLN/T US.0 or US.0 FN /THERML TO ON/LE K IT Screw Hole/EMI/ES ischarge harger (ISL) R/0.V(RT0LGQW) V/V (RT0MGQW).V (HP00RTER) GFX_ORE (OZ) 0.V (OZ).0_PH (OZ) IMVP (ISL) KL Power On Sequence E Tracking Record POWER PLNE V_RT VPU VPU V LNV V.V.0V_PH VOLTGE 0V~0V.0V~.V.V V V.V PGE,,,,,,,,,, 0,0,,0,,,,,0,,,,, 0,0,0,0,,,,,0,,,,,,,,,,,,,,,0,,,,, 0,0,0,0,0,,,, ESRIPTION MIN POWER ONTROL SIGNL VV_EN VV_EN VV_EN LN_ON V_S V,,,,, PH SUS POWER S_ON V_S.V 0,0,0,0,0,,,,,, Sys Management,PH Resume S_ON Well,Intel H udio,us,wln WiMX POWER 0.V_R_VTT V.V 0.V V.V.V.V.0V,,,,,,0,, 0,0,,, 0,0,,,,0,,,,,,,,,,,,,0, 0,0,,, Power States RT ITE0 POWER / POWER I SOURE LRGE POWER LN POWER R SOIMM REFERENE POWER SLP_S# TRL POWER SLP_S# TRL POWER LVS,NVM POWER Mini PIe,Express ard POWER SYS_PWROK MINON MINON MINON MINON MINON TIVE IN GFX_ORE 0.V~.V,, VG ORE POWER MINON S0 V_ORE 0,, PH ORE POWER PU ORE POWER LV.V L Power INT_LVS_VEN S0 T-V 0V~V MIN TTERY VRON HG_PTT S0~S S0~S S0~S S0~S S0~S S0~S S0~S S0 S0 S0 S0 S0 S0 S0 S0~S PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom Front page Friday, October, 00 ate: Sheet of

3 [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_omp Sandy ridge Processor (MI,PEG,FI) INT_eP_HP_Q ep_omp connect to PIN W:mils/S:mils/L: 00mils. ep_omp connect to PIN W:mils/S:mils/L: 00mils. G E F G F0 H E F 0 E G E0 G 0 F J J H0 J H F G E F U0 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] MI_TX[] MI_TX[] FI0_TX#[0] FI0_TX#[] FI0_TX#[] FI0_TX#[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI0_TX[0] FI0_TX[] FI0_TX[] FI0_TX[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI0_FSYN FI_FSYN FI_INT FI0_LSYN FI_LSYN ep_ompio ep_iompo ep_hp ep_ux ep_ux# ep_tx[0] ep_tx[] ep_tx[] ep_tx[] ep_tx#[0] ep_tx#[] ep_tx#[] ep_tx#[] PU-P-rPG MI Intel(R) FI ep PI EXPRESS* - GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] J J H K M L J J H H G G0 F E E J L K H H G G F F0 E E F E M M M L L K K J0 J H G E F F E M M M0 L L K0 K J J H G E F E PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN0_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXN_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP0_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_TXP_ PEG_OMP PEG_OMP connect to PIN H&J W:mils/S:mils/L: 00mils. PEG_OMP connect to PIN J W:mils/S:mils/L: 00mils. PEG_RXN[0..] [] PEG_RXP[0..] [] [,,,] PLTRST# [] [0] U N IN [] [] [,] [0] SN_IV# N. at SN ES # 0.v H_SN_IV# E_PEI H_PROHOT# PM_THRMTRIP# PM_SYN H_PWRGOO V GNOUT.0V_PH PU_PLTRST# V_S LVG0GW TP0 TP R 0.U/0V_ R R PU_PLTRST# R R R /J_ *Short N *0.U/0V_ *Short N 0K/J_ [] /J_ /J_ [,] SKTO# TP_TERR# H_PROHOT#_R PM_SYN_R H_PWRGOO_R PM_RM_PWRG_R PU_PLTRST#_R SYS_PWROK PM_RM_PWRG Sandy ridge Processor (LK,MIS,JTG) RV *EG-00 N L N L N M P V R U0 PRO_SELET# SKTO# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# PU-P-rPG R R 0/J_ *0/J_ MIS THERML PWR MNGEMENT V_S LOKS R MIS JTG & PM U 0 *0.U/0V_ *HG0GW LK LK# PLL_REF_LK PLL_REF_LK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM_RM_PWRG_Q R R K P P R R P0 R P L T R R0 T0 P R T R.V_PU R0 00/F_ R */J_ LK_PLL_SSLKP_R LK_PLL_SSLKN_R SM_ROMP_0 SM_ROMP_ SM_ROMP_ XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO XP_RST# Rb Rc LK_PU_LKP [] LK_PU_LKN [] Ra PU_RMRST# [] SM_ROMP[0] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:0mils/S:0mils/L: 00mils, SM_ROMP[] W:mils/S:0mils/L: 00mils, 0/F_ R R R R R XP_RST# [] PM_RM_PWRG_R R TP TP TP TP TP TP TP *IS@0/J_ *IS@0/J_ 0/F_./F_ 00/F_ SW@0X.0V_PH LK_PLL_SSLKP [] LK_PLL_SSLKN [] Ra Rb Rc 0 IS only SW/UM N 0 ohm 0 ohm N 0 ohm N PM_RM_PWRG_Q R0 *K/F_ Q *MEN00E MINON# [,] FI isable R0 *IS@K/F_ R0 R0 R0 R0 *IS@K/F_ *IS@0/J_ *IS@0/J_ *IS@0/J_ FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN FI_FSYN can gang all these signals together and tie them with only one K resistor to GN (G V0. h..). PEG x (UM Non-stuff) PEG_TXP[0..] [] PEG_TXP0_ IS@0.U/0V_ PEG_TXP0 PEG_TXN0_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP0_ IS@0.U/0V_ PEG_TXP0 PEG_TXN0_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ 0 IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ PEG_TXP_ IS@0.U/0V_ PEG_TXP PEG_TXN_ 0 IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ IS@0.U/0V_ PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN[0..] [] P & PEG ompensation.0v_ph.0v_ph.0v_ph R0./F_ PEG_OMP PEG_IOMPI and ROMPO signals should be routed within 00 mils typical impedance = mohms PEG_IOMPO signals should be routed within 00 mils typical impedance =. mohms R R 0K_./F_ INT_eP_HP_Q ep_omp ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms Processor pull-up(pu).0v_ph H_PROHOT# R /F_ XP_TO R /J_ XP_TMS R /J_ XP_TI_R R /J_ XP_PREQ# R */J_ XP_TLK R /J_ XP_TRST# R /J_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom Sandy ridge / Friday, October, 00 ate: Sheet of

4 Sandy ridge Processor (R) 0 U0 U0 [] M Q[:0] [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q F0 F G0 G F F G G K K K J J J J K M N0 N N M0 M N M G G K K H H J J J K J K H H L L P N L M M L P N J H L K L K J H E0 F0 V E F S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] V S_LK[] S_LK#[] S_KE[] V0 RSV_TP[] RSV_TP[] RSV_TP[] W RSV_TP[] RSV_TP[] RSV_TP[] W0 S_S#[0] K S_S#[] L RSV_TP[] G RSV_TP[] H S_OT[0] H S_OT[] G G RSV_TP[] RSV_TP[0] H S_QS#[0] S_QS#[] G S_QS#[] J S_QS#[] M S_QS#[] L S_QS#[] M S_QS#[] R S_QS#[] M S_QS[0] S_QS[] F S_QS[] K N S_QS[] S_QS[] L S_QS[] M R S_QS[] S_QS[] M 0 S_M[0] W S_M[] W S_M[] S_M[] W S_M[] V V S_M[] S_M[] W W S_M[] V S_M[] W S_M[] S_M[0] V S_M[] S_M[] W S_M[] F V S_M[] S_M[] V M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M QSN[:0] [] M QSP[:0] [] M [:0] [] [] M Q[:0] [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0 G F F G G F F G J J K0 K J J0 K K M N N N M N M M M M R P N N N P P N T T P N R R R J T T H R J H T N R T T N R T R 0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] RSV_TP[] S_S#[0] S_S#[] RSV_TP[] RSV_TP[] S_OT[0] S_OT[] RSV_TP[] RSV_TP[0] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] E R E R0 T T0 E E E E F K N N P K P G J M N P K P T R T T T T R T R R T 0 R R M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M QSN[:0] [] M QSP[:0] [] M [:0] [] PU-P-rPG PU-P-rPG.V_SUS R K/F_ R *0/J_ [,] R_RMRST# R K/F_ PU_RMRST#_R PU_RMRST# [] [] RMRST_NTRL_PH R *Short N Q MEN00E 0.0U/0V_ R.K/F_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom Sandy ridge / ate: Friday, October, 00 Sheet of

5 U/.V_ 0 U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ Reserved *U/.V_ PU ore Power SN W:,(TP) uf x uf x (Non-stuff) U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ *U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0 U/.V_ 0 U/.V_ U/.V_ 0 U/.V_ Sandy ridge Processor (POWER) V_ORE G G G G G G0 G G G G F F F F F F0 F F F F Y Y Y Y Y Y0 Y Y Y Y V V V V V V0 V V V V U U U U U U0 U U U U R R R R R R0 R R R R P P P P P P0 P P P P U0F V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 POWER ORE SUPPLY SENSE LINES SVI PEG N R VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSSIO_SENSE H H0 G0 0 Y0 U0 P0 L0 J J J J H H H G G G F F F F E E E J J J0 J J J V_PH.0V_VTT_0 H_PU_SVILRT# H_PU_SVILK H_PU_SVIT PU VTT SN W:. uf x 0 uf x (Non-stuff) U/.V_ *U/.V_ *U/.V_ 0 0U/.V_ *U/.V_ VTT_SENSE [] TP uf (Reserved) *U/.V_ R R [,,] U/.V_ U/.V_ *0/short_ R0 *U/.V_ U/.V_ 0U/.V_ 00/J_ 00/J_ SMR_VREF U/.V_ 0U/.V_ *U/.V_.0V_PH PU VPL SN W:. 0uF/mohm x 0uF x uf x U/.V_ U/.V_ V_ORE V_SENSE [] VSS_SENSE [] R.V PU VGT SN W: uf x uf x (Reserved) V_GFX *0/J_ 0 U/.V_ 0 U/.V_ 0 U/.V_ *U/.V_ R0 0 0U/.V_ VR_REF_PU Ra U/.V_ 0 U/.V_ U/.V_ *U/.V_ *IS@0/J_ IS Ra 0 ohm 0 U/.V_ H_PU_SVILK H_PU_SVIT Sandy ridge Processor (GRPHI POWER) U/.V_ U/.V_ U/.V_ *U/.V_ SW N 0 U/.V_ Layout note: need routing together and LERT need between LK and T Place PU resistor close to PU.0V_PH U/.V_ U/.V_ U/.V_ *U/.V_ 0 *0U/V_ R R 0/F_ T T T T0 T T R R R R0 R R P P P P0 P P N N N N0 N N M M M M0 M M L L L L0 L L K K K K0 K K J J J J0 J J H H H H0 H H *Short N R U0G VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VXG VXG VXG VXG VXG VXG0 VXG VXG VXG VXG VPLL VPLL VPLL PU-P-rPG Place PU resistor close to PU *Short N POWER GRPHIS.V RIL.0V_PH.0V_PH SVI LK lose to VR R./F_ SVI T lose to VR R 0/F_ SENSE LINES S RIL R -.V RILS VREF MIS VXG_SENSE VSSXG_SENSE SVI LERT SM_VREF VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VS VS VS VS VS VS VS VS VS_SENSE F_ VS_VI K K L F F F Y Y Y U U U P P P M M L J J J H H H VR_SVI_LK [] H_F_ VR_SVI_T [] TP TP VR_REF_PU [] VR_REF_PU Note: VR_REF_PU should have 0 mil trace width 0U/.V_ 0 0U/.V_ 0U/.V_ R R 0K/J_ R R 0U/.V_ 0U/.V_ 0U/.V_ 0K/J_ VUS_SENSE [0] VS_SEL [0] MINON_V 00/J_ 00/J_.V_SUS V_GFX V_XG_SENSE [] VSS_XG_SENSE [] PU MH SN W: 0 0uF/mohm x 0uF x 0U/.V_ *0U/V_ 0 0U/.V_ PU S SN W: 0uF/mohm x 0uF x [,] 0 0U/.V_ U/.V_ 0.V MINON#.V_PU uf (Reserved) *0U/.V_. U/.V_ Q O 0 *0P/0V_.V_PU R0 0/J_ Q N00K 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.V_SUS / add for Intel. Placement close to PU..0V_PH PU-P-rPG MINON_V Q0 MEN00E R 00K/J_ H_PU_SVILRT# R0 /J_ R /J_ VR_SVI_LERT_L# R *Short N VR_SVI_LERT# [] PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom Sandy ridge / Friday, October, 00 ate: Sheet of

6 U0H T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T VSS T0 VSS0 T VSS T VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS0 R VSS R VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS P VSS0 P0 VSS P VSS P VSS P VSS N0 VSS N VSS N VSS N VSS N VSS N VSS0 N VSS N0 VSS N VSS N VSS M VSS M VSS M VSS M VSS M VSS M VSS0 M0 VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L VSS L0 VSS L VSS L VSS L VSS K VSS K0 VSS0 K VSS K VSS K VSS K VSS K VSS K VSS K0 VSS K VSS K VSS J VSS0 Sandy ridge Processor (GN) VSS U0I VSS J VSS J VSS J T VSS VSS J T VSS VSS J0 T VSS VSS J T VSS VSS J T VSS VSS J T0 VSS VSS J T VSS VSS0 J T VSS VSS H T VSS VSS H T VSS0 VSS H P VSS VSS H0 P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H P VSS VSS H N VSS VSS00 H N VSS VSS0 H N VSS VSS0 H N VSS0 VSS0 H N VSS VSS0 G N0 VSS VSS0 G N VSS VSS0 G N VSS VSS0 F N VSS VSS0 F N VSS VSS0 F M VSS VSS0 F L VSS VSS E L0 VSS VSS E L VSS0 VSS E L VSS VSS E L VSS VSS E L VSS VSS E0 L VSS VSS E L VSS VSS E L VSS VSS E L VSS VSS0 E L VSS VSS E K VSS VSS K VSS00 VSS K VSS0 VSS K VSS0 VSS J VSS0 VSS J VSS0 VSS H VSS0 VSS H0 VSS0 VSS H VSS0 VSS0 H VSS0 VSS H VSS0 VSS H VSS0 VSS H VSS VSS 0 H VSS VSS H0 VSS VSS H VSS VSS H VSS VSS H VSS VSS Y H VSS VSS0 Y H VSS VSS Y H VSS VSS Y H VSS0 VSS Y H VSS VSS Y H VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS W G VSS VSS0 W0 G0 VSS VSS W G VSS VSS W G VSS0 VSS W F VSS VSS W F VSS VSS U F VSS VSS U VSS U VSS U VSS U VSS0 U VSS VSS F VSS F VSS E0 VSS E VSS E VSS E VSS0 E VSS E VSS E VSS E0 VSS E VSS E VSS E VSS E VSS E VSS E VSS0 E VSS E VSS E VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS [] SMR_VREF_Q0_M [] SMR_VREF_Q_M TP TP TP FG0 FG FG FG FG FG SMR_VREF_Q0_M SMR_VREF_Q_M Sandy ridge Processor (RESERVE, FG) R *K/J_ dd for Pre-ES TP R *K/J_ U0E K FG[0] K FG[] L FG[] L FG[] K FG[] L FG[] L0 FG[] M FG[] M FG[] M0 FG[] M FG[0] M FG[] N FG[] N FG[] N FG[] M FG[] K FG[] N FG[] J VXG_VL_SENSE H VSSXG_VL_SENSE J V_VL_SENSE H VSS_VL_SENSE J RSV RSV F RSV F RSV F RSV0 RSV G RSV G RSV E RSV RSV 0 RSV RSV 0 RSV RSV 0 RSV0 RSV 0 RSV RSV J0 RSV RSV VIO_SEL J RSV RSV PU-P-rPG RESERVE RSV L RSV G RSV0 E RSV K RSV W RSV T RSV M RSV J RSV T RSV J RSV H RSV0 G RSV R RSV T RSV T RSV P RSV R RSV RSV RSV RSV RSV0 RSV J RSV K V_IE_SENSE RSV T RSV T RSV R KEY H RSV N TP RSV M TP Reserved for Intel ebug For rpg socket, RSV pin should be left N 0 PU-P-rPG PU-P-rPG Processor Strapping FG (PEG Static Lane Reversal) The FG signals have a default value of '' if not terminated on the board. Normal Operation 0 Lane Reversed FG FG FG R R R K/F_ *K/F_ *K/F_ FG FG R0 R *K/F_ *K/F_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG (P Presence Strap) FG (PEG efer Training) isable; No physical P attached to ep PEG train immediately following xxreset de assertion Enable; n ext P device is connected to ep PEG wait for IOS training PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom Sandy ridge / ate: Friday, October, 00 Sheet of

7 ougar Point (LVS,I) 0 [] [] SUS_PWR_K_R E_PWROK_R MI_OMP MI_RIS XP_RST# PIE_WKE# [] XP_RST# K SYS_RESET# WKE# PIE_WKE# [,,] *U/0V_ [] PM_RM_PWRG [] [] SIO_PWRTN# SYS_PWROK E_PWROK RSMRST# SUS_PWR_K [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [].0V_PH MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R R R R R0 R R0 R0 *Short N *0/J_ *Short N *Short N./F_ 0/F_ *0/J_ *Short N SYS_PWROK_R E_PWROK_R PWROK_R PM_RM_PWRG RSMRST# SUS_PWR_K_R ougar Point (MI,FI,PM) U E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H P L L0 K E0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_PWROK PWROK PWROK RMPWROK RSMRST# MI System Power Management V V_S V_S V_S FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SLP_S# / GPIO SLP_S# SUSWRN#/SUSPWRNK/GPIO0 V_S SLP_S# PWRTN# SWVRMEN PWROK LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_# J Y E H J G0 G G F G E G J0 H W V 0 V 0 E N G N 0 H F G0 R SWVREN *Short N LKRUN# LP_P# PH_SUSLK SLP_S# SLP_# R TP TP TP0 TP FI_TXN0 [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXN [] FI_TXP0 [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_TXP [] FI_INT [] FI_FSYN0 [] FI_FSYN [] FI_LSYN0 [] FI_LSYN [] *Short N PWROK LKRUN# [] PM_SLP_S# [] SIO_SLP_S# [] RSMRST# RV *EG-00 [] [] INT_RT_HSYN INT_RT_VSYN [] [] INT_LVS_LON [] INT_LVS_VEN [] [] [] [] [] [] [] [] [] [] [] [] [] LVS_RIGHT_PWM R0 R0 [] [] INT_EILK INT_EIT R V INT_TXLLKOUTN INT_TXLLKOUTP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP INT_RT_LU INT_RT_GRE INT_RT_RE INT_LK INT_T /J_ /J_ 0ohm for SW; ohm for UM R0 R.K/F_ INT_EILK INT_EIT TP LV_IG INT_TXLLKOUTN INT_TXLLKOUTP INT_TXLOUTN0 INT_TXLOUTN INT_TXLOUTN INT_TXLOUTP0 INT_TXLOUTP INT_TXLOUTP INT_RT_LU INT_RT_GRE INT_RT_RE INT_RT_HSYN_R INT_RT_VSYN_R _IREF R K/F_.K/J_.K/J_ J M P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F N P T T M0 M M T T U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN ougarpoint_rp0 LVS RT igital isplay Interface SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y M M T T H F E F E J G INT_HMI_HP_Q P_HP_PU P_HP_PU V INT_HMI_SL [0] INT_HMI_S [0] INT_HMI_TXN [0] INT_HMI_TXP [0] INT_HMI_TXN [0] INT_HMI_TXP [0] INT_HMI_TXN0 [0] INT_HMI_TXP0 [0] INT_HMI_TXN [0] INT_HMI_TXP [0] INT. HMI INT. P [] _PRESENT R *Short N _PRESENT_R PM_TLOW# PM_RI# H0 E0 0 PRESENT / GPIO SW TLOW# / GPIO V_S RI# V_S SLP_SUS# PMSYNH SLP_LN# / GPIO G P K SLP_LN# TP TP PM_SYN [] R0 R0 R place close to PH 0/F_ 0/F_ INT_RT_LU INT_RT_GRE INT_HMI_HP_Q R *00K/J_ Q MEN00E INT_HMI_HP [0] R0 00K/J_ ougarpoint_rp0 R0 0/F_ INT_RT_RE PH Pull-high/low(LG) V V_S LKRUN# R.K/J_ PM_RI# R 0K/J_ XP_RST# R0 0K/J_ PM_TLOW# R0.K/J_ R0 *K/J_ PIE_WKE# R0 0K/J_ RSMRST# R 0K/J_ SLP_LN# R0 *0K/J_ SYS_PWROK R 00K/J_ SUS_PWR_K R 0K/J PRESENT R 0K/J_ PM_RM_PWRG R *00/F_ / hange topology; 00ohm PU to V_S System PWR_OK(LG) [,] SYS_PWROK SYS_PWROK U TSH0FU(F) V_S *0.U/0V_ R 00K/J_ IMVP_PWRG [] E_PWROK V_RT R 0K/J_ SWVREN R *0K/J_ On ie SW VR Enable High = Enable (efault) Low = isable PWROK FOR SW V_SW V_S *R00V-0 VPU *R00V-0 Q *PTEU VPU VPU R *0K_ R *0K_ Q *N00 PWROK 0 *0.U/0V_ add cap to timing tune V P_HP_PU R 0K/J_ P_HP_PU R 0K/J_ Follow PG ep disable guide PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom ougar Point / Friday, October, 00 ate: Sheet of

8 RT ircuitry(rt) V_SW VPU 0mils V_RT_0 R0 *0/J_ V_RT R 0/J_ V_RT_ R 0K/J_ V_RT_ 0MIL T U/.V_ 0mils R K/J_ R0 0K/J_ U/.V_ U/.V_ 0MIL T T_ONN H us(lg) *P/0V_ [] Z_ITLK R0 /J_ [] Z_SYN R /J_ [] Z_RST# R /J_ [] Z_SOUT R /J_ PH JTG ebug (LG) V_S To Separate odec Sync by P Z_ITLK_R Z_SYN_OE Z_RST#_R Z_SYN_OE Z_SOUT_R Q RT_RST# J *SHORT_ P SRT_RST# J *SHORT_ P V Z_SYN_R MEN00E PH(LG) 00 P/0V_ P/0V_ V_RT [] Y.KHZ [] [] SPKR Z_SIN0 INTEL_T_OFF# [0] R OR_I R 0M/J_ M/J_ TP TP TP TP TP TP RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK_R Z_SYN_R SPKR Z_RST#_R Z_SOUT_R OR_I PH_JTG_TK_R PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R ougar Point (H,JTG,ST) U 0 RTX FWH0 / L0 FWH / L 0 RTX FWH / L FWH / L 0 RTRST# FWH / LFRME# G SRTRST# LRQ0# K INTRUER# V LRQ# / GPIO INTVRMEN N H_LK L H_SYN T0 SPKR K H_RST# E H_SIN0 G H_SIN H_SIN H_SIN H_SO N J H K H RT IH ST LP ST G H_OK_EN# / GPIO V H_OK_RST# / GPIO V_S JTG_TK JTG_TMS JTG_TI JTG_TO JTG SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STROMPO E LP_RQ#0 K L_K_OFF V M M P P M0 M P P0 H H 0 F F Y Y Y Y Y Y0 ST_OMP R LP_L0 [,] LP_L [,] LP_L [,] LP_L [,] LP_LFRME# [,] LP_RQ#0 [] L_K_OFF# [] IRQ_SERIRQ [,] IRQ_SERIRQ O_PRSNT# L_K_OFF# ST_T# INTEL_T_OFF# ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP [] ST H ST_RXN [] ST_RXP [] ST_TXN [] ST O ST_TXP [] ST_RXN [] ST_RXP [] ST_TXN [] EST # ST_TXP []./F_.0V_PH R0 R R R0 R 0 V.K/J_ *0K/J_ 0K_ 0K_ 0K/J_ R *0/F_ R0 *0/F_ R0 *0/F_ STOMPI ST_OMP R./F_ R *00/F_ R *00/F_ PH_JTG_TMS_R PH_JTG_TI_R PH_JTG_TO_R PH_JTG_TK_R R R *00/F_ */J_ PH Strap Table [] PH_SPI_LK [] PH_SPI_S0# VPU R *0K/J_ [] PH_SPI_SI [] PH_SPI_SO PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO T SPI_LK Y SPI_S0# T SPI_S# V SPI_MOSI U SPI_MISO ougarpoint_rp0 SPI V V STRIS STLE# ST0GP / GPIO STGP / GPIO H P V P ST_RIS ST_T# S_IT0 R 0/F_ ST_T# [] O_PRSNT# [] PH ual SPI (LG) PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO R0 R0 R /J_ /J_ /J_ MXL0MI-G: KEFP0Z00 WXVSSIG: KEZP0N00 Socket: G PH_SPI_LK_R PH_SPI_SI_R PH_SPI_SO_R P/0V_ U0 E# SK SI SO WP# MXL0 V HOL# VSS R00.K/J_ V_PH_SPI 0.U/0V_ Pin Name Strap description Sampled onfiguration 0 = efault (weak pull-down 0K) SPKR No reboot mode setting PWROK = Setting to No-Reboot mode GNT# / GPIO GNT# / GPIO GPIO Top-lock Swap Override oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] PWROK PWROK PWROK 0 = "top-block swap" mode = efault (weak pull-up 0K) INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up GNT# 0 GNT0# 0 oot Location SPI LP * V V_RT R R0 R *K/J_ 0K/J_ SPKR PI_GNT# [] PH_INVRMEN efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] R R *K/J_ *K/J_ *K/J_ S_IT [] S_IT0 V_PH_SPI R.K/J_ H_SO Flash escriptor Security RSMRST 0 = Override = efault (weak pull-up 0K) V_S R *K/J_ Z_SOUT_R V R 0R V_PH_SPI F_TVS GPIO MI/FI Termination voltage On-die PLL Voltage Regulator PWROK RSMRST# 0 = Set to Vss = Set to Vcc (weak pull-down 0K) 0 = isable = Enable (efault) R R R *K/J_.K/J_.K/J_.V PLL_OVR_EN [0] F_TVS [0] H_SN_IV# [] V_S R *0R H_SYN On-ie PLL VR Voltage Select RSMRST 0 = Support by.v (weak pull-down) = Support by.v V_S R K/J_ Z_SYN_R GPIO Integrated lock hip Enable RSMRST# Should be pull-down (weak pull-up 0K) SPI_MOSI itpm function isable PWROK 0 = efault (weak pull-down 0K) = Enable V R0 *K/J_ PH_SPI_SI NV_LE Intel nti-theft H protection PWROK 0 = isable (Internal pull-down 0kohm) PROJET KL Quanta omputer Inc. Size ocument Number Rev ougar Point / Friday, October, 00 ate: Sheet of

9 U 0 [,] [] [] [] [] RF_ON S_IT T_IS PI_GNT# O_M# TP TP TP [] LK_LP_EUG [] LK_PI_ O_M# LK_PI_F *0P/0V/OG_ RF R0 R R R LK_PI_F_R *0_ /J_ /J_ /J_ PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_HOL_RST# GPU_PWR_EN# S_IT T_IS PI_GNT# MP_PWR_TRL# O_M_R# EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH PI_PLTRST# LK_PI_F_R LK_PI_LP_R LK_PI_E_R For RF Please lose to U RV0 *EG-00 G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 UE TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 REQ# / GPIO REQ# / GPIO GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI ougarpoint_rp0 RSV PI V V V V V V V V V V US V_S V_S V_S V_S V_S V_S V_S V_S RSV Y V RSV U RSV RSV G RSV T0 RSV U RSV RSV T RSV T RSV0 T RSV Y T RSV RSV V RSV V RSV RSV RSV RSV RSV RSV0 E RSV RSV F NV_LE RSV V RSV V0 RSV T Y RSV RSV RSV T F RSV USP0N USP0P USPN USPP USPN USPP USPN K USPP H USPN E USPP USPN USPP USPN USPP USPN N USPP M USPN L0 USPP K0 USPN G0 USPP E0 USP0N 0 USP0P 0 USPN L USPP K USPN G USPP E USPN USPP US_IS USRIS# USRIS US_O0# O0# / GPIO US_O# O# / GPIO0 K0 US_O# O# / GPIO US_O# O# / GPIO US_O# O# / GPIO L US_O# O# / GPIO US_O# O# / GPIO0 US_O# O# / GPIO R TP USP0- [] USP0 [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] USP0- [] USP0 []./F_ US_O0# [] US_O# [] US_O# [] US/eST ombo #(Phoenix debug) US#0-> L port((ios debug) WWN(common design reserved) luetooth US(common design reserved) US #-->R port(&ios debug) ard Reader LK_FLEX LK_M LK_M_R_ US port,disable for HM. *0P/0V/OG_ RF *0P/0V/OG_ RF *0P/0V/OG_ RF LK_UF_LKN LK_UF_LKP *0P/0V/OG_ RF *0P/0V/OG_ RF EHI EHI LN WLN E--0 US.0 LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M For RF [] [] [] [] PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN [] [] [] [] [] [] [] [] PIE_RXN PIE_RXP PIE_TXN PIE_TXP PIE_RXN PIE_RXP PIE_TXN PIE_TXP *0P/0V/OG_ RF *0P/0V/OG_ RF *0P/0V/OG_ RF *0P/0V/OG_ RF0 *0P/0V/OG_ RF *0P/0V/OG_ RF *0P/0V/OG_ RF 0.U/0V_ PIE_TXN_LN_ 0.U/0V_ PIE_TXP_LN_ 0.U/0V_ PIE_TXN_ 0.U/0V_ PIE_TXP_ 0 *0.U/0V_ PIE_TXN_ 0 *0.U/0V_ PIE_TXP_ LKOUT_PIEN LKOUT_PIEP PIELKRQ# LKOUT_PIEN LKOUT_PIEP PIELKRQ# US.0 E--0 LKOUT_PIEN LKOUT_PIEP PIELKRQ# [] IS_ULE_LE TP LK_PH_ITPN_R TP0 LK_PH_ITPP_R G J V U E F Y G J V U F E Y G H Y J G U V G0 J0 Y0 0 E W Y Y0 Y J M V0 Y Y Y Y L V V L 0 E V0 V T V V K K K PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP ougarpoint_rp0 V_S PI-E* PIELKRQ0# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO0 PIELKRQ# / GPIO PIELKRQ# / GPIO PIELKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P V_S PEG LKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO LKOUT_ITPXP_N LKOUT_ITPXP_P V V LOKS V_S V_S V_S V_S V_S V_S V_S SMUS V_S V V V V V_S SMLLERT# / PHHOT# / GPIO V_S SMLLK / GPIO V_S SMLT / GPIO ontroller Link FLEX LOKS SMLERT# / GPIO SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T L_LK L_T L_RST# PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N LKOUT_P_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO LKOUTFLEX / GPIO E H G E M M T P0 M0 V U M M F E J0 G0 G E K K K H V V Y K F H K SMLERT# SM_PH_LK SM_PH_T RMRST_NTRL_PH SM_ME0_LK SM_ME0_T SMLLERT#_R SM_ME_LK SM_ME_T L_LK L_T L_RST# PEG_LKREQ# LKOUT_PEG N LKOUT_PEG P LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LKN LK_UF_LKP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M LK_PI_F XTL_IN XTL_OUT XLK_ROMP LK_FLEX LK_M LK_M_R_ R 0./F_ R0 _ TP TP TP TP TP RMRST_NTRL_PH [].0V_PH E--0 LK_PU_LKN [] LK_PU_LKP [] LK_PLL_SSLKN [] LK_PLL_SSLKP [] R0 R M/J_ *0_ LK_M_R [] Y MHZ P/0V_ P/0V_ PH_LKM [] E--0 Please lose to U E--0 GPU Power ON [,,] PI_PLTRST# PLTRST# GFXON PLTRST#(LG) GPU RST#(LG) GPU_HOL_RST# R0 IS@00K/J_ V_S R0 V U R IS@MVHG0FTG R0 U TSH0FU(F) *0_ PLTRST# V *IS@0_ PLTRST# IS@0.U/0V_ U IS@TSH0FU(F) R *IS@0_ 0 0.U/0V_ R 00K/J_ *IS@0_ PLTRST# [,,,] MINON [,,,,,,,0,] GPU_RST# [] IS@MEN00E US_O# US_O# US_O# US_O# MP_PWR_TRL# T_IS PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# RF_ON RF_ON Q0 V R IS@K_ GPU_HOL_RST# GPU_PWR_EN# PI/USO# Pull-up(LG) V_S R 0 R R R R R 0KX V R 0 R 0KX R.K/J_.K/J_.K/J_.K/J_ 0K/J_ 00K/J_ US_O# US_O# US_O0# US_O# EXTTS_SNI_RV0_PH GPU_PWR_EN# O_M_R# EXTTS_SNI_RV_PH V *0K/J_ V PEG LK detect WLN LN [] [] [] [] [] [] US.0 hip PEG_LKREQ# PIE_LKREQ_WLN# [] [] [] [] LK_PIE_WLNN LK_PIE_WLNP LK_PIE_LNN LK_PIE_LNP PIE_LKREQ_LN# LK_00_US0_P LK_00_US0_N LK_PIE_VGP LK_PIE_VGN SW:Stuff UM:Non-stuff MP Switch ontrol MP_PWR_TRL# MP_PWR_TRL# Q IS@MEN00E R R R R0 R R0 GFXPG [0,] E--0 LKOUT_PIEN LKOUT_PIEP LKOUT_PEG P LKOUT_PEG N IS@0X Low = MP ON High = MP OFF (efault) R *K/J_ 0X *Short_@N PEX_LKREQ# [] PIELKRQ# LKOUT_PIEN LKOUT_PIEP 0X *Short_@N PIELKRQ# 0X LKOUT_PIEP LKOUT_PIEN SMus(LK) SW:Ra UM:Rb V R0 R0 V_S SM_PH_T PEG_LKREQ# LK_UF_LKN LK_UF_LKP SM_PH_LK LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M IS_ULE_LE V V LK_REQ/Strap Pin(LG) R R0 R 0K/J_ 0K/J_ 0K/J_ 0K/J_ IS@0K/J_ PIE_LKREQ_WLN# PIE_LKREQ_LN# IS_ULE_LE PIELKRQ# R R R R R R R R R R Q MEN00E Q MEN00E PEG_LKREQ# R 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ SM_RUN_T SM_RUN_LK E--0 E--0 *UM@0K/J_ 0K/J_ 0K/J_ 00K/J_ R0.K/J_ R.K/J_ SM_RUN_T [,] SM_RUN_LK [,] SMus/Pull-up(LG) V_S R R R R R R R0 [,,] [,,] M_LK M_T K/J_ 0K/J_.K/J_.K/J_.K/J_.K/J_ 0K/J_ LK Gen(LK) 0/0 EL for Pre-ES PU_LK select(lk) PU_SEL RMRST_NTRL_PH SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SMLLERT#_R V_S V_S 0 PU0/=MHz (default) PU0/=00MHz R0.K/J_ SM_ME_LK Q MEN00E R.K/J_ SM_ME_T Q MEN00E PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom ougar Point / Friday, October, 00 ate: Sheet of

10 [,] E_EXT_SMI# [] E_EXT_SI# TP0 [] LN_ISLE# S_GPIO R 00_ E_EXT_SMI# OR_I E_EXT_SI# I_EN# LN_ISLE# HOST_LERT#_R ougar Point (GPIO,VSS_NTF,RSV) UF T MUSY# / GPIO0 V V TH / GPIO 0 PU_I TH / GPIO V V TH / GPIO R.K/F_ H TH / GPIO V V TH / GPIO0 OLOR_ENGINE_ET R0 E TH / GPIO V V TH / GPIO 0 OR_I E--0 0 GPIO V_S LN_PHY_PWR_TRL / GPIO V_S G GPIO V_S 0GTE P 0K_ V E_0GTE [] GPIO Pull-up/Pull-down(LG) LN_ISLE# E_EXT_SMI# E_EXT_SI# E_0GTE E_RIN# TEMP_LERT# T_ON# R R R R R0 R R 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ 0K/J_ V_S V 0 GFXPG_R GFXPG_R E--0 [] PLL_OVR_EN [] T_ON# [,] TEMP_LERT# R U IS@MVHG0FTG V TP *IS@0_ R0 T_ON# GPIO OR_I0 GFXPG_R IOS_RE US0_I GPIO SYSTEM_I FI_OVRVLTG MFG_MOE GPU_PRSNT# TEST_SET_UP SV_ET HWPG [,,,,0,,] GFXPG [,] *Short N U STGP / GPIO V 0 T E TH0 / GPIO V SLOK / GPIO V GPIO / MEM_LE V_S E P GPIO GPIO SW V_S K STP_PI# / GPIO V K GPIO V V M N STGP / GPIO V STGP / GPIO V SLO / GPIO V M V V STOUT0 / GPIO STOUT / GPIO STGP / GPIO V V V GPIO V_S E E F F VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ ougarpoint_rp0 E_RIN# PH_THRMTRIP# / onnected to GN G rev0. SGPIO S_GPIO V V V GPIO NTF PU/MIS PEI RIN# PROPWRG THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ U P Y Y0 T Y H K H0 K0 P G G H H J J J J J J E E F F R R R00 0/J_ 0K/J_ *0/J_ V TP E_RIN# [] H_PWRGOO [] PM_THRMTRIP# [] F_TVS [] oard I oard I For Function SV SIV SIT SVT SOVP TEST_SET_UP HOST_LERT#_R R Low = isable (efault) High = Enable SYSTEM_I GPIO R R R R R R SV_SET_UP GPIO High = Strong (efault) GFXPG_R I GPIO OR_I0 OR_I OR_I OR_I V_S Intel ME rypto Transport Layer Security (TLS) cipher suite I GPIO R0 R *0K/J_ 0K/J_ 0K/J_ 0K/J_ PU_I 0K/J_ SYSTEM_I 0K/J_ 0K/J_ *0/J_ K/J_ V R R US0_I R R R0 R R0 R OR_I [] V V I0 GPIO R0 R R 0K/J_ IS@0K/J_ 0K/J_ *0K/J_ *0K/J_ *0K/J_ *0K/J_ E-- *0K/J_ I GPIO V *0K/J_ *0K/J_ V_S Stuff No Stuff US0_I E--0, E-- SV_ET US0 I: 0-->Support -->Nonsupport OR_I0 OR_I OR_I I: 0--> layer --> layer Optimus R R R UM R R 0K/J_ V_S oard I use below GPIO: System I: 0-->KL -->KL PU_I: 0-->W -->W R GPU_PRSNT# R *UM@0K/J_ 00K/J_ IS@00K/J_ R 00K/J_ FI TERMINTION VOLTGE OVERRIE FI_OVRVLTG R LOW - Tx, Rx terminated to same voltage *K/F_ GPIO MI TERMINTION VOLTGE OVERRIE Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) R *00K/F_ IOS_RE R R IOS REOVERY 0K/J_ *0/J_ High = isable (efault) Low = Enable MFG-TEST MFG_MOE R0 R V 0K/J_ *0/J_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom ougar Point / ate: Friday, October, 00 Sheet 0 of

11 PH(LG).0V_PH R.0V_PH R.0V_PH L.0V_PH R 0/F_0.0V_PH_V.0V_PH_VPLL_EXP *Short N.0V_VPLL_EXP *uh/m_.0v_vio VccIO =.0 (mils) 0/F_0 V.0V_PH VFI_VRM.0V_PH.V.0V_PH U/.V_ *0U/.V_ U/.V_ R R R VccORE =. (0mils) U/.V_ U/.V_ U/.V_ Vcc_ =0.0 (0mils) *Short N R R00 V_V_EXP *0/J_ *Short N U/.V_ VFI_VRM 0/J_ *0/J_ U/.V_ 0 0U/.V_ 0 0.U/0V_ 0 0U/.V_ VFI_VRM.0V_VPLL_FI.0V_VPLL_FI F F G G G G G G J J J J J VVRM:.V (estop).v (Mobile) N J N N N N N P P P P T N N H P G P U0 OUGR POINT (POWER) UG VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] VVRM[] VccFIPLL VIO[] VMI[] ougarpoint_rp0 POWER V ORE VIO FI RT LVS FT / SPI MI HVMOS V VSS VLVS VSSLVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] VVRM[] VMI[] VLKMI VFTERM[] VFTERM[] VFTERM[] VFTERM[] VSPI U U K K M M P P V V T T0 G G J J V R *0/J_ VFI_VRM V Vcc =m(mils) L VLVS V VccLVS=m(mils) R SW@0/J_ V_TX_LVS VccTX_LVS=0m(0mils) L V_V_GIO VVRM = m(0mils) U/.V_ 0.0U/V_ R 0.U/0V_ VP_NN V_VME_SPI VFI_VRM.V_V_MI_I *0U/.V_ R 0.U/0V_ U/.V_ 0.0U/V_ 0.0U/V_ *Short N R L V *Short N R0 0/J_ 0.U/0V_.V *0/J_ 0 U/.V_ V.V_V_MI V_MI_I V_S R R Ra Rb Ra Rb 0ohm/ *IS@0/J_ *IS@0/J_ IS SW 0 ohm N 0 ohm N VMI = m(0mils) *0uH_ 0U/.V_ R U/.V_.0V_PH.0V_PH VPNN = 00 m(0mils) VSPI = 0m(mils) V.V VLKMI = 0m(mils) R R SW@0.uH_ *Short N */F_ 0/J_.0V_PH m(mils).0v_ph VRT<m(mils) L.0V_PH.0V_PH.0V_PH V_RT V_S V_SW VPLL_PY_PH VME(.0V) =??(??mils) R R R R R0 R0 *0uH/00m_ 0/F_0.0V_PH VSW_= m.0v_vepw VccSW =. (0mils) *Short N *0/J_ R R *Short N *Short N *Short N U/.V_ *U/.V_.U/.V_ 0 U/.V_ 0/J_ *0/J_.0V_PH *0U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0.U/0V_ 0 0.U/0V_ R 0.U/0V_ R U/.V_ U/.V_ VFI_VRM m(0mils) m(mils) PH_VSW VRTEXT VFI_VRM.0V_V PL VIFFLK VIFFLKN VSST VLK VPSW V_SUS_LKF VPLL_PY VSUS.0V_V PL VIFFLKN= m(0mils) VSS= m(0mils) *0/J_ 0.U/0V_ 0.U/0V_ 0 0.U/0V_ *0.U/0V_ *Short N *U/.V_ 0.U/0V_ V.0V_SSV V.0M_VSUS VTT_VPPU ougar Point-M (POWER) T V T H L L W W W W W W W N Y F F F F G G V T V J UJ VLK VSW_ PSUSYP V_[] VPLLMI VIO[] PSUS[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] PRT VVRM[] VPLL VPLL VIO[] VIFFLKN[] VIFFLKN[] VIFFLKN[] VSS PSST PSUS[] PSUS[] V_PRO_IO VRT ougarpoint_rp0 POWER lock and Miscellaneous PU RT ST PI/GPIO/LP US MIS H VIO[] VIO[0] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VIO[] VREF_SUS PSUS[] VSUS_[] VREF VSUS_[] VSUS_[] VSUS_[] VSUS_[] V_[] V_[] V_[] V_[] VIO[] VIO[] VIO[] VIO[] VPLLST VVRM[] VIO[] VIO[] VIO[] VSW[] VSW[] VSW[] VSUSH N P P T T T T V V P T M N N P N0 N P0 P W T J F H H F V_VPUS V_VUG VUPLL V_PH_VREFSUS V_USSUS V_VPSUS V_PH_VREF V_VPSUS V_VPORE V 0.U/0V_ V.0S_ST K V.LN_VPLL VVRM= m(mils) F T V T P VFI_VRM.0V_VIO U/.V_ V._._H_IO *U/.V_ R.0V_VUSORE *U/.V_.0V_VEPW 0 0.U/0V_ R 0 U/.V_ R R *Short N 0.U/0V_ 0.U/0V_ U/.V_ V.0V_PH 0.U/0V_ 0.U/0V_ *Short N *Short N.0V_PH V_S VREF= m VME =.0(0mils) VREFSUS=m V_S V_S V V V_S V.0V_PH??m(??mils).0V_PH.0V_PH.V_SUS V_S VSUS_ = m(mils) VSUS_ = m(mils) 0 U/0V_ VPORE = m(0mils) 0 0.U/0V_ U/0V_ 0 *0U/.V_ *Short N L R R R R R R R R 0/F_ R00V-0 0/F_ R00V-0 *Short N *Short N *Short N *0uH/00m_ *Short N VSUSH= 0m(mils) *0/J_ 0/J_.0V_PH L 0uH/00m.0V_V PL V *0U/.V_ U/.V_ R R *0/J_ /F_ V_SUS_LKF_R L 0uH/00m_ V_SUS_LKF L 0uH/00m.0V_V PL 0U/.V_ U/0V_ 0 *0U/.V_ 0 U/.V_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom ougar Point / Friday, October, 00 ate: Sheet of

12 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL ougar Point / ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL ougar Point / ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL ougar Point / ustom Friday, October, 00 IEX PEK-M (GN) PH(LG) UI ougarpoint_rp0 UI ougarpoint_rp0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J UH ougarpoint_rp0 UH ougarpoint_rp0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L

13 M 0 M M M M M M 0 M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM_S0 IMM_S SMR_VREF_Q SMR_VREF_Q_M SMR_VREF_Q_M SMR_VREF_Q_M M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M QSP[:0] [] M QSN[:0] [] M OT0 [] M OT [] M Q[:0] [] R_RMRST# [,] PM_EXTTS#0 [] SM_RUN_LK [,] SM_RUN_T [,] SMR_VREF_Q_M [] SMR_VREF [,,].V_SUS V 0.V_R_VTT SMR_VREF_IMM V V SMR_VREF_IMM V.V_SUS 0.V_R_VTT SMR_VREF_Q.V_SUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM-0 ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM-0 ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM-0 ustom Friday, October, 00 Place these aps near So-imm.. R_RVS(R) GMK00000 GMK00000 GMK0000 ST H GMK000 ST H FOX LTK SUY SKT Standard H type:r--00-0p- VREF Q M Solution 0/ Remove 0ohm to GN GMK00000 GMK000 GMK000 GMK000 0 U/.V_ 0 U/.V_ 0U/.V_ 0U/.V_ 0.U/.V_ 0.U/.V_ U/.V_ U/.V_ P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 *0U/.V_ *0U/.V_ U/0V_ U/0V_ U/0V_ U/0V_ 0.u/0V_ 0.u/0V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0u/.V_ 0u/.V_.U/.V_.U/.V_ 0 0U/.V_ 0 0U/.V_ 0 0.u/0V_ 0 0.u/0V_ U/.V_ U/.V_ R0 0K/J_ R0 0K/J_ 0 *0U/.V_ 0 *0U/.V_ P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q U/.V_ U/.V_ 0U/.V_ 0U/.V_ R K/F_ R K/F_ 0 U/0V_ 0 U/0V_ 0.u/0V_ 0.u/0V_ R0 *0/J_ R0 *0/J_ R 0K/J_ R 0K/J_ 0 0U/.V_ 0 0U/.V_ R K/F_ R K/F_ U/0V_ U/0V_ 0.u/0V_ 0.u/0V_ 0U/.V_ 0U/.V_ R 0K/J_ R 0K/J_ R 0/J_ R 0/J_ R *0/J_ R *0/J_.U/.V_.U/.V_

14 M 0 M M M M M M 0 M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q IMM0_S0 IMM0_S SMR_VREF_IMM PM_EXTTS#0 SMR_VREF_Q0 SMR_VREF_Q0_M SMR_VREF_Q0_M SMR_VREF_IMM SMR_VREF SMR_VREF_Q0_M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M QSP[:0] [] M QSN[:0] [] M OT0 [] M OT [] M Q[:0] [] SM_RUN_LK [,] SM_RUN_T [,] R_RMRST# [,] SMR_VREF_Q0_M [] SMR_VREF [,,] PM_EXTTS#0 [].V_SUS V 0.V_R_VTT V.V_SUS.V_SUS SMR_VREF_IMM V.V_SUS 0.V_R_VTT SMR_VREF_Q0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM- ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM- ustom Friday, October, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET KL RIII SO-IMM- ustom Friday, October, 00. R_RVS(R) VREF Q0 M Solution Place these aps near So-imm0. 0/ Remove 0ohm to GN 0U/.V_ 0U/.V_ R 0K/J_ R 0K/J_ 0.u/0V_ 0.u/0V_ R *0/J_ R *0/J_ 0 U/.V_ 0 U/.V_ R 0K/J_ R 0K/J_ U/.V_ U/.V_.U/.V_.U/.V_ *0U/.V_ *0U/.V_ U/0V_ U/0V_ U/.V_ U/.V_ *0U/.V_ *0U/.V_ U/0V_ U/0V_ 0U/.V_ 0U/.V_ R 0K/J_ R 0K/J_ 0P/0V_ 0P/0V_ 0U/.V_ 0U/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ *0U/V_ *0U/V_.U/.V_.U/.V_ 0U/.V_ 0U/.V_ P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q 00 U/0V_ 00 U/0V_ 0U/.V_ 0U/.V_ R *0/J_ R *0/J_ R 0K/J_ R 0K/J_ U/.V_ U/.V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ R 0K/J_ R 0K/J_ R 0/J_ R 0/J_ P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) P00 R SRM SO-IMM (0P) JIM R SOIMM(0P,H.0,RVS) V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT 0 GN 0 GN 0 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_.U/.V_.U/.V_ R0 *0/J_ R0 *0/J_ 0 U/0V_ 0 U/0V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ R K/F_ R K/F_

15 E--00 / PI_EXPRESS.0V_GFX_PIE PEX_LKREQ# [] EV@0.U/0V/XR_ PEX_IOV_0 (N) PEX_LKREQ E GPU_RST# PEX_RST* GPU_RST# [] 00 EV@0.U/0V/XR_ PEX_IOV_0 0 EV@U/.V/XR_ PEX_IOV_0 E 0 EV@U/.V/XR_ PEX_IOV_0 F LK_PIE_VGP [] EV@.U/.V/XR_ PEX_IOV_0 PEX_REFLK 0 G PEX_REFLK* 0 R LK_PIE_VGN [] 0 EV@0U/.V/XR_ PEX_IOV_0 *EV@0K/F_ EV@U/.V PEG_RX0 PEG_RXP PEX_TX0 0 EV@0.U/0V/XR_ PEG_RXP [] _PEG_RX#0 PEG_RXN PEG_RXN [] PLE NER LLS PEX_TX0* EV@0.U/0V/XR_ PEX_IOVQ_0 _PEG_RX PEG_RXP PEX_TX EV@0.U/0V/XR_ PEX_IOVQ_0 PEG_RXP [] For PIE clock request signal 0/0.0V_GFX_PIE _PEG_RX# 0 EV@0.U/0V/XR_ PEG_RXN PEX_TX* PEG_RXN [] EV@0.U/0V/XR_ PEX_IOVQ_0 _PEG_RX PEG_RXP PEG_RXP [] EV@0.U/0V/XR_ PEX_TX EV@0.U/0V/XR_ PEX_IOVQ_0 _PEG_RX# EV@0.U/0V/XR_ PEG_RXN PEX_TX* PEG_RXN [] 0 EV@U/.V/XR_ PEX_IOVQ_0 _PEG_RX PEG_RXP PEX_TX EV@0.U/0V/XR_ PEG_RXP [] 0 EV@U/.V/XR_ PEX_IOVQ_0 _PEG_RX# PEG_RXN PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] EV@.U/.V/XR_ PEX_IOVQ_0 _PEG_RX PEG_RXP V_GPU PEX_TX EV@0.U/0V/XR_ PEG_RXP [] EV@0U/.V/XR_ PEX_IOVQ_0 _PEG_RX# PEG_RXN PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] EV@U/.V_ PEX_IOVQ_0 E _PEG_RX PEG_RXP0 PEX_TX EV@0.U/0V/XR_ PEX_IOVQ_0 PEG_RXP0 [] F _PEG_RX# PEG_RXN0 V PEG_RXN0 [] PLE UNER LLS PEX_TX* EV@0.U/0V/XR_ PEX_IOVQ_ G _PEG_RX PEG_RXP PEX_TX EV@0.U/0V/XR_ PEX_IOVQ_ PEG_RXP [] _PEG_RX# PEG_RXN GFX_ORE PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] _PEG_RX PEG_RXP PEX_TX EV@0.U/0V/XR_ R PEG_RXP [] _PEG_RX# PEG_RXN PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] EV@0K/F PEG_RX EV@0.U/0V/XR_ PEG_RXP PEG_RXP [] PLE UNER LLS PEX_TX R. _PEG_RX# EV@0.U/0V/XR_ PEG_RXN PEX_TX* PEG_RXN [] EV@0K/F_ EV@0.0U/V/XR_ J0 _PEG_RX EV@0.U/0V/XR_ PEG_RXP PEG_RXP [] EV@0.0U/V/XR_ V_0 PEX_TX J _PEG_RX# PEG_RXN PEX_TX* 0 EV@0.U/0V/XR_ PEG_RXN [] GFXPG [,0] EV@0.0U/V/XR_ V_0 J _PEG_RX0 PEG_RXP PEX_TX0 EV@0.U/0V/XR_ PEG_RXP [] EV@0.0U/V/XR_ V_0 J _PEG_RX#0 PEG_RXN PEX_TX0* 0 EV@0.U/0V/XR_ PEG_RXN [] EV@0.0U/V/XR_ V_0 L _PEG_RX 0 EV@0.U/0V/XR_ PEG_RXP V_0 PEX_TX PEG_RXP [] M _PEG_RX# PEG_RXN Q PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] EV@0.U/0V/XR_ V_0 M _PEG_RX PEG_RXP PEX_TX 0 EV@0.U/0V/XR_ PEG_RXP [] EV@SST0T EV@0.U/0V/XR_ V_0 M _PEG_RX# PEG_RXN PEX_TX* EV@0.U/0V/XR_ PEG_RXN [] 0 EV@0.U/0V/XR_ V_0 N _PEG_RX PEG_RXP PEX_TX EV@0.U/0V/XR_ PEG_RXP [] EV@0.U/0V/XR_ V_0 N _PEG_RX# PEG_RXN PEG_RXN [] EV@0.U/0V/XR_ PEX_TX* EV@0.U/0V/XR_ V_0 N _PEG_RX PEG_RXP PEG_RXP [].V_GPU R EV@0K/F_ PEX_TX EV@0.U/0V/XR_ R V_ N _PEG_RX# PEG_RXN PEG_RXN [] EV@U/V/XR_ PEX_TX* EV@0.U/0V/XR_ V_ *EV@0_ N _PEG_RX EV@0.U/0V/XR_ PEG_RXP0 *EV@000P/0V/XR_@N PEX_TX E PEG_RXP0 [] EV@U/V/XR_ V_ N _PEG_RX# PEG_RXN0 Q PEG_RXN0 [] EV@U/V/XR_ PEX_TX* E EV@0.U/0V/XR_ V_ N EV@PTTT V_ N V_ N EV@U/.V_ V_ P EV@U/.V_ V_ P V_ P PLE NER LLS V_0 P.V_GPU R EV@0K/F_ Q0 V_ P EV@PTTT V_ P PEG_TXP V_ PEX_RX0 E *EV@000P/0V/XR_@N PEG_TXP [] P PEG_TXN V_ PEX_RX0* F PEG_TXN [] R PEG_TXP V_ PEX_RX G PEG_TXP [] R PEG_TXN V_ PEX_RX* G PEG_TXN [] R PEG_TXP V_ PEX_RX F PEG_TXP [] R PEG_TXN V_ PEX_RX* E PEG_TXN [] R PEG_TXP V_ PEX_RX E PEG_TXP [] R PEG_TXN V_0 PEX_RX* F PEG_TXN [] R PEG_TXP V_ PEX_RX G PEG_TXP [] R PEG_TXN V_ PEX_RX* G PEG_TXN [] T PEG_TXP0 V_ PEX_RX F PEG_TXP0 [] T PEG_TXN0 V_ PEX_RX* E PEG_TXN0 [] T PEG_TXP V_ PEX_RX E PEG_TXP [] U PEG_TXN V_ PEX_RX* F PEG_TXN [] U PEG_TXP For power-down sequency V_ PEX_RX G PEG_TXP [] W0 PEG_TXN V_ PEX_RX* G PEG_TXN [] W PEG_TXP V_ PEX_RX F PEG_TXP [] W PEG_TXN PEG_TXN [] V_GPU.V_GPU V_GPU GFX_ORE V_0 PEX_RX* E W PEG_TXP V_ PEX_RX E PEG_TXP [] W PEG_TXN V_ PEX_RX* F PEG_TXN [] W PEG_TXP V_ PEX_RX0 G 0 PEG_TXP [] PEG_TXN PEG_TXN [] TP GPU_V_SENSE PEX_RX0* G W PEG_TXP V_SENSE PEX_RX F PEG_TXP [] W PEG_TXN GN_SENSE PEX_RX* E EV@R00V-0 EV@R00V-0 PEG_TXN [] E PEG_TXP V_SENSE (N) PEX_RX E PEG_TXP [] E PEG_TXN GN_SENSE (GN) PEX_RX* F PEG_TXN [] PEG_TXP PEX_RX G PEG_TXP [] V_GPU 0m PEG_TXN V_0 PEX_RX* F PEG_TXN [] EV@.U/.V/XR_ PEG_TXP.0V_GFX_PIE V_0 PEX_RX G PEG_TXP [] EV@U/.V/XR_ PEG_TXN V_0 PEX_RX* G PEG_TXN [] EV@0.U/0V/XR_ PEG_TXP0 V_0 PEX_RX F PEG_TXP0 [] EV@0.U/0V/XR_ E PEG_TXN0 PEG_TXN0 [] L V_0 PEX_RX* E EV@0.U/0V/XR_ F EV@LMPGSN(0,000M)_ V_0 PLE UNER LLS V EV@0.U/0V/XR_ 0m PEX_PLLV F PEX_PLLV.0V_GFX_PIE V EV@U/V/XR_ 0 EV@.U/.V/XR_ PLE NER LLS.0V_GFX_PIE ~ mils R. *EV@00_ PEX_TERMP EV@0.U/0V/XR_ EV@.U/.V/XR_ 0 EV@U/.V/XR_ R EV@.K/F_ E0 F0 G G0 U NM PEX_TSTLK_OUT* PEX_TSTLK_OUT PEG_SV (N) PEX_TERMP EV@U_GPU_G_ PEG_TXP[0..] PEG_TXN[0..] PEG_RXN[0..] PEG_RXP[0..] PEG_TXP[0..] [] PEG_TXN[0..] [] PEG_RXN[0..] [] PEG_RXP[0..] [] [,,] GFXON R0 EV@0/J_ *EV@U/.V_ R *EV@0_ R Q *EV@MMT0 EV@0K/F_ R *EV@.K_ Q V_GPU R *EV@00K/F_ *EV@MEN00E V_GPU_EN power up sequence V_GPU_EN [] NVV GPIO I/O.V VG_RST# Friday, October, 00 ate: Sheet of PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom NM(PIE I/F) / GPU_PWR_EN# = GFXON >>.0_GFX_PIE >> V_GPU_EN >> V_GPU >> NVV =NVV_PG >>._GPU >>.V_GPU NVV Maximum Settling Time tsnvv<= us PEX_RST timing Trise >= 00mS Tfail <=0nS

16 E--00.V_GPU.V_GPU.0V_GFX_PIE L R R R [] VM_LK0 [] VM_LK0# [] VM_LK [] VM_LK#. EV@0.0U/V/XR_ EV@0.0U/V/XR_ EV@0.0U/V/XR_ EV@0.0U/0V/XR_ EV@0.0U/0V/XR_ EV@0.0U/0V/XR_ EV@.U/.V/XR_ [] F_M0 F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M0 [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M F_M [] F_M [] F_M [] F_M0 [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M [] F_M0.V_GPU VM_LK0 VM_LK0# VM_LK VM_LK# EV@0./F_ F_L_P_VQ EV@0./F_ F_L_PU_GN EV@0./F_ F_L_TERM_GN R *EV@0./F_ F_EUG 0m For debug only mils width m EV@LMPG00SN(0,)_ F_PLLV PLE UNER LLS EV@0.U/0V/XR_ EV@U/V/XR_ EV@0U/.V/XR_ PLE NER LLS R T U NM FVQ_0 FVQ_0 FVQ_0 FVQ_0 FVQ_0 E FVQ_0 F FVQ_0 F FVQ_0 F FVQ_0 F FVQ_0 F FVQ_ F FVQ_ F FVQ_ H FVQ_ H FVQ_ J FVQ_ J FVQ_ J FVQ_ J FVQ_ L FVQ_0 L FVQ_ L FVQ_ M FVQ_ N FVQ_ U FVQ_ Y FVQ_ G F_M0 F F_M F F_M F F_M G F_M G F_M G F_M J F_M J F_M H F_M H F_M0 J F_M G F_M G F_M J F_M J F_M M F_M L F_M J F_M K F_M K F_M0 M F_M K F_M M F_M N F_M M F_M K F_M K F_M K F_M M F_M L F_M0 F F_LK0 F F_LK0* N F_LK N F_LK* F_L_P_VQ F_L_PU_GN F_PLLV F_LLV EV@U_GPU_G_ / FRME_UFFER (F_) F_0 (F_0) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_0) F_ (F_) F_0 (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_0) F_ (F_) F_ (F_) F_0 (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_0) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_0 (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_0 (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_0) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_0 (F_) F_ (F_0) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_ (F_) F_0 (F_) F_ (F_0) F_ (F_) F_ (QM) F_QM0 (QM) F_QM (QM) F_QM (QM0) F_QM (QM) F_QM (QM) F_QM (QM) F_QM (QM) F_QM F_L_TERM_GN (WP) F_QS_WP0 (WP) F_QS_WP M F_EUG0 (WP) F_QS_WP (WP0) F_QS_WP (WP) F_QS_WP (WP) F_QS_WP (WP) F_QS_WP (WP) F_QS_WP F_PLLV (N) (RN) F_QS_RN0 (RN) F_QS_RN (RN) F_QS_RN (RN0) F_QS_RN (RN) F_QS_RN (RN) F_QS_RN (RN) F_QS_RN (RN) F_QS_RN F_VREF E E E F 0 F0 F E U V V R T R P P W W W V W W W V R V V R T N N T T E T T E R Y R VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS F_VREF TP [] VM_Q[..0] [] VM_M[..0] [] VM_WQS[..0] [] VM_RQS[..0] F_M0 R F_M R F_M R F_M R F_M0 R EV@0K/F_ EV@0K/F_ EV@0K/F_ EV@0K/F_ EV@0K/F_ UI NM / GN_N N_0 GN_0 N_0 GN_0 PGOO GN_0 GN_0 0 GN_0 GN_0 GN_0 GN_0 GN_0 F GN_0 F GN_ F GN_ F GN_ F0 GN_ F GN_ F GN_ F GN_ F GN_ GN_ GN_0 GN_ GN_ 0 GN_ GN_ GN_ GN_ GN_ E GN_ E GN_0 E GN_ E0 GN_ E GN_ E GN_ E GN_ E GN_ H GN_ H GN_ J GN_ J GN_0 J GN_ K GN_ K GN_ L GN_ L GN_ L GN_ L GN_ L GN_ L GN_ L GN_0 L GN_ L GN_ M GN_ M GN_ M GN_ M GN_ M GN_ P GN_ P GN_ P GN_0 P GN_ P GN_ P GN_ T GN_ T GN_ T GN_ T GN_ T GN_ U GN_ U GN_0 U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ V GN_0 V GN_ W GN_ W GN_ W GN_ Y GN_ Y GN_ Y GN_ Y GN_ EV@U_GPU_G_ J R EV@0K/F_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom NM(MEMORY I/F & GN) / ate: Friday, October, 00 Sheet of

17 E m (.0V /- % ) IFP_PLLV TP R0 EV@0K_ UF NM / IFP IFP_PLLV IFP_RSET IFP_TX0* IFP_TX0 IFP_TX* IFP_TX IFP_TX* IFP_TX V V Y W IFP_PLLV N TP M R EV@0K_ UG NM / IFPE IFP_PLLV IFP_RSET VI P IFP_UX* IFP_UX 0 m (.V) IFP_IOV R EV@0K_ V V IFP_IOV IFP_IOV T IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX V W W W IFPE_IOV H IFPE_IOV R EV@0K_ EV@U_GPU_G_ TX TX TX0 TX0 TX TX TX TX IFP_L* IFP_L IFP_L* IFP_L IFP_L* IFP_L IFP_L0* IFP_L0 E F F LOK IFP_TX* IFP_TX EV@U_GPU_G_ UH NM IFP_TX* IFP_TX U 0 m IFP_PLLV TP R0 EV@0K_ P R / IFP IFP_PLLV IFP_RSET VI P IFP_UX* IFP_UX G G _V R EV@0K_ TP TP W R V NM / _V _VREF _RSET _HSYN _VSYN _RE _GREEN _LUE U U T T R m (.0V /- % ) IFP_IOV J IFP_IOV TX TX TX0 TX0 TX TX IFP_L* IFP_L IFP_L* IFP_L IFP_L* IFP_L J H K L M M EV@U_GPU_G_.0V_GFX_PIE L LK_M_VG R0 EV@0K_ PLE UNER LLS EV@0.U/0V/XR_ EV@0.U/0V/XR_ EV@0.U/0V/XR_ EV@0.U/0V/XR_ EV@U/.V_ PLE NER LLS EV@U_GPU_G_ EV@LMEGSN(0,)_ R R TX IFP_L0* N TX IFP_L0 P NV_PLLV EV@0K/F_ 0m m m K K L *EV@0_ XTL_SSIN 0 UJ NM EV@U_GPU_G_ / XTL_PLL PLLV VI_PLLV SP_PLLV XTL_SSIN XTL_IN XTLOUT XTL_OUTUFF E E0 XTLOUT XTL_OUT Y EV@MHZ 0ppm R EV@0K/F_ R EV@0K/F_ IFPE_PLLV TP F UE NM / IFPE IFPE_PLLV(_V) IFP_RSET(_RSET) E VI P G IFPE_UX* IFPE_UX F E TX IFPE_L* TX IFPE_L E TX0 IFPE_L* TX0 IFPE_L TX IFPE_L* TX IFPE_L TX IFPE_L0* TX IFPE_L0 V_GPU R R EV@0K_ *EV@0.U/0V/XR_ *EV@0_ 0 m _VREF _RSET R00 *EV@/F V U NM / G _V _HSYN _VSYN F _VREF E _RSET _RE _GREEN _LUE EV@U_GPU_G_ E E TP TP0 TP TP TP EV@P/0V_ STUFF Ps on XTLSSIN and XTLOUTUFF WHEN EXT_SS Install it when not connected to Spread spectrum device EV@P/0V_ EV@U_GPU_G_ PROJET KL Quanta omputer Inc. Size ocument Number Rev ustom NM(ISPLY) / ate: Friday, October, 00 Sheet of