qt6a_d3a_0090_qim_d3a

Transcription

1 P STK UP QT LOK IGRM 0 able ocking PGE 0 L LYER : TOP LYER : SGN LYER : IN LYER : SGN LYER : SV LYER : IN LYER : SGN LYER : OT VG RJ- IR/Pwr btn SPIF Out Stereo MI Headphone Jack US Port VOL ntr SYSTEM HRGER(ISLHZ-T) PGE SYSTEM POWER ISLIRZ-T PGE R II SMR_VTERM.V/.VSUS(TPSREGR) PGE VP.V N GMH.0V(RT0) PGE RII-SOIMM RII /00 MHz PGE, ST - -ROM PGE E-ST RII-SOIMM PGE, ST - H PGE PGE ccelerometer PGE LISLV0L RII /00 MHz ST0 0M ST 0M ST 0M SMUS FS /00/0.KHz MI LINK LP PU Penryn P (upg)/w PGE, NORTH RIGE antiga PM,GM PGE ~ SOUTH RIGE IH-M.KHz PGE,,, M ONN PGE PI-Express X PU THERML SENSOR PGE US.0 0,,, US.0 Ports luetooth Webcam X PGE PGE PGE PI-E zalia PS0 PGE 0 nvii NM-GE NP-GS PGE ~ nalog ITH PGE LK_PU_LK,LK_PU_LK# LK_MH_LK,LK_MH_LK# REFLK,REFLK# REFSSLK,REFSSLK# MHz it it p NSRLK, NSRLK# Mini PI-E ard (Wireless LN/TV) ual Link HMI ON L ONN X X X PGE LN RT PGE 0 PGE 0 PGE Fingerpr PGE Realtek PIE-LN RTL0E/ (0/00/GagaLN) PGE,.MHz LOK GEN LPRS MLFPIN MHz Mini PI-E ard x Express ard x able ocking x R for UM RTSE PGE Express ard (NEW R) PGE PGE,,0, X.Hz JMIRO 0 for iscrete PGE VGORE(.0V)Oz PGE PU ORE ISL PGE Keyboard Touch Pad PGE apacitive Sense SW PGE ENE K K 0 PGE SPI PGE UIO mplifier TP0 PGE MHz RJ PGE IEEE connect for iscrete only PGE Memory ardreader PGE GMT GPU FN PGE 0 SPI PGE microphone PGE 0 udio Jacks (Phone/ MI) PGE 0 Jack to Speaker PGE N PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom lock iagram ate: Tuesday, February, 00 Sheet of

2 V L H0KF-T_ L V_K_PU H0KF-T_ V 0U/.V_ L H0KF-T_ 0U/.V_ R 0K/F_ TME 0=overclocking of PU and SR llowed = overclocking of PU and SR not llowed 0U/.V_.U/0V_ 0.U/0V_.U/0V_ [] PT_SM [] PLK_SM V_K_MIN.U/0V_ V_K_MIN.U/0V_ 0.U/0V_.U/0V_ Q MEN00E Q MEN00E V V Y G_XIN.MHZ 0 P/0V_.U/0V_.U/0V_ R 0K/F_ 0.U/0V_.U/0V_ [] K_PWG R 0K/F_ GT_SM GLK_SM G_XOUT P/0V_.U/0V_ *00K/F_ V_K_MIN V_K_PU V_K_MIN PU_SEL R R [0,,,,] GLK_SM [0,,,,] GT_SM G_XIN G_XOUT.K_ FS U VPLL V VPI VREF VSR VPU VI/O VPLLI/O VSRI/O VSRI/O VSRI/O VPU_IO N X X K_PWRG/P# FSL/TEST_MOE SLK ST GN GN GN GNPU GNPI GNREF 0 GNSR GNSR GNSR EP [,,,0,,,,,,0,,,,,,,,,,0,,,,,,,] V [,,,,,,,,,0,].0V PULKT0 PULK0 0 PULKT PULK PUT_ITP/SRT PU_ITP/SR OTT_/SRT0 0 OT_/SR0 MHz_Nonss/SRLK/SE Mhz_ss/SRL/SE SRLKT/STL SRLK/STL SRLKT/R#_ SRLK/R#_ SRLKT SRLK PI_STOP# PU_STOP# SRLKT SRLK SRLKT/R#_F SRLK/R#_E 0 SRLKT SRLK SRLKT0 SRLK0 K0 SRLKT/R#_H 0 SRLK/R#_G PILK0/R#_ PILK/R#_ 0 PILK/TME PILK PILK/_SELET PI_F/ITP_EN US_MHZ/FSL FSL/TST_SL/REF SLQT SR SR# SR0 SR0# SR SR# R_LK_NEWR_OE# R_LK_MH_OE# TME R_PLK_K M_SEL ITP_EN FS FS FSL LK_PU_LK [] LK_PU_LK# [] LK_MH_LK [] LK_MH_LK# [] LK_PIE_NEW [] LK_PIE_NEW# [] LK_PIE_R [] LK_PIE_R# [] LK_PIE_GPLL [] LK_PIE_GPLL# [] PM_STPPI# [] PM_STPPU# [] LK_PIE_IH [] LK_PIE_IH# [] LK_PIE_WLN [] LK_PIE_WLN# [] LK_PIE_LN [] LK_PIE_LN# [] LK_PIE_ST [] LK_PIE_ST# [] LK_PIE_TV [] LK_PIE_TV# [] R /F_ R0 /F_ R _ R _ SR SR# SR0 SR0# SR SR# R _ R0 _ R0 *_ R.K_ PU_SEL0 R 0K/F_ PU_SEL R _ RP RP RP RP0 RP discrete discrete LK_NEWR_OE# [] LK_MH_OE# [] PLK_EUG [] PLK_K [] *PR-S-0 *PR-S-0 PR-S-0 *PR-S-0 PR-S- PLK_IH [] LK_M_US [] LK_M_R [] LK_M_IH [] 0 LK_PU_ITP [] LK_PU_ITP# [] REFLK [] REFLK# [] LK_PIE_VG [] LK_PIE_VG# [] REFSSLK [] REFSSLK# [] M_NONSS [] M_SS [] V hange to p des R 0K/F_ M_SEL R *0K/F_ M_SEL PIN 0=UM PIN0 OTT PIN OT PIN SRT/LT_00 PIN SRT/LT_00 = External VG SRT0 SR0 Mout-NSS Mout-SS K0 IS Silego Realtek QFN ISLPRSKLF SLGSPVTR RTMN-0-V-GR LPRS000 LSP000 L LK_MH_OE# R LK_NEWR_OE# R V 0K/F_ 0K/F_ 0=UM = External VG V *0K/F_ R ITP_EN 0K/F_ R Enable ITP LK R_PLK_K R *0K/F_ PU lock select.0v.0v [] PU_SEL0 PU_SEL R 0_ [] PU_SEL MH_SEL [] PU_SEL R 0_ [] PU_SEL MH_SEL [] R R R *K/F_ *K/F_ *K/F_ PU_SEL0 R 0_ K to N only when XP is implement.no XP can use 0 ohm MH_SEL0 [] FS FS FS PU SR PI RSV 00 N 0 *P/0V_ 0 *P/0V_ *P/0V_ *0P/0V_ *0P/0V_ 0 *P/0V_ for EMI PLK_K PLK_IH PLK_EUG LK_M_US LK_M_R LK_M_IH PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom lock Generator ate: Tuesday, February, 00 Sheet of

3 ITP_TI ITP_TMS ITP_TK ITP_TO ITP_TRST# H_PURST# ITP_TK *00P/0V_.0V R0 R0 */F_ *./F_ R R0./F_./F_ [] LK_PU_ITP# [] LK_PU_ITP Populate ITP00Flex for bringup R R GROUP 0 R GROUP IH ONTROL XP/ITP SIGNLS./F_ ITP_TK ITP_TRST#.0V SYS_RST# ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# ITP_PM# ITP_PM# *.U/0V_ *.U/0V_ SI- R *./F_.0V GTLREF_TL.0V.0V R */F_ T GRP 0 T GRP R */F_ ITP_PM#0 ITP_PM# ITP_PM# ITP_PM# [,,,,,,,,,0,] GT^00000 GT^0000 U [] H_#[:] H_# J H_# []# S# H H_S# [] [] H_#[:0] L U H_#[:0] H_# []# NR# E H_NR# [] L H_#0 H_# H_# []# PRI# G H_PRI# [] E H_# [0]# []# Y K H_# H_# []# F H_# []# []# M H_# H_# []# EFER# H H_EFER# [] E H_# []# []# V N H_# H_# []# RY# F H_RY# [] G H_# []# []# V J H_# H_#0 []# SY# E H_SY# [] F H_# []# []# V N H_# H_# [0]# G H_# []# []# T P H_# H_# []# R0# F HREQ#0 [] E H_# []# []# U P H_# H_# []# E H_IERR# H_# []# []# U L H_#0 H_# []# IERR# 0 R./F_.0V K H_# []# [0]# Y P H_# H_# []# INIT# H_INIT# [] G H_#0 []# []# W P H_# H_# []# J H_# [0]# []# Y R H_# []# LOK# H H_LOK# [] J H_# []# []# W H_# [] H_ST#0 M ST[0]# H_PURST# [] H H_# []# []# W H_# [] H_REQ#[:0] H_REQ#0 RESET# F H_RS#0 H_# []# []# K H_# H_REQ# REQ[0]# RS[0]# F K H_RS# H_# []# []# H H_# H_REQ# REQ[]# RS[]# F H H_RS# []# []# K H_REQ# REQ[]# RS[]# G H_RS#[:0] [] [] H_STN#0 J STN[0]# STN[]# Y H_STN# [] J H_TRY# [] [] H_STP#0 H_REQ# REQ[]# TRY# G H STP[0]# STP[]# H_STP# [] L H_#[:] REQ[]# [] H_INV#0 H INV[0]# INV[]# U H_INV# [] H_HIT# [] H_# HIT# G Y H_#[:0] H_#[:0] H_HITM# [] H_# []# HITM# E U H_# H_# H_# []# N ITP_PM#0 H_# []# []# E R H_# H_#0 []# PM[0]# K ITP_PM# H_# []# []# W H_#0 H_# [0]# PM[]# P ITP_PM# H_# []# [0]# U H_# H_# []# PM[]# R ITP_PM# H_#0 []# []# Y H_# H_# []# PM[]# L ITP_PM# H_# [0]# []# U H_# H_# []# PRY# M ITP_PM# H_# []# []# R L H_# H_# []# PREQ# ITP_TK H_# []# []# 0 T M H_# H_# []# TK ITP_TI SI- H_# []# []# E T P H_# H_# []# TI ITP_TO H_# []# []# F W P H_# H_# []# TO ITP_TMS H_# []# []# W P H_# H_# []# TMS ITP_TRST# H_# []# []# E Y T H_# H_#0 []# TRST# H_# []# []# U H_#0 SYS_RST# [] R H_# [0]# R# 0 H_# []# [0]# V L H_# H_# []#.0V H_#0 []# []# W R *0_ H_# H_PROHOT# [] T H_# []# dd R H_# [0]# []# F N H_# H_# []# THERML []# []# [] H_STN# L H_STN# [] H_# []# PROHOT# STN[]# STN[]# E R _.0V R []# PROHOT# [] H_STP# M STP[]# STP[]# F H_STP# [] [] H_ST# V K/F_ ST[]# THERM H_THERM [] [] H_INV# N INV[]# INV[]# 0 H_INV# [] THERM H_THERM [] H_GTLREF OMP0 [] H_0M# PU_TEST GTLREF OMP[0] R R./F_ 0M# OMP [] H_FERR# PM_THRMTRIP# [,] MIS PU_TEST TEST OMP[] U R./F_ FERR# THERMTRIP# R OMP [] H_IGNNE# PU_TEST TEST OMP[] R./F_ IGNNE# K/F_ OMP TP PU_TEST TEST OMP[] Y R./F_ [] H_STPLK# STPLK# H LK TP F PU_TEST TEST [] H_INTR LINT0 TP F H_PRSTP# [,,] PU_TEST TEST PRSTP# E [] H_NMI LINT LK[0] LK_PU_LK [] TP H_PSLP# [] PU_TEST TEST PSLP# [] H_SMI# SMI# LK[] LK_PU_LK# [] TP TEST PWR# H_PWR# [] [] PU_SEL0 SEL[0] PWRGOO H_PWRG [] For Q PU Quard ore Only [] PU_SEL SEL[] SLP# H_PUSLP# [].0V R */F_ F TI_/RSV RSV[0] [] PU_SEL SEL[] PSI# E PM_PSI# [] TO_/RSV Penryn all-out Rev a ITP_PM#0 N R -->.K for Quad ore ITP_PM# MP_#[0]/RSV M PU_TEST R *K/F_ ITP_PM# MP_#[]/RSV ITP_PM# MP_#[]/RSV E MP_#[]/VSS PU_TEST TP R *K/F_ GTLREF_TL LKPH_/VSS F.0V H_GTLREF LKPH_/VSS For Q Support H_THERM GTLREF_/RSV [] H_THERM T H_THERM THRM_/RSV [] H_THERM V R0 THRM_/RSV HFPLL_/VSS on't install for hange to V *K/F_ TP TP SPRE_[]/VSS V TP R#/V SI- H_GTLREF Penryn all-out Rev a R *K/F_ R JITP TI TMS TK TO TRST# ITP_RST# RESET# FO LKN LKP 0 GN0 GN GN GN 0 GN GN *ITP00Flex./F_ VTT0 VTT VTP R# # PM0# PM# PM# PM# PM# PM# N0 N GN_0 GN_ 0 R */F_ R *0K/F_ R */F_ R0 *0K/F_ T GRP T GRP R *00K/F_ Q *MMT0--F ITP_PM#0 R ITP_PM# R ITP_PM# R ITP_PM# R.0V Q0 *MEN00E *0_ ITP_PM#0 *0_ ITP_PM# *0_ ITP_PM# *0_ ITP_PM# N R *K/F_ 0 PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom Penryn / ate: Tuesday, February, 00 Sheet of

4 MLK MT SYS_SHN-# PM_THRM_R# VORE 0 0 U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_.0V For Q 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ U *EM-0 0 SLK V LMV S P H_THERM LERT# N H_THERM OVERT# P H_THERM [] GN N *00P/0V_ H_THERM [] R 0K/F_ R 0K/F_ [,,,0,,,,,,0,,,,,,,,,,0,,,,,,,] V [,,,,,,,,,0,].0V VORE [,,,,,,,,0,].V VORE [] VORE U U V[00] V[0] 0 V[00] V[0] VSS[00] VSS[0] P 0 V[00] V[00] VSS[00] VSS[0] P V[00] V[0] VSS[00] VSS[0] P V[00] V[0] VSS[00] VSS[0] R V[00] V[0] VSS[00] VSS[0] R V[00] V[0] VSS[00] VSS[0] R V[00] V[0] VSS[00] VSS[0] R 0 V[00] V[0] F VSS[00] VSS[0] T V[00] V[0] VSS[00] VSS[00] T V[0] V[0] VSS[00] VSS[0] T 0 V[0] V[0] 0 VSS[0] VSS[0] T V[0] V[00] VSS[0] VSS[0] U V[0] V[0] VSS[0] VSS[0] U V[0] V[0] VSS[0] VSS[0] U V[0] V[0] VSS[0] VSS[0] U V[0] V[0] VSS[0] VSS[0] V 0 V[0] V[0] E VSS[0] VSS[0] V V[0] V[0] E0 VSS[0] VSS[0] V 0 V[00] V[0] E VSS[0] VSS[00] V V[0] V[0] E VSS[00] VSS[0] W V[0] V[0] E VSS[0] VSS[0] W V[0] V[00] E VSS[0] VSS[0] W V[0] V[0] E VSS[0] VSS[0] W V[0] V[0] E0 VSS[0] VSS[0] Y V[0] V[0] F VSS[0] VSS[0] Y 0 V[0] V[0] F0 VSS[0] VSS[0] Y V[0] V[0] F VSS[0] VSS[0] Y V[0] V[0] F VSS[0] V[00] V[0] F VSS[0] VSS[0] V[0] V[0] F VSS[00] V[0] V[0] F.0V VSS[0] VSS[] E V[0] V[00] F0 VSS[0] VSS[] E V[0] VSS[0] VSS[] E0 V[0] VP[0] G VSS[0] VSS[] E V[0] VP[0] V E VSS[0] VSS[] E V[0] VP[0] J E VSS[0] VSS[] E V[0] VP[0] K E 0 VSS[0] VSS[] E V[0] VP[0] M E *0u_V_ VSS[0] VSS[] E V[00] VP[0] J E VSS[0] VSS[0] E0 V[0] VP[0] K E VSS[00] VSS[] F V[0] VP[0] M E.V VSS[0] VSS[] F V[0] VP[0] N E VSS[0] VSS[] F0 V[0] VP[0] N E VSS[0] VSS[] F V[0] VP[] R F VSS[0] VSS[] F V[0] VP[] R VSS[] F V[0] VP[] T F VSS[0] VSS[] F V[0] VP[] T F 0 0 VSS[0] VSS[] F V[0] VP[] V F.0U/V_ 0U/.V_ VSS[0] F0 V[00] VP[] W F VSS[0] VSS[0] F VSS[00] VSS[] V[0] V[0] F VSS[0] VSS[] 0 V[0] V[0] F VSS[0] VSS[] V[0] G VSS[0] VSS[] V[0] VI[0] PU_VI0 [] G VSS[0] VSS[] V[0] VI[] F PU_VI [] G VSS[0] VSS[] V[0] VI[] E PU_VI [] G VSS[0] VSS[] V[0] VI[] F PU_VI [] H VSS[0] VSS[] 0 V[0] VI[] E PU_VI [] H VSS[0] VSS[] V[00] VI[] F PU_VI [] H VSS[0] VSS[0] 0 V[0] VI[] E PU_VI [] H VSS[00] VSS[] 0 V[0] J VSS[0] VSS[] V[0] J VSS[0] VSS[] V[0] VSENSE F VSENSE [] J VSS[0] VSS[] V[0] J VSS[0] VSS[] E V[0] K VSS[0] VSS[] E V[0] VSSSENSE E VSSSENSE [] K VSS[0] K VSS[0] VSS[] E Penryn all-out Rev a K R R VSS[0] VSS[] E. L 00/F_ VSS[0] VSS[0] E 00/F_ L VSS[00] VSS[] E L VSS[0] VSS[] E L VSS[0] VSS[] E M VSS[0] VSS[] M V VSS[0] VSS[] F M SI- VSS[0] VSS[] F M VORE VSS[0] VSS[] F N VSS[0] VSS[] F N VSS[0] VSS[] F N R VSS[0] VSS[0] F N 0_ R *0_ VSS[00] VSS[] F SYS_SHN# [,] P VSS[0] VSS[] VSS[] F mils LMV Penryn all-out Rev a. *R0V-0 R 0K/F_.U/0V_ 0 [,] MLK [,] MT MLK MT U SLK S LERT# OVERT# LMIMM RESS: H V XP XN GN 00P/0V_ H_THERM [] H_THERM [] R0 0_ Q MMT0--F R0V-0 R 0K/F_ 0_RST# [,] EPWROK [,,] V PM_THRM_R# 0_ R PM_THRM# [] SYS_SHN-# 0 *R0V-0 VG_OVT# [] N PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom Penryn & TH Monitor / ate: Tuesday, February, 00 Sheet of

5 H_# H_# H_# H_#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_REQ#0 H_REQ# H_# H_# H_# H_REQ# H_REQ# H_# H_# H_# H_REQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_SWING H_ROMP H_VREF H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_SWING H_VREF H_ROMP H_RS#0 H_RS# H_RS# H_REQ#[:0] [] H_#[:0] [] H_#[:] [] H_S# [] H_RY# [] H_SY# [] H_EFER# [] H_NR# [] H_PRI# [] HREQ#0 [] H_ST#0 [] H_ST# [] LK_MH_LK [] LK_MH_LK# [] H_PWR# [] H_HITM# [] H_HIT# [] H_LOK# [] H_TRY# [] H_INV# [] H_INV# [] H_INV# [] H_INV#0 [] H_STN# [] H_STN# [] H_STN# [] H_STN#0 [] H_PURST# [] H_STP# [] H_STP# [] H_STP# [] H_STP#0 [] H_PUSLP# [] H_RS#[:0] [].0V [,,,,,,,,,0,].0V.0V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Host & VSS / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Host & VSS / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Host & VSS / ustom Tuesday, February, 00 0 R -->. ohm for Quad ore R --> ohm for Quad ore R K/F_ R K/F_ VSS VSS NTF VSS S N U0J NTIG_PM VSS VSS NTF VSS S N U0J NTIG_PM VSS_ G VSS_0 W VSS_0 U VSS_0 P VSS_0 N VSS_0 H VSS_0 F VSS_0 VSS_0 R VSS_0 M VSS_0 J VSS_ G VSS_ 0 VSS_ 0 VSS_ W0 VSS_ T0 VSS_ J0 VSS_ G0 VSS_ Y0 VSS_ N0 VSS_0 K0 VSS_ F0 VSS_ 0 VSS_ 0 VSS_ G VSS_ VSS_ G VSS_ VSS_ W VSS_ T VSS_0 R VSS_ M VSS_ H VSS_ VSS_ VSS_ U VSS_ N VSS_ N VSS_0 K VSS_ G VSS_ E VSS_ G VSS_ W VSS_ VSS_ G VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 G VSS_ E VSS_ F VSS_ V VSS_ T VSS_ M VSS_ VSS_ J VSS_ VSS_ VSS_0 VSS_ Y VSS_ N VSS_ H VSS_ Y VSS_ N VSS_ G VSS_ VSS_ G0 VSS_0 V0 VSS_ T0 VSS_ J0 VSS_ E0 VSS_ 0 VSS_ H VSS_ VSS_ G VSS_0 VSS_ M VSS_ N VSS_ VSS_ M0 VSS_ F VSS_ H VSS_ Y VSS_ L VSS_00 E VSS_0 VSS_0 Y VSS_0 U VSS_0 N VSS_0 J VSS_0 E VSS_0 VSS_0 N VSS_0 J VSS_0 G VSS_ VSS_ V VSS_ T VSS_ VSS_ M VSS_ M VSS_ VSS_ VSS_ H VSS_ VSS_0 Y VSS_ L VSS_ J VSS_ H VSS_ F VSS_ E VSS_ VSS_ V VSS_ L VSS_NTF_ F VSS_NTF_ VSS_NTF_ V VSS_NTF_ J0 VSS_NTF_ M VSS_NTF_ F VSS_NTF_ VSS_NTF_ U VSS_NTF_ U VSS_NTF_0 L0 VSS_NTF_ V0 VSS_NTF_ VSS_NTF_ L VSS_NTF_ J VSS_NTF_ VSS_NTF_ U VSS_S_ H VSS_S_ H VSS_S_ VSS_S_ VSS_S_ N_ E N_ N_ N_ N_0 N_ N_ N_ N_ N_ N_ N_ N_ N_ F N_0 E N_ N_ VSS_0 R VSS_ P VSS_ VSS_ R VSS_ U VSS_ P VSS_ F VSS_ W VSS_ E VSS_0 F VSS_ H VSS_ J VSS_ VSS_ VSS_ Y VSS_ M VSS_ K VSS_ M VSS_ VSS_ P VSS_0 H VSS_ VSS_ V VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_00 L.U/0V_.U/0V_ HOST U0 NTIG_PM HOST U0 NTIG_PM H_#_0 P H_#_ R H_#_ N H_#_ M H_#_ E H_#_ P H_#_ F H_#_ G0 H_#_ H_#_ J H_#_0 E0 H_#_ H H_#_ J0 H_#_ L H_#_ H_#_ H_#_ L H_#_ H_#_ J H_#_ H0 H_#_ H_#_0 H_#_ K H_#_ H_#_ F H_#_ H H_#_ H_#_ M H_#_ J H_S# H H_ST#_0 H_ST#_ G H_NR# H_PRI# F H_REQ# G HPLL_LK# H H_PURST# HPLL_LK H H_#_0 F H_REQ#_ F H_REQ#_ H_#_ G H_#_0 M H_#_0 L H_#_0 N0 H_#_0 H_#_0 H_#_0 E H_#_ H_#_ H H_SY# 0 H_#_ M H_#_ J H_#_ J H_#_ N H_#_ J H_#_ P H_#_ L H_#_ R H_#_ N H_#_ F H_#_ M H_#_ J H_#_ N H_#_ R H_#_ N H_#_ N H_#_ P H_#_ N H_#_ L H_#_ E H_#_ M H_#_ Y H_#_ H_#_ Y H_#_ Y0 H_#_ Y H_#_ Y H_#_ Y H_#_ W H_#_ G H_#_ Y H_#_ H_#_ H_#_ H_#_ H_#_ 0 H_#_ H_#_ E H_#_ E H_#_ H H_#_ H_#_ H_#_ H_#_ H_#_ E H_#_ F H_#_ H_#_ E H_#_ H_#_ H H_#_ E H_#_ G H_#_ H_#_ F H_EFER# E H_INV#_0 J H_INV#_ L H_INV#_ Y H_INV#_ Y H_PWR# J H_RY# F H_STN#_0 L0 H_STN#_ M H_STN#_ H_STN#_ E H_STP#_0 L H_STP#_ M H_STP#_ H_STP#_ E H_VREF H_VREF H_TRY# H_HIT# H H_HITM# E H_LOK# H H_REQ#_0 H_REQ#_ K H_REQ#_ H_#_ 0 H_#_ F H_#_ K H_#_ L0 H_SWING H_PUSLP# E H_ROMP E H_RS#_0 H_RS#_ F H_RS#_ VSS U0I NTIG_PM VSS U0I NTIG_PM VSS_ U VSS_ VSS_ R VSS_ L VSS_ VSS_ W VSS_ N VSS_ J VSS_ F VSS_ VSS_0 VSS_ Y VSS_ T VSS_ N VSS_ L VSS_ G VSS_ VSS_ VSS_ V VSS_0 R VSS_ M VSS_ V VSS_ R VSS_ P VSS_ H VSS_ F VSS_ F VSS_ H VSS_ VSS_0 VSS_ Y VSS_ U VSS_ T VSS_ M VSS_ F VSS_ VSS_ V VSS_ U VSS_ M VSS_0 J VSS_ VSS_ G VSS_ Y VSS_ T VSS_ N VSS_ J VSS_ E VSS_ N VSS_ L VSS_0 VSS_ U VSS_ M VSS_ H VSS_ VSS_ VSS_ Y VSS_ U VSS_ T VSS_ M VSS_0 G VSS_ VSS_ G0 VSS_ 0 VSS_ V0 VSS_ N0 VSS_ H0 VSS_ E0 VSS_ T VSS_ M VSS_0 J VSS_ E VSS_ N VSS_ L VSS_ VSS_ H VSS_ VSS_ VSS_ U VSS_ H VSS_0 VSS_ VSS_ Y VSS_ U VSS_ T VSS_ J VSS_ F VSS_ VSS_ VSS_00 M VSS_0 E VSS_0 P VSS_0 L VSS_0 J VSS_0 F VSS_0 VSS_0 H VSS_0 VSS_0 Y VSS_0 U VSS_ T VSS_ F VSS_ M VSS_ J VSS_ F VSS_ E VSS_ W VSS_ VSS_ VSS_0 G VSS_ VSS_ VSS_ V VSS_ R VSS_ L VSS_ H VSS_ VSS_ P VSS_ L VSS_0 H VSS_ N VSS_ K VSS_ F VSS_ VSS_ VSS_ N VSS_ T VSS_ N VSS_ K VSS_0 H VSS_ F VSS_ VSS_ G VSS_ VSS_ VSS_ V VSS_ T VSS_ R VSS_ J VSS_0 G VSS_ E VSS_ VSS_ Y VSS_ P VSS_ K VSS_ H VSS_ F VSS_ VSS_ F VSS_0 H VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ H VSS_ VSS_ VSS_ V VSS_0 R VSS_ J VSS_ VSS_ Y VSS_ N VSS_ L VSS_ J VSS_ G VSS_ E VSS_ F VSS_ F VSS_ VSS_0 W VSS_ T VSS_ N VSS_ J VSS_ H VSS_ VSS_ G VSS_ U VSS_ T VSS_ H VSS_ VSS_ L VSS_ Y VSS_ G VSS_ E VSS_ G VSS_ VSS_ Y VSS_ J VSS_ F VSS_ R VSS_ K VSS_0 J VSS_ F VSS_ H VSS_ Y VSS_ K VSS_0 VSS_ J.U/0V_.U/0V_ R./F_ R./F_ R /F_ R /F_ R K/F_ R K/F_ R 00/F_ R 00/F_

6 MH_FG_ MIx selection Low = MI X High = MI X (efault) MH_FG_ FS ynamic OT Low = ynamic OT disabled High = ynamic OT enabled (default) MH_FG_ PI Express Graphic Lane Low: Reverse Lane High: Normal operation(efault) MH_FG_ MI Lane Reversal Low = Normal operation (efault) High = Reverse Lanes MH_FG_ itpm Host Interface Low =The ITPM Host Interface is enabled High = The ITPM Host Interface is disabled (default) MH_FG_ Intel (R) Management Engine rypto Low: Intel (R) Management Engine rypto TLS cipher suite with no confidentiality High: Intel (R) Management Engine rypto TLS cipher suite with no confidentiality (efault) MH_FG_0 PIe Lookback Enable Low = Enabled High: isabled (efault) MH_FG_/ XOR/LLZ/LOK Un-gating MH_FG_ MH_FG_ onfiguration 0 0 Reserved 0 XOR Mode enabled 0 ll-z Mode enabled Normal operation (efault) MH_FG_0 igital isplay Port (SVO/P/iHMI) oncurrent with PIE Low = Only digital display port (SVO/P/iHMI) or PIE is operational (default) High = igital display port (SVO/P/iHMI) and PIE are operating simultaneously via the PEG port MH_FG:0 000 = FS0 00 = FS00 0 = FS Others = Reserved [,] [] [] [] [] PM_SYN# [,,] H_PRSTP# [0,] PM_EXTTS#0 [] PM_EXTTS# ELY_VR_PWRGOO [,] PLT_RST-R# [,] PM_THRMTRIP# [,] PRSLPVR V R R0 MH_SEL0 MH_SEL MH_SEL TP TP TP TP0 TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP 0K/F_ 0K/F_ Z_ITLK_MH R *_ R0 *P/0V_ 00/F_ PM_EXTTS#0 PM_EXTTS# TP TP TP TP MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_ MH_FG_0 PM_EXTTS#0 PM_EXTTS# RST_IN#_MH M N R T H H0 H H K T M Y G F H F L K N M T R P P0 P N M E N P T R0 M0 L H P R T R N P T0 T T0 R U0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV ME_JTG_TK ME_JTG_TI ME_JTG_TO ME_JTG_TMS FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_ FG_0 PM_SYN# PM_PRSTP# PM_EXT_TS#_0 PM_EXT_TS#_ PWROK RSTIN# THERMTRIP# PRSLPVR G N_ F N_ N_ N_ H N_ G N_ E N_ H N_ F N_ G N_0 H N_ H N_ H N_ H N_ G N_ H N_ F N_ H N_ G N_ E N_0 G N_ F N_ N_ N_ F N_ N_ NTIG_PM RSV ME JTG FG PM N R LK/ ONTROL/OMPENSTION LK MIS MI GRPHIS VI ME H S_K_0 S_K_ S_K_0 S_K_ S_K#_0 S_K#_ S_K#_0 S_K#_ S_KE_0 S_KE_ S_KE_0 S_KE_ S_S#_0 S_S#_ S_S#_0 S_S#_ S_OT_0 S_OT_ S_OT_0 S_OT_ SM_ROMP SM_ROMP# SM_ROMP_VOH SM_ROMP_VOL SM_VREF SM_PWROK SM_REXT SM_RMRST# PLL_REF_LK PLL_REF_LK# PLL_REF_SSLK PLL_REF_SSLK# PEG_LK PEG_LK# MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ GFX_VI_0 GFX_VI_ GFX_VI_ GFX_VI_ GFX_VI_ GFX_VR_EN L_LK L_T L_PWROK L_RST# L_VREF P_TRLLK P_TRLT SVO_TRLLK SVO_TRLT LKREQ# IH_SYN# TSTN# H_LK H_RST# H_SI H_SO H_SYN P T V U0 R R U V0 Y Y Y V R Y F Y G H F H SM_ROMP_VOH SM_ROMP_VOL V 0.VSMVREF_MH R SW_PWROK_N F SM_REXT TP_SM_RMRST# E F F E E E E H E0 E E H0 E E E H E F H G F E H H N J H N M G E K H 0 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP GFXVR_VI_0 GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ GFXVR_VI_ GFXVR_EN P_TRLLK PP_TRLT MH_TSTN Z_SIN_MH M LK0 [0] M LK [0] M LK0 [0] M LK [0] M LK0# [0] M LK# [0] M LK0# [0] M LK# [0] M KE0 [0,] M KE [0,] M KE0 [0,] M KE [0,] M S#0 [0,] M S# [0,] M S#0 [0,] M S# [0,] M OT0 [0,] M OT [0,] M OT0 [0,] M OT [0,] SM_ROMP R SM_ROMP# R0 REFLK [] REFLK# [] REFSSLK [] REFSSLK# [] LK_PIE_GPLL [] LK_PIE_GPLL# [] MI_TXN[:0] [] MI_TXP[:0] [] MI_RXN[:0] [] MI_RXP[:0] [] TP TP TP TP TP0 TP L_LK0 [] L_T0 [] EPWROK [,,] 0. V L_RST#0 [] MH_LVREF R00 R R0 TP [,,,0,,,,,,0,,,,,,,,,,0,,,,,,,] [,,0,,0,] [,,,,,,,,,0,] [,,,,,,,,,0,].VSUS [,] [,] [,,] [,,] [,] PST_PWM LVS_LON Z_ITLK_MH [] Z_RST#_MH [] Z_SIN [] Z_SOUT_MH [] Z_SYN_MH [] EILK EIT ISP_ON [,0] LK [,0] T [,0] HSYN_OM [,0].0V [,0] [,0] [,0] R.U/0V_ /F_ TP TP SVO_LK [0] SVO_T [0] LK_MH_OE# [] MH_IH_SYN# [].0V./F_ R 0_ 0./F_ 0./F_ 0K/F_ /F_ RT_ RT_G RT_R VSYN_OM R K/F_ V R R R R R0 R [] [] [] [] [] [] [] [] [] [] [] [] R R [] [] [] [] R R R SM_ROMP_VOH SM_ROMP_VOL 0.VSMVREF_MH *0K/F_ *0_ *0_ L_TRL_T EILK_INT EIT_INT *0_ ISP_ON_INT *.K/F_LVS_IG LVS_VG TP0 L_LK# L_LK L_LK# L_LK L_TN0 L_TN L_TN TP L_TP0 L_TP L_TP TP L_TN0 L_TN L_TN TP L_TP0 L_TP L_TP TP hange to ohm to GN R R *0_ *0_ hange to 0 ohm to GN.U/0V_ R R R R R R R R R R0 R0 *0_ *0/F_ *0_ *0/F_ *0_ *0/F_ L_TN L_TP L_TN L_TP TV_OMP TV_Y/G TV_/R RT RT_R_ *0_ LK_INT *0_ T_INT *_ HSYN_INT *.0K/F_ RTIREF *_ VSYN_INT.VSUS V.VSUS.0V.0V_PEG *0_ PST_PWM_INT *0_ LVS_LON_INT *0K/F_ L_TRL_LK *0_ *0_ *0_ 0P/0V_.0U/V_.0U/V_ TV_ONSEL0 TV_ONSELE RT_G_ HP SVTP TEST R *K/F_ L G M M K J M E E 0 H E G0 0 H F0 0 H G J G F K F H K H E G J G H J J E L.U/.V_.U/.V_ R 0_ *K/F_ U0 L_KLT_TRL L_KLT_EN L_TRL_LK L_TRL_T L LK L T L_V_EN LVS_IG LVS_VG LVS_VREFH LVS_VREFL LVS_LK# LVS_LK LVS_LK# LVS_LK LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ LVS_T#_0 LVS_T#_ LVS_T#_ LVS_T#_ LVS_T_0 LVS_T_ LVS_T_ LVS_T_ TV_ TV_ TV_ TV_RTN TV_ONSEL_0 TV_ONSEL_ RT_LUE RT_GREEN RT_RE RT_IRTN RT LK RT T RT_HSYN RT_TVO_IREF RT_VSYN NTIG_PM.VSUS R K/F_ R.0K/F_ R K/F_ R LVS TV VG [0] 0.VSMVREF [0,] PEG_TX#[:0] PEG_TX[:0] PEG_RX#[:0] PEG_RX[:0] PI-EXPRESS GRPHIS PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX#[:0] [] PEG_TX[:0] [] PEG_RX#[:0] [] PEG_RX[:0] [] PEG_OMP PEG_TX RP *PR-S-0 IN_LK [0] PEG_TX# IN_LK# [0],,0, Need to install for GM,,0, Level: 0.V V R *0K/F_ HMI_HP# HMI_HP_ON PEG_OMPI PEG_OMPO PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_0 PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX#_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_0 PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_RX_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_0 PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX#_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_0 PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ PEG_TX_ T T For UM HMI Function RP *PR-S-0 RP RP0 HP# Inverting Level Shifting ircuit 0.0V_PEG H PEG_RX#0 J PEG_RX# L PEG_RX# L0 PEG_RX# N PEG_RX# P PEG_RX# N PEG_RX# T PEG_RX# U PEG_RX# Y PEG_RX# Y PEG_RX#0 Y PEG_RX# PEG_RX# PEG_RX# PEG_RX# PEG_RX# H PEG_RX0 J PEG_RX L PEG_RX R L PEG_RX HMI_HP# N0 PEG_RX P PEG_RX *0_ N PEG_RX T PEG_RX U PEG_RX Y PEG_RX W PEG_RX0 Y PEG_RX PEG_RX PEG_RX PEG_RX 0 PEG_RX J _PEG_TX#0.U/0V_ PEG_TX#0 M _PEG_TX#.U/0V_ PEG_TX# M _PEG_TX# 0.U/0V_ PEG_TX# M0 _PEG_TX#.U/0V_ PEG_TX# M _PEG_TX#.U/0V_ PEG_TX# R _PEG_TX#.U/0V_ PEG_TX# N _PEG_TX#.U/0V_ PEG_TX# T0 _PEG_TX#.U/0V_ PEG_TX# U _PEG_TX#.U/0V_ PEG_TX# U0 _PEG_TX#.U/0V_ PEG_TX# Y0 _PEG_TX#0.U/0V_ PEG_TX#0 _PEG_TX#.U/0V_ PEG_TX# _PEG_TX#.U/0V_ PEG_TX# 0 _PEG_TX#.U/0V_ PEG_TX# _PEG_TX#.U/0V_ PEG_TX# _PEG_TX# 0.U/0V_ PEG_TX# J _PEG_TX0.U/0V_ PEG_TX0 L _PEG_TX.U/0V_ PEG_TX M _PEG_TX 0.U/0V_ PEG_TX M _PEG_TX.U/0V_ PEG_TX M _PEG_TX.U/0V_ PEG_TX R _PEG_TX.U/0V_ PEG_TX N _PEG_TX.U/0V_ PEG_TX T _PEG_TX.U/0V_ PEG_TX U _PEG_TX.U/0V_ PEG_TX U _PEG_TX.U/0V_ PEG_TX Y _PEG_TX0.U/0V_ PEG_TX0 Y _PEG_TX.U/0V_ PEG_TX _PEG_TX.U/0V_ PEG_TX _PEG_TX.U/0V_ PEG_TX _PEG_TX.U/0V_ PEG_TX _PEG_TX.U/0V_ PEG_TX dis *PR-S-0 *PR-S-0 R *00K/F_ R./F_ Q *MEN00E IN_ [0] IN_# [0] IN_ [0] IN_# [0] IN_0 [0] IN_0# [0] R0 *.K/F_ PROJET : QT Quanta omputer Inc.

7 0 [0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U0 J S_Q_0 J S_Q_ N S_Q_ M S_Q_ J S_Q_ J0 S_Q_ M S_Q_ M S_Q_ N S_Q_ N S_Q_ U0 S_Q_0 T S_Q_ N S_Q_ N S_Q_ U S_Q_ U S_Q_ V S_Q_ Y S_Q_ 0 S_Q_ S_Q_ V S_Q_0 Y S_Q_ S_Q_ 0 S_Q_ Y S_Q_ S_Q_ V S_Q_ T S_Q_ Y S_Q_ S_Q_ V S_Q_0 W S_Q_ S_Q_ U S_Q_ S_Q_ S_Q_ U S_Q_ V S_Q_ S_Q_ S_Q_ S_Q_0 S_Q_ U0 S_Q_ V S_Q_ S_Q_ S_Q_ Y S_Q_ S_Q_ V S_Q_ V S_Q_ T S_Q_0 N S_Q_ U S_Q_ U S_Q_ T S_Q_ N0 S_Q_ M S_Q_ M S_Q_ J S_Q_ J S_Q_ N S_Q_0 M S_Q_ J S_Q_ J S_Q_ NTIG_PM R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_RS# S_S# S_WE# S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_QS_0 S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS_ S_QS#_0 S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_QS#_ S_M_0 S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_ S_M_0 S_M_ S_M_ S_M_ S_M_ G T 0 0 Y0 M T Y U Y T J J T W U M J T Y U M M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M G M H M G M M M G M F M W M M 0 G M H M H M Y M M S#0 [0,] M S# [0,] M S# [0,] M RS# [0,] M S# [0,] M WE# [0,] M M[:0] [0] M QS[:0] [0] M QS#[:0] [0] M [:0] [0,] [0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U0E K S_Q_0 H S_Q_ P S_Q_ P S_Q_ J S_Q_ J S_Q_ M S_Q_ P S_Q_ U S_Q_ U S_Q_ S_Q_0 Y S_Q_ T S_Q_ R S_Q_ S_Q_ S_Q_ S_Q_ S_Q_ G S_Q_ F S_Q_ E S_Q_0 S_Q_ F0 S_Q_ F S_Q_ G S_Q_ F S_Q_ H S_Q_ G S_Q_ H0 S_Q_ G S_Q_ G S_Q_0 H S_Q_ H S_Q_ G S_Q_ H S_Q_ G S_Q_ H S_Q_ F S_Q_ F S_Q_ G S_Q_ S_Q_0 S_Q_ Y S_Q_ Y S_Q_ F S_Q_ F S_Q_ S_Q_ S_Q_ V S_Q_ U S_Q_ R S_Q_0 N S_Q_ Y S_Q_ V S_Q_ P S_Q_ R S_Q_ L S_Q_ L S_Q_ J S_Q_ H S_Q_ M S_Q_0 M S_Q_ H S_Q_ J S_Q_ NTIG_PM R SYSTEM MEMORY S_S_0 S_S_ S_S_ S_RS# U S_S# G S_WE# F S_M_0 M S_M_ Y S_M_ 0 S_M_ F S_M_ G S_M_ S_M_ P S_M_ K S_QS_0 L S_QS_ V S_QS_ G S_QS_ G S_QS_ H S_QS_ S_QS_ U S_QS_ N S_QS#_0 L S_QS#_ V S_QS#_ H S_QS#_ H S_QS#_ G S_QS#_ S_QS#_ T S_QS#_ N S_M_0 V S_M_ S_M_ S_M_ U S_M_ W S_M_ S_M_ U S_M_ W S_M_ T S_M_ S_M_0 S_M_ W S_M_ Y S_M_ H S_M_ U M M0 M M M M M M M M M M M M M M M QS0 M QS M QS M QS M QS M QS M QS M QS M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M 0 M M M M M M M M M M 0 M M M M M S#0 [0,] M S# [0,] M S# [0,] M RS# [0,] M S# [0,] M WE# [0,] M M[:0] [0] M QS[:0] [0] M QS#[:0] [0] M [:0] [0,] PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom antiga R / ate: Tuesday, February, 00 Sheet of

8 VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF VSM_LF V_XG_SENSE VSS_XG_SENSE.0V [,,,,,,,,,0,].VSUS [,,0,,0,].VSUS.0V.0V.0V.0V.VSUS.0V.0V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Vcc / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Vcc / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N antiga Vcc / ustom Tuesday, February, 00 V_SM_ through V_SM_ can be left as N for R desgins. Ivcc=0.0.=.m Ivcc_axg=.m 00m 0 0U/.V_ 0U/.V_.U/0V_.U/0V_ 0 0U/.V_ 0 0U/.V_ 0U/.V_ 0U/.V_.U/.V_.U/.V_ 0U/.V_ 0U/.V_ POWER V SM V GFX V GFX NTF V SM LF U0G NTIG_PM POWER V SM V GFX V GFX NTF V SM LF U0G NTIG_PM V_SM_0 Y V_SM_0 F V_SM_0 W V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ W V_SM_ V V_SM_ U V_SM_ T V_SM_ R V_SM_ P V_SM_ N V_SM_ H V_SM_ G V_SM_ N V_SM_ G0 V_SM_ H V_SM_ G V_SM_ F V_SM_ V_SM_ V_SM_ V_SM_ V_SM_ Y V_SM_ H V_SM_ V V_SM_ U V_SM_ T V_SM_ R V_XG_NTF_0 V V_XG_NTF_ M V_XG_NTF_ L V_XG_NTF_ K V_XG_NTF_ W V_XG_NTF_ V V_XG_NTF_ U V_XG_NTF_ M0 V_XG_NTF_ K0 V_XG_NTF_ W0 V_XG_NTF_ V V_XG_NTF_0 U0 V_XG_NTF_ M V_XG_NTF_ L V_XG_NTF_ K V_XG_NTF_ J V_XG_NTF_ H V_XG_NTF_ G V_XG_NTF_ F V_XG_NTF_ E V_XG_NTF_ V_XG_NTF_ W V_XG_NTF_0 V_XG_NTF_ Y V_XG_NTF_ W V_XG_NTF_ V V_XG_NTF_ U V_XG_NTF_ M V_XG_NTF_ K V_XG_NTF_ H V_XG_NTF_ G V_XG_NTF_ F V_XG_NTF_ V V_XG_NTF_0 E V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ Y V_XG_NTF_ W V_XG_NTF_ V V_XG_NTF_ M V_XG_NTF_ L V_XG_NTF_ K V_XG_NTF_ J V_XG_NTF_ W V_XG_NTF_0 H V_XG_NTF_ G V_XG_NTF_ F V_XG_NTF_ E V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V_XG_NTF_ V V_XG_NTF_ W V_XG_NTF_ V V_XG_NTF_ W V_SM_ P V_SM_ G V_SM_ F V_XG_NTF_ W V_SM_ P V_XG_ Y V_XG_ E V_XG_ V_XG_ V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ E V_XG_0 V_XG_ V_XG_ V_XG_ J V_XG_ G V_XG_ E V_XG_ V_XG_ V_XG_ Y V_XG_ H0 V_XG_0 F0 V_XG_ E0 V_XG_ 0 V_XG_ 0 V_XG_ 0 V_XG_ T V_XG_ M V_XG_ L V_XG_0 J V_XG_ H V_XG_ F V_XG_ V_SM_LF V V_SM_LF V_SM_LF M0 V_SM_LF V V_SM_LF Y V_SM_LF M0 V_SM_LF V_XG_ T V_XG_ G V_XG_ V_XG_ Y V_XG_ V V_XG_ U V_XG_ N V_XG_0 M V_XG_ U V_XG_ T V_XG_SENSE J VSS_XG_SENSE H V_XG_NTF_ Y V_XG_NTF_ W V_XG_NTF_ V V_XG_NTF_0 U V_SM_/N V_SM_/N V_SM_/N V_SM_/N V_SM_0/N W V_SM_/N W V_SM_/N T V_XG_ E 0U/.V_ 0U/.V_.U/.V_.U/.V_ 0.U/.V_ 0.U/.V_.U/.V_.U/.V_ 0U/.V_ 0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ U/.V_ U/.V_ U/.V_ U/.V_.U/.V_.U/.V_ 0U/.V_ 0U/.V_ 0U/.V_X.ESR0 0U/.V_X.ESR0 U/.V_ U/.V_.U/.V_.U/.V_.U/0V_.U/0V_ 0 0U/.V_ 0 0U/.V_ R0 0_ R0 0_.U/0V_.U/0V_ POWER V NTF V ORE U0F NTIG_PM POWER V NTF V ORE U0F NTIG_PM V_NTF_ M V_NTF_0 0 V_NTF_ J V_NTF_ K V_NTF_ V_NTF_0 Y V_NTF_ W V_NTF_ U V_NTF_ M0 V_NTF_ L0 V_NTF_ K0 V_NTF_ G0 V_NTF_ F0 V_NTF_ E0 V_NTF_ L V_NTF_ W0 V_NTF_ V0 V_NTF_ K V_NTF_0 H V_NTF_ G V_NTF_ E V_NTF_ L V_NTF_ K V_NTF_0 L V_NTF_ K V_NTF_ J V_NTF_ K V_NTF_ H V_NTF_ G V_NTF_ E V_NTF_ V_NTF_ V_NTF_ V_NTF_ Y V_NTF_ W V_NTF_ V V_NTF_ U0 V_NTF_ L V_NTF_ K V_NTF_ H0 V_NTF_ 0 V_NTF_ 0 V_NTF_ Y0 V_ G V_ V_ V_ V_ Y V_ V V_ U V_ M V_ K V_0 J V_ G V_ F V_ E V_ V_ V_ Y V_ W V_ V V_ U V_0 H V_ F V_ V_ V_ J V_ G V_ E V_ V_ H V_ G V_0 F V_ G V_ J V_ H V_ F V_ T V_NTF_ K R0 0_ R0 0_ *0u_.V_ *0u_.V_.U/0V_.U/0V_ 0U/.V_ 0U/.V_

9 .0V.0V.0V_MH_PLL R.V L L L.0V.0V [,,,,,,,,,0,] V [,,,0,,,,,,0,,,,,,,,,,0,,,,,,,].V [,,,,,,,,0,] m.vsus [,,0,,0,] V RT_.0V_PEG [,,,,,,,,,0,] V R *0_ *.U/0V_ *.0U/V_.0V_PLL.V_TV.0V_PLL.0V_HPLL.0V_MPLL hange to X0000(0 ohm,.) as current request (L,L) SI- SI- PV uild 0 0U/.V_ PV uild *0uH/00M_ *0U/.V_.U/0V_ L H0KF-T_.U/0V_.U/.V_ *0uH/00M_ H0KF-T_ *.0U/V_ *.U/0V_.U/0V_ 0./F_.0U/V_.U/0V_.V_Q U/.V_.0V_PEGPLL.0V.V V V PV uild *0U/.V_.0V R Intel esign Guide. thermal management is enabled on discrete graphics motherboard L *0U/.V_.U/0V_ *.U/0V_ H0KF-T_ R /F_.V.VSUS SI- PV uild PV uild.0v SM R *0_ u m.m.vsus_tx_lvs J V_LVS *000P/0V_ J VSS_LVS 0m m.0v SM_K 0U/.V_.U/0V_ m V TV_ 0u.m 0m.V_PEG_G 0U/.V_ 0U/.V_ 0U/.V_.U/.V_ U/.V_.U/.V_ L *H0KF-T_ 0 *0U/.V_ *.U/0V_.U/0V_ R *.U/0V_ *0_.V_TV.V_Q.0V_MPLL.0V_PEGPLL.VSUS_GMH_V.V_H m *U/.V_ *0U/.V_ 0m 0.m.U/0V_ 0m.U/0V_.0V_PEGPLL U0H V_RT V_RT *0_ V G V G VSS G *.U/0V_ *.0U/V_.0V_PLL F total.m V_PLL m.m.0v_pll.0v_hpll.0v_mpll L E V_PLL V_HPLL V_MPLL 0.U/0V_ NTIG_PM V_PEG_G V_PEG_PLL R0 V_SM_ P0 V_SM_ N0 V_SM_ R V_SM_ P V_SM_ N V_SM_ T V_SM_ R V_SM_ P V_SM_ V_TV V_TV F V_HPLL V_PEG_PLL RT PLL LVS PEG SM P V_SM_K_ N V_SM_K_ P V_SM_K_ N V_SM_K_ N V_SM_K_ M V_SM_K_NTF_ M V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M V_SM_K_NTF_ L V_SM_K_NTF_ M L V_H V_TV V_Q M V_LVS_ L V_LVS_ TV H LVS VTTLF_P VTTLF_P VTTLF_P POWER K TV/RT XF SM K MI HV PEG VTT VTTLF VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_ VTT_0 VTT_ VTT_ VTT_ VTT_ VTT_ V_XF_ V_XF_ V_XF_ V_SM_K_ V_SM_K_ V_SM_K_ V_SM_K_ V_TX_LVS V_HV_ V_HV_ V_HV_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_PEG_ V_MI_ V_MI_ V_MI_ V_MI_ VTTLF VTTLF VTTLF U T U T U T U0 T0 U T U T U T U T U T V U V U T V U F H0 G0 F0 K V U V U U H F H G L.m.m V_HV.0V_RXR_MI VTTLF_P VTTLF_P VTTLF_P 0.U/.V_.0V_XF.VSUS_SM_K.VSUS_TX_LVS 0.m.U/0V_ U/.V_ 0U/.V_ m m 0.U/.V_.0V_PEG.0V.VSUS_SM_K_L.0V.0V_HV_MH.VSUS V_HV R0 V 0_ m PV uild 0U/.V_ 0.U/0V_.U/0V_.U/.V_.U/0V_.U/.V_ L R0 /F_ 0U/.V_ 0.U/.V_ uh/00m_ L 00 *000P/0V_ *0U/.V_ *0U/.V_ R0V-0 0 *0u_.V_ 0U/.V_ PV uild PV uild Modify 0.0V *0U/.V_X.ESR0.0V.VSUS *uh/00m_.0v 0 Modify to U0#F power to.0v_mpll as R change 0U/.V_.U/.V_.U/.V_.U/.V_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom antiga Power / ate: Tuesday, February, 00 Sheet of

10 GT_SM GLK_SM M LK0 M OT[0..] M LK0# M LK M LK# M S#[0..] M Q[0..] M [..0] M QS[0..] M QS#[0..] M M[0..] M WE# M LK M S# M Q[0..] M QS[0..] M LK# M LK0 M QS#[0..] M S#[0..] M M[0..] M RS# M LK0# M KE[0..] M S#[0..] M [..0] M OT[0..] 0.VSMVREF_IM M WE# M S# M RS# M KE[0..] M S#[0..] M LK0# M LK0 M LK# M LK M M M M M M0 M M M M M M M M M M IM_S0 IM_S M M M QS M WE# M S# M RS# M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q0 M QS M QS# M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS0 GLK_SM GT_SM M QS M S#0 M S# M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M QS M QS M QS M S# M S#0 M S# M OT M OT0 M M M M M M 0 M M M 0 M M M M M QS M KE0 M KE M S# M S# M S#0 M LK0 M LK0# M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q PM_EXTTS#0 M QS M QS M QS M QS M LK M LK# M M M M0 M M M M M M M M M M M M M WE# M S# M RS# M QS M QS# M QS# M QS# M QS# M QS# M QS#0 M QS# M QS# M M M 0 M M M M M 0 M M M M M M OT0 M OT GLK_SM GT_SM IM_S IM_S0 M S#0 M S# M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M QS0 M QS M QS M KE0 M KE IM_S0 IM_S IM_S0 IM_S M S# [,] M RS# [,] M S#[0..] [,] M WE# [,] M KE[0..] [,] M LK0 [] M LK# [] M LK [] M LK0# [] M OT[0..] [,] M S#[0..] [,] M QS#[0..] [] M M[0..] [] M Q[0..] [] M QS[0..] [] M [..0] [,] M S#[0..] [,] M RS# [,] M S# [,] M WE# [,] M KE[0..] [,] M LK# [] M OT[0..] [,] M LK0 [] M S#[0..] [,] M LK0# [] M LK [] M QS#[0..] [] M QS[0..] [] M Q[0..] [] M [..0] [,] M M[0..] [] GT_SM [,,,,] GLK_SM [,,,,] 0.VSMVREF [,] PM_EXTTS#0 [,].VSUS [,,,,0,] V [,,,,,,,,,0,,,,,,,,,,0,,,,,,,] V 0.VSMVREF_IM.VSUS V.VSUS 0.VSMVREF_IM.VSUS V.VSUS 0.VSMVREF_IM V.VSUS 0.VSMVREF_IM V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N R IMM ustom 0 Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N R IMM ustom 0 Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N R IMM ustom 0 Tuesday, February, 00 Place these aps near So-imm. SO-IMM YPSS PLEMENT : No Vias etween the Trace of PIN to P. Place these aps near So-imm. Place these aps near So-imm No Vias etween the Trace of PIN to P. SO-IMM YPSS PLEMENT : Place these aps near So-imm. 0 H. SMbus address SMbus address 0 H. GMK00000 GMK00000.U/.V_.U/.V_ R *0K/F_ R *0K/F_.U/.V_.U/.V_.U/.V_.U/.V_ SO-IMM N RII H=. SO-IMM N RII H=. Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0.U/0V_.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/.V_ 0.U/.V_ 0P/0V_ 0P/0V_ R0 0K/F_ R0 0K/F_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_.U/0V_.U/0V_ R0 0K/F_ R0 0K/F_.U/0V_.U/0V_ SO-IMM N RII H=. SO-IMM N RII H=. Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 0.U/.V_ 0.U/.V_ 0.U/.V_ 0.U/.V_.U/.V_.U/.V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ R 0_ R 0_.U/.V_.U/.V_ R 0K/F_ R 0K/F_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ R 0K/F_ R 0K/F_ R *0K/F_ R *0K/F_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/.V_ 0.U/.V_

11 RII UL HNNEL,. RII HNNEL RII HNNEL 0.VSMVTT 0.VSMVTT.U/0V_.U/0V_.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ 0.U/0V_ 0.VSMVTT 0.VSMVTT 0.U/0V_.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ Layout note: Place one cap close to every pullup resistors terminated to SMR_VTERM [,0] M OT0 [,0] M KE [,0] M S#0 [,0] M RS# [,0] M S# [,0] M WE# [,0] M S# M_OT0 M M M M M M KE M M 0 M S#0 M M M M M S# M M M M RP RP RP RP RP RP RP RP RP RP R R X X X X X X X X X X./F_./F_ 0.VSMVTT V Uninstall [,0] M S# [,0] M KE0 [,0] M S# [,0] M RS# [,0] M S#0 [,0] M WE# [,0] M S# [,0] M S#0 [,0] M S#0 [,0] M OT0 [,0] M OT [,0] M S# [,0] M S# [,0] M OT [,0] M KE [,0] M KE0 [,0] M S# M 0 M M M M M M M M M M M 0 M 0 M M_OT M_OT M RP RP RP RP RP RP0 RP RP RP RP RP0 RP RP RP RP RP X X X X X X X X X X X X X X X X 0.VSMVTT M [..0] M [..0] M [..0] [,0] M [..0] [,0] U R *00_ 0 *.0U/V_ [,0,,,] GLK_SM [,0,,,] GT_SM [,0] PM_EXTTS#0 [] PM_EXTTS# R *0_ GLK_SM GT_SM PM_EXTTS#0 PM_EXTTS#_ SLK S LERT# OVERT# *LMIMM V XP XN GN LM_V R_THERM R_THERM Q *MMT0--F 0.VSMVTT [] V [,,,,0,,,,,0,,,,,,,,,,0,,,,,,,] N PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom R termination ate: Tuesday, February, 00 Sheet of

12 VG.V U/.V_.U/.V_ VG.V U/.V_.U/.V_ Near G VG.V L.U/.V_ U/.V_ U/.V_ 0nH_ U/.V_.U/.V_ V U/.V_.U/.V_.U/0V_.U/.V_ nvii Suggest / PEX_PLLV.U/0V_ U/.V_.U/0V_.U/0V_ ~ 00m.U/.V_ 00m U G-NVII-NP-GS OMMON K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ K PEX_IOV_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_ G PEX_IOVQ_0 G PEX_IOVQ_ G PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_ J PEX_IOVQ_0 K PEX_IOVQ_ K0 PEX_IOVQ_ K PEX_IOVQ_ K PEX_IOVQ_ L PEX_IOVQ_ PEX_RX0 P PEX_RX0* N PEX_RX N PEX_RX* P PEX_RX R PEX_RX* R0 PEX_RX P0 PEX_RX* N0 PEX_RX N PEX_RX* P PEX_RX R PEX_RX* R PEX_RX P PEX_RX* N PEX_RX N PEX_RX* P PEX_RX R PEX_RX* R PEX_RX P PEX_RX* N PEX_RX0 N PEX_RX0* P PEX_RX R PEX_RX* R PEX_RX P PEX_RX* N PEX_RX N PEX_RX* P PEX_RX R PEX_RX* R PEX_RX R PEX_RX* P PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX0 PEG_TX#0 PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# PEG_TX PEG_TX# _PEG_RX0.U/0V_ PEX_TX0 L _PEG_RX#0 PEX_TX0* M.U/0V_ J0 _PEG_RX PI EXPRESS PEX_TX M.U/0V_ V_ J _PEG_RX# 0.U/0V_ V_ PEX_TX* M J _PEG_RX.U/0V_ V_ PEX_TX L J _PEG_RX#.U/0V_.U/0V_ V_ PEX_TX* K J _PEG_RX PEX_TX L0.U/0V_ V PEG_RX#.U/0V_ PEX_TX* M0 _PEG_RX.U/0V_ PEX_TX M _PEG_RX# 0.U/0V_ PEX_TX* M 0 _PEG_RX PEX_TX L.U/0V_ V_SENSE _PEG_RX# PEX_TX* K.U/0V PEG_RX.U/0V_ PEX_TX L _PEG_RX#.U/0V_ PEX_TX* M _PEG_RX.U/0V_ GN_SENSE PEX_TX M _PEG_RX#.U/0V_ 00m PEX_TX* M _PEG_RX PEX_TX L.U/0V_ ~ mils width _PEG_RX# PEX_TX* K.U/0V_ G _PEG_RX PEX_TX L.U/0V_ PEX_PLLV _PEG_RX#.U/0V_ PEX_TX* M _PEG_RX0 PEX_TX0 M 0.U/0V PEG_RX#0.U/0V_.U/0V_.0U/V_ PEX_TX0* M G _PEG_RX.U/0V_ PEX_L_P_VQ PEX_TX L _PEG_RX#.U/0V_ PEX_TX* K _PEG_RX 0.U/0V_ PEX_TX K _PEG_RX# PEX_TX* L 0.U/0V_ G0 _PEG_RX PEX_L_PU_GN PEX_TX M.U/0V PEG_RX# PEX_TX* M0 00.U/0V PEG_RX.U/0V_ PEX_TX M _PEG_RX# PEX_TX* M.U/0V PEG_RX N_ PEX_TX N 0.U/0V PEG_RX# 0.U/0V_ N_ PEX_TX* P N_ F N_ G N_ J N_ K N_ L N_ N_ E N_0 E N_ F N_ H N_ M N_ P N_ P N_ R N_ U N_ V N_ PEX_REFLK R PEX_REFLK* R PEX_TSTLK_OUT J PEX_TSTLK_OUT* J PEX_RST* M PEX_LKREQ* R PEX_TERMP G TESTMOE P LK_PIE_VG LK_PIE_VG# VG_RST# T PEX_TERMP TESTMOE R R R R0 *00_ 00/F_.K/F_ 0K/F_ PEG_TX0 [] PEG_TX#0 [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX0 [] PEG_TX#0 [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_TX [] PEG_TX# [] PEG_RX0 [] PEG_RX#0 [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX0 [] PEG_RX#0 [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] PEG_RX [] PEG_RX# [] LK_PIE_VG [] LK_PIE_VG# [] *R0V-0 R0 *00K/F_ PLT_RST-R# PLT_RST-R# [,] R 0_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom NVX (PIE I/F) / ate: Tuesday, February, 00 Sheet of

13 VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_M0 VM_M VM_M VM_M VM_M VM_M VM_M VM_M VM_WQS0 VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_WQS VM_RQS0 VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_RQS VM_LK0 VM_LK0# VM_LK VM_LK VM_LK# VM_LK0 VM_LK0# VM_LK F_VREF F_PLLV F_EUG F_EUG F_L_P_VQ F_L_PU_GN F_L_TERM_GN F_PLLV VM_KE VM_OT VM_OT VM_KE VM_MH [] VM_S0# [] VM_WE# [] VM_M [] VM_0 [] VM_KE [] VM_OT [] VM_MH [] VM_M [] VM_RS# [] VM_M [] VM_M0 [] VM_ [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_S# [] VM_M [] VM_M0 [] VM_M [] VM_M [] VM_MH [] VM_MH [] VM_MH [] VM_S0# [] VM_WE# [] VM_M [] VM_0 [] VM_KE [] VM_OT [] VM_MH [] VM_M [] VM_RS# [] VM_M [] VM_M0 [] VM_ [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_S# [] VM_M [] VM_M0 [] VM_M [] VM_M [] VM_MH [] VM_MH [] VM_Q[..0] [] VM_M[..0] [] VM_WQS[..0] [] VM_RQS[..0] [] VM_RQS[..0] [] VM_WQS[..0] [] VM_M[..0] [] VM_Q[..0] [] VM_LK [] VM_LK# [] VM_LK0# [] VM_LK0 [] VM_LK [] VM_LK0# [] VM_LK0 [] VM_LK# [].V.V.V VG.V.V.V.V.V.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX (MEMORY I/F) / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX (MEMORY I/F) / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX (MEMORY I/F) / ustom Tuesday, February, 00 use ernal Vref, ext divider no stuff R no stuff for R need use M(KE) and M(OT) For G only R Install for R For ebug only mils width mils width For NP-GSonly 0.U/.V_ 0.U/.V_.U/0V_.U/0V_.U/0V_.U/0V_ R *0./F_ R *0./F_ L0 H0KF-T_ L0 H0KF-T_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_ R 0K/F_ R 0K/F_.U/.V_.U/.V_.U/0V_.U/0V_.U/0V_.U/0V_ R 0./F_ R 0./F_.U/0V_.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_.U/.V_.U/.V_.U/0V_.U/0V_.U/.V_.U/.V_ R *0./F_ R *0./F_ R 0K/F_ R 0K/F_.U/0V_.U/0V_.U/.V_.U/.V_ R0 *K/F_ R0 *K/F_.U/.V_.U/.V_ R 0./F_ R 0./F_ MEMORY I/F OMMON G-NVII-NP-GS U MEMORY I/F OMMON G-NVII-NP-GS U F_VREF J F_WS* H F_WS G F_WS* E F_WS F_WS* M F_WS L F_WS0* R F_WS0 P F_QS_RN J F_QS_RN J F_QS_RN F_QS_RN F_QS_RN G F_QS_RN H F_QS_RN L F_QS_RN0 N F_QS_WP J F_QS_WP J F_QS_WP F_QS_WP E F_QS_WP H F_QS_WP J F_QS_WP L F_QS_WP0 N F_QM L F_QM L F_QM F F_QM F F_QM H F_QM J0 F_QM P F_QM0 P0 F_PLLV0 F F_LLV0 G F_EUG T0 F_LK* 0 F_LK F_LK0* T F_LK0 T F_0 R0 F_ R F_ P F_ N0 F_ L F_ M F_ M0 F_ L0 F_ P F_ P F_0 N F_ P F_ N F_ L F_ L F_ N F_ K F_ K0 F_ G0 F_ K F_0 G F_ H0 F_ F0 F_ G F_ H F_ K F_ K F_ G F_ K F_ E F_0 E F_ G F_ G0 F_ H F_ G F_ F F_ F0 F_ 0 F_ F_ E0 F_0 E F_ F F_ F F_ E F_ E F_ E F_ F_ F_ N F_ K F_0 L F_ M F_ L F_ K0 F_ J0 F_ H0 F_ M F_ H F_ H F_ H F_0 H F_ M F_ L F_ J F_M0 V F_M W F_M U F_M Y F_M F_M F_M W F_M W F_M W0 F_M T F_M0 T F_M F_M Y0 F_M Y F_M W F_M 0 F_M F_M Y F_M U F_M Y F_M0 U F_M Y F_M W F_M V0 F_M U F_M U0 F_M U F_M 0 F_M F_M T F_M0 W FVQ_ J FVQ_ J FVQ_ J FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ FVQ_ E FVQ_ J FVQ_0 FVQ_ E FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ G FVQ_ H FVQ_ J FVQ_ J FVQ_0 J FVQ_ J FVQ_ J0 FVQ_ J FVQ_ J 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ R *K/F_ R *K/F_ U/.V_ U/.V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ MEMORY I/F G only OMMON G-NVII-NP-GS U MEMORY I/F G only OMMON G-NVII-NP-GS U F_WS* G F_WS G F_WS* G F_WS G F_WS* G F_WS G F_WS0* G F_WS0 G F_QS_RN F_QS_RN F_QS_RN F_QS_RN F F_QS_RN F_QS_RN E F_QS_RN 0 F_QS_RN0 F_QS_WP F_QS_WP F_QS_WP F_QS_WP E F_QS_WP F_QS_WP F_QS_WP 0 F_QS_WP0 E0 F_QM F_QM F_QM F_QM F_QM F_QM F_QM 0 F_QM0 F F_L_TERM_GN M F_L_PU_GN L F_L_P_VQ K F_PLLV J F_LLV J F_EUG G F_LK* E F_LK F_LK0* F_LK0 E FVQ_ Y FVQ_ W FVQ_ V FVQ_ V FVQ_ V FVQ_ U FVQ_ U FVQ_ T FVQ_0 R FVQ_ P FVQ_ N F_0 F_ E F_ F0 F_ F_ F F_ F F_ E F_ F F_ F_ F_0 F_ F_ F_ F_ F_ 0 F_ F_ E F_ F F_ F F_0 F F_ E F_ F F_ F F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ E F_ F F_ F F_ E F_ F F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ E F_ F F_0 0 F_ E F_ F_ F_ F F_ E F_ F_ F_ F_ F_0 F_ F_ F_ F_M0 F_M F_M F_M F F_M F_M F_M F_M E0 F_M G F_M F0 F_M0 F F_M F F_M F_M F_M F_M F F_M F_M E F_M 0 F_M F_M0 F_M F_M 0 F_M E F_M F_M F F_M F_M F F_M F_M 0 F_M0 0.U/.V_.U/.V_.U/.V_.U/.V_ R *0./F_ R *0./F_ 0.U/.V_ 0.U/.V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ R 0K/F_ R 0K/F_ R 0K/F_ R 0K/F_

14 .V.V L L H0KF-T_ 0.U/.V_ H0KF-T_.U/.V_ 0 00P/V_.U/.V_ 0P/0V_ 00P/V_ IFP_PLLV IFP_IOV 00P/V_ R0 0P/0V_ 00 m *K/F_ 0P/0V_ K J G G0 U G-NVII-NP-GS OMMON IFP_PLLV IFP_RSET 0 m IFP_IOV 0 m IFP_IOV IFP(LVS) IFP_TX IFP_TX* IFP_TX0 IFP_TX0* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* IFP_TX IFP_TX* M M M L M0 M K0 L0 K L P N N P P0 N0 R R0 N P EXT_TXLLKOUT [] EXT_TXLLKOUT- [] EXT_TXLOUT0 [] EXT_TXLOUT0- [] EXT_TXLOUT [] EXT_TXLOUT- [] EXT_TXLOUT [] EXT_TXLOUT- [] EXT_TXULKOUT [] EXT_TXULKOUT- [] EXT_TXUOUT0 [] EXT_TXUOUT0- [] EXT_TXUOUT [] EXT_TXUOUT- [] EXT_TXUOUT [] EXT_TXUOUT- [] L U/.V_ VG.V L H0KF-T_ 0b.U/.V_ H0KF-T_.U/.V_ 00P/V_ U/.V_ IFP_PLLV 0P/0V_ IFP_IOV U/.V_ 00P/V_ R 0P/0V_ K/F_ 0P/0V_ J K J K IFP_PLLV IFP_RSET IFP_IOV IFP_IOV IFP IFP IFP UX* UX PL_TX PL_TX PL_TX0 PL_TX0 PL_TX PL_TX PL0_TX PL0_TX UX UX PL_TX PL_TX PL_TX0 PL_TX0 PL_TX PL_TX PL0_TX PL0_TX N P R P M M M L M M N P R R P N N P R R N_TX_HMI- N_TX_HMI N_TX0_HMI- N_TX0_HMI N_TX_HMI- N_TX_HMI N_TX_HMI- N_TX_HMI TMS channel two Fix all out and Pin Name N_TX_HMI- [0] N_TX_HMI [0] N_TX0_HMI- [0] N_TX0_HMI [0] N_TX_HMI- [0] N_TX_HMI [0] N_TX_HMI- [0] N_TX_HMI [0] V IFPEF_PLLV T R0 0K/F_ R 0K/F_ J L E IFPEF_PLLV IFPEF_RSET IFPE_IOV IFPF_IOV IFPEF IFPE_UX IFPE_UX* IFPE_L0 IFPE_L0* IFPE_L IFPE_L* IFPE_L IFPE_L* IFPE_L IFPE_L* IFPF_UX IFPF_UX* IFPF_L0 IFPF_L0* IFPF_L IFPF_L* IFPF_L IFPF_L* IFPF_L IFPF_L* E H H H G F F E E F F L L J J J H H H isplay port output L_RT_R R 0/F_ L0 H0KF-T_ 0b 0.U/.V_ 00P/V_ 0 0P/0V_.U/0V V _VREF _RSET R0 /F_ J K K _V _VREF _RSET (RT) _RE _GREEN _LUE _HSYN _VSYN I_SL I_S M M L M L G G L_RT_R L_RT_G L_RT_ RT_HSYN RT_VSYN L_LK L_T R 0_ R 0_ R 0_ R _ R0 _ R 0_ R 0_ RT_R [,0] RT_G [,0] RT_ [,0] HSYN_OM [,0] VSYN_OM [,0] LK [,0] T [,0] L_RT_G L_RT_ R 0/F_ R 0/F_ lose to GPU R 0K/F V T T G K H _V _VREF _RSET (RT) _RE _GREEN _LUE _HSYN _VSYN K L J M M V 0K/F_ R _V T _V _VREF (TV) I_SL I_S _RE _GREEN G G I_SL I_S R R.K_.K_ VG.V L H0KF-T_ U/.V_ U/.V_ U/.V_.00 NV_PLLV.U/0V_.U/0V_ T m 0m m E F _RSET PLLV VI_PLLV SP_PLLV XTL_PLL _LUE _SYN XTL_SSIN XTL_OUTUFF XTL_IN XTL_OUT Y XTL_SSIN XTLOUT XTLIN XTLOUT T Y *MHZ R 0_ R 0_ PLE LOSE TO GPU M_SS [] M_NONSS [] *P/0V_ * package *P/0V_ STUFF Ps on XTLSSIN and XTLOUTUFF WHEN EXT_SS IS NOT USE V SPRE SPETRUM V R0 *_ SI uild XTL_SSIN M_SS XTLOUT R *0K/F_ R *0K/F_ GFXM_L *0P/0V_ R0 *0K/F_ R *0K/F_ ISS_P U P# V V_SS R *._ V [,,] EILK [,,] EIT XTLOUT LKIN LKOUT ISS_RFO EILK REFOUT R0 EIT SL S GN *0K/F_ *IS0MLF-T I RESS: 0xH 0 0 *.U/0V_ *.U/.V_ *0P/0V_ *.U/.V_ Install it when not connected to Spread spectrum device N PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom NVX (ISPLY) / Tuesday, February, 00 ate: Sheet of

15 V.U/.V_.U/0V_ SI- V 0.U/.V_.U/0V_ elete,r,r,r,r elete R,R,R0,R0,0 as Nvidia recommand P R T U U T N W Y F UE G-NVII-NP-GS OMMON MIO_VQ_ MIO_VQ_ MIO_VQ_ MIO_VQ_ MIO_L_P_VQ MIO_L_PU_GN MIO_VREF MIO_VQ_ MIO_VQ_ MIO_VQ_ MIO_VQ_ MIO_L_P_VQ MIO_L_PU_GN MIO_VREF MIO MIO MIO_0 MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_0 MIO_ MIO_ MIO_ MIO_ MIO_TL MIO_HSYN MIO_VSYN MIO_E MIO_LKOUT MIO_LKOUT* MIO_LKIN MIO_0 MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_0 MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_ MIO_TL MIO_HSYN MIO_VSYN MIO_E N P P P P T T T U U U U R T N P N L N R T N Y Y Y E E U W Y W W V W W W Y T MIO_0 MIO_HSYN T0 R T T 0K/F_ MIO_ MIO_0 STRP0 STRP STRP T T T0 T elete T NP-GS (G) Straps NM-GE (G) Straps GPIO SSIGNMENTS GPIO 0 0 I/O IN IN OUT OUT OUT OUT OUT OUT IN OUT OUT OUT IN OUT OUT TIVE N/ N/ HIGH HIGH HIGH N/ N/ N/ LOW LOW N/ N/ N/ LOW HIGH USGE PI_EVI[]/SUVENOR ROM_SI ROM_SO ROM_SLK PRIMRY VI HOTPLUG SEONRY VI HOTPLUG R PNEL KLIGHT PWM.K/F_ PNEL POWER ENLE PNEL KLIGHT ENLE NVV VI0 NVV VI FV VI0 SEE atasheet for details on Gx Straps! THERML LERT FN PWM R FVREF SELET.K/F_ SLI SYN0 STRP0 STRP ETET STRP PS ONTROL OR HMI_E R PS ONTROL R *K/F_ *K/F_ R.K/F_ R *.K/F_ R *K/F_ R 0K/F_ V V R *K/F_ R K/F_ R 0K/F_ R *K/F_ MIO_LKOUT MIO_LKOUT* MIO_LKIN V W E R 0K/F_ EIT EILK V [,] MLK [,] MT [,,] EILK [,,] EIT [0] HMI_SL [0] HMI_S [] [] [] [] [] NV_H_LK NV_H_RST Z_SIN NV_H_SO NV_H_SYN GFX_S GFX_SL EILK EIT VG THERMIL IRUIT R R R *00_ *0_ *0_ R R MX_V V *.U/0V_ GN *GPUF R _ R _ H udio Level :V U ST SLK GN T R 0_ 0.K/F_ 0.K/F_ OVT LERT XP XN GFX_THM JTG_TK JTG_TMS JTG_TI JTG_TO JTG_TRST# NV_H_LK NV_H_RST NV_H_SI NV_H_SO NV_H_SYN I_SL_G I_S_G I_SL_G I_S_G IE_SL_G IE_S_G STRP_REF_V STRP_REF_MIO V R *.K_ MX_O# MX_# GFX_THM GFX_THM- 0 *00P/0V_ GFX_THM- P R N N P E E E E F G E J J N M I RESS: 0xH R R THERMN GPIO0 GPIO GPIO THERMP GPIO GPIO GPIO JTG_TK MIS GPIO JTG_TMS (GPIOS,JTG,THERM,I) GPIO JTG_TI GPIO JTG_TO GPIO JTG_TRST* GPIO0 GPIO GPIO IS_SL GPIO IS_S GPIO I_SL GPIO I_S GPIO I_SL GPIO I_S GPIO IE_SL GPIO IE_S GPIO0 GPIO GPIO GPIO ISN_N ISP_N H_LK H_RST* H_SI H_SO H_SYN STRP_REF_V STRP_REF_MIO *0_ VG_OVT# *0_ LERT MIS(ROM) ROM_S* ROM_SI ROM_SO ROM_SLK IH_SL IH_S SPIF UFRST* PGOO_OUT* RFU RFU_GN THERML TRE ONSTRINTS Use 0MIL Guard(GN) Trace around THERM and THERM K K K H H H H H H J K K H J J L L L M L L K L M F G K K T PST_PWM T VG_OVT# LERT T T GFX_GPIO ROM_SI ROM_SO ROM_SLK HP_SL HP_S SPIF_VG HMI_ET [0] PST_PWM [,] ISP_ON [,] LVS_LON [,] V_PWRNTL [] VG_GPIO [] VG_OVT# [] TP SI build R *K/F_ SI- dd for VG Power switch NX VRM onfiguration Table RM_FG[:0] ESRIPTION 0 R Mxx, bit, M 00 R Mxx, bit, M 00 R Mxx, bit, M other Reserved JTG_TMS JTG_TI VG_OVT# LERT IE_SL_G R0 IE_S_G R JTG_TK JTG_TRST# PST_PWM Logical Strapping it V SI uild Logical Strapping it Logical Strapping it Logical Strap it Mapping PU-V P K K K K 0 00 K 0K K K 0 Logical Strapping it0 ROM_SO ROM_SLK ROM_SI STRP STRP XLK_ PI_EVIE[] RMFG[] PI_EVI[] GIO_PFG[] TVMOE] SU_VENOR RMFG[] PI_EVI[] GIO_PFG[] TVMOE[] SLOT_LK_FG RMFG[] PI_EVI[] GIO_PFG[] TVMOE[0] PEX_PLL_EN_TERM00 RMFG[0] PI_EVI[0] GIO_PFG[0] STRP0 USER[] USER[] USER[] USER[0] Vendor Hynix HYPSFP- Qimonda HYTF- Samsung KNQE-Z R0 R0 R R R0 R R 0K/F_ 0K/F_ 0K/F_ 0K/F_.K_.K_ 0K/F_ 0K/F_ K/F_ PI_EVI: NM-GE 0x0E NM-GS 0x0E NP-GE 0x0 NP-GS 0x0 STRP R PU PU PU PU XXXX XXXX 000 K 0K K 0K HP ROM SI uild hange P/N U 0 V GN T WP SL S HP_SL HP_S Waiting onfirm from Nvidia V.U/0V_ V V R 0K/F_ HP_S R 0K/F_ SI uild HP_SL R *0K/F_ HP ROM Low: rypto ROM HP_SL Hi: I ROM SF RES HIP.K /W -%(00) SF RES HIP.K /W -% (00) RM I: ROM_SI R SM QIM HYN P P P 0.K.K.K PROJET : QT Quanta omputer Inc. N Size ocument Number Rev NVX (GPIO & STRRPS) / ate: Tuesday, February, 00 Sheet of

16 VGORE 0 L L L L L L L L L L0 L L L L L M M M M M0 M M P P P P P UF G-NVII-NP-GS OMMON V_00 V_00 V_00 V_00 V_00 V_00 V_00 V_00 V_00 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 NVV V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_0 V_ P P P R R R R R R R R R R0 R R R R R T T T T T0 T T V V V V V V V V W W W W W W W W W W0 W W W W W Y Y Y Y Y0 Y Y VGORE GN_ GN_0 E GN_ GN_0 E NVV ecoupling GN_ GN_0 E.U/.V_.U/.V_.U/0V_ 0.U/0V_ PXE.V I/O.V NVORE PLE NER LLS Follow esign Guide G-0-00.uFx and 0.x0 uf instead of 0.uF x0 PXE.V.U/.V_.U/.V_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/0V_.U/0V_.U/.V_.U/.V_.U/0V_.U/0V_ NM: VGORE 0.0V (Normal),.0V power up sequence NER G.U/.V_.U/.V_.U/.V_ 0.U/0V_.U/0V_.U/.V_.U/.V_ VGORE PV uild 0U/.V_0 UG G-NVII-NP-GS OMMON GN_ GN_ GN_ GN_ GN_ GN_ GN_0 0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ 0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ GN_0 GN_ GN_ GN_ GN_ GN_ GN_ GN_ E GN_ E GN_ E GN_0 E GN_ E GN_ E GN_ E GN_ E GN_ E GN_ E0 GN_ E GN_ E GN_ E GN_0 E GN_ E GN_ G GN_ G GN_ G GN_ G GN_ K GN_ K GN_ K GN_ K GN_0 L GN_ L GN_ L GN_ L GN_ L GN_ L GN_ L0 GN_ L GN_ L GN_ N GN_0 N GN_ P GN_ P GN_ P GN_ P GN_ P GN_ P GN_ P GN_ P0 GN_ P GN_0 P GN_0 P GN_0 GN_0 GN_0 GN_0 GN_0 GN_0 GN_0 0 GN_0 GN_00 GN_0 GN_0 GN_0 GN_0 E GN_0 GROUN GN_0 E GN_00 E0 GN_0 E GN_0 E GN_0 F GN_0 F GN_0 F GN_0 F GN_0 J GN_0 J GN_0 J GN_0 J GN_ L GN_ M GN_ M GN_ M GN_ M GN_ M GN_ M GN_ M GN_ M GN_0 M GN_ M GN_ M GN_ M GN_ N GN_ N GN_ N GN_ N GN_ N GN_ N GN_0 N GN_ N GN_ N GN_ N0 GN_ N GN_ N GN_ N GN_ N GN_ N GN_ P GN_0 P GN_ P GN_ P GN_ P0 GN_ P GN_ P GN_ R GN_ R GN_ R GN_ R GN_0 T GN_ T GN_ T GN_ T GN_ T GN_ T GN_ T GN_ T GN_ U GN_ U GN_0 U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ U GN_ U0 GN_ U GN_ U GN_0 U GN_ U GN_ U GN_ V GN_ V GN_ V GN_ V GN_ V GN_ V0 GN_ V GN_0 V GN_ V GN_ V GN_ V GN_ Y GN_ Y GN_ Y GN_ Y GN_ Y GN_ Y GN_0 Y GN_ Y.VFQ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom NVX (POWER & GN) / ate: Tuesday, February, 00 Sheet of

17 VM_S0# VM_WE# VM_RS# VM_KE VM_S# VM_M VM_M VM_ VM_M VM_M0 VM_M VM_M VM_M VM_0 VM_M VM_M VM_M VM_M VM_M VM_M0 VMREF0 VMREF VM_S# VM_M0 VM_S0# VM_M VM_M VM_ VM_0 VM_M VM_M VM_M VM_KE VM_M0 VM_M VM_M VM_M VM_RS# VM_WE# VM_M VM_M VM_M VM_S0# VM_WE# VM_M VM_M VM_MH VM_M VM_S# VM_M VM_RS# VM_M0 VM_KE VM_ VM_M0 VM_MH VM_0 VM_M VM_MH VM_M VM_M VM_MH VM_M VM_KE VM_M VM_0 VM_M0 VM_S0# VM_MH VM_M VM_MH VM_RS# VM_M VM_M VM_M VM_MH VM_M VM_MH VM_ VM_WE# VM_S# VM_M0 VM_OT VM_OT VM_OT VM_OT VM_LK VM_LK# VMREF VM_LK0# VM_LK0 VM_LK# VM_LK VM_LK VM_LK# VM_LK0 VM_LK0# VMREF0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_M VM_M0 VM_RQS VM_WQS0 VM_WQS VM_RQS0 VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_RQS VM_WQS VM_M VM_WQS VM_M VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_RQS VM_WQS VM_RQS VM_M VM_M VM_WQS VM_WQS VM_RQS VM_M VM_RQS VM_WQS VM_M VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_LK0 VM_LK0# VM_S0# [] VM_RS# [] VM_KE [] VM_WE# [] VM_S# [] VM_ [] VM_M [] VM_0 [] VM_M [] VM_M [] VM_M0 [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M0 [] VM_MH [] VM_MH [] VM_MH [] VM_MH [] VM_Q[..0] [] VM_RQS[..0] [] VM_M[..0] [] VM_WQS[..0] [] VM_OT [] VM_LK0 [] VM_LK0# [] VM_LK [] VM_LK# [].V.V.V.V.V.V.V.V.V.V.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 mil mil Mb : KJGT^0 Mb : KG-T^0 mil mil NM/NP-GS/NP-GE: R NM-GE: 0%, R ( K ) NM-GE: 0%,R ( K ) For : NP : KG-T0(Samsung,M*) NM : KFG-TW(Hynix,M*) (y pass capacitor) SF RES HIP /W -%(00) KFG-T^0(Qimonda M*) NP-GE/NP-GS/NM: 0% FV NP-GE/NP-GS/NM: 0% FV SI uild R /F_ R /F_.U/.V_.U/.V_.U/.V_.U/.V_.U/0V_.U/0V_ R K/F_ R K/F_.U/0V_.U/0V_.0U/V_.0U/V_ R0 /F_ R0 /F_ 000P/0V_ 000P/0V_.0U/V_.0U/V_ 0.U/0V_ 0.U/0V_ 000P/0V_ 000P/0V_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R 0 000P/0V_ 0 000P/0V_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ R K/F_ R K/F_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R.U/0V_.U/0V_ 0 000P/0V_ 0 000P/0V_ R K/F_ R K/F_.U/.V_.U/.V_ R K/F_ R K/F_.0U/V_.0U/V_.0U/V_.0U/V_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_

18 VMREF VM_M VM_M VM_M VM_0 VM_M VM_M VM_M VM_M VM_M VM_MH VM_M0 VM_M VM_MH VM_MH VM_MH VM_M0 VM_M VM_M VM_ VM_KE VM_RS# VM_S0# VM_OT VM_S# VM_WE# VM_M VM_S# VM_M VM_KE VM_WE# VM_M VM_S0# VM_0 VM_M VM_RS# VM_M VM_M VM_OT VM_M0 VM_M VM_ VM_M VM_M VM_M VM_M VM_M0 VM_S# VM_M VM_KE VM_WE# VM_S0# VM_0 VM_M VM_RS# VM_M VM_OT VM_M0 VM_M VM_ VM_M VM_M VM_M VM_M0 VM_KE VM_S0# VM_M0 VM_M VM_MH VM_0 VM_MH VM_WE# VM_S# VM_OT VM_M VM_MH VM_RS# VM_M VM_M VM_M VM_M VM_MH VM_M VM_ VM_M0 VMREF0 VMREF0 VMREF VM_LK0 VM_LK0# VM_LK# VM_LK VM_LK0 VM_LK0# VM_LK# VM_LK VM_LK# VM_LK0 VM_LK0# VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_M VM_M VM_RQS VM_RQS VM_WQS VM_WQS VM_RQS VM_M VM_WQS VM_RQS VM_M VM_WQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_RQS0 VM_WQS0 VM_M VM_RQS VM_M0 VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_WQS VM_WQS VM_M VM_M VM_RQS VM_WQS VM_RQS VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_LK VM_RS# [] VM_WE# [] VM_OT [] VM_S0# [] VM_KE [] VM_Q[..0] [] VM_WQS[..0] [] VM_M[..0] [] VM_RQS[..0] [] VM_ [] VM_0 [] VM_M [] VM_M [] VM_M0 [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M [] VM_M0 [] VM_S# [] VM_MH [] VM_MH [] VM_MH [] VM_MH [] VM_LK0 [] VM_LK# [] VM_LK [] VM_LK0# [].V.V.V.V.V.V.V.V.V.V.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N NVX VRM-(GR G) ustom Tuesday, February, 00 mil mil mil mil NM-GE:0%, R( K ) NM-GE: 0%,R ( K ) NM/NP-GS/NP-GE: R NP-GE/NP-GS/NM: 0% FV NP-GE/NP-GS/NM: 0% FV SF RES HIP /W -%(00) SI- KFG-T0 I SRM(P) KNQG-H(FG) I SRM(P)HYTF-(TFG) KFG-T^0 I SRM(P) HYPSFP-(FG) KFG-TW Hynix Qimonda Samsung NM-GE NP-GS VRM Vendor PV uild.0u/v_.0u/v_.u/.v_.u/.v_ 0.U/0V_ 0.U/0V_.0U/V_.0U/V_ 000P/0V_ 000P/0V_.U/.V_.U/.V_.U/0V_.U/0V_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R.U/0V_.U/0V_ R K/F_ R K/F_ R K/F_ R K/F_ R K/F_ R K/F_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R *0U_.V ESR *0U_.V ESR.U/.V_.U/.V_.U/0V_.U/0V_ 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_.0U/V_.0U/V_ R /F_ R /F_ R /F_ R /F_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R *.U/.V_ *.U/.V_.U/0V_.U/0V_ 000P/0V_ 000P/0V_ *.U/.V_ *.U/.V_ U HYTF- U HYTF- V N VSS VSSQ UQS VQ UQ VSSQ UM UQS VSSQ UQ VQ UQ VQ VQ UQ0 VQ UQ VSSQ UQ UQ VSSQ UQ V E N E VSS E VSSQ E LQS E VQ E LQ F VSSQ F LM F LQS F VSSQ F LQ F VQ G LQ G VQ G VQ G LQ0 G VQ0 G LQ H VSSQ H LQ H LQ H VSSQ0 H LQ H VL J VREF J VSS J VSSL J K J V J KE K WE K RS K K K OT K N L 0 L L S L S L 0 M M M 0 M V M VSS N N N N N P P P P VSS P V R R N R N R N R R K/F_ R K/F_.U/.V_.U/.V_.U/0V_.U/0V_

19 . If L connector near GPU, then place these series Resistors near GPU. If L connector near N/, then place these series Resistors near N/ [] L_LK [] L_LK# [] L_TP0 [] L_TN0 [] L_TP [] L_TN [] L_TP [] L_TN [] L_LK# [] L_LK [] L_TP0 [] L_TN0 [] L_TP [] L_TN [] L_TN [] L_TP [] EXT_TXLLKOUT [] EXT_TXLLKOUT- [] EXT_TXLOUT0- [] EXT_TXLOUT0 [] EXT_TXLOUT [] EXT_TXLOUT- [] EXT_TXLOUT [] EXT_TXLOUT- [] EXT_TXULKOUT [] EXT_TXULKOUT- [] EXT_TXUOUT0 [] EXT_TXUOUT0- [] EXT_TXUOUT- [] EXT_TXUOUT [] EXT_TXUOUT- [] EXT_TXUOUT OPTION SIGNL FROM N FOR UM VG RP *PR-S-0 RP *PR-S-0 RP *PR-S-0 RP *PR-S-0 RP0 RP RP RP OPTION SIGNL FROM Nvidia to VG RP PR-S-0 RP PR-S-0 RP PR-S-0 RP PR-S-0 RP RP0 RP RP PR-S-0 PR-S-0 PR-S-0 PR-S-0 TXLLKOUT TXLLKOUT- TXLOUT0 TXLOUT0- TXLOUT TXLOUT- TXLOUT TXLOUT- *PR-S-0 *PR-S-0 TXULKOUT- TXULKOUT TXUOUT0 TXUOUT0- *PR-S-0 TXUOUT TXUOUT- *PR-S-0 TXUOUT- TXUOUT TXLLKOUT TXLLKOUT- TXLOUT0- TXLOUT0 TXLOUT TXLOUT- TXLOUT TXLOUT- TXULKOUT TXULKOUT- TXUOUT0 TXUOUT0- TXUOUT- TXUOUT TXUOUT- TXUOUT V R0 VIN R.U/0V_ [,] PST_PWM L V.K_.K_ EILK EIT FM HM0-T R/F_ LOGO_PWR [,,,,0,,,,,0,,,,,,,,,,0,,,,,,,] V [,0,,,,,,0,,,] V [,,,0,,,,] VIN [,,0,,,,,,] VPU [,,,] VLW VIN_LIGHT 000 use 00 ohm and must change back to ohm PV uild R.0U/0V_ R 0.U/0V_ *0_ VL_ON V *0U/V_ Keep pin N to prevent burning 000P/0V_ SI- hange Pin define / FWF0MS00 VIN_LIGHT VIN_LIGHT VIN_LIGHT PV uild VL_ON EILK [,,] VJ [,,] EIT LOGO_PWR 0 LON_ON amera Pin 0 Modify 000P/0V_TXLLKOUT TXULKOUT TXLLKOUT- 0 TXULKOUT- TXLOUT0 TXUOUT0 TXLOUT0- TXUOUT0- TXLOUT 0 TXUOUT TXLOUT- TXUOUT- TXLOUT TXUOUT TXLOUT- TXUOUT- 0 N L ONN [] PWM_VJ R 0_ VJ *.U/.V_.U/0V_ PV uild elete N0,R,(Remove Logo light) R0V-0 PN_LON LON_ON lose to E R K/F_ [,] LVS_LON LI_E# [,] [] L_K Q TEU R0V-0 R 00K/F_ VPU R K_ P/0V_ [,] ISP_ON Q TEU VSUS R 00K/F_.v R0 0K_ VLW Q MEN00E O0 I current. LONG Q O0.0U/V_ LON# V.U/0V_ VL L PY00T-/0 R _ LISHG Q MEN00E.0U/V_ VL_ON ISP_ON R 00K/F_ LVS_LON R 00K/F_.U/0V_ 0U/.V_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev L ONN/Lid function ate: Tuesday, February, 00 Sheet of

20 RT_R_ON RT_G_ON RT ON R 0/F_ R 0/F_ V R 0/F_ V VRT F 0 mils VRT 0 MIL FUSEV_POLY SSM spec is 0V L L L.P/0V_.P/0V_.P/0V_ NQ00T-0Y-N_ NQ00T-0Y-N_ NQ00T-0Y-N_ RT_R RT_G RT_.U/0V_.P/0V_.P/0V_.P/0V_ EMI R 0_ [,,,,0,,,,,,,,,,,,,,,0,,,,,,,] [,,,,,,,0,,,] RT PORT LK FSFR0 0 V V PV uild hange Layout footpr to dsub-00fr0sxzr-p-v RT ONN N V V PV uild hange ES protection to V *VW *VW *VW *VW 0 RT_R_ON RT_G_ON RT ON LK.U/0V_ R 0_ R 0_ RTVSYN RTHSYN *VW U R 0_ T PR_VSYN [,] VSYN_OM PR_VSYN [] U MVHGTFG MVHGTFG *0P/0V_ *P/0V_ *P/0V_ *0P/0V_ *VW PR_HSYN [,] HSYN_OM PR_HSYN [] V [,] LK V [,] T R LK R T.K_.K_ V V Q MEN00E Q MEN00E VRT R0V-0 LK [] LK T T [] V_RT R.K_ R.K_ [,] [] [] [] PR_RE PR_GEN PR_LU PR_INSERT# RT_R_ON RT_G_ON RT ON U RT SWITH I0 I I0 Y I Y I0 Y 0 I Y I0 I SEL V /E GN T PV uild 0.U/0V_ EMI RT_R [,] RT_G [,] RT_ [,] V R 0K/F_ inputs /E SET L L H L H X 0 *VW function Y - port 0 Y - port isconnect T For UM HMI function V 0 *.U/0V_ L EMI *0_ V_LS 0 *.0U/V_ *.U/0V_ R *K/F_ SVO_T SVO_LK P0 R P R REXT R RT_EN# R FG R0 FG0 R V [] EQULIZTION SETTING P:P0=0:0 d P:P0=0: d Recommanded P:P0=:0 d P:P0=: 0d SLZ/SZ Low-level input/output Voltage FG:FG0=0:0 VIL:<0.V VOL:0.V (efault) GF:GF0=0: VIL:<0.V VOL:0.V GF:GF0=:0 VIL:<0.V VOL:0.V GF:GF0=: VIL:<0.V VOL:0.V *0_ *0_ *0_ *0_ *0_ *0_ 00 *.0U/V_ *.0U/V_ *.0U/V_ R0 *K/F_ [] [] [] [] [] [] [] [] [] [] IN_LK IN_LK# IN_0 IN_0# IN_ IN_# IN_ IN_# SVO_LK SVO_T HMI_HP_ON V R *.K_ R *.K_ R *.K_ R0 *.K_ R0 *.K_ R */F_ N_TX_HMI- TX_HMI TX_HMI- TX0_HMI TX0_HMI- TX_HMI TX_HMI- TX_HMI TX_HMI- _EN P0 P FG FG0 RT_EN# REXT 0 0 *PR-S-0 *PR-S-0 *PR-S-0 *PR-S-0 V V V V V V V V SL S HP U _EN P0 P UF_EN FG RT_EN# OE# REXT ONTROL POWER GN RP RP IN_ IN_- IN_ IN_- IN_ IN_- IN_ IN_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- GN GN GN GN GN GN GN GN GN GN EP *PIVPLSZE 0 SL_SINK S_SINK HP_SINK 0 HMI_SL HMI_S HMI_ET V Q MEN00E R0V-0 R _ R _ N_TX_HMI N_TX_HMI N_TX0_HMI N_TX_HMI _TX_HMI- _TX_HMI N_TX_HMI- TX_HMI TX_HMI- TX0_HMI TX0_HMI- TX_HMI TX_HMI- TX_HMI TX_HMI- N_TX_HMI- N_TX0_HMI- R R R R R0 R R R0 R0 K/F TX_HMI _TX_HMI _TX0_HMI HMI_SL_ HMI_S_ UM : 0R NM-GE/NP-GS: 0.uF /F_ /F_ /F_ /F_ /F_ /F_ /F_ /F_ R00 K/F_ 00 _TX_HMI _TX_HMI- _TX_HMI- _TX_HMI- _TX0_HMI- _TX_HMI-.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ L 0_ L *0P/0V_ V HMI_ET_N 0_ F L0 0_ HMISL HMIS 0 *0P/0V TX_HMI N_TX_HMI N_TX_HMI- N_TX_HMI N_TX_HMI- RP N_TX_HMI N_TX_HMI- RP N_TX0_HMI N_TX0_HMI- _TX_HMI- _TX0_HMI _TX0_HMI- _TX_HMI FUSEV_POLY HMI_ET_ HMISL HMIS V_HMI 0P/0V_ R 0K/F_ HMI_ET_N [] HMI_ET V_HMI [] HMI_SL [] HMI_S For EXT VG [] N_TX_HMI [] N_TX_HMI- [] N_TX_HMI [] N_TX_HMI- [] N_TX0_HMI [] N_TX0_HMI- [] N_TX_HMI [] N_TX_HMI- Only for NVII V VW R 00K/F_ FHMR0 N SHELL 0 SHELL Shield V_HMI - Shield Shield *.0U/V_ 0-0 K K Shield K- E Remote N for EMI request LK T GN V HP ET SHELL SHELL HMI PORT HMI ONN N PROJET : QT Quanta omputer Inc. Size ocument Number Rev RT/PS0 HMI onn ate: Tuesday, February, 00 Sheet 0 of

21 VPU VRT SI build R00V-0 0 U/.V_ 0 P/0V_ [,,0,,,,,,] VPU [] VRT [,,,,0,,,,,,0,,,,,,,,,0,,,,,,,] V [,,,,,,,,0,].V [,,,,,,,,,0,].0V [,,,,] VS 0MIL VRT_ R K/F_ VRT_T update footpr (00) [] ST_LE# For R0(Large) T T_ONN HP Request 0 R00V-0 SI build T_OMO_EN# R *K/F_ R R.U/0V_ V 0K_ M/F_ R G *SHORT_ P.U/0V_ SI- Notice: GPIO is also a strap pin. on't pull it to high. 0K/F_ R0 0K/F_ IH_ST_LE# U MVHG0FTG U/.V_ ST H [] ST_RXN0 [] ST_RXP0 [] ST_TXN0 [] ST_TXP0 [] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP ST O Y R 0M_ G.KHZ *SHORT_ P U RT_X 0 RT_X RTX P/0V_ RTX RT_RST# SRT_RST RTRST# F0 SM_INTRUER# SRTRST# INTRUER# IH_INTVRMEN LN00_SLP INTVRMEN LN00_SLP TP TP GLN_LK LN_RSTSYN E GLN_LK LN_RSTSYN LN_RX0 TP F LN_RX LN_RX0 TP0 G LN_RX LN_RX TP LN_RX LN_TX0 TP LN_TX LN_TX0 TP LN_TX LN_TX TP E LN_TX TP GPIO 0 GPIO.V R0./F_ GLN_OMP GLN_OMPI GLN_OMPO Z_LK F Z_SYN H_IT_LK H H_SYN Z_RST# E H_RST# [] Z_SIN0 F H_SIN0 [] Z_SIN G H_SIN [] Z_SIN H H_SIN [] Z_SIN E H_SIN Z_SOUT G H_SOUT TP G H_OK_EN#/GPIO [] T_OMO_EN# E H_OK_RST#/GPIO IH_ST_LE# G STLE#.0U/V_ ST_RXN0_ J.0U/V_ ST_RXP0_ ST0RXN H.0U/V_ ST_TXN0_ ST0RXP F.0U/V_ ST_TXP0_ ST0TXN G ST0TXP 0.0U/V_ ST_RXN_ H.0U/V_ ST_RXP_ STRXN J.0U/V_ ST_TXN_ STRXP G.0U/V_ ST_TXP_ STTXN F STTXP IHM REV.0 RT LP LN / GLN PU IH ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/GPIO 0GTE 0M# PRSTP# PSLP# FERR# PUPWRG IGNNE# INIT# INTR RIN# NMI SMI# STPLK# THRMTRIP# TP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP ST_LKN ST_LKP STRIS# STRIS K L0 [,] K L [,] L.0V L [,] K L [,] K LFRME# [,] J IH_RQ#0 TP0 J IH_RQ# TP0 R R R 0K/F_ V *./F_ *./F_ N GTE0 [] J H_0M# [] J E J H_PWRG [] F.0V H_IGNNE# [] E H_INIT# [] H_INTR [] L RIN# [] R 0K/F_ V R F H_NMI []./F_ F H_SMI# [] H H_STPLK# [] G H_THERMTRIP_R R./F_ G H J G F IH_TP H ST_RXN_ J ST_RXP_ 0 E0 ST_TXN_ F0 ST_TXP_ H J J ST_RIS_PN H TP.0U/V_.0U/V_.0U/V_.0U/V_ LK_PIE_ST# [] LK_PIE_ST [] R./F_ ST_RXN [0] ST_RXP [0] ST_TXN [0] ST_TXP [0] H_PRSTP# [,,] H_PSLP# [] R0./F_.0V PM_THRMTRIP# [,] E-ST ONNET Z_RST# R _ Z_SOUT R0 _ Z_SYN R00 _ Z_LK R0 _ For H udio R./F_ H_FERR# [] Z_RST#_UIO [] Z_SOUT_UIO [] Z_SYN_UIO [] IT_LK_UIO [] *0P/0V_ *0P/0V_ *0P/0V_ S Strap IH-M Internal VR Enable strap (Internal VR for Vccsus_0,VccSus_ and VccL_) VRT IH_INTVRMEN IH-M LN00_SLP Strap (Internal VR for VccLN_0 and VccL.0) Low = Internal VR disable Low = Internal VR disable INTVRMEN High = Internal VR LN00_SLP High = Internal VR enable(efault) enable(efault) R K/F_ R *0_ VRT R K/F_ LN00_SLP R *0_ XOR hain Entrance Strap IH_TP 0 0 V H_SOUT 0 0 Z_SOUT escription RSV Enter XOR hain Normal opration(efault) Set PIE port config bit Z_RST# R _ Z_SOUT R _ Z_SYN R0 _ Z_LK R _ Z_RST# R Z_SOUT R Z_SYN R Z_LK R Low = swap override enabled Z_RST# R _ R PI_GNT# IH_GPIO Low: efault Z_SOUT R _ Hi = efault Z_SYN R _ *K/F_ Z_LK R _ R IH_TP [] IH oot IOS select STRP PI_GNT0# SPI_S# SPI 0 PI 0 LP *K/F_ *K/F_ R swap override strap *K/F_ R R (default) GNT0# [] SPI_S#_R [] GNT# [] No Reboot Strap Low: efault Z_SPKR Hi: No reboot R *K/F_ V TPM physical presence VS R0 *0K/F_ Z_SPKR [,,] For M For UM *0P/0V_ *_ *_ *_ *_ *0P/0V_ lose to U For iscrete *0P/0V_ Z_RST#_M [] Z_SOUT_M [] Z_SYN_M [] IT_LK_M [] *0P/0V_ *0P/0V_ Z_RST#_MH [] Z_SOUT_MH [] Z_SYN_MH [] Z_ITLK_MH [] 0 0 *0P/0V_ *0P/0V_ NV_H_RST NV_H_RST [] NV_H_SO NV_H_SO [] NV_H_SYN NV_H_SYN [] NV_H_LK NV_H_LK [] 0 *0P/0V_ *0P/0V_ *K/F_ R0 00K/F_ IH_GPIO [] PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom IH-M Host / ate: Tuesday, February, 00 Sheet of

22 SWP PIE PORT to PORT (Lan and New card swap) -->Rename the port name by function and port MINI R PI-E(WLN) SI- PIE-LN TV R PI-E SI- EXPRESS R (NEW R) R *0K/F_ V *.U/0V_ U R0 *_ SPI_S#0_R V E# R *_ SPI_LK_R SK R0 *_ SPI_MOSI SPI_HOL# SI SPI_MISO HOL# SO R0 *_ VSS K byte SPI ROM For HP only For GM HP [] PIE_RXN0 [] PIE_RXP0 [] PIE_TXN0 [] PIE_TXP0 [] PIE_RXN_LN [] PIE_RXP_LN [] PIE_TXN_LN [] PIE_TXP_LN [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP [] SPI_S#_R SPI_WP# WP# *WX0VSSIG PV uild R *0_ *0P/0V_ SPI_LK_R EMI 0 *.U/0V_ PLK_IH V.U/0V_.U/0V_.U/0V_.U/0V_ SI-.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ R *0K/F_ PIE_RXN0 PIE_RXP0 PIE_TXN0_ PIE_TXP0_ PIE_TXN_ PIE_TXP_ SPI_LK_R SPI_S#0_R SPI_MOSI SPI_MISO INT# INT# INT# INT# U N PERN N PERP P PETN P PETP L PERN L PERP M PETN M PETP J PERN J PERP K PETN K PETP PIE_RXN G PIE_RXP PERN G PIE_TXN_ PERP H PIE_TXP_ PETN H PETP IHM REV.0 PI-Express irect Media Interface MI0RXN V MI0RXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP PIE_RXN E PIE_RXP PERN MI_LKN T E PIE_TXN_ PERP MI_LKP T F PIE_TXP_ PETN F PETP MI_ZOMP F PIE_RXN MI_IROMP F PIE_RXP PERN/GLN_RXN PIE_TXN_ PERP/GLN_RXP USP0N PIE_TXP_ PETN/GLN_TXN USP0P PETP/GLN_TXP USPN USPP SPI_LK USPN SPI_S0# USPP F SPI_S#/GPIO/LGPIO USPN USPP SPI SPI_MOSI USPN E SPI_MISO USPP US_O#0 USPN N US_O# O0#/GPIO USPP N US_O# O#/GPIO0 USPN N US W US_O# O#/GPIO USPP W P US_O# O#/GPIO USPN Y M US_O# O#/GPIO USPP Y N US_O# O#/GPIO USPN W M US_O# O#/GPIO0 USPP W M US_O# O#/GPIO USPN V N US_O# O#/GPIO USPP V N US_O#0 O#/GPIO USP0N U P US_O# O0#/GPIO USP0P U P O#/GPIO USPN U USRIS_PN USPP U G USRIS G USRIS# R./F_ U 0 E E E0 G 0 F F E F0 0 F 0 F F G H G H G 0 H PI Interrupt I/F J PIRQ# E PIRQ# J PIRQ# PIRQ# IHM REV.0 REQ0# F GNT0# G REQ#/GPIO0 GNT#/GPIO REQ#/GPIO F GNT#/GPIO F REQ#/GPIO E GNT#/GPIO F /E0# /E# /E# /E# IRY# PR E PIRST# R EVSEL# PERR# E PLOK# SERR# J STOP# TRY# F FRME# PLTRST# PILK PME# R PIRQE#/GPIO H PIRQF#/GPIO K PIRQG#/GPIO F PIRQH#/GPIO G USP- USP REQ0# GNT0# REQ# GNT# REQ# GNT# REQ# GNT# IRY# EVSEL# PERR# LOK# SERR# STOP# TRY# FRME# PI_PME# INTE# INTF# INTG# INTH# MI_RXN0 [] MI_RXP0 [] MI_TXN0 [] MI_TXP0 [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] MI_RXN [] MI_RXP [] MI_TXN [] MI_TXP [] LK_PIE_IH# [] LK_PIE_IH [] MI_IROMP_R USP0- [0] USP0 [0] USP- [0] USP [0] USP- [0] USP [0] USP- [0] USP [0] USP- [] USP [] USP- [0] USP [0] GNT0# [] GNT# [] SERR# [] PLT_RST-R# [,] PLK_IH [] INTH# [] [,,,,,,,,0,].V [,,,,0,,,,,,0,,,,,,,,,0,,,,,,,] V [,,0,,0,,,] VSUS.V US onnector E-ST and US onnector FINGERPRINT arama US ocking LUETOOTH USP- [] USP [] NEW R USP- [0] USP [0] US onnector USP- [0] USP [0] US onnector USP0- [] USP0 [] Robson Min-ard USP- [] USP [] TV Min-ard TP TP R 00K/F_ R./F_ U *MVHG0FTG PLT_RST-R# VS V V V VS R0 0_ SI- elete elete RP,RP and tied from S to R(US) USP- USP INTF# LOK# IRY# PERR# REQ# FRME# TRY# REQ# INTH# INT# SERR# INT# US_O# US_O# US_O# US_O# US_O# US_O# US_O# US_O# PI_PME# 0 *.U/0V_ R *00K/F_ 0 R des RP 0 RP PLTRST# [,,,,] N SI- 0PR-.K RP 0 0PR-.K 0PR-.K RP 0 0PR-.K R0 R R R.K/F_.K/F_.K/F_.K/F_ 0K/F_ USP_R- [] USP_R [] REQ0# INTG# INTE# INT# EVSEL# REQ# STOP# INT# US_O#0 US_O# US_O#0 US_O# VS VS V V V VS PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom IH-M PIE / ate: Tuesday, February, 00 Sheet of

23 [,,,,,,,,,0,] [,,,,0,,,,,,0,,,,,,,,,0,,,,,,,] [,,,,] [,0,,0,,,].V V VS VSUS SI- [] PLK_SM [] PT_SM [] SYS_RST# [] PM_SYN# [] PM_STPPI# [] PM_STPPU# [] LKRUN# [,,] PIE_WKE# [] SERIRQ [] PM_THRM# [] KSMI# [] SI# [] SWI# [] LE_EN [] L_K [] RF_OFF# [] IH_GPIO# SI- dd for SM function [] IH_GPIO [,,] Z_SPKR [] MH_IH_SYN# [] IH_TP U G SMLK SM_LINK_LERT# SMT E SM_LK_ME LINKLERT#/GPIO0/LGPIO SM_T_ME SMLINK0 SMLINK SM PM_RI# F RI# TP PM_SUS_STT# R SUS_STT#/LPP# G SYS_RESET# M PMSYN#/GPIO0 SM_LERT# SMLERT#/GPIO PM_STPPI_IH# PM_STPPU_IH# STP_PI# E STP_PU# L LKRUN# E0 WKE# M SERIRQ J THRM# VR_PWRGO_LKEN VRMPWRG TP 0 TP TP G GPIO H GPIO G GPIO LN_PHYP GPIO T ENERGY_ET GPIO OR_I GPIO E TP GPIO K GPIO F OR_I GPIO0 J SLOK/GPIO GPIO IH_GPIO GPIO TP L IH_GPIO# STLKREQ#/GPIO E MFG_MOE SLO/GPIO TP G R_SV_ET_R STOUT0/GPIO TP F MI_TERM_SEL STOUT/GPIO TP H GPIO GPIO/LGPIO M SPKR J MH_SYN# IH_TP TP TP H0 IH_TP TP TP J0 IH_TP0 TP TP0 J TP0 IHM REV.0 ST GPIO locks SYS GPIO Power MGT MIS GPIO ontroller Link ST0GP/GPIO STGP/GPIO STGP/GPIO STGP/GPIO LK LK SUSLK SLP_S# SLP_S# SLP_S# S_STTE#/GPIO PWROK PRSLPVR/GPIO TLOW# PWRTN# LN_RST# RSMRST# K_PWRG LPWROK SLP_M# L_LK0 L_LK L_T0 L_T L_VREF0 L_VREF L_RST0# L_RST# MEM_LE/GPIO GPIO0/SUS_PWR_K GPIO/_PRESENT WOL_EN/GPIO H OR_I F OR_I0 E OR_I 0 OR_I H F P E G 0 G0 M R 0 R R F F F 0 SUSLK SLP_S# S_STTE# PM_IH_PWROK LN_RST# IH_SLP_M# L_VREF0_IH L_VREF_IH SUS_PWR_K _PRESENT IH_WOL_EN LK_M_IH [] LK_M_US [] TP TP TP TP TP R SUS# [] SUS# [] PRSLPVR [,] PM_TLOW# [] EPWROK L_LK0 [] L_LK [] L_T0 [] L_T [] 00K/F_ NSWON# [] RSMRST# [] K_PWG [] L_RST#0 [] L_RST# [] *.U/0V_ T_OFF# [0] R *.K/F_ R */F_ VS V R.K/F_ 0.0V R.U/0V_ /F_ SWI# PM_RI# SM_LK_ME SM_T_ME NSWON# PLK_SM PT_SM SM_LERT# PIE_WKE# PM_TLOW# R R R0 R R R R R0 R R00 SM_LINK_LERT# R SYS_RST# R T_OFF# R VS 0K/F_ 0K/F_ 0K/F_ 0K/F_ 0K/F_.K_.K_ 0K/F_ 0K/F_.K/F_ 0K/F_ 0K/F_ 0K/F_ V V IH_TP R *0K/F_ PR K/F_ V iscrete UM PM_THRM# SERIRQ R R.K/F_ 0K/F_ PV uild elete R,G as ios_rec can be cover by ios [] VR_PWRG_K0# Q0 S0--F VR_PWRGO_LKEN R0 00K/F_ R R R R 0K/F_ OR_I0 *0K/F_ OR_I *0K/F_ OR_I *0K/F_ OR_I R R R R *0K/F_ 0K/F_ 0K/F_ 0K/F_ LKRUN# KSMI# SI# IH_GPIO R R0 R R0.K/F_ 0K/F_ 0K/F_ *0K/F_ R 0K/F_ OR_I R *0K/F_ V VSUS R 0K/F_ OR_I R *0K/F_ SUS_PWR_K R 0K/F_ LK_M_US LK_M_IH R R 0_ *_ 0P/0V_ *0P/0V_ [,] ELY_VR_PWRGOO [,,] EPWROK R *K/F_ U R 0_ *.U/0V_ *MVHG0FTG PM_IH_PWROK R 0K/F_ oard I 0: -->iscrete, 0-->UM oard I oard I oard I oard I oard I RSMRST# R 0K/F_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom IH-M GPIO / ate: Tuesday, February, 00 Sheet of

24 V_VPORE_IH VREF V_L_IH TP_VSUS_0_IH_ VS_S_.0V_L_INT_IH.0V_LN_IH TP_VSUS IH_.V_IH_VMIPLL VREF_SUS VS_S_.V_IH_GLNPLL.VSUS_INT_IH V_PI_IH.0V_PU_IO.V_PLL_IH V_MI_IH V_ST_IH V_GLN_IH TP_VSUS_0_IH_ V_VPUX.V_PIE_IH.V_ST_IH.V_US_IH VSUSH.V_L_INT_IH.0V_IH_MI.V_VH.V_PIE_IH.0V.VS.0V VS V VRT VS VS V.0V V.V V V V.V.V.V VS.VS VS V.V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N IH-M Power / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N IH-M Power / ustom Tuesday, February, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : QT N IH-M Power / ustom Tuesday, February, 00 m m V TOTL. m m m m m 0m m. m m m V_ 0m m m VSUS _ m m R Vout=.(R/R) R Install for UM model dis UM dis UM PV uild PV uild PV uild PV uild PV uild PV uild 0U/.V_ 0U/.V_ R 0_ R 0_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ *U/.V_ *U/.V_ U/.V_ U/.V_.U/0V_.U/0V_.U/0V_.U/0V_ 0.0U/V_ 0.0U/V_ R0V-0 R0V-0.U/0V_.U/0V_ 0 U/.V_ 0 U/.V_ L 0uH/00M_ L 0uH/00M_ R0 0_ R0 0_ L H0KF-T_ L H0KF-T_.U/0V_.U/0V_.U/0V_.U/0V_ U *I(P) G (SOT-)EP U *I(P) G (SOT-)EP SHN GN VIN VOUT SET R 0_ R 0_ R0 *00K/F_ R0 *00K/F_ UE IHM REV.0 UE IHM REV.0 VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[0] VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] H VSS[0] F VSS[0] F VSS[0] F VSS[00] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G0 VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[00] J VSS[0] J VSS[0] J VSS[0] J VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] 0 VSS[0] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[00] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[0] G VSS[0] G VSS[0] G VSS[0] G VSS[00] G VSS[0] G VSS[0] G VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] H VSS[0] J VSS[0] J VSS[0] J VSS[] VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[0] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[0] P VSS[] P VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[0] U VSS[] U VSS[] U VSS[] U VSS[] U VSS[] VSS[] U VSS[] U VSS[] U VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] VSS_NTF[0] H VSS_NTF[0] H VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[0] J VSS_NTF[] VSS_NTF[] VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[0] G VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] H VSS[] F VSS[] VSS[] R0 *0_ R0 *0_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0.U/0V_ 0.U/0V_ R *.K/F_ R *.K/F_ R *0_ R *0_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_.U/.V_.U/.V_ 0.U/0V_ 0.U/0V_.U/0V_.U/0V_ L0 uh/00m_ L0 uh/00m_ L H0KF-T_ L H0KF-T_ 0.U/0V_ 0.U/0V_.U/.V_.U/.V_ TP TP R0 0_ R0 0_.U/0V_.U/0V_.U/0V_.U/0V_ L uh/00m_ L uh/00m_.u/0v_.u/0v_ ORE VGP TX RX US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 ORE VGP TX RX US ORE PI GLN POWER VP_ORE VPSUS VPUS UF IHM REV.0 VREF VREF_SUS E V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] E V [0] E V [] E V [] E V [] E V [] F V [] G V [] H V [] H V [] J V [] J V [0] K V [] K V [] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [0] P V [] P V [] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [0] U V_[0] G VMIPLL R V [0] V [0] V [0] V [0] E V [0] F VSTPLL J V_[0] J V [0] V [0] VUSPLL J VLN_0[] 0 VLN_0[] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] E V_0[0] F V_0[0] L V_0[0] L V_0[0] L V_0[0] L V_0[] L V_0[] L V_0[] M V_0[] M V_0[] P V_0[] P V_0[] T V_0[] T V_0[] U V_0[0] U VLN_[] VLN_[] VH J VSUSH J V_PU_IO[] V_PU_IO[] V_[0] F V_[0] G V_[] G V_[] J V_[] J V_[] K VRT VSUS_[0] VSUS_[0] VSUS_[0] VSUS_[0] E VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[0] T VSUS_[] T VSUS_[] U VSUS_[] U VSUS_[] V VSUS_[] V VSUS_[] W VSUS_[] W V [] G0 VSUS_0[] VSUS_0[] F V [] G V [] V [] V [] V [] VSUS_[0] F V_[0] V [] V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V V_0[] V VGLN_[] E VGLN_[] VGLN_[] E VGLN_[] VGLN_ VGLNPLL V_[0] VSUS_[] Y VSUS_[] VSUS_[] F V_MI[] Y V_MI[] W VL_0 G VL_[] VL_[] VL_ G V [] W V [] V V [] U V [] W V [] U V [] V V [] K V [] Y V [] Y V [0] G V [0] H V [0] J V [] E V [] F VSUS_[] Y V_[0] F0 V_[0] G V_[0] 0 V_[0] 0 V [0] V [] G0 V [] V [] V [] V [] J0 V [] H0 V [] G V [] V [] V [0] VSUS_[0] T.U/0V_.U/0V_.U/0V_.U/0V_.0U/V_.0U/V_ U/.V_ U/.V_ 0U/.V_ 0U/.V_ TP TP.U/0V_.U/0V_ 0 *.U/.V_ 0 *.U/.V_.U/.V_.U/.V_ U/.V_ U/.V_ R 0_ R 0_.U/.V_.U/.V_ 0 *0U/.V_ 0 *0U/.V_ R 0_ R 0_ TP TP.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ U/.V_ U/.V_.0U/V_.0U/V_ 0.U/.V_ 0.U/.V_.U/0V_.U/0V_ R0V-0 R0V-0 U/.V_ U/.V_ 0.U/0V_ 0.U/0V_

25 R_LE# USP_R- USP_R LK_M_R For E VSUS SI- Fix Y layout footpr to XTL-X_-_ (ME placement) R R *0K/F_ R R R0 *.P/0V_ R *0K_ VSUS R SI- modified -- If S_T connect to SP, MO_SEL need to let it to N. R0 *.P/0V_ For *P/0V_ XTLO XTLI *0_ G000 MOE_SEL XTLO R *00K/F_ U X_LE/F_ X_E#/F_ R_LEO# X_LE/F_ *0_ F_# GPIO0 F_0 S_T/X_RE#/F_ 0 F_ S_T/X_WE#/F_ F_ X_RY/F_ X_# F_/SM_# S_T/X_WP#/F_ SP F_/X_# 0 S_# F_0/SM_WPM#/S_WP S_M F_0/S_# S_T/X_0/F_ SP F_MK# S_LK/X_/MS_LK/F_ F_/X_ S_T/X_/MS_/F_ F_MRQ F_S0# 0 RREF MS_INS#/F_IOR# *.K/F_ RREF S_T/X_/MS_/F_IOWR# S_T0/X_/MS_0/F_RST# S_T/X_/MS_/F_IORY M X_/MS_S/F_ *0_ *0_ P M P V_PLL_IN *MHz Y XTLO XTLI MOE_SEL *00K/F RST# RST# *U/.V_ *Realtek RTS SP SP SP SP SP SP SP S_M_R SP SP SP0 MS_# SP SP SP SP VREG_OUT 0 VREG V_IN V_ IN V_ IN *.U/0V_ V_OUT V_OUT R_V_OUT G G_PLL GN GN *.U/0V_ *.U/0V_ VR VSUS 0 *.U/.V_ SP SP Vreg out.v from Internal.VLO *U/.V_ *.U/0V_ *U/.V_ *.U/0V_ For R *0_ For E VSUS_RTS VSUS R0 *.U/0V_ VR S_T L000 -->RTSE L >RTS *.U/0V_ *0_ R *.U/.V_ *0_ *.U/0V_ VSUS *.U/0V_ *.U/0V_ Note: S/MM MS X SP0 SP X_# SP S_WP SP S_# SP S_T X_ SP MS_S X_ SP S_T MS_ X_ SP S_T0 MS_0 X_ SP S_T MS_ X_ SP MS_INS# SP0 S_T MS_ X_ SP S_LK MS_SLK X_ SP S_T X_0 SP S_T X_WP# SP X_R/# SP S_T X_WE# SP S_T X_RE# SP X_LE SP X_E# SP X_LE For RTS SP R *0_ MS_T0_S_T0 SP R R *0_ *0_ X- MS_T R *0_ X- SP MS_T_X_ SP R *0_ S_T SP R R *0_ *0_ X-RE# MS_S R *0_ X- SP R *0_ S_T R *0_ X_WE SP R *0_ RTS_S/MS_LK R *0_ X- SP S_WP SP X-WP# SP X-LE SP X- SP0 R *0_ MS_T R *0_ X- SP X-R# SP X-0 SP X-LE SP X-E# S_M_R S_M SI- hange net name as lk trace layout T-stub VR X-WP# VR R0 *0K/F_ R0 0_ MS_# 0.U/.V_ LOSE ONN *0P/V_ R 0K/F_ X-R# X-RE# X-E# X-LE X-LE X_WE X-WP#_L X-0 X- S_T S_T S_M S_MS_LK MS_T MS_# MS_T_X_ MS_T0_S_T0 MS_T MS_S VR.U/0V_ IN R REER X,MM/S,MS/MSP PV uild VR SI uild N X-R/ GN X-RE GN X-E GN 0 X-LE GN X-LE GN X-WE X-WP S-/ X-T0 S--SW X-T S-W/P 0 S-T S-WP-SW S-T X- S-M X-V GN X-T MS-V X-T MS-SLK X-T 0 MS-T S-T MS-INS X-T MS-T X-T MS-T0 X-T 0 MS-T S-T0 MS-S S-LK GN S-V.U/0V_ *IN R REER SOKET FHMR00 in-00-p-l 0.U/0V_ M_PWR_TRL_0# V VR X_# S_# S_# S_WP S_WP X_# X- X- X- S_T X- X- MS_T_X_ MS_T0_S_T0 S_MS_LK Q *ME0T 0mils R R0V-0 R0V-0 0P/0V_ VR 0mils S_# SI- V VR MS_# S_# hange net name as lk trace layout T-stub R andn R change to ohm SI- *0K/F_ R 0_ 0 *0P/V_ MIO00 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO MIO MIO MIO JM 0 Note: MI0 S_T0 MS_0 X_0 MI S_T MS_ X_ MI S_T MS_ X_ MI S_T MS_ X_ MI S_M MS_S X_WE# MI S_LK MS_SLK X_E# MI S_WP X_WP# MI X_LE MI S_T X_ MI S_T X_ MI0 S_T X_ MI S_T X_ MI X_RE# MI X_R/# MI X_LE R_LEN S_LE# MS_LE# X_LE# R_PTLN S_PTL#MS_PTL#X_PTL# R_0 S_# X_V# R_ MS_# X_# S/MM MS X For JM0 R 0_ MS_T0_S_T0 R0 R 0_ 0_ X-0 S_T R 0_ MS_T R0 0_ X- R 0_ MS_T_X_ R0 0_ S_T R 0_ MS_T R 0_ S_T R 0_ X- R 0_ S_M R 0_ MS_S R 0_ X_WE R _ R _ R 0_ R0 0_ R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ R 0_ JM 0 Note: JM_S/MS_LK X-E# S_WP X-WP# X-LE X- X- X- X- X-RE# X-R# X-LE VR N X-R# X-RE# x-r/ X-E# x-re X-LE x-e X-LE x-le X_WE x-le X-WP#_L x-we X-0 x-wp X- x-0 S_T x- 0 S_T S-T S_M S-T S-M GN S_MS_LK MS-V MS_T MS-SLK MS_# MS-T MS_T_X_ MS-INS MS_T0_S_T0 MS-T MS_T MS-T0 0 MS_S MS-T MS-S GN lose to N From JM0 PV uild Update N library to IN-R0--LM-P-L TI TWUM IN R REER SOKET JM_S/MS_LK R0 0_ S_MS_LK From RTSE RTS_S/MS_LK R *0_ S_MS_LK New add R0,R for S/MS LK trace layout N SI- GN GN GN GN N 0 N S- S-WP x- x-v x- x- x- 0 S-T x- x- x- S-T0 S-LK S-V S_# S_WP X_# X- X- X- S_T X- X- MS_T_X_ MS_T0_S_T0 S_MS_LK FHMR00 VR PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom RTS & R SOKET &HOLE ate: Tuesday, February, 00 Sheet of

26 V TP0N TP0P PV uild Modify N layout footpr to -00FR00S0ZL-P-H-QT.0U/V_.0U/V_ TP0N TP0P TPIS0 TPIS0 R./F_ R./F_ 0.U/.V_ FH0FR00.0U/V_.0U/V_ 0U/.V_ R M/F_ Y.MHZ 0P/0V_ 0P/0V_ Modify Y size to *. 0.V_R MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO0 MIO00 V 0 R K/F_ U0 V TXIN TXOUT MIO MIO MIO MIO V MIO MIO MIO MIO0 TREXT TPIS_ TPP TPN TPP TPN V 0 TV MIO MIO MIO0 JM0-QGZ0 MIO MIO TPS MIO MIO R_LEN V 0 V V R_PTLN R_0N R_N E_WKEN N R R_PPE# MIO0 MIO0 MIO0 MIO MIO MIO MIO R_LE# V 0K/F_.V_R M_PWR_TRL_0# TP R.K_ TP0N TP0P TP0P TP0N V dd TP for E R.K_ L *WM0-0 L R R SI- *WM0-0 S_# MS_#./F_./F_ TP0P TP0N TP0P TP0N 0P/0V_ Modify N layout footpr to -00FR00S0ZL-P-H-QT (/) R0V-0 R IH_GPIO# SI- dd for E SI- _ONN N / hange Library.K/F_ SI- hange to 0K PLTRST# LK_PIE_R# LK_PIE_R PIE_TXP PIE_TXN PIE_RXN PIE_RXP 00 0 EP XRSTN XTEST PLKN.U/0V_.U/0V_ PLKP PV.V_R PGN PREXT PRXP R PIE_RXN_ PIE_RXP_ PRXN.K/F_.V_R PV 0 PTXN PTXP JM0 don't needs it at MP vesion HIP.V L SI- hange to 0K *H0KF-T_ 0U/.V_.0U/V_.0U/V_.U/.V_.V_R SI- MIO0 R MIO R 0K/F_ 0K/F_ VR R 0K/F_ MIO0 R 00K/F_ MIO R 00K/F_ MIO V PROJET : QT Quanta omputer Inc..U/.V_ N Size ocument Number Rev JM0 ontroller/ ate: Tuesday, February, 00 Sheet of

27 [] Z_SOUT_UIO [] IT_LK_UIO [] Z_SIN0 [] Z_SYN_UIO [] Z_RST#_UIO [,,] Z_SPKR V PV uild V_V lose to Pin SI- U hange P footpr as IT datasheet QFN-X--P-H.U/0V_ 0U/.V_ U/.V_ [0] IGITL_LK [] EP# [] SPIF [0] IGITL_.V R *0_ SI uild V_V R 0_ is V_V lose to Pin IGITL_ GN R0 hange to no-stuff 0K/F_ PV uild.u/0v_ V_V VREFOUT_E_L R *.K_ S_# -->EXT MI R0 *0_ R *.K_ R00 *0_ lose to Pin VREFOUT L R.K_ S_E#--> OK MI R.K_ R0 *0_.VV.U/0V_ udio JK: Normal Open R *0_ MI_R.U/.V_ EXT_MI_R GN MI_L.U/.V_ EXT_MI_L TO udio Jack MI R0 *0_ R.K_ GN R R *0_ PV uild.k/f_ GN SHIEL OK_MI_R 0.U/.V_ OK_MI_R R 0K/F_ R *0_ JK_SEN# R.K/F_ SENSE_ OK_MI_R [] TO OKING GN SHIEL OK_MI_L.U/.V_ OK_MI_L R 0K/F_ OK_MI_L [] MI 000P/0V_ S_# R 0K/F_ 0 GN SHIEL 000P/0V_ R.K_ GN TO UIO/ ON. [,] IR_IN 0 SI- UM TP R VPU S_# S_# 0 GN GN *0P/0V_ *0P/0V_ 0 *P/0V_ EMI 0 *0P/0V_ V_.V_VIO.U/0V_ FFFR 0.U/0V_ GN GN.U/0V_ PV uild ERP_L ERP_R EXT_MI_L EXT_MI_R 0 *P/0V_ R _ R 0_ 0P/0V_ GN _ITLK SI- PV uild GN U R _ Z_SIN0_ K_.U/0V_ N UIO ONN 0 0 GN OK_MI_L GN EP SPIF0 EP MI_LK GPIO / SPIF OUT GPIO GPIO VSS** PORT_R V_ORE VOL_UP/MI_0 V_IO VOL_N/MI_ SO ITLK VSS SI_OE V_ORE SYN RESET# PEEP SENSE_ PORTE_L IT HPXNLGXX PORTE_R PORTF_L PORTF_R OK MI ETET R 0K/F_ N N GN N 0 N 0 PORT_L PORT_L PORT_R.VV.VV lose to Pin.U/.V_ 0U/.V_ PV uild.u/0v_ hange P/N and Layout footpr V** PORT_L R 0K/F_ N PORT-_R PORT-_L SENSE_ / N P MONO_OUT VREFOUT-E / GPIO GPIO 0 VREFOUT- VREFOUT- PORT_R GN R 0K/F_ V GN VREF_FLT.VV SI- 0U/V_ESR GN SHIEL ERPO_R ERP_R 0U/V_ESR GN SHIEL ERPO_L ERP_L GN SHIEL TO Internal Speakers SENSE_ VREFOUT_E IT_GPIO# VREFOUT_ VREFOUT_ Q KMI_SEN Q MMT0--F R MMT0--F K_ U/.V_ VREFFILT VSS V GN TO Headphone jack.u/0v_ S_E# U/.V_ HP-R [] HP-L [] GN PV uild Q0 MEN00E VREFOUT_E_L IT_GPIO# [] VREFOUT L VREFOUT L PV uild 0U/.V_ PV uild [] JK_SEN# R 00K/F_ S_# GN.VV V GN U/.V_ R0.K/F_ SI- R P/0V_ Fixed loss connecting R *0_ U/.V_ V.U/0V_ JK_SEN# R0 00K/F_.K/F_ SI uild 0U/.V_ GN GN S_E# U/.V_ GN GN hange, to 0pf elete R0 0K/F_ Q N00E Q N00E L U Vout Vin YP U/.V_ GN EN TPS VLW GN _ITLK Q GN N00E *0_ MINON Vset=.V Z_SIN0_ ERPO_L FOR EMI S_# -->EXT HP ERPO_R Q N00E R *0_ *P/0V_ R *0_ V R Q N00E 0_.0U/V_ R.U/0V_ 0_ V_ EP#.0U/V_ MINON [,,0,,,] SI- / Reserve for EP# R *.K/F_ V_V *P/0V_ N PV uild U/.V_ PORT MONO_OUT PORT PORT PORT PORT PORT E PORT F M GN E V PV-uild elete R0,R dd for switch circuit as Hp request PV uildhange P/N and Layout footpr 0U/V_ESR R R *0_ 0U/V_ESR *0_.U/0V_ OK_RSPK [] OK_LSPK [] PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom zalia ITH ate: Tuesday, February, 00 Sheet of E PLE TO X HP OUT M/ MI X Internal Speckers ocking MI X IGITL MI TO OK Headphone 0U/.V_

28 V UIO MPLIFIER R 0_ [] HP-L [] HP-R VMP Swap udio input source as Speaker o noise issue hange R,R from 0K to 0 ohm as HP request 0U/.V_ R 0_ HP_L_.0U/V_ R 0_ HP_R_.0U/V_ PV uild P_EEP.U/0V_ MP_GN.U/0V_.0U/V_.U/0V_ VMP UIO_G0 UIO_G E H udio _SPKR_L _SPKR_R MP_YPSS hange R0 from 00K to 0K(S0F) [] VOLMUTE# [] EP# L_SPK- U PV ROUT PV ROUT- V LOUT LIN- LOUT- RIN- SHUTOWN LIN RIN N EP 0 YPSS GN GN GIN0 GN GIN GN 0 TP0/FN0/LM V R0 MP_GN 0K/F_ MP_SHUT# T SI- 00P/0V_ MP_GN 00P/0V_ 00P/0V_ 00P/0V_ R_SPK R_SPK- L_SPK L_SPK- R 0_ R 0_ 00P/0V_ SI- R 0_ R0 0_ 00P/0V_ SI- R_SPK 00P/0V_ L_SPK R_SPK- 00P/0V_ N INT SPEKER ONN INT. SPEKER hange Power source to VPU MUTE_LE as power situation Low -->un-mute VPU High-->Mute PV uild R0 hange R0 from 0K to 00K 00K/F_ SI- GN [] KEY_EEP [,,] Z_SPKR MP_GN VMP *.U/V/0 SI- *0.UF/0 P_EEP L00K0 L0K P0,L000K00 dd in SI- dd,u,r,r,r0,,,0 for P-eep function R, change to no-stuff for SI- test -->/ R *K/0 0 Gain Table GIN0 GIN V RIN 0 0 d 0K VMP 0 0d 0K 0.d K.d K MP_GN V [] VOLMUTE# [] IT_GPIO# [,] MUTE_LE R0 0K/F_ T SI- MUTE_LE_R PV uild R *0_ R *0_ Q MEN00E U *NSZ GN R *0_ R0 *K/0 GN MP_GN.U/0V_ MP_GN 0.U/0V_ R R 00K/F_ *00K/F_ R UIO_G0 UIO_G R *K/F_ K/F_ R GN *0_ MP_GN ccelerometer Sensor V U HP0LTR V reserved second source 0 0U/.V_.U/0V_.U/0V_ Vdd_IO V Reserved Reserved *.U/0V_ 0 *0.U/.V_ U V V_IO Reserved Reserved 0 [] INTH# [,0,,,] GT_SM [,0,,,] GLK_SM V R *0K/F_ PV uild INT INT SO S/SI/SO SL/SP S hange R to no stuff as ernal pull high Pin : Low Pin : unconnected/floating GN GN GN GN 0 hex hex INTH# GT_SM GLK_SM INT SI SK S SO GN *OSH M0 N PROJET : QT Quanta omputer Inc. Size ocument Number Rev ustom MP_TP0/ccelerometer ate: Tuesday, February, 00 Sheet of

29 Modem ONN M.U/0V_ is 0_ R *0_ UM R V.V V E VPU_LE [] V_LE [] V_LE [] N 0.U/0V_.U/.V_ 000P/0V_ GN REV [] Z_SOUT_M _SO REV GN V [] Z_SYN_M R SIN_M _SYN GN [] Z_SIN _SI GN 0 [] Z_RST#_M _RST# _LK IT_LK_M [] *0P/0V_ M ONN *0P/0V_ PV uild H M00 H M00 Needs to change Library as ME request LE PWR ONTROL R 0_ Q *TEU *TEU Q 朝前 VLW *MEN00E PV uild 0~0mils (White) Vf -->.~. V V_LE 0_ R R0 00/F_ [] ST_LE# ST_R_LE LE R LE P WHITE/MER V *00K/F_ Q (mber) Vf -->.~ [] LEV_EN# R0 *M/F_LE_TL Q *MEN00E *.U/V_ *U/V_ 0 *.U/V_ 0U/.V_ 0.U/0V_ LE V [] LEV_EN# R0 *0K/F_ [] LE_EN Q TEU SI- hange P footpr as SMT request LELTW-SKF--P-QT Swap pin,pin and Pin as Library pin hange Q to O0 as LE current limited Modify LE,LE,LE layout footpr to ledl-s0kgct-p-qt (/) 朝前 LE P WHITE LE R _ PWR_R_LE [,] PWR_LE# R 0_ VPU_LE 朝前 LE P WHITE LE R0 _ Q 0~0mils MT_R_LE [] MTLE0# *O0 VPU_LE P WHITE LE V V_LE 朝前 LE R _ R_LE [,] R_LE# V SI-.U/0V_ *0U/.V_ [] PSLE# 朝上 LE P WHITE P_LE R _ V_LE LE_TL R 0_ Q *MEN00E PV uild dd R,R,R as HP LE spec change dd for reserve 0~0mils VPU VPU_LE [] TP_LE0# [] TP_LE# LE Vf 朝上 (mber) R /F_ TP_LE0# TPL R 00/F_ TP_LE# TPL (White) For P LE LE P WHITE/MER R I = Vcc -Vf / R V_LE V_LE Vcc LE_TL 0 0U/.V_.U/0V_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom M/LE ate: Tuesday, February, 00 Sheet of E

30 LUETOOTH VPU VSUS PV uild hange N P/N to FH0MR0 N LUE TOOTH ONN -000-P-L LEFT SIE USX and E-ST/US OMO 0 [] T_OFF# R.K_ PV uild Q TEU *.0U/V_ Q ME0T mil VSUS_T 0U/.V_.U/0V_ TON_P LUELE USP- USP VSUS_T FH0MR0 T LUELE [,] USP- [] USP [] SI- N and N -000-P-L hange footpr as ME request(pitch.mm to.0mm) VSUS U/.V_ U VIN VIN EN GN GPU OUT OUT OUT O 0 mils (Iout=) VSUS_USP0 0 0P/0V_.U/0V_ 00UF V 0P/0V_ US 0.U/0V_ *00UF V Touch Screen [] USP0- [] USP0 L *WM0-0 VSUS_USP0 USP0- USP0 N GN GN GN GN US ONN SI- N0,N US-00MR00SZR-P-R-H elete Touch-Screen in SI- N,0,L SI- uild hange onnector layout type from SM P to ip as SMT request [] USP- [] USP L *WM0-0 US & EST VSUS_USP0 USP- USP N0 US Vcc - GN [] IGITL_ [] IGITL_LK [] USP- [] USP US MER /IGITL MI ONNET SI- uild N hange Footpr to -000-P-L-QT SI- dd for EMI solution IGITL_LK_L PV uild 0P/0V_ U/.V_ V L PV uild L U0 VIN SHN K0HS0-T_ *WM0-0 GN SET TH-.KER SI- modified for fix camera power fail.v_m VOUT R *0_ R R USP- USP *.U/.V_ V SI- N MER-OR Fixed layout footpr 0b IGITL_LK_L FH0MR0 lose to N R *K/F_ R *00K/F_.V_M.0U/V_.U/.V_ US fingerpr ON V PV uild.u/0v_ hange Pin define 0 FWF0MS00 V_FINGER FINGER PRINTER ONN PV uild hange N to L-0R-P-L-QT-. ES GN. SYSTEM GN. US-. US. US PWR(V) N [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP lose to N PV uild hange N to L-0R-0P-L-QT-.U/0V_ RIGHT SIE USX [] USP [] USP- [] USP [] USP- [] USP [] USP- GN Shield - Shield GN - Shield 0 GN Shield US_EST_OMO US--000-P-H-QT VSUS 0 N UL US ONN PROJET : QT Quanta omputer Inc. Vout=.(R/R) N Size ocument Number Rev ustom T/W/FT/TS/EST/US ate: Tuesday, February, 00 Sheet 0 of

31 T : Stuffed for RTL(0/00/000) E : Stuffed for 0E/0E(0/00) R *0_ [] TRL SI- Stuffed for 0E TRL_E [] F R 0_ LN_._F Stuffed for RTL and nostuff 0E VLNV R 0_ TRL_E 0U/.V_ 0U/.V_ 0.U/0V_ LN_. R 0_ LN_._SRV For 0E/ LN_TX# LN_._SRV Stuffed for 0E/RTL VLNV R 0_ V_GV enable switch regular Stuffed for RTL(0/00/000) V LN LN_LE_00# R 0_ LN_GLINK00# XTL LN_GLINK0# SI- 0E U# wider than 0 mils U# wider than 0 mils LN_GLINK0# LN_GLINK00# LN_GLINK000# LN_TX# LN_._F Y MHZ P/0V_ No Mount No Mount,R mount SI-.U/0V_ New add and lose to Pin SI- R From Vendor EMI suggest = No Mount 0E = Mount SI- [,,] Swap PIE from Port to PIE Port [,,,,] [] [] PIE_TXP_LN PIE_TXN_LN [] LN_GLE# LN_YLE# PIE_WKE# LN_. LN_E. PLTRST# LN_REST# PV uild Remove and 0E support in PV uild. elete R (For ). elete R0 and T. elete R and U# for support. elete R as RSET. elete R,R,R,R,, 0E support 0 P/0V_ R0 0_ T *.U/0V_ R0V-0 *.U/0V_ *.0U/V_ R *.0U/V_.K/F_ Link *0_ XTL V_GV TRL_E PIE_WKE# LNRSET U 0 PIE_TXP_LN PIE_TXN_LN R 0_ R T T SROUT V MIP0 MIN0 F MIP MIN V MIP MIN V MIP MIN V N V *0_ LN_RESET# Stuffed for RTL0E 0 EP RSET VSR ENSR KTL KTL 0 V V LE_TX# LE_00# LE_0# LE_000# V V GPO GPI 0 V Pin RTL-V-GR N N LNWKE# PERST# V EV HSIP HSIN EGN REFLK_P REFLK_N EV HSOP HSON EGN V 0 0.0U/V_.0U/V_.0U/V_.0U/V_ MI0 MI- MI0- MI MI- MI MI- MI LN_. R *0_ V_ V_ V_ V_ 0 EESK EEI/UX V EEO EES V N N N 0 N V V ISOLTE# N N LKREQ U TT T TT T TT T TT T LK_PIE_LN# LK_PIE_LN EESK EEI EEO EES PIE_RXN_LN_L PIE_RXP_LN_L LN_GLINK000# LN_MT0 LN_MT LN_MT LN_MT LN_. V_LN V_LN L000 L00E00 MT MX MT MX MT MX MX- MX- MT MX RX- RX RX0- TX- TX RX0 TX0- TX0 T- T- MX- MX- T- T- NS0 0 V LN-GN.U/0V_ V_LN LN_LE_ETET [] ISOLTE LN_E. LK_PIE_LN# [] LK_PIE_LN [] LN-GN R *K/F_ R K/F_ LN_MX0 [] SI uild LN_MX0- [] R 0.0U/00V_00 LN_MX [] LN_MX- [] R LN_MX [] LN_MX- [] R LN_MX [] LN_MX- [] PIE_RXN_LN [] PIE_RXP_LN [] I TRL(P) RTL-V-GR(QFN) I TRL(P) RTL0E-V-GR(QFN) dd,,00,0 as HP request SI uild 0.0U/00V_00 SI uild U/00V_00 SI uild 0 0.0U/00V_00.U/0V_ Isolate pull low:.an only disable RTL..RTL0E can't disable PV uild hange back to R at / R *R0V-0 R 00/F_ /F_ /F_ /F_ /F_ LN_ISLE# [] V_LN V_LN for used. N if is used. if ISOLTE pin pull-low,the LN chip will not drive it's PI-E outputs ( excluding PIE_WKE# pin ) R SI- Swap PIE from Port to PIE Port 000P/KV_0 R R SI uild *0K/F_ FOR EMI *.U/0V_ V_LN EES EESK S V EEI SK EEO I ORG O GN *M-WMNTP.K/F_ R V_LN 0/F_ 0/F_ U PV uild R R LN_GLE LN_GLE# TRL V LN MI0 MI0- LN_._F MI MI- LN_. MI MI- LN_. MI MI- LN_. LN_. R V_LN LN_MX- LN_MX LN_MX- LN_MX- LN_MX LN_MX LN_MX0- LN_MX0 FOR EMI LN_YLE LN_YLE# SI uild *0_ *0_ *.U/0V_ LN-GN FTJFR0 RJ N LE_GRE_P 0 LE_GRE_N LE_YEL_P LE_YEL_N RJ_ONN GN V_LN GN *.U/0V_ NS0:GIGIT 0TLN0 PROJET : QT Quanta omputer Inc. NS0:0/00 0ZLN0 N Size ocument Number Rev ustom RTL/0E/RJ Tuesday, February, 00 ate: Sheet of

32 T : Stuffed for RTL(0/00/000) E : Stuffed for 0E/0E(0/00) LNV.W m PV uild V_LN Power trace Layout 寬度 > 0mil VLNV.U/.V_ 0.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ these P are for LN HIP LNV pins--,, and.placement close lan chip PV uild V LN V-0MN00 0E S0000J0 For Giga must change L to Inductor (hipset include switch power) TRL will become to switch power phase placement close to lan chipset 0.U/0V_.U/0V_ these P are for LN HIP LN_. pins-- and.placement close lan chip L for Gaga lan use.uh power choke >00m tolerance ±% Power trace Layout 寬度 > 0mil SI uild TRL L.UH_0 *.U/.V_ *0U/.V_ SI build 0 0U/.V_ SI build.u/.v_.u/.v_ L 0_.U/0V_ F [].U/0V_.U/0V_ LN_..U/0V_.U/0V_ these cap are for lan chip LN_. pins--,, and. placement close chip Power domain chart RTL(P) RTL0E LNV.V LN_..V For 0E SI- Remove R0,L,L -->For 0E STUFF 00 ohm E R0 0_ L 0_.U/0V_ LN_E. hange to u for 0E U/.V_ LN-GN these cap are for lan chip LN_. pins, such as and. placement close lan chip LN_. LN_..V.V Only For application Power trace Layout 寬度 > 0mil LN_. PV uild change to uf [] TRL L *0_ *.U/.V_ *.U/.V_ *.U/.V_ *.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ 00.U/0V_.U/0V_ For 0E these cap are for lan chip LN_. pins--,,,,,,,, and.placement close lan chip PROJET : QT Quanta omputer Inc. Size ocument Number Rev LN Power N ate: Tuesday, February, 00 Sheet of

33 E V PV uild 0U/.V_ V_O 0.U/0V_ ST -ROM NEWR 0 mils NEWR (PIEXPRESS* US*) 0.U/0V_.U/0V_.U/0V_ [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP V_O ST H ONNETOR FH0MR00 urrent rating: 0. SI uild R0 K/F_ FHMR00 N S GN TXP TXN GN RXN RXP GN S P P V 0 V M GN GN P ST O Fixed layout footpr 0b ST--0-P-R-H-QT VNEWR Fixed layout footpr 0/ N EXPR-0-00-P-L-QT US- GN_ US US- PUS# US PUS# RSV_0 RSV_ SMLK SMT.VNEWR.V_0 0 R0 *0_ WKE#.V_ WKE# VUX PERST#.VUX PERST#.V_.V_ PPE# LKREQ# PPE# REFLK- L *WM0-0 REFLK 0 PIE_RXN GN_ PIE_RXP PERn0 PERp0 PIE_TXN GN_ N PIE_TXP PETn0 N PETp0 L *WM0-0 GN_ [] USP- [] USP [,0,,,] GLK_SM [,0,,,] GT_SM [,,] PIE_WKE# [] LK_NEWR_OE# [] LK_PIE_NEW# [] LK_PIE_NEW [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP PI-Express TX and RX direct to connector Swap Port to PIE Port SI uild SI- SI- N N N N 0 hange N#, as ME request for Hole pad expcard-0-00-p-l-qt as ME modify Pad size(pin,) Move N#,0 Pin as ME request(molex confirm drawing) SI uild N ST H(ST) Main H V: ( Pin) V: ( Pin) Gnd : ( Pin) [,,,,] PLTRST# T NEW_O# 0. PLTRST# PPE# VS VUX PUS# PERST# 0 0 U STY#.VIN UXIN.VIN UXOUT SYSRST# PPE# PUS# PERST#.VOUT SHN#.VOUT RLKEN O#.VOUT GN.VOUT.VIN.VIN V.V VNEWR.VNEWR V_H V_H Modify 固定孔 Size as SMT request GS0-0-F-0P-L-QT SI- ST_TXP0 [] ST_TXN0 [] ST_RXN0 [] ST_RXP0 [] SI- VNEWR.VNEWR VS V TPSRGP add Pin ~ as U Thermal pad tied to Gnd.V VUX 0.U/0V_.U/0V_.U/0V_ U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_.U/0V_ V_H PV uild V V_H V_H For HP request to reserve PIE_RXN PIE_RXP V_H SI uild R *0_ V *0U/.V_ 0U/.V_.U/.V_.U/0V_ 0 *0U/.V_ *.U/0V_ PIE_TXN PIE_TXP SI- *.U/0V_ *.U/0V_ *.U/0V_ *.U/0V_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom O/H/NEW R ate: Tuesday, February, 00 Sheet of E

34 .VSUS.VSUS.VSUS [] MY[0..] MY[0..] [] MX[0..] MX[0..].U/0V_.U/0V_.U/0V_ VPU PV uild hange N to L-0R-P-L-QT- MY MY MY 0P/0V_ 0P/0V_ 0P/0V_ MY MY MY 0P/0V_ 0P/0V_ 0P/0V_ MX MX0 MX 0 0P/0V_ 0P/0V_ 0P/0V_.0V.0V.0V MY 0 0P/0V_ MY0 0 0P/0V_ MX 0 0P/0V_ lose to U For EMI NSWON# G *SHORT_ P NSWON# *.U/0V_ VPU VPU_LE [,] LI_E# [] NSWON# [,] PWR_LE# EMI 0.U/0V_ R *_ R _ PWLEV PWR_LE# POWER OTTON ONNET PWLEV LI_E# PWR_LE#.U/0V_ *.U/0V_ N PWR TN ONN FWF0MS0 0 *.U/0V_. VPU(LISWITH PWR). LEV(VPU). LISWITH.POWERON#. PWRLE#. GN POWRER SW ONNET P SW ONNET PV uild hange N to L-0R-P-L-QT- MY MY MY0 MY 0P/0V_ 0P/0V_ 0P/0V_ 0P/0V_ MX MX MX MX P/0V_ 0P/0V_ 0P/0V_ 0P/0V_ FOX FFFR00 SY N0 KEYOR PULL-UP MX MX MX MX MX MX MY RP MY MY MX 0 MX MY MY MX MX MY MY MY0 MY0 MY0 MY MX MX MY MX MX MY MY MY 0 MY VPU 0PR-.K MX0 MX0 MY RP MY MY MY 0 MY MY MY MY MY MY MY0 MY MY MY MY MY MY MY MY MY MY MY MY 0PR-.K MY MY 0 MY MY MY MY0 MY0 MY MY PV uild dd and close to N K ONN GRF0--XF-P-L hange N to L-0R-P-L-QT- hange N0 to GRF0--XF-P-L as Foxconn drawing MY MY MY MY 0P/0V_ 0P/0V_ 0P/0V_ 0P/0V_ 缺料號 N0 0 0 *K ONN bl--rl-p-l-qt VPU PV uild build V_LE PV uild 0 m FF0FR V_LE [] ES_LK [] ES_T PV uild L L 0.U/0V_ [,] MLK [,] MT [] I_INT [] NUMLE# V_LE_P.U/0V_ K0HS0 K0HS0 0P/0V_ P_ES_LK P_ES_T 0P/0V_ 缺料號 N P SW OR. VPU. MLK. MT. P_INT. GN. NUM LOK LE. V_LE. ES_LK. ES_T 0.U/0V_.U/0V_ V_LE_KLIGHT N L-0R-TN MLK MT I_INT NUMLE# 0 *.U/0V_ 0 *.U/0V_ 00 *.U/0V_ *.U/0V_ PROJET : QT Quanta omputer Inc. N Size ocument Number Rev ustom K/P/POWER ONN ate: Tuesday, February, 00 Sheet of