david_lewis_mb_r20_0420

Transcription

1 YTEM PE REF. PE lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R O-IMM_0 R O-IMM_ R _Q VOLTE VI controller 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y PWR PH_IEX()_P,LV,RT PH_IEX()_PI,NVRM,U PH_IEX()PU,PIO,MI PH_IEX()_POWER, PH_IEX()_POWER, PH_PI ROM,OTH LK_ILPR 0 E_IT(/) E_IT(/)K, TP RT_Reset ircuit HNKVILLE LN_RJ OE-L U_mp & Jack U_FM00 0 _R _R _in ardreader _Neward U_ebug RT_L Panel RT_-ub isplay Port TV_HMI 0 FN_Fan & ensor X_H & O U_U Port * MINIR(WLN) LE_Indicator _ischarge 0 _ & T onn. T_luetooth ontent TUN_TV Tuner ME_onn & kew Hole E_ET PH_XP, ONFI V_MXM V_LV witch PW_VORE(MX0) PW_YTEM(MX00) PW_I/O_VTT_PU&+.VM PW_I/O_R & VTT& +.V PW_I/O_VM & ME_+VM_PWE PW_+VFX_ORE(MX0) PW_HRER(MX0) PW_ETET PW_LO WITH PW_PROTET PW_INL PW_FLOWHRT avid Lewis schematic Rev. HMI RT Page Page L Panel INT. MI Page Touchpad Page Keyboard Line In LOK IRM Page mp. Page Page Page HMI RT nvii NP- LV ebug onn. E ITE IT Page 0 PI ROM Page zalia odec Realtek L0 Page 0 LV RT zalia odec Realtek L TP0 Page Page Page Page Page PIE x LP PI zalia zalia PWM Fan PU rrandale / larksfield FI x lock enerator ILR Page Page 0 MI x PH HM T Page ~ Page 0~ O PIE x U Page H() Page ischarge ircuit Page Reset ircuit Page R 00/0MHz H() Page ET Page Miniard WLN hirley Peak/ Echo Peak NE up000 igaln Miniard TV Tuner TP luetooth MO amera U Port() U Port() & TT. onn. Page 0 kew Holes Page R O-IMM R O-IMM R O-IMM Page Page Page Page Page Page Page Page UTeK OMPUTER IN. N Page ~ U.0 U.0 RJ Page Power VORE ystem.v &.0V R & VTT +.V harger etect avid Lewis Load witch Power Protect Page Page Page 0 Page Page Page Page Page Page 0 Page Page lock iagram aniel Huang.0 Wednesday, pril 0, 00 ate: heet of

2 PH_IEX PIO PH_IEX PIO Use s PIO 00 PI PIO 0 PIO [:] PI PI PIO 0 PIO 0 PIO 0 PI PI PI PIO 0 PIO 0 Native Native PIO PI PIO Native PIO PI PIO Native PIO PO PIO PI PIO PI PIO Native PIO PI PIO 0 Native PIO PI PIO PO PIO Native PIO PIO PO Native PIO Native PIO PO PIO PO PIO Native PIO 0 PO PIO Native PIO PIO PIO PI PIO PI PIO PO PIO PO PIO PO PIO PI PIO PI PIO 0 Native PIO Native PIO Native PIO Native PIO Native PIO Native PIO Native PIO PI PIO PI PIO PO Native Native Native PO Native Native Native PO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Native Native Native Native Native Native Native Native Native Native Native Native PIO Internal & ignal Name External Power Pull-up/down N_TP EXT PU +V N_TP EXT PU +V - EXT PU +V HP_INTR# EXT PU +V U_MI# EXT PU (Not used) +V EXT_MI# EXT PU & INT PU +VU U_O# EXT PU (Not used) +VU U_O# EXT PU (Not used) +VU EXT_I# EXT PU +VU N_TP - +VU N_TP INT P +VU U_O# EXT PU (Not used) +VU T_LE EXT P +VU PU_HOL_RT# EXT PU (Not used) +V PU_PWROK EXT P & INT T +V LKREQ_TV# EXT P +V TP EXT PU +V LKREQ#_WLN EXT P +V T0P EXT PU +V WLN_LE - +V N_TP INT PU +V N_TP - +VU LK_REQ# EXT PU (Not used) +VU LKREQ_U# EXT P +VU N_TP - +VU WLN_ON# - +VU - - +VU ME_usPwrnck EXT PU +VU ME PREENT EXT PU +VU PM_LKRUN# EXT PU +V H_OK_EN# - +V TP_PI# EXT PU +V T_LK_REQ# EXT P +V dpu_pwr_en#_pio EXT PU/P +V PU_PRNT# EXT P +V P_I0 EXT P +V P_I EXT P +V U_O# EXT PU (Not used) +VU U_O# EXT PU (Not used) +VU U_O# EXT PU (Not used) +VU U_O# EXT PU (Not used) +VU LK_REQ# EXT PU +VU N_TP EXT PU (Not used) +VU N_TP EXT PU (Not used) +VU LKREQ_PE# EXT P +VU N_TP EXT PU (Not used) +V PH_TEMP_LERT# EXT PU +V PI_REQ# EXT PU (Not used) +V PI_NT# INT PU +V dpu_elet# EXT PU/P +V PU_PWM_ELET#_R EXT PU/P +V PI_REQ# EXT PU +V PI_NT# INT PU +V LKREQ_LN# EXT P +VU T_ON EXT PU(IOE) +VU ML_LK EXT PU +VU U_O0# EXT PU (Not used) +VU ML0LERT# EXT PU +VU N_TP - +VU N_TP - +VU N_TP - +VU N_TP INT T +V N_TP INT T +V EI_ELET# INT T +V N_TP INT T +V PM_TLOW# EXT PU (Not used) +VU LK_REQ0# EXT PU (Not used) +VU MLLERT# EXT PU (Not used) +VU ML_T EXT PU +VU E IT E PIO Use s ignal Name P0 P P O O PWR_LE# H_LE# H_FULL_LE# P P P P P P0 P P P P P P P P0 P P P P O O O O IO IO O O O IO IO O I - L_L_PWM FN0_PWM K_LE_PWM - TEL_0 TEL_ - M0_LK M0_T 0TE RIN# PM_RMRT# - M_LK M_T PM_PWRTN# _IN_O# P O OP_# P P P0 I I I T_IN_O# RFON_W# PWRLIMIT# P P I I PM_U# UF_PLT_RT# P P P P P PE0 PE PE PE PE PE PE PE O O O I O O O O I I EXT_I# EXT_MI# L_KOFF# FN0_TH - VU_ON E (IT0 ddress/ata connect) E (IT0 ycle tart connect) ELK (IT0 lock connect) PWR_W# - LI_W# - PF0 O PH_PI_OV PF PF PF PF PF PF PF P0 P I I IO O I - EXP_TE# - TP_LK TP_T THRO_PU - - PM_U# P - P - PH0 PH PH IO O O PM_LKRUN# FX_VR_ON H_EN PH PH O O U_E# U_E# PH PH O O - P_LE# PI0 - PI PI PI PI PI PI PI PJ0 PJ PJ PJ PJ I I I I I I I O O O O O U_PWR LL_YTEM_PWR VRM_PWR FX_VR PU_VRON PM_PWROK VET_E IET_E - PJ O LV_PU_W PIE U 0 U Port () PIE Minicard WLN U PIE U U Port () PIE U U Port () PIE U PIE LN U PIE U PIE U ard Reader(.0) U WiFi/WiMax U amera T 0 T H () U 0 T T O U T U luetooth T U M_U RE : PH Master M-us evice M-us ddress lock enerator(ilr) 000x ( ) O-IMM x ( 0 ) O-IMM 0000x ( ) VI ontroller(m) 000x ( ) WiFi/WiMax N/ E Master (M) M-us evice M-us ddress PU Thermal ensor() 0000x ( ) evice Identification PU Thermal ensor P/N: component name st 0000 F lock en P/N: component name st ILR UTeK OMPUTER IN. N aniel Huang avid Lewis ystem etting Wednesday, pril 0, 00 ate: heet of.0

3 U00 MI_TXN0 MI_RX#[0] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXP0 MI_RX[0] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_TXP MI_RX[] MI_RXN0 MI_TX#[0] MI_RXN MI_TX#[] MI_RXN F MI_TX#[] MI_RXN H MI_TX#[] MI_RXP0 MI_TX[0] MI_RXP F MI_TX[] MI_RXP E MI_TX[] MI_RXP MI_TX[] FI_TXN[:0] FI_TXN0 E FI_TXN FI_TX#[0] FI_TXN FI_TX#[] FI_TXN FI_TX#[] FI_TXN FI_TX#[] FI_TXN FI_TX#[] E FI_TXN FI_TX#[] F FI_TXN FI_TX#[] FI_TX#[] FI_TXP[:0] FI_TXP0 FI_TXP FI_TX[0] FI_TXP FI_TX[] 0 FI_TXP FI_TX[] FI_TXP FI_TX[] FI_TXP FI_TX[] E0 FI_TXP FI_TX[] F0 FI_TXP FI_TX[] FI_TX[] FI_FYN0 F FI_FYN[0] FI_FYN E FI_FYN[] FI_INT FI_INT FI_LYN0 F FI_LYN[0] FI_LYN FI_LYN[] For Intel FX display MI Intel(R) FI PI EXPRE -- RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RI PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] K J J F F E 0 J H H F E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K 0 F E PE_IROMP_R EXP_RI PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN0 PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXN PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP R00 R00 X00 X00 X00 X00 X00 X00 X00 X00 X00 X00 X0 X0 X0 X0 X0 X0 X0 X0 X0 X00 X0 X0 X0 X0 X0 X0 X0 X0 X0 X00 X0 X0 % % 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V.Ohm PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIEN_RXN[:0] 0 R00,R0,R0 near U00 PIEN_RXP[:0] 0 +VTT_PU For E request, to read PEI via E. onnection: R0.-->Q00.-->U00. PIE_RXN[:0] 0 PIE_RXP[:0] 0 +VTT_PU +VTT_PU,,0,,,,,,,0, R00 don't remove, H_PEI H_PUPWR THRO_PU H_PROHOT_# H_THRMTRIP# OHM H_PURT# PM_YN# H_RM_PWR H_VTTPWR R00 H_PWR_XP UF_PLT_RT# % R00 % R00.Ohm % R00.Ohm % R00 R0 H_OMP H_OMP H_OMP H_OMP0 TP_KTO#.Ohm % R00 H_TERR# R00 R0 R00 R0 T00 H_PEI_IO H_PROHOT_#_R H_THRMTRIP#_R H_PURT# LK_PU_LK LK_PU_LK# LK_ITP_LK_R LK_ITP_LK#_R LK_EXP_P LK_EXP_N LKREF LKREF# M_ROMP0 M_ROMP M_ROMP PM_EXTT# XP_PREQ# XP_TLK XP_TM XP_TRT# PM_YN#_R L T XP_TI_R R0 PM_YN TI XP_TO_R TO R XP_TI_M VPWROO R TI_M R N XP_TO_M R00 VPWROO_ TO_M P N H_R#_R R0 VPWROO_0_R R# N R0 VPWROO_0 J XP_O0_R RX0 VPWROO_R PM#[0] K K XP_O_R RX0 R0 M_RMPWROK PM#[] K XP_O_R RX0 PM#[] J XP_O_R RX00 PM#[] M J XP_O_R RX0 VTTPWROO PM#[] H XP_O_R RX0 PM#[] K XP_O_R RX0 PM#[] M H XP_O_R RX0 TPPWROO PM#[] R.0 T00 OHM R0.KOhm % PLT_RT#_R R0 % KTO#:pulled to ground on processor. may use to determine if PU is present T T T H K T N K P L U00 OMP OMP OMP OMP0 KTO# TERR# PEI PROHOT# THERMTRIP# REET_O# RTIN# OKET MI THERML PWR MNEMENT LOK R MI JT & PM LK LK# LK_ITP LK_ITP# PE_LK PE_LK# PLL_REF_LK PLL_REF_LK# M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] PM_EXT_T#[0] PM_EXT_T#[] PRY# PREQ# TK TM TRT# R.,item L R0 T0 E F L M N N P LKREF LKREF# +VTT_PU T P N P T RN00 RN00 R0 R0 Place near R0,R0. R0 R0 R0 % % % 0KOHM 0KOHM L0 L KOhm KOhm LK selection 0.Ohm 0OHM M_RMRT#,, XP_PRY# XP_PREQ# XP_TLK XP_TM XP_TRT# XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O Main oard LK_ITP_LK LK_ITP_LK# LK_REF LK_REF# 0MHz from PH. PM_EXTT#0,, heck here XP_REET#, XP_O[:0] OKET 000 R.,item L +VTT_PU JT MPPIN LK_PU_P_PH R0 LK_PU_N_PH R0 LK_MI_PH R0 LK_MI#_PH R0 FI disable: (For discrete graphic). N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XENE,V_XENE. Pull-down to via KΩ ± % resistor: FI_FYN[0:],FI_LYN[0:],FI_INT,FX_IMON ~mw power saving.( R0. P.0) LK_PU_LK LK_PU_LK# LK_EXP_P LK_EXP_N H_PURT# XP_TM XP_TI_R XP_PREQ# XP_TO_R XP_TLK XP_TRT# R0 OHM R0 Ohm R0 Ohm R0 Ohm R0 Ohm R0 Ohm R00 Ohm H_PURT# KOhm R0 XP_TI_R XP_TO_M XP_TI_M XP_TO_R UF_PLT_RT# L00 00 R0 R0 R0 L00 00 XP_TI XP_TO RMPWROK: (U R.) VPWROO_R +.V R00.KOhm % R0.0KOHM %. onnected to : VX,. an be connected to directly: PLL_REF_LK,PLL_REF_LK#. onnect to +V.0 rail: VFIPLL U Item 0, H_PROHOT_# H_PROHOT_# FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_INT KOhm F R0 KOhm F R0 KOhm F R0 KOhm F R0 KOhm F R0 0, PWRLIMIT# 00 RV-0 R.,item L0. Q00 HN00 THRO_PU 0 UTeK OMPUTER IN. N aniel Huang avid Lewis PU()_MI,PE,FI,LK,MI.0 Thursday, pril, 00 ate: heet of

4 Main oard U00 U00 M Q[:0] M 0 M M M # M R# M WE# M Q0 0 M Q 0 M Q M Q M Q 0 M Q 0 M Q E0 M Q M Q M Q F0 M Q0 E M Q F M Q E M Q M Q E M Q M Q H0 M Q M Q K M Q J M Q0 M Q 0 M Q J M Q J0 M Q L M Q M M Q M M Q L M Q L M Q K M Q0 N M Q P M Q H M Q F M Q K M Q K M Q F M Q M Q J M Q J M Q0 J0 M Q J M Q L0 M Q K M Q K M Q L M Q K M Q L M Q N M Q M0 M Q0 R M Q L M Q M M Q N M Q T M Q P M Q M M Q N M Q M M Q T M Q0 T M Q L M Q R M Q P U E E _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] P Y Y P E E F H M M N0 N F J N H K P T F H M H K0 N R Y W V V T Y U T U T V M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_#0 M_# M_OT0 M_OT M M[:0] M Q#[:0] M Q[:0] M [:0], M Q[:0],,,,,, M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M 0 M M M # M R# M WE# E F F F F H J J J J J K L M K K M N F J K J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY - _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] W W M V V M E H K H L R T F J L H L R R E H M L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_# M_# M_OT M_OT M M[:0], M Q#[:0], M Q[:0], M [:0], OKET OKET UTeK OMPUTER IN. N aniel Huang avid Lewis PU()_R.0 Thursday, pril, 00 ate: heet of

5 Main oard U00H U00E U00I T0 E V V J T E RV V V J R E RV V V R E K V V V P R E0 K RV V V V L H R E K RV RV V V V L K R E K RV RV V V V L R0 E J RV V V V J L R E J0 RV RV V R T00 V V R E J RV RV V0 V0 V M R 0 J RV V V V L J R H 0mil trace RV RV V V V IMM0_VREF_Q J J R H 0mil trace RV RV V V V0 IMM_VREF_Q H R H RV0 V V V P0 H RV V V V P H RV V E P T00 V V P H RV RV0 T T00 V V V E0 P0 H RV RV V V V P H V V V T T00 P 0 H RV V0 V00 V R T00 P H RV V V0 V N H V V0 V N H V V0 V0 N H V V0 V L N0 T0 F0 RV V V0 V M0 L N 0 T0 F F[0] RV V V0 V M P0 M Y 0 T0 F F[] RV V V0 V P P M Y T0 F F[] RV V V0 V L L M Y T0 F F[] RV V V0 V L0 T M0 W T0 F F[] RV0 V0 V0 V M T M W F0 T0 F F[] RV V V V N P M W F T0 F F[] RV V V V M R M W F T0 F F[] RV V V V0 K T T00 M W F T00 F F[] RV K T T00 V V V M W0 F T0 F0 F[] RV V V V K P T00 M W F T0 F F[0] RV V V V J R T00 L W E T0 F F[] RV V V V N0 R L E T0 F F[] RV V V W V V N L W E T0 F F[] V V V V J L0 W E T0 F F[] V0 V0 V J E L V0 E T00 F F[] RV V V V J0 F L U E T0 F F[] RV0 V V V K0 L U E T0 F F[] RV V V V00 H L U E F[] RV V V V0 L T E RV J RV_R R00 V0 V V K T E RV H RV_R R00 V V V0 K T E T TP_MP_V_NTF T0 RV V V V0 V_NTF K T T TP_MP_V_NTF T0 V V V0 V_NTF K0 T 0 R RV V V V0 V_NTF K T0 RV V0 V0 V0 V_NTF J T R00 H_RV_R V V V0 V_NTF 0 J T TP_MP_V_NTF T0 R00 H_RV_R RV V V V0 V_NTF 0 J0 T TP_MP_V_NTF T0 RV V V V0 V_NTF J T RV V V V U J T RV RV V V V T R J R0 RV0 RV V V V J P RV V V V J P RV RV0 V V V J P RV RV V V V H N 0 RV V0 V0 V R H N RV V V V H N T0 RV V V V E H N T00 RV RV V V V0 H N RV V V V H0 N0 V _K[] V V V RV M_LK_R H N V _K#[] V V V RV M_LK_R# H N N _KE[] V V V RV M_KE H N J _#[] V V V RV RV M_# H N J _OT[] V V V RV RV0 M_OT H0 N W _K[] V0 V0 V RV M_LK_R H M0 T0 W _K#[] V V V RV RV M_LK_R# H L T0 N _KE[] V V V RV RV M_KE H L E _#[] V V V0 RV M_# H L T0 _OT[] V V V RV0 RV M_OT H L T0 V V V 0 L RV V V V F L V V P F K RV V V F K V V E K0 V0 V0 REERVE NTF OKET OKET OKET F strapping information: F[:0]: PI Express Port ifurcation:(larksfield Only) - = x PE (efault) - 0 = x PE F[]: PIE tatic Numbering Lane Reversal.(uburndale Only) - :Normal Operation (efault) - 0:Lane Numbers Reversed -> 0, ->,... F[]: Embedded isplayport etection.(uburndale Only) - :isabled - No Physical isplay Port attached to Embedded isplayport - 0:Enabled - n external isplay Port device is connected to the Embedded isplay Port F[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples pre-e) - onnect to with.0k Ohm/% resistor For a common motherboard design (for U and F), the pull-down resistor should be used. oes not impact U functionality. Unmount if Intel has fixed this issue. F0 F F R0 R0 R0 % % %.0KOHM.0KOHM.0KOHM F R0.0KOHM % Note: (uburndale)hardware traps are sampled on the asserting edge of VPWROO_0 and VPWROO_ and latched inside the processor. Note: (larksfield)hardware traps are sampled after RTIN# de-assertion. R.,item UTeK OMPUTER IN. N aniel Huang avid Lewis PU()_F,RV, Thursday, pril, 00 ate: heet of.

6 +VFX_ORE U00 Main oard +VORE U00F V V V V V 0 V V V V V0 F V F V F V F V F V F0 V F V F V F V F V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V00 PU ORE UPPLY POWER ENE LINE PU VI.V RIL POWER VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT PI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRLPVR VTT_ELET IENE V_ENE V_ENE VTT_ENE V_ENE_VTT H H H H0 J J H H F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M +VTT_PU VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI PM_PRLPVR_R VENE_R VENE_R VTT_ENE TP_V_ENE_VTT H_VTTVI VTT_TET T N J J R0 0UF/.V 00 0UF/.V 0 I_MON 0 +VTT_PU UF/.V 0 0UF/.V 00 0UF/.V 0 R00 0UF/.V 00 0UF/.V 0 UF/.V 0UF/.V 00 0UF/.V 00 VR_VI[0:] 0 T0 T0 0UF/.V 0 +VORE 0UF/.V 0 +VTT_PU 0UF/.V PM_PI# 0 R00 0 % R00 0 % 0UF/.V PM_PRLPVR 0 VENE 0 VENE 0 +VTT_PU V._VTT (rrandale) V.0_VTT (larksfield) P UF 00 P 0UF 00 NIEL 00 R00 R0 r00_h r00_h NIEL 00 0UF/V E0 PNONI/EEFX0XE ER=mOhm/Ir= + +VTT_PU + F 0UF/V E0 PNONI/EEFX0XE ER=mOhm/Ir= +VTT_PU +VTT_PU R00 0UF/V E0 PNONI/EEFX0XE ER=mOhm/Ir= + UF/.V 00 UF/.V 0 R R UF/.V 0 UF/.V 0 R R NIEL 00 0UF/.V 0 c00 VX P UF 00 P 0UF 00 UF/.V 0 NIEL 00 UF/.V 0 UF/.V 0 UF/.V 0 Processor ecoupling +VORE 0UF/.V 0 c00 R UF/.V 0 UF/.V 0 R T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H F E E ecoupling guide from Intel chematic R0.: VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT OKET VORE uf * pcs 0uF * pcs FI PE & MI 0uF* pcs( no stuff). 0 RPHI UF/.V POWER chematic hecklist R0.: VORE uf * pcs 0 ENE LINE RPHI VIs UF/.V R -.V RIL.V.V VX_ENE VX_ENE 0uF * pcs 0uF* pcs( no stuff). 0 UF/.V FX_VI[0] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VR_EN FX_PRLPVR FX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VPLL VPLL VPLL R T M P N P M P N R T M J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI FX_VRON_EN FXVR_PRLPVR_R V_X_ENE V_X_ENE VR_PWR_MON VR_VI[0:] R00: R does not have.k pull-down. VR_PWR_MON UF/0V 0 0 UF/0V 0 R00 R0 R00 0UF/.V UF/.V 0 R0 UF/0V 0 UF/0V 0 UF/0V 0.UF/0V 0 F R UF/.V 0 UF/0V 0 0.UF/.V 0 UF/0V 0 0UF/.V UF/.V 0 UF/.V 0 R0.KOhm UF/.V 0 F FX_VR_ON 0, FX_VR 0 R00 0KOhm 0UF/V E00 PNONI/EEFX0XE ER=mOhm/Ir= + KOhm +VTT_PU +VTT_PU +.V FXVR_PRLPVR R00:Itel hecklist recommendation VPLL P.UF 00 P.0UF 00 P UF 00 P.UF 00 +.V NIEL UF/.V UF/.V UF/.V OKET / delete 0 (UF,.V) for layout placement. (+.V,VPLL) UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V UTeK OMPUTER IN. N aniel Huang avid Lewis PU()_PWR.0 Thursday, pril, 00 ate: heet of

7 Main oard PU XP connector +VTT_PU R.,item L J00 IE 0 0 IE 0 FP_ON_0P T00 T0 R00 PUPWR_XP KOhm R00 HPM# T0 HPM# T0 HPM# T0 HPM0# T0 Ohm R0 XP_RT#_R KOhm R00 H_PWR_XP XP_TRT# H_PUPWR, XP_PREQ# XP_PRY# XP_TO XP_TI XP_TM XP_TLK XP_REET#, H_PURT# M_T_,,,,, M_LK_,,,,, LK_ITP_LK# LK_ITP_LK () () () ( ) ( ) () () () () () () () (0) () +VTT_PU XP_RT#_R R0 UF_PLT_RT#,,0,,,,,,,0 T0 T0 T0 T0 T0 T0 T0 T0 T00 XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O PM_PWRTN#_R J00 FF path Put these test point near J00. Put it away from the FF path. UTeK OMPUTER IN. N PU()_XP James_Wu M0J Thursday, pril, 00 ate: heet of.0

8 UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet of.0

9 Main oard UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet of.0

10 Main oard UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet 0 of.0

11 Main oard UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet of.0

12 Main oard UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet of.0

13 Main oard UTeK OMPUTER IN. N N_**** aniel Huang ustom avid Lewis ate: Wednesday, pril 0, 00 heet of.0

14 M Q M M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q# M Q M M M Q M Q M Q M Q0 M Q M Q M Q M Q# M Q M Q M Q M Q M M M Q M Q M M M Q M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q M Q# M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M WE#, M_# M_LK_R M_KE M_LK_R# M_LK_R M_KE M #, M R#, M_LK_R# M_# M_OT M_OT M_T_,,,,, M_LK_,,,,, M M[:0], M Q#[:0], M Q[:0], M, M 0, M, M_RMRT#,, M [:0], M Q[:0], PM_EXTT#0,, +0.V +0.V +.V M_VREF_IMM M_VREFQ_IMM +.V +V +V ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_.0 N Tommy_hiang ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_.0 N Tommy_hiang ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_.0 N Tommy_hiang NIEL 0 Layout Note: Place these caps near O IMM R. NIEL 0 WP Mus lave ddress: H Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM NIEL 0 R. R0 0KOhm R0 0KOhm 0UF/.V 0UF/.V UF/.V UF/.V + E0 0UF/.V + E0 0UF/.V 0 0.UF/V 0 0.UF/V R0 R0 UF/.V UF/.V 0 0.UF/V 0 0.UF/V 0.UF/0V 0.UF/0V EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P R J0 R_IMM_0P R 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V 0 0.UF/V 0 0.UF/V 0 0/P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q J0 R_IMM_0P R J0 R_IMM_0P R UF/.V UF/.V 0.UF/0V 0.UF/0V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V UF/.V UF/.V R0 0KOhm R0 0KOhm 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V

15 M M M M M M M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M # M_LK_R#0 M M 0 M M M[:0] M Q#[:0] M Q[:0] M_T_,,,,, M_LK_,,,,, M WE# PM_EXTT#0,, M_# M R# M_#0 M_OT0 M_OT M_RMRT#,, +V +.V +0.V M_VREF_IMM0 M_VREFQ_IMM0 +0.V +.V +.V ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_0. avid Lewis aniel Huang ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_0. avid Lewis aniel Huang ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_0. avid Lewis aniel Huang Mus lave ddress: 0H Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near O IMM 0 R. R UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V UF/0V UF/0V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V + E0 0UF/.V + E0 0UF/.V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0.UF/0V 0.UF/0V R0 R0 UF/0V UF/0V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V R0 0KOhm R0 0KOhm R0 0KOhm R0 0KOhm 0UF/.V 0UF/.V UF/0V UF/0V 0 0/P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P 0 0.UF/V 0 0.UF/V UF/0V UF/0V

16 M M M M M M M M M M M M0 M Q# M Q M Q M Q M Q M Q# M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q0 M Q M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M M M M M Q M Q M Q# M Q# M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M WE#, M_# M_LK_R M_KE M_LK_R# M_LK_R M_KE M #, M R#, M_LK_R# M_# M_OT M_OT M_T_,,,,, M_LK_,,,,, M M[:0], M Q#[:0], M Q[:0], M, M 0, M, M_RMRT#,, M [:0], M Q[:0], PM_EXTT#0,, +0.V +0.V +.V +.V M_VREF_IMM M_VREFQ_IMM +.V +V +V ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_. M0JV H_Lin ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_. M0JV H_Lin ate: heet of Thursday, pril, 00 UTeK OMPUTER IN. N R O-IMM_. M0JV H_Lin Mus lave ddress: H Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM R. R. WP UF/0V UF/0V 0 0.UF/V 0 0.UF/V 0.UF/0V 0.UF/0V 0 0UF/.V 0 0UF/.V UF/0V UF/0V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V UF/0V UF/0V 0UF/.V 0UF/.V R0 0KOhm R0 0KOhm 0 0.UF/V 0 0.UF/V + E0 0UF/.V + E0 0UF/.V 0 0UF/.V 0 0UF/.V 0.UF/V 0.UF/V R0 0KOhm R0 0KOhm 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V 0 0/P 0 /# # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P UF/0V UF/0V R0 R0 EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P 0 0.UF/V 0 0.UF/V 0.UF/0V 0.UF/0V

17 UTeK OMPUTER IN. N aniel Huang avid Lewis R TERMINTION.0 Wednesday, pril 0, 00 ate: heet of

18 For R_VREF command & address. alpella larksfield R O-IMM VREFQ Platform esign uide hange etails R Vref Intel ocument Number: 00 +.V M_VREF_R efault M R0 KOHM M_VREF_IMM0 R0 R0 Near J0<000 mil R0 0.UF/0V KOHM R R0 M_VREF_IMM M_VREF_IMM +.V R R KOHM R0 M_VREFQ_IMM0 M_VREFQ_IMM M_VREFQ_IMM Near J0<000 mil 0 R 0.UF/0V KOHM R0 R0 R IMM0_VREF_Q R0 IMM_VREF_Q R0 F IMM_VREF_Q R F Near J0<000 mil +.V R KOHM R0 M F M: Processor enerated O-IMM VREFQ New Requirement Option: Mount=R0,R0,R0,R0 Unmount=R0,R0,R0,M block 0 R 0.UF/0V KOHM R +V +.V 0 0.UF/0V c00 R 0KOhm r00_h R 0KOhm r00_h + - U0 V+ V- LMVIVR 0 0.UF/0V c00 UTeK OMPUTER IN. N aniel Huang avid Lewis R _Q VOLTE.0 Thursday, pril, 00 ate: heet of

19 UTeK OMPUTER IN. N aniel Huang ustom avid Lewis VI ontroller.0 ate: Wednesday, pril 0, 00 heet of

20 RT battery V +V_RT JP00 +RTT 00 MM_OPEN_MIL +RT_T R00 KOhm T +V_RT 00 UF/0V TT_HOLER_P T +V_RT RTRT# R delay should be ms~ms Request by for MO clear function TX PF R00 0KOhm % 00 UF/0V JRT00 L_JUMP MO ettings lear MO Keep MO JRT00 hunt Open (efault) 00 c00 ITIZEN PF PF/0V X00.Khz ITIZEN R00 0MOhm U00 R00 MOhm R00 0KOhm % Z_LK_U Z_YN_U, Z_RT#_U Z_OUT_U Z_IN0_U H_OK_EN# TPM ettings 00 UF/0V lear ME RT Registers Keep ME RT Registers JRT00 hunt JRT00 L_JUMP Open (efault) RX0 RX0 RX0 RX0 R.,item KOhm R0 0 esign uide R. Update: page PIO: This signal should be only asserted low through an external pull-down in manufacturing or debug environments ONLY. Without connecting PIO, customers may not be able to override PI flash contents. Ohm Ohm Ohm Ohm H_YN: elect VVRM.V or.v Z_LK Z_YN Z_RT# Z_OUT Z_IN R.,item L 0 T00 PH_PI_OV R.,item L Q00 HN00 +VU_OR +V,0,0 MoW0 IbexPeak JT requirements: 00 c00 +V PI_LK PI_#0 PI_I XRT R00: For Xtal measurement R00 0KOhm PF/0V R00 KOhm R0 +V_RT R.,item L0 H_OK_EN# H_OK_RT# houd we connect to E? R0 T00 R00 R00 T00 T00 T00 T0 Ohm PI_O X_RT X_RT RTRT# RTRT# M_INTRUER# 0KOhm Z_OUT Z_LK Z_YN Z_RT# Z_IN Z_IN_M Internal PU 0K H PH_JT_TK PH_JT_TM PH_JT_TI PH_JT_TO PH_JT_RT# _PI0# _PI# 0 P 0 0 F0 E F J0 M K K J J V Y Y V RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/PIO H_OK_RT#/PIO JT_TK JT_TM JT_TI JT_TO JT_RT# PI_LK PI_0# PI_# PI_MOI PI_MIO IEXPEK-M RT IH PI JT LP T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPO TIOMPI TLE# T0P/PIO TP/PIO F K K K K H H H H F F F F H H F F F F T Y V PH_RQ#0 LP_RQ# Primary master of T controller T_TXN0_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T_TXP0_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V econdary master of T controller T_TXN_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T_TXP_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T,: E.0: T port,port may not be available in all PH KUs. Primary master of T controller T_TXN_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T_TXP_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T_TXN_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V T_TXP_H ML 0.0UF/V (00) XR 0% X00 0.0UF/V.Ohm T_OMP % R00 +V 0KOhm R0 T_LE# T0P PH XP TP PH XP LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, T00 T00 INT_ERIRQ 0 T_RXN0 T_RXP0 T_TXN0 T_TXP0 NIEL 0 T_RXN T_RXP T_TXN T_TXP T_RXN T_RXP T_TXN NIEL 0 T_TXP T_RXN T_RXP T_TXN T_TXP ore power plane +VTT_PH_VIO trap information: H_PKR: No reboot strap Low: isable. High:Enable H_OK_EN#:.Flash descriptor security: ampled low: override ampled high: in effect..pio low on the rising edge of PWROK, Will also disable Intel ME. VTP ssumed as.v +VU_OR hange resister divider to 0/0K? ignal Name Power Well river uring Reset R0 R00 % JT_TI uspend Internal Pull-up PH_JT_TO % 0 0 JT_TM uspend Internal Pull-up R0 R0 % INT_ERIRQ 0KOhm PH_JT_TM R0 JT_TK uspend Internal Pull-down % 0 0 R0 R0 % T0P TRT# uspend Internal Pull-up 0KOhm PH_JT_TI R0 % 0 0 JT_TO uspend R0 TP 0KOhm PH_JT_RT# R0 R0 PH_JT_TK R0 0KOhm.KOhm 0KOhm +V PH XP? % PI_MOI: itpm strap. Mount R0: Enable Unmount R0: isable(default) NIEL 0 UTeK OMPUTER IN. N aniel Huang avid Lewis PH_IEX()T,IH,RT,LP. Thursday, pril, 00 ate: heet of 0

21 U00 R.,item L PIE: WLN PIE: U0 PIE_RXN_TV PIE_RXP_TV PIE_TXN_ PIE_TXP_ PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_ PIE_TXP_ PIE_RXN_U0 PIE_RXP_U0 PIE_TXN_ PIE_TXP_ 0.UF/V X0 0.UF/V X0 0.UF/V X0 0.UF/V X0 0.UF/V X0 0.UF/V X0 PIE_TXN_TV PIE_TXP_TV PIE_TXN_WLN PIE_TXP_WLN PIE_TXN_U0 PIE_TXP_U0 0 J0 F H W U0 T0 U V E PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP Mus MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PIO MLLK/PIO MLT/PIO H J M E0 ML0LERT# ML0_LK ML0_T MLLERT# ML_LK ML_T T0 T0 T0 T0 EXT_I# 0 L ML_LK ML_T R.,item L To E heck here R.,item EXT_I# ML0LERT# L ML0_LK ML0_T ML_LK 0KOhm R0 0KOhm R.KOhm R.KOhm R.KOhm R.KOhm R.KOhm R +VU_OR PIE: LN F H J PIE_RXN_LN PIE_RXP_LN W PIE_TXN_ 0.UF/V X PIE_TXN_LN PIE_TXP_ 0.UF/V X PIE_TXP_LN T U U V Port & may not be available in all Ibex Peak KUs J J K K LK_REQ0# P Ohm LK_PH_R_N LK_PIE_TV#_PH RX0 M LK_PIE_TV_PH Ohm RX0 LK_PH_R_P M LKREQ_TV# R0 LKREQ_TV_N U LK_PH_R_N LK_PIE_WLN#_PH RX0 M LK_PIE_WLN_PH RX0 LK_PH_R_P M LKREQ_WLN_N LKREQ_WLN# R N PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PI-E* PIELKRQ0#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO0 From LK UFFER ontroller PE Link L_LK L_T L_RT# PE LKRQ#/PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_T_N/K_N LKIN_T_P/K_P T T T H N N T T W P P F E H H LK_PIE_PE#_PH_L LK_PIE_PE_PH_L RX RX0 LK_REF#_L RX LK_REF_L R.,item L RX L_LK L_T L_RT# LKREQ_PE# 0 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 LK_MI#_PH LK_MI_PH LK_REF# LK_REF LK_MI# LK_MI LK_PH_LK# LK_PH_LK LK_OT# LK_OT LK_T# LK_T ILR output with integrated ohm sereis resistor R F 0 ML_T MLLERT# R.,page :.KOhm R 0KOhm R The pull-up resistor value for ML0T and ML0LK has been updated from. K ±% to. K ±% to support 00-kHz bus speed LK_PIE_U0N_PH LK_PIE_U0P_PH LKREQ_U0# LK_PIE_LN_N_PH LK_PIE_LN_P_PH LKREQ_LN# RX0 RX0 R RX RX R H H LK_REQ# LK_PH_U0_N M LK_PH_U0_P M LKREQ_U0#_H M J0 J LK_REQ# H LK_PH_PE_N K LK_PH_PE_P K LKREQ_LN#_H P LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PE N LKOUT_PE P PE LKRQ#/PIO lock Flex REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO P J H X_IN H X_OUT F XLK_OMP T LK_OUT0 P LK_OUT T LK_OUT N0 LK_OUT R 0.Ohm % T T T T +VTT_PH_VIO heck IO NIEL 0 LK_IH LK_PI_F NIEL 0 R R R0 R XOUT R0: For Xtal measurement PF/0V X0 Mhz R 0 PF/0V ignal Name PIELKRQ0# Power Well uspend PIELKRQ# ore PIELKRQ# ore PIELKRQ[:]# uspend PH LKREQ etting: river uring Reset Value External Pull-up 0K External Pull-up 0K External Pull-up 0K External Pull-up 0K Not connected to device. +VU_OR LK_REQ0# R 0KOhm LK_REQ# R0 0KOhm LK_REQ# R 0KOhm Note: Place these resisters near to PIe lots IEXPEK-M onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +V LKREQ_WLN_N LKREQ_TV_N R 0KOhm R 0KOhm +V +VU_OR R.,item, PU_PWROK R R R KOhm R Q0 N00 LKREQ_PE# LKREQ_U0#_H LKREQ_LN#_H LK_REQ#_ LKREQ_TV_N LK_REQ#_ LKREQ_WLN_N LKREQ_LN#_H LKREQ_PE# LKREQ_U0#_H R 0KOhm R 0KOhm R 0KOhm R0 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm UTeK OMPUTER IN. N aniel Huang avid Lewis PH_IEX()_PIE,LK,M,PE. Wednesday, pril, 00 ate: heet of

22 pre-e not support Reversal Feature UXPWROK_R R 0KOhm R.,page For platforms that do not support Intel LN, LN_RT# should be pulled down to ground via a. kω to 0 kω pull-down resistor. heck pull-up power plane PM_RI# PM_TLOW# PIE_WKE# ME_usPwrnck PM_LKRUN# R 0KOhm R.KOhm R KOhm R0 0KOhm R.,item L +VU_OR R.KOhm +V, E.0: Intel LN XP_REET# +V +VTT_PH_OR 0, Test use only Enabled : LN_RT# connected to the same source as MEPWROK isabled : LN_RT# must be grounded isabled : LP_LN#-->N. P. isabled : VLN connected to. KOhm R 0 R0.Ohm %.,page0: R.,item L 0 R.,item L MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP H_RM_PWR MI_OMP R.,item L +V LL_YTEM_PWR 0,,0 VRM_PWR ME_usPwrnck PM_PWRTN#_R 0 PM_PWRTN# PM_PWROK_PH No Intel MT support R 0KOhm R PM_RMRT#_PH ME PREENT_PH +VU_OR Y_REET# R R R.,item L R R R 0KOhm R R R MPWROK_R UXPWROK_R PM_RMRT#_R U00 J W0 J0 0 0 E F 0 E H 0 H F T M K 0 M P P MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP Y_REET# Y_PWROK PWROK MEPWROK LN_RT# RMPWROK RMRT# U_PWR_K/PIO0 PWRTN# PREENT/PIO MI ystem Power Management FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN WKE# LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# LP_M# TP H J E F W J F H J J Y P PM_U_TT# F U_LK E LP_# H LP_#_R P LP_#_R K LP_M#_R N PM_LP_W# R0 R T0 T0 T0 T0 FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FYN0 FI_FYN FI_LYN0 FI_LYN PIE_WKE#,, PM_LKRUN# 0 PM_U# 0 PM_U# 0 R.,item L T0 T0 PM_TLOW# TLOW#/PIO PMYNH J0 PM_YN# T0 PM_RI# F RI# LP_LN# F ME_PM_LP_LN#_PH T0 R.,item L IEXPEK-M R.,item L 0'MoW0: Optional if ME FW is Ignition FW 0KOhm R +VU_OR 0KOhm R 0KOhm R Power failure solution (0-->,-->): PM_PWROK,PM_RMRT#: previous platform solution. ME_PWROK,ME PREENT: reserved for test. PM_PWROK_PH R 0 0KOhm PM_PWROK 0 PM_RMRT#_PH R0 0 0KOhm PM_RMRT# 0 ME PREENT_PH R 0 0KOhm ME PREENT 0 0 T 0 0: Prevent E drive hign, U_PWR sink low in -->. U_PWR 0,, 0KOhm R T UTeK OMPUTER IN. N aniel Huang avid Lewis PH_IEX()_FI,MI,Y PWR. Thursday, pril, 00 ate: heet of

23 +V L_TRL_LK R 0KOhm L_TRL_T R 0KOhm EI_LK_PH R.KOhm EI_T_PH R.KOhm witchable FX, set EI_T_PH to high. set F[] no connect (isable) LV isable: (For discrete graphic). N: LV_T [:0], LV_T# [:0], LV_LK, LV_LK#, LV_T [:0], LV_T# [:0], LV_LK, LV_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to : VccLV,VccTX_LV 0 ohm RT PH RT PH RT_R_PH RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE JP0HORT_PIN JP0HORT_PIN JP0HORT_PIN U Item R R R R R % % % R L_KEN_PH L_VEN_PH L_KLTTL_PH EI_LK_PH EI_T_PH T0 L_TRL_LK T0 L_TRL_T.KOHM R R0 % R0 R0 R LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH LV_ULKN_PH LV_ULKP_PH LV_U0N_PH LV_UN_PH LV_UN_PH LV_U0P_PH LV_UP_PH LV_UP_PH. ohm RT PH_H RT PH_H RT_R_PH_H _LK_PH _T_PH RT_HYN_PH RT_VYN_PH U00 T L_KLTEN T L_V_EN Y L_KLTTL L LK Y L T L_TRL_LK V L_TRL_T P LV_I P LV_V T LV_VREFH T LV_VREFL V LV_LK# V LV_LK Y V 0 Y V P P Y T U T Y T U0 T V V Y Y LV LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T RT_LUE RT_REEN RT_RE RT LK RT T RT_HYN RT_VYN R 0.% KOHM _IREF RT_IRTN IEXPEK-M R R0., R0.: K+/-0.% Intel checklist recommand:.0k P resistor to 0.% RT igital isplay Interface VO_TVLKINN J VO_TVLKINP VO_TLLN J VO_TLLP VO_INTN F VO_INTP H VO_TRLLK T VO_TRLT T P_UXN P_UXP J P_HP U P_0N P_0P P_N J P_P P_N 0 P_P 0 P_N W P_P P_TRLLK Y P_TRLT P_UXN E P_UXP P_HP V0 P_0N E0 P_0P 0 P_N F P_P H P_N P_P P_N P_P P_TRLLK U0 P_TRLT U P_UXN P_UXP P_HP T P_0N J0 P_0P 0 P_N J P_P P_N F P_P H P_N E P_P P_HP: Vil max=0.v, Vih min=v R. TM_TRLLK TM_TRLT TM_HP HMI_TXN_PH HMI_TXP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN0_PH HMI_TXP0_PH HMI_LKN_PH HMI_LKP_PH NIEL isplay Port isplay Port isplay Port VO RT_HYN,RT_VYN. -kω ±0.% pull-down to : _IREF. onnected to : RT_ITRN. onnect to +V.: V PH_IEX()_P,LV, aniel Huang UTeK OMPUTER IN. N avid Lewis. Thursday, pril, 00 ate: heet of

24 change to PI_LK to sync I 0 LK_PI_F LK_KPI_PH LK_EU EMI 0 0.UF/V PI_REQ# PU_PWM_ELET#_R LOE TO U00 T0 R.,item L PI_PME#: Internal PU to suspend plane. Ohm Ohm Ohm T0 T0 T0 T RX0 RX0 RX0 PI_INT# PI_INT# PI_INT# PI_INT# PI_REQ0# PI_REQ# PI_REQ# PI_NT0# PI_NT# PU_PWM_ELET#_R PI_NT# PI_RT# PI_INTE# PI_INTF# PI_INT# PI_INTH# PI_ERR# PI_PERR# PI_IRY# PI_PR PI_EVEL# PI_FRME# PI_LOK# PI_TOP# PI_TRY# PI_PME# PLT_RT# LK_PI_R LK_PI_F_R LK_KPI_PH_R LK_EU_R H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 F M H J0 H H F M F K F H K K E E0 H F M N P P P P U00E /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ0# REQ#/PIO0 REQ#/PIO REQ#/PIO NT0# NT#/PIO NT#/PIO NT#/PIO PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PIRT# ERR# PERR# IRY# PR EVEL# FRME# PLOK# TOP# TRY# PME# PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI PI NVRM U NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP0N UP0P UPN UPP UPN UPP UPN UPP URI# URI O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO Y P V P P T T V E J J Y U V Y Y V F HEK U INMENT Place within 00 mils of PH H U_PN0 avid Lewis Recommand settings J U_PP0 U_PN 0 U port (U.0) N0 U_PP U_PN U port (U.0) P0 J0 U_PP U_PN et L0 F0 U_PP U_PN U port 0 0 U_PP U_PN TV Tuner 0 M U_PP ELN TEK U N Port, not avalibale in HM H U_PN J E U_PP U_PN WiFi/WiMax LM(.0) or UW(./.0) F U_PP amera U_PN 0 H L U_PP U_PN ard Reader(.0) U port (th) or ocking M U_PP T (.) URI_PN R +VU_OR.Ohm % Place within 00 mils of IH N 0KOHM RN0 J 0KOHM RN0 F 0KOHM RN0 L 0KOHM RN0 E 0KOHM RN0 0KOHM RN0 F 0KOHM RN0 T 0KOHM RN0 R.,item L PI_INT# PI_INT# PI_INTE# PI_TOP# PI_INT# PI_ERR# PI_EVEL# PI_LOK# PI_INT# PI_IRY# PI_REQ# PI_REQ0# PI_INT# PI_INTF# PI_REQ# PI_TRY# PI_INTH# PI_PERR# PI_FRME# RP0 RP0 RP0 RP0 RP0 RP0F RP0 RP0H RP0E RP0H RP0 RP0 RP0 RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0F RP0 RP0H RP0E +V 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 IEXPEK-M NT0#,NT#: oot IO trap. oot IO trap R.,item L 0PF/0V 0 R.,item L PI_NT# PI_NT0# oot IO Location 0 0 LP 0 PI 0 Reserved PI (PH) NT#: swap override trap/ Top-lock swap override jumper +V ampled on rising edge of PWROK. PI_NT0# PI_NT# R 0KOhm +V R 0KOhm Low=Enabled swap override/ Top-lock swap override High=efault PI_NT# R KOhm PLT_RT# U0 V Y NZ0PX_NL R UF_PLT_RT#,,0,,,,,,,0 R0 KOhm R KOhm This signal has a weak pull-up This signal has a weak pull-up The internal pull-up is disabled after PIRT# deasserted NIEL 0 UTeK OMPUTER IN. N aniel Huang avid Lewis Thursday, pril, 00 ate: heet of PH_IEX()_PI,NVRM,U.

25 +V +V +V R0 0KOhm T T0 PIO0 PIO Y U00F MUY#/PIO0 TH/PIO LKOUT_PIEN LKOUT_PIEP H H R 0KOhm R 0KOhm P_I0 U_MI# U_MI# T00 T PIO : efault internal P 0K. 0 R.,item L EXT_MI# dpu_hol_rt# T T PU_HP_INTR#_R U_MI# PM_LNPHY_EN J F0 K T TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO PIO TP/PIO MI LKOUT_PIEN LKOUT_PIEP 0TE LKOUT_LK0_N/LKOUT_PIEN F F U M 0TE 0 LK_PU_N_PH +VTT_PU R R 0KOhm 0KOhm P_I R.,item, PIO :Enable VVRM,Low=disable. efault internal pull up. PIO : efault internal PU 0K. WLN_ON# PU_PWROK WLN_LE U0_EL T R.,item L T dpu_pwr_en#_pio T PU_PWROK VRM_EN R.,item L R0 TP_PI# T_LK_REQ# F Y H0 V M V TH0/PIO LOK/PIO MEM_LE/PIO PIO PIO TP_PI#/PIO TLKREQ#/PIO TP/PIO PIO PU LKOUT_LK0_P/LKOUT_PIEP PEI RIN# PROPWR THRMTRIP# TP M 0 T E0 0 R PM_THRMTRIP# T LK_PU_P_PH H_PEI RIN# 0 H_PUPWR, R OHM HEK HERE R0 H_THRMTRIP#, OHM R.,item 0'WW MoW dpu_prnt# PU_PRNT# TP/PIO TP W T P_I0 V LO/PIO TP T P_I P TOUT0/PIO TP Y T T LK_REQ# H PIELKRQ#/PIO TP Y T T LK_REQ# F PIELKRQ#/PIO TP V T R.,item L 0, T PH_TEMP_LERT# T_ON EMIL_LE F TOUT/PIO TP/PIO PIO TP TP TP V F M T T TP0 N R.,item L +VU_OR EXT_MI# 0KOhm R LK_REQ# 0KOhm R LK_REQ# 0KOhm R PM_LNPHY_EN 0KOhm R PH XP +V R.,item R.,item L 0 E E F F H H H H J J J J J J0 J J E E V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_ V_NTF_0 V_NTF_ IEXPEK-M NTF RV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P INT_V# 0 TP_PH_T T0 T T T dpu_pwr_en#_pio 0KOhm R0 PH_TEMP_LERT# 0KOhm R PU_HP_INTR#_R 0KOhm R PIO0 0KOhm R PIO 0KOhm R TP_PI# 0KOhm R EMIL_LE 0KOhm R PU_PWROK R 0KOhm T_LK_REQ# R 0KOhm R.,item 0'WW0 MoW UTeK OMPUTER IN. N aniel Huang avid Lewis PH_IEX()PU,PIO,MI. Thursday, pril, 00 ate: heet of

26 +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO +VTT_PH_VIO +V_V +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR +VFI_VRM +.V +VTT_PH_.V_.V +.V +VTT_PH_OR +V_NVRM_VPNN +V_V_IO +V +VTT_PU +VM_VPEP +VU_OR +VTT_PU_V_MI +VTT_PH_OR +V_NVRM_VQ +.V_VMI_VRM +V +V +VTT_PH +VTT_PH_V +VTT_PH_OR +VTT_PH_OR +VTT_PH_VIO +V +VFI_VRM +.V_VMI_VRM +V_V_LV +.V +V +.V +V_NVRM_VQ +V +.V +.V_VT_LV ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER, ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER, ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER,. 0 max m 0 idle 00m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max +VTT_PH_VPLL_EXP.. 0 max +VTT_PH_V_EXP.0 0 max R.,item L R.,item L0 m 0 max check power plane R R 0 0UF/.V 0 0UF/.V UF/.V R UF/.V R R R R R R0 R R0 R 0.UF/V 0.UF/V R R 0.0UF/V R 0.0UF/V R L0 KOhm/00Mhz L0 KOhm/00Mhz V[] V[] 0 V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] 0 V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] E V[] E V[] F V[] F V[] P V[] F V[] F V[] F V[] F V[0] F V[] V[] V[] H V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] J V[] J V[] J0 V[] J V[] J V[] J V[] J V[] J V[0] J V[] T V[] J V[] K V[] K V[] K V[] K V[] K V[0] K0 V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[0] K V[] L V[] L V[] M V[] M0 V[] M V[] M V[] M V[00] M V[0] M0 V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] U0 V[] M V[] V V[] M V[] M V[] 0 V[] N V[] N0 V[] N V[0] P V[] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[] T V[] T V[] T V[] V V[] V V[] V0 V[] V V[0] V0 V[] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[0] W V[] F V[] W V[] W V[] W0 V[] W V[] Y V[] Y V[] Y V[0] Y V[] U V[] N V[] 0 V[0] V[] V V[] U V[] M V[] M V[] N V[] H V[] V[0] H V[0] V[] V[] U00H IEXPEK-M U00H IEXPEK-M 0 0UF/.V 0 0UF/.V R0 R0 R R 0 0UF/.V 0 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz R F R F 0.UF/V R 0.UF/V R 0.0UF/V R 0.0UF/V R L0 KOhm/00Mhz R L0 KOhm/00Mhz R R R R R UF/.V UF/.V R R R R 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R0 R0 0 UF/.V 0 UF/.V R R R0 F R0 F R0 R0 0 UF/.V 0 UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL L0 KOhm/00Mhz L0 KOhm/00Mhz 0 0.0UF/V R 0 0.0UF/V R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V L KOhm/00Mhz L KOhm/00Mhz R R 0 UF/.V 0 UF/.V R R 0 UF/.V 0 UF/.V 0 0UF/.V R 0 0UF/.V R 0 0UF/.V 0 0UF/.V R0 R0 VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K VPNN[] K0 VIO[] N VIO[] N VIO[] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[0] E VIO[] VIO[] VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LV[] P VTX_LV[] P VLV H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LV[] T VTX_LV[] T V_[] F V_LV H V_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M VME_[] P VME_[] P VPNN[] K VPNN[] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEK-M 0 UF/.V 0 UF/.V

27 +V.0_INT_VU TP_PH_VW +VT PRT +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_V PL +V_VPU +.0VM_OR +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU +V_RT +VTT_PH_VIO +V_V_ +VTT_PU +VTT_PH_.V_.V +VU_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_VPLL +V_PH_VREF +VU_VPU +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_OR +V +VU_OR +.0VM_OR +VU_OR +V_V_ +VU_OR +VTT_PH_VIO +V_V_ +V +VPLLVRM +VU_PH_VREFU +VTT_PH_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_OR +VTT_PH_.V_.V +VPLLVRM +.0V +.0VM_OR +V +V_V_ +VU_H +VU_OR +VU +VU_OR +VU +VU_OR +.0VM_OR ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER, ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER, ate: heet of Wednesday, pril 0, 00 UTeK OMPUTER IN. N. avid Lewis aniel Huang PH_IEX()_POWER, m 0 max m 0 max 0 max m 0 max m 0 max?? +.VM_VEPW >m 0 max m 0 max +VTT_PH_V.+m 0 max m 0 max +VTT_PH_VUORE m 0 max +VTT_PH_V_T +V_VPPI +V_VPORE 0mil trace at least R.,item L R.,item L R.,item L R.,item L R.,item L R.,item L R. P.: R.,item L 00m 0 max R.,item L isable Intel LN EMI EMI EMI LOE TO U00 LOE TO U00 UF/.V UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V PUYP Y0 VME[] VME[] VME[] VME[] F VME[] F VUH L0 VU_[] U VIO[] V VIO[] VIO[] F0 VIO[] F VME[] V VME[] V VME[] V VME[0] Y VME[] Y VME[] Y VREF K V_[] J V_[] L V_[0] M V_[] N V_[] P V_[] U VRT VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] E VU_[] E VU_[0] F VU_[] F VU_[] VU_[] VU_[] H VU_[] H VU_[] J VU_[] J VU_[] L VU_[] L VU_[0] M VU_[] M VU_[] N VU_[] N VU_[] P VU_[] P VU_[] U VU_[] U VU_[] U VU_[] V VIO[] 0 VIO[0] VIO[0] H VPLL[] VPLL[] VIO[] J VREF_U F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[] F V_[] VIO[] H VVRM[] T0 PU Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V VIO[] F VME[] F VIO[] H VIO[] H PT V VTPLL[] K VTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VU_[] P VU_[0] U VU_[] U0 VU_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEK-M 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V UF/.V UF/.V + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0.UF/V 0.UF/V R R 0.UF/V 0.UF/V L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R UF/.V UF/.V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V R R 0 T 0 T 0 T 0 T JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0 0.UF/V 0 0.UF/V R0 R0 R R JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL V[] Y V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] 0 V[] V[] 0 V[] V[] V[] V[] V[0] V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] H V[] V[] V[] V[] E V[] E V[] E0 V[] E V[] E0 V[00] E V[0] E V[0] E V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] F V[0] F V[0] F V[] V[] V[] V[] 0 V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] H V[] H V[] H V[] V[] 0 V[] V[] E V[] E V[0] E0 V[] E V[] E0 V[] E V[] E V[] E V[] E V[] E V[] K V[] K V[] L V[] L V[] L V[] L V[0] L V[] L V[] L0 V[] L V[] M V[] M V[] M0 V[] N V[] M V[] M V[0] M V[] M V[] M V[] M V[] M V[] N V[] P V[] P V[] P0 V[0] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[00] T V[0] T V[0] T V[0] U0 V[0] U V[0] U V[0] U V[0] P V[0] V V[0] P V[0] V V[] V0 V[] V V[] V0 V[] V V[] V V[] V V[] E V[] E V[0] F V[] F V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[0] V[] V[] V V[] V V[] V V[0] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[] Y V[0] Y V[] Y V[] Y V[] Y V[] Y V[] Y0 V[] Y V[] Y V[] Y V[] Y V[0] Y V[] Y V[] Y V[] Y V[] P V[] P V[] V[] F V[] H V[] H0 V[] H0 V[] H V[] H V[] H V[] T V[] V[] T V[] V[0] Y V[] T V[] M V[] T V[] M V[] K V[] K V[] V V[] K V[] K V[] H V[0] H V[] J U00I IEXPEK-M U00I IEXPEK-M UF/.V UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R R 0 R 0 R R UF/.V UF/.V 0.UF/V 0.UF/V 0UF/.V 0UF/.V UF/.V UF/.V 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. R 0 R 0 UF/.V UF/.V R R UF/.V UF/.V 0.UF/V 0.UF/V UF/.V UF/.V UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V.UF/.V.UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V