k42f_2.0_gerber

Transcription

1 KF SHEMTI For OM Rev.0 Power VORE Page 0 System LOK IRM.VS &.0VS Page Page R & VTT HMI RT L Panel HMI RT M PRKXTS LVS LVS RT Page 0 PIE x FI x PU RRNLE MI x Page ~ R 00/0MHz NV_Q R SOIMM ONFI raidwood Miniard WLN Page ~ Page Shirley Peak/ Echo Peak Page +.VS harger etect Load Switch Power Protect Page Page Page Page 0 Page Touchpad Keyboard ebug onn. E IT00EL SPI ROM LP PH Ibex PeakM PIE x US Miniard TV Tuner igaln HNKSVILLE Page Page R.,removed. RJ Page Page EST controller PREES ST solution Remove when fixed. Page Page 0~ Expressard R.,added. udio mp Jack Page INT. MI Page Page Page Page 0 zalia odec Realtek L lock enerator IS ISLPR Page Page ardreader+ Ricoh RU0 ardreader Page 0 Page 0 zalia PIE VI controller PWM Fan Page Page Page 0 ST 0 O H() Page H() Page Page est Page ischarge ircuit Page Reset ircuit Page 0 0 US Port() US Port() US Port() & TT. onn. Page 0 Skew Holes Page Page Page Page Page US Port() Page N Page MOS amera Miniard TV Tuner luetooth. Finger Print. N OLE N Page Page Page Page Page US Port() Page SUSTeK OMPUTER IN. N lock iagram KF Tuesday, November 0, 00 ate: Sheet of.0

2 PH_IEX PIO PH_IEX PIO Use s Signal Name PIO 00 PO PIO 0 PO PIO [:] Native PIO 0 PO PU_HP_INTR# PIO 0 PO PIO 0 PI EXT_SMI# PIO 0 Native US_O# PIO 0 Native US_O# PIO PI EXT_SI# PIO Native PM_LYPHY_EN PIO PO PIO PO _S# PIO PO WLN_ON PIO PO PU_HOL_RST# PIO PO PU_PWROK PIO Native LKREQ#_TV PIO PO PIO 0 Native LKREQ#_WLN PIO PO PIO PO WLN_LE PIO Native LRQ# PIO PO PIO Native LKREQ#_NEWR PIO Native LKREQ# PIO PO PIO PO T_LE PIO Native ME_PM_SLP_LN# PIO 0 Native ME_Sus_Pwrnck PIO Native ME PRESENT PIO Native PM_LKRUN# PIO PO PIO Native STP_PI# PIO Native ST_LK_REQ# PIO PO PU_PWR_EN# PIO PI PU_PRSNT# PIO PI P_I0 PIO PI P_I PIO 0 Native US_O# PIO Native US_O# PIO Native US_O# PIO Native US_O# PIO Native LK_REQ# PIO Native LK_REQ# PIO Native LK_REQ# PIO Native LKREQ_PE# PIO PO PIO PO PU_RST# PIO 0 Native PI_REQ# PIO Native PI_NT# PIO PO PIO PO PIO PO PIO PO PIO Native LKREQ_LN# PIO PO T_ON PIO Native SML_LK PIO Native US_O0# PIO 0 PO PIO Native PM_SUS_STT# PIO Native SUS_LK PIO Native PM_SLP_S# PIO Native LK_OUT0 PIO Native LK_OUT PIO Native LK_OUT PIO Native LK_OUT PIO PO PIO Native LK_REQ0# PIO PO PIO Native SML_T INT PU Internal & External Power Pullup/down +VS INT T +VS EXT PU +VS INT T +VS INT T +VS EXT PU & INT PU +VSUS EXT PU +VSUS EXT PU +VSUS EXT PU +VSUS EXT PU +VSUS +VSUS EXT PU(IOE NI) +VSUS INT P +VSUS +VS EXT P & INT T +VS EXT PU(NI)/P +VS +VS EXT PU(NI)/P +VS +VS EXT P +VS INT PU +VS +VSUS EXT PU(NI)/P +VSUS EXT PU (Not used) +VSUS INT WEK PU +VSUS EXT P +VSUS EXT PU(NI)/P(NI) +VSUS EXT PU +VSUS EXT PU +VSUS EXT PU +VS +VS +VS EXT PU/P(NI) +VS +VS EXT PU EXT PU EXT P EXT P EXT PU (Not used) EXT PU (Not used) EXT PU (Not used) EXT PU (Not used) EXT PU (Not used) EXT PU (Not used) EXT PU (Not used) EXT P EXT PU (Not used) INT PU INT PU EXT PU(NI)/P EXT PU(IOE) EXT PU EXT PU (Not used) INT T INT T INT T INT T EXT PU (Not used) EXT PU (Not used) EXT PU +VS +VS +VS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VS +VS +VS +VS +VS +VS +VS +VS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VSUS +VS +VS +VS +VS +VSUS +VSUS +VSUS +VSUS E IT E PIO Use s Signal Name P0 O PWR_LE# P O H_LE# P P P O L_L_PWM P O FN0_PWM P P P0 O SUS_E# P O SUS_E# P P IO SM0_LK P IO SM0_T P O 0TE P O R_IN# P O PM_RSMRST# P0 P IO SM_LK P IO SM_T P O PM_PWRTN# P I _IN_O# P OP_S# P I T_IN_O# P I RFON_SW# P0 P I PM_SUS# P I UF_PLT_RST# P O EXT_SI# P O EXT_SMI# P O L_KOFF# P I FN0_TH P PE0 O VSUS_ON PE O E (IT0 ddress/ata connect) PE O ES (IT0 ycle Start connect) PE O ELK (IT0 lock connect) PE I PWR_SW# PE PE I LI_SW# PE I P_K# PF0 PF PF I EXP_TE# PF PF I TP_LK PF IO TP_T PF O THRO_PU PF P0 P I PM_SUS# P P PH0 IO PM_LKRUN# PH PH O FX_VR_ON PH O T_LERN PH PH O NUM_LE# PH O P_LE# I SUS_PWR I LL_SYSTEM_PWR I VRM_PWR I FX_VR I LS_ PI0 PI PI PI PI PI PI PI PJ0 PJ PJ PJ PJ O O O O O PU_VRON PM_PWROK VSET_E ISET_E TP_LE PJ E IT0 E PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO0 PIO PIO PIO PIO PIO PIO PIO PIE PIE ST 0 ST ST ST Use s I I I I O O O ST H () ST O ST H () EST SUSTeK OMPUTER IN. N System Setting Signal Name ME_PM_SLP_M# ME_SusPwrnck ME_+VM_PWR ME_PM_SLP_LN# ME PRESENT ME_PWROK ME_SLP_M_E# SM_US RESS : PH Master SMus evice SMus ddress lock enerator(islpr) 000x ( ) SOIMM x ( 0 ) SOIMM 0000x ( ) VI ontroller(sm) 000x ( ) WiFi/WiMax N/ E Master (SM) SMus evice V Thermal I() PIE Minicard TV Tuner PIE Minicard WLN PIE Newcard PIE PIE EST (for prees) PIE LN SMus ddress PU Thermal Sensor(0) 0000x ( ) 000x ( ) US 0 US US US US US US US US US US 0 US US US KF US Port () US Port () US Port () US Port () MOS amera Neward Minicard TV Tuner WLN luetooth Finger Printer Tuesday, November 0, 00 ate: Sheet of.0

3 FI_TXN[:0] FI_TXP[:0] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN F MI_RXN H MI_RXP0 MI_RXP F MI_RXP E MI_RXP FI_TXN0 E FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN E FI_TXN F FI_TXN FI_TXP0 FI_TXP FI_TXP 0 FI_TXP FI_TXP FI_TXP E0 FI_TXP F0 FI_TXP FI_FSYN0 F FI_FSYN E FI_INT FI_LSYN0 F FI_LSYN For Intel FX display U00 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] MI_TX[] MI_TX[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_FSYN[0] FI_FSYN[] FI_INT FI_LSYN[0] FI_LSYN[] MI Intel(R) FI PI EXPRESS RPHIS PE_IOMPI PE_IOMPO PE_ROMPO PE_RIS PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_IROMP_R R00 EXP_RIS R00 K J J F F E 0 J H H F E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K 0 F E %.Ohm % R00,R0,R0 near U00 For E request, to read PEI via E. onnection: R0.>Q00.>U00.,,,,, UF_PLT_RST# +VTT_PU R00 R00 R00 R00 R00 H_PEI H_THRMTRIP# H_XPRST# PM_SYN# H_PUPWR H_RM_PWR H_VTTPWR H_PWR_XP % % % % % T00 R0.KOhm %.Ohm.Ohm H_PROHOT_S# H_OMP H_OMP H_OMP H_OMP0 TP_SKTO#.Ohm H_TERR# PLT_RST#_R R0 % T T T H K T N K P L N N K M M L U00 OMP OMP OMP OMP0 SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWROO_ VPWROO_0 SM_RMPWROK VTTPWROO TPPWROO RSTIN# 00 SOKET 0.UF/0V MIS THERML PWR MNEMENT LOKS R MIS JT & PM LK LK# LK_ITP LK_ITP# PE_LK PE_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] R0 T0 E F L M N N P LKREF LKREF# SM_ROMP0 SM_ROMP SM_ROMP +VTT_PU RN00 RN00 T P N P T T R R P N J K K J J H K H PM_EXTTS# XP_TI_R XP_TO_R XP_TI_M XP_TO_M R0 R0 R0 XP_OS0 XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS R0 R0 0KOhm 0KOhm % % % LK_PU_P_PH LK_PU_N_PH LK_ITP_LK LK_ITP_LK# LK_MI_PH LK_MI#_PH M_RMRST#, PM_EXTTS#0, XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# IPU IPU KOhm KOhm 0.Ohm XP_RESET#, Main oard 0KOhm RN00 0KOhm RN00 IPU IPU IPU IPU IPU XP_OS[:0] SOKET H_PUPWR H_RM_PWR H_VTTPWR UF/0V 0.UF/0V 0.UF/0V H_XPRST# XP_TMS XP_TI_R XP_PREQ# XP_TLK R0 R0 R0 R0 R0 +VTT_PU OHM Ohm Ohm Ohm Ohm JT MPPIN XP_TI_R XP_TO_M R0 R00 R0 P P XP_TI XP_TO XP_TRST# R0 %.Ohm XP_TI_M XP_TO_R R0 R0 P RMPWROK: (WW MoW) hoose either one solution: >hoose solution. This pin should have an external pullup of K Ohms to 0K Ohms to a rail of.0/.v which is ON in S0S. onnect this pin through a voltage divider circuit; recommend.k Ohms pullup to R Power Rail (VQ) of +V.U and a K Ohms pulldown to ground to convert to processor s VTT level. +VTT_PU R0 OHM +.V H_PROHOT_S# H_RM_PWR R00 %.KOHM R0 % KOhm Q00 N00 S THRO_PU SUSTeK OMPUTER IN. N PU()_MI,PE,FI,LK,MIS KF Thursday, November, 00 ate: Sheet of.0

4 Main oard U00 U00 M Q[:0] M S0 M S M S M S# M RS# M WE# M Q0 0 M Q 0 M Q M Q M Q 0 M Q 0 M Q E0 M Q M Q M Q F0 M Q0 E M Q F M Q E M Q M Q E M Q M Q H0 M Q M Q K M Q J M Q0 M Q 0 M Q J M Q J0 M Q L M Q M M Q M M Q L M Q L M Q K M Q0 N M Q P M Q H M Q F M Q K M Q K M Q F M Q M Q J M Q J M Q0 J0 M Q J M Q L0 M Q K M Q K M Q L M Q K M Q L M Q N M Q M0 M Q0 R M Q L M Q M M Q N M Q T M Q P M Q M M Q N M Q M M Q T M Q0 T M Q L M Q R M Q P U E E S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F H M M N0 N F J N H K P T F H M H K0 N R Y W V V T Y U T U T V M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_S#0 M_S# M_OT0 M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M S0 M S M S M S# M RS# M WE# E F F F F H J J J J J K L M K K M N F J K J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E H K H L R T F J L H L R R E H M L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_S# M_S# M_OT M_OT M M[:0] M QS#[:0] M QS[:0] M [:0] SOKET SOKET SUSTeK OMPUTER IN. N PU()_R KF Thursday, November, 00 ate: Sheet of.0

5 Main oard F[0:] : IPU F U00E P RSV L RSV L RSV L RSV J RSV RSV M RSV L RSV J RSV H RSV0 RSV RSV E RSV E0 RSV M0 F[0] M F[] P F[] L F[] L0 F[] M F[] N F[] M F[] K F[] K F[] K F[0] J F[] N0 F[] N F[] J F[] J F[] J0 F[] K0 F[] H F[] RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV RSV J RSV J RSV RSV RSV RSV0 RSV RESERVE RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV J J H K L R J J P T T R L L P0 P L T T P R T T P R R E F J H R R E V V N W W N E P U00H T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS 0 VSS F VSS F VSS F VSS E VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E E E E E0 E E E E E Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 U00I K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS VSS VSS 0 VSS VSS VSS VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF T T R SOKET SOKET SOKET F strapping information: F[:0]: PI Express Port ifurcation:(larksfield Only) = x PE (efault) 0 = x PE F[]: PIE Static Numbering Lane Reversal.(rrandale Only) :Normal Operation (efault) 0:Lane Numbers Reversed > 0, >,... F[]: Embedded isplayport etection.(rrandale Only) :isabled No Physical isplay Port attached to Embedded isplayport 0:Enabled n external isplay Port device is connected to the Embedded isplay Port F[]: Fixed for PI Express.0 jitter specifications.(larksfield) larksfield (only for early samples prees) onnect to with.0k Ohm/% resistor For a common motherboard design (for U and F), the pulldown resistor should be used. oes not impact rrandale functionality. Unmount if Intel has fixed this issue. F R0 %.0KOHM For rrandale F strapping information: For larksfield Note: (uburndale)hardware Straps are sampled on the asserting edge of VPWROO_0 and VPWROO_ and latched inside the processor. Note: (larksfield)hardware Straps are sampled after RSTIN# deassertion. SUSTeK OMPUTER IN. N PU()_F,RSV, KF Tuesday, November 0, 00 ate: Sheet of.0

6 VTT_SELET VTT_SENSE TP_VSS_SENSE_VTT VR_VI VR_VI VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_PWR_MON PM_PRSLPVR I_MON VR_VI[0:] VSENSE VSSSENSE V_X_SENSE VSS_X_SENSE VR_PWR_MON FXVR_PRSLPVR FX_VRON, PM_PSI# VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI +VORE +VTT_PU +VTT_PU +VTT_PU +.V +VORE +VFX_ORE +.VS +.VS_HPLL +VTT_PU +VFX_ORE +.V ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N PU()_PWR.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N PU()_PWR.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N PU()_PWR.0 KF Main oard Intel use u Intel use u Intel use u Intel use u VTT_TEST T Max Max Imax=. 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 UF/0V 0 UF/0V R00.KOhm R00.KOhm 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 00 0UF/.V 0 UF/0V 0 UF/0V 0 UF/.V 0 UF/.V 0 0.UF/V 0 0.UF/V 0 0UF/.V 0 0UF/.V 00 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 00 0UF/.V 00 0UF/.V 0 UF/.V 0 UF/.V T0 T0 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V ISENSE N VTT_SENSE PSI# N VI[0] K VI[] K VI[] K VI[] L VI[] L VI[] M VI[] M PRO_PRSLPVR M VTT_SELET V_SENSE J VSS_SENSE_VTT V V V V V V 0 V V V V0 V F V F V F V F V F V F0 V F V F V F V0 F V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V Y V Y V Y V Y V Y V Y0 V Y V Y V Y V0 Y V V V V V V V V V V V V0 V V V V V V V0 V V U V U V U V U V U V U0 V U V U V U V0 U V R V R V R V R V R V R0 V R V R V R V0 R V P V P V P V P V P V P0 V P V P V P V00 P VTT F0 VTT E0 VTT 0 VTT 0 VTT Y0 VTT W0 VTT U0 VTT0 T0 VTT J VTT J VTT H VTT H VTT H VTT H0 VTT J VTT J VTT H VTT H VTT VTT0 VTT VTT VTT F VTT F VTT F VTT F VTT E VTT E VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VSS_SENSE J VTT J VTT J POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS U00F SOKET POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS U00F SOKET + E00 0UF/V PNSONI/EEFSX0XE ESR=mOhm/Ir= + E00 0UF/V PNSONI/EEFSX0XE ESR=mOhm/Ir= 0 UF/0V 0 UF/0V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/0V 0 UF/0V R0 KOhm R0 KOhm 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V FX_VI[0] M FX_VI[] P FX_VI[] N FX_VI[] P FX_VI[] M FX_VI[] P FX_VI[] N FX_VR_EN R FX_PRSLPVR T FX_IMON M VX_SENSE R VSSX_SENSE T VX T VX T VX T VX T VX R VX R VX R VX R VX P VX0 P VX P VX P VX N VX N VX N VX N VX M VX M VX M VX0 M VX L VX L VX L VX L VX K VX K VX K VX K VX J VX0 J VX J VX J VX H VX H VX H VX H VTT J VTT J VTT H VTT K VTT J VTT0 J VTT J VTT H VTT VTT VTT VTT F VTT E VTT E VQ J VQ F VQ E VQ E VQ VQ VQ VQ Y VQ W VQ0 W VQ U VQ T VQ T VQ P VQ N VQ N VQ L VQ H VTT P0 VTT0 N0 VTT L0 VTT K0 VPLL L VPLL L VPLL M VTT J VTT J0 VTT J VTT H VTT H0 VTT H POWER RPHIS VIs RPHIS R.V RILS FI PE & MI SENSE LINES.V.V U00 SOKET POWER RPHIS VIs RPHIS R.V RILS FI PE & MI SENSE LINES.V.V U00 SOKET 0 0UF/.V 0 0UF/.V R00.KOhm R00.KOhm 0.UF/0V 0.UF/0V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V T T 0 UF/0V 0 UF/0V 0 UF/0V 0 UF/0V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 00 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V PL00 /00Mhz PL00 /00Mhz 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V T0 T0 00 0UF/.V 00 0UF/.V

7 Main oard PU XP connector +VTT_PU, H_PUPWR H_PWR_XP R00 R update 0 XP_PREQ# XP_PRY# XP_OS0 XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS XP_OS P P T00 T0 T0 XP_TLK KOhm PUPWR_XP.Ohm HOOK PIE_LK_XP_P PIE_LK_XP_N SM_T_XP SM_LK_XP XP NP_N NP_N XP_RST#_R R00 +VTT_PU LK_ITP_LK LK_ITP_LK# P KOhm H_XPRST# XP_TRST# XP_TI XP_TMS R0.Ohm P XP_RESET#, XP_TO to_on_0p P SUSTeK OMPUTER IN. N PU()_XP KF Thursday, November, 00 ate: Sheet of.0

8 M M M M M M M M M M M M M M M M0 M QS M QS# M QS M QS M QS M QS# M QS M QS# M QS# M QS M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M M M 0 M M M M M 0 M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M S# M_LK_R#0 M S M S0 M S M M[:0] M QS#[:0] M QS[:0] SM_T_S,, SM_LK_S,, M WE# PM_EXTTS#0, M_S# M RS# M_S#0 M_OT0 M_OT M_RMRST#, +VS +.V +0.VS M_VREF_IMM M_VREFQ_IMM +0.VS +.V +.V +.V ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_0.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_0.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_0.0 KF REV.mm SMus Slave ddress: 0H Layout Note: Place these caps near SO IMMS R. O 0.UF/V 0.UF/V 00PF/0V 00PF/0V R0 KOhm % R0 KOhm % 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# IMM R_IMM_0P 00X IMM R_IMM_0P 00X 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V UF/0V UF/0V 0 0/P 0 /# S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS IMM R_IMM_0P 00X IMM R_IMM_0P 00X + E0 0UF/V ESR=mOhm/Ir=. + E0 0UF/V ESR=mOhm/Ir=. 0UF/.V 0UF/.V 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V R0 KOhm % R0 KOhm % 0.UF/V 0.UF/V 0.UF/V 0.UF/V + E0 0UF/V ESR=mOhm/Ir=. + E0 0UF/V ESR=mOhm/Ir=. 00PF/0V 00PF/0V UF/0V UF/0V R0 KOhm % R0 KOhm % R0 KOhm % R0 KOhm %

9 M M M M M M M M M M M M0 M QS# M QS M QS M QS M QS M QS# M QS# M QS#0 M QS M QS# M QS0 M QS# M M M M M M M 0 M M M M M 0 M M M M M M M M M QS M QS M QS# M QS# M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M WE# M_S# M_LK_R M_KE M_LK_R# M_LK_R M_KE M S# M RS# M_LK_R# M_S# M_OT M_OT SM_T_S,, SM_LK_S,, M M[:0] M QS#[:0] M QS[:0] M S M S0 M S M_RMRST#, M [:0] M Q[:0] PM_EXTTS#0, +0.VS M_VREF_IMM M_VREFQ_IMM +.V +VS +VS ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_.0 KF ate: Sheet of Thursday, November, 00 SUSTeK OMPUTER IN. N R SOIMM_.0 KF SMus Slave ddress: H ST.mm SWP O EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 RS# 0 RESET# 0 S#0 S# S0 S 0 SL 0 S 00 TEST V V0 00 V 0 V 0 V V V V V V V V V V V V V V VSP VREF VREFQ VSS VSS 0 VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VTT 0 VTT 0 WE# IMM R_IMM_0P 00 IMM R_IMM_0P /P 0 /# S# K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q QS#0 0 QS# QS# QS# QS# QS# QS# QS# QS0 QS QS QS QS QS QS QS IMM R_IMM_0P 00 IMM R_IMM_0P 00

10 PH SPI ROM +V_E +V_SPI R +VSUS R /0 +VS R PH SPI ROM +V_SPI 0KOhm RN 0KOhm RN RN 0KOhm RN 0KOhm 0 0.UF/V SPI_S#0 SPI_SO R R SPI_S#0_R SPI_SO_R +VM_SPI_WP0# U0 S# SO/SIO WP#/ V HOL# SLK SI/SIO0 +VM_SPI_00 SPI_LK_R SPI_SI_R R R SPI_LK SPI_SI MXL0MI (Mb) close to U0 R /0 E_SPI_O E_SPI_E# E_SPI_I E_SPI_K SUSTeK OMPUTER IN. N R _Q VOLTE KF Thursday, November, 00 ate: Sheet of 0.0

11 SUSTeK OMPUTER IN. N E ate: Tuesday, November 0, 00 Sheet of.0 VI ontroller KF

12 Request by S for MOS clear function MOS Settings lear MOS Keep MOS JRST00 Shunt Open (efault) +V_RT RTRST# R delay should be ms~ms R00 0KOhm % JRST00 SL_JUMP TPM Settings lear ME RT Registers Keep ME RT Registers RTRST# 00 UF/0V JRST00 Shunt Open (efault) 00 PF/0V 00 PF/0V +V_RT X00.Khz 000 X_RT R00 0MOhm X_RT PH_INTRUER# 00KOhm RN00 PH_INTVRMEN 00KOhm RN00 00KOhm RN00 00KOhm RN00 0PF/0V 0 S_SPKR X_RT X_RT RTRST# SRTRST# PH_INTRUER# PH_INTVRMEN Z_LK Z_SYN 0 P U00 RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR RT LP FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP F K K K K LP_0,0 LP_,0 LP_,0 LP_,0 LP_FRME#,0 LP_RQ#0 T00 LP_RQ# T00 INT_SERIRQ ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 VS_Native_IPU R00 0KOhm % JRST00 SL_JUMP SRTRST# 00 UF/0V.0 P RTRST# and SRTRST# can not be shorted together Strap information: H L Z_SYN: Select VVRM.V or.v.v.v (IP) S_SPKR: No reboot strap (IP) No reboot isable No reboot PH_SPI_OV_RW: (IPU) No Flash ME FW Flash ME FW SPI_SI: itpm strap. (IP) Enable isable PH_INTVRMEN Enable isable Integrated.0 V VRM Enable /isable Z_RST#_U RN00 0OHM Z_LK_U RN00 0OHM Z_SOUT_U RN00 0OHM Z_SYN_U RN00 0OHM +VS RN00 0KOhm RN00 0KOhm RN00 0KOhm RN00 0KOhm +VS R0 0KOhm PH_SPI_OV_RW R0 Q0 00KOhm PH_SPI_OV N00 S Z_RST# Z_LK Z_SOUT Z_SYN INT_SERIRQ ST_LE# VTT_PU_SEL VTT_PU_SEL +VS R00 KOhm S_SPKR PH_JT_TK_UF R0 Ohm Z_SIN0_U VS_PO_IPU VSUS_PI_IP IP IPU IPU IPU T00 T00 T00 T0 T0 SPI_LK SPI_S#0 SPI_SI T00 SPI_SO Z_RST# Z_SOUT PH_SPI_OV_RW H_OK_RST# PH_JT_TK_UF PH_JT_TMS PH_JT_TI PH_JT_TO PH_JT_RST# SPI_LK IPU IPU 0 0 F0 E F H J0 M K K J J V Y Y V H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO H_OK_EN#/PIO H_OK_RST#/PIO JT_TK JT_TMS JT_TI JT_TO JT_RST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IEXPEKM IH SPI JT ST STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# ST0P/PIO STP/PIO H H H H F F F F H H F F F F T Y V ST_RXN ST_RXP ST_TXN ST_TXP ST,: ES.0: ST port,port may not be available in all PH SKUs. +VTT_PH ST_OMP R00 %.Ohm ST_LE# 0 VTT_PU_SEL VS_PI VS_PI VTT_PU_SEL 0 0PF/0V PH SPI ROM UT OFF SUSTeK OMPUTER IN. N PH_IEX()ST,IH,RT,LP KF Thursday, November, 00 ate: Sheet of.0

13 +VSUS Update /0 R.0 +VS PIE: WLN PIE: LN Note: Place these resisters near to PIe Slots LK_REQ0# LK_REQ# LK_REQ# LK_REQ# PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RX_LN_N PIE_RX_LN_P PIE_TX_LN_N PIE_TX_LN_P LK_PIE_WLN#_PH LK_PIE_WLN_PH PH LKREQ Setting: Not connected to device. PH LN_N PH LN_P LKREQ_WLN# LKREQ_LN# Jmc do not support +VSUS LK_REQ# LK_REQ# LK_REQ# PIE_TXN_ PIE_TXP_ PIE_TXN_ PIE_TXP_ PIE,: ES.0: port,port may not be available in all PH SKUs. WLN do not support 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN VSUS_Native_IPU 0.UF/V 0.UF/V 0.UF/V X 0.UF/V X VS_Native RX0 RX0 X0 X0 R RX0 RX0 R LK_REQ0# LK_REQ# LK_PH_SR_N LK_PH_SR_P LKREQ_WLN#_R VS_Native VSUS_Native LK_PH_PE N LK_PH_PE P VSUS_Native VSUS_Native LKREQ_LN#_R VSUS_Native 0 J0 F H W U0 T0 U V E F H J W T U U V J J K K P M M U M M N H H M M M J0 J H K K P U00 PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP LKOUT_PIE0N LKOUT_PIE0P PIELKRQ0#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO0 LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PE N LKOUT_PE P PE LKRQ#/PIO IEXPEKM PIE* SMus From LK UFFER lock Flex ontroller PE Link SMLERT#/PIO SMLK SMT SML0LERT#/PIO0 SML0LK SML0T SMLLERT#/PIO SMLLK/PIO SMLT/PIO L_LK L_T L_RST# PE LKRQ#/PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_ST_N/KSS_N LKIN_ST_P/KSS_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT XLK_ROMP LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO H J M E0 T T T H N N T T W P P F E H H P J H H F T P T N0 SML0_LK SML0_T SML_LK SML_T PRK_PELK_REQ# VSUS_Native LK_REF#_EP LK_REF_EP X_IN X_OUT XLK_OMP LK_OUT0 LK_OUT LK_OUT LK_OUT PH_SMLK PH_SMT +VTT_PH VS_Native_IP VS_Native_IP VS_Native_IP VS_Native_IP E_SI#.0 P When unused, L_LK, L_T and L_RST# may be left unconnected. R 0.Ohm % T T T0 T0 T T WLN_ON VSUS_Native T_ON VSUS_Native VSUS_Native To E VSUS_Native LK_MI#_PH LK_MI_PH _PH_MI# _PH_MI _PH_LK# _PH_LK _M_OT# _M_OT _PH_ST# _PH_ST _M_PH LK_PI_F VSUS_Native R MOhm PH_SMLK PH_SMT XOUT R0: For Xtal measurement +VS.KOhm.KOhm.KOhm.KOhm Q0 UMKN Update /0 R.0 SML_LK SML_T If not use crystal,please change 0 to 0 OHM 0 PF/0V X0 Mhz 0 PF/0V +VS Q0 UMKN E_SI# WLN_ON T_ON SML_LK SML_T SML0_LK SML0_T.0 Section...: dded MHz rystal routing guideline. ll Mobile Intel Series hipsetbased Integrated raphics platforms are required to use a MHz crystal on the PH XTL_IN/OUT to enable the PH to generate the display clocks. isplay lock generation is integrated into the PH. Integrated raphics platforms that implement VI/P/HMI/eP are required to use isplay lock Integration (I) (M crystal to generate PH display clocks) to improve signal integrity and mitigate risk of electrical compliance and associated functional failures WW Update:Integrated raphics platforms that use onlylvs and/or V isplays may use uffer Through Mode (TM) and leave MHz crystal and R components unstuffed Q0 UMKN Q0 UMKN 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0.KOHM RN.KOHM RN.KOHM RN.KOHM RN SM_LK_S,, SM_T_S,, SM_LK SM_T +VSUS +VS+VSUS LK_REQ# PRK_PELK_REQ# LKREQ_WLN#_R LKREQ_LN#_R 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN SUSTeK OMPUTER IN. N PH_IEX()_PIE,LK,SM,PE KF Thursday, November, 00 ate: Sheet of.0

14 prees not support Reversal Feature PM_RI# PM_TLOW# ME_SusPwrnck PH_LN_RST# +VSUS 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN +VTT_PH R0.Ohm % MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_OMP U00 MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP MIRXP 0 MIRXP 0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP H MI_ZOMP F MI_IROMP MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 H J E F W J F H J FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN FI_LSYN +VS +VSUS PM_LKRUN# SYS_RESET# PIE_WKE# 0KOhm RN 0KOhm RN 0KOhm RN RN 0KOhm, XP_RESET# P R SYS_RESET# 0 PM_PWROK_PH 0.UF/0V PH_LN_RST# H_RM_PWR 0 0.UF/0V PM_RSMRST#_PH VSUS_PI ME_SusPwrnck PM_PWRTN# VSUS_PI ME PRESENT_PH T M K 0 M P P SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# SUS_PWR_K/PIO0 PWRTN# PRESENT/PIO System Power Management WKE# LKRUN#/PIO SUS_STT#/PIO SUSLK/PIO SLP_S#/PIO SLP_S# SLP_S# SLP_M# TP J Y P F E H P K N VS_Native PM_SUS_STT# SUS_LK SLP_S# ME_PM_SLP_M# T0 T0 T0 T0 PIE_WKE# PM_LKRUN# VSUS_Native VSUS_Native VSUS_Native PM_SUS# PM_SUS# VSUS_Native_IPU T0 PM_TLOW# TLOW#/PIO PMSYNH J0 PM_SYN# T0 PM_RI# F RI# SLP_LN# F ME_PM_SLP_LN#_PH T0 IEXPEKM R.,item L Power failure solution (S0>,S>): +VSUS PM_PWROK,PM_RSMRST#: previous platform solution. ME_PWROK,ME PRESENT: reserved for test. 0'MoW0: Optional if ME FW is Ignition FW R 0KOhm RN KOHM HNE K NO K 排阻 PM_PWROK_PH KOHM RN PM_PWROK PM_RSMRST#_PH KOHM RN PM_RSMRST# ME PRESENT_PH KOHM RN ME PRESENT 0 0: Prevent E drive hign, SUS_PWR sink low in S>. ME Ignition Firmware is for M SPI core, only PM can support on it. TW 0 SUS_PWR,, TW SUSTeK OMPUTER IN. N PH_IEX()_FI,MI,SYS PWR KF Thursday, November, 00 ate: Sheet of.0

15 +VS EI_T_PH EI_LK_PH L_TRL_T L_TRL_LK.KOhm RN.KOhm RN.KOhm RN.KOhm RN U00 L_KEN_PH L_VEN_PH EI_LK_PH EI_T_PH T0 T0 T0 L_KLTTL_PH L_TRL_LK L_TRL_T T T Y Y V L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T SVO_TVLKINN SVO_TVLKINP SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP J J F H R0.KOHM % R0 PH_LVS_I PH_LV_V P P LV_I LV_V SVO_TRLLK SVO_TRLT T T LVS isable: (For discrete graphic). N: LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK#, LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to : VccLVS,VccTX_LVS RT PH RT PH RT_R_PH U Item LVS_LLKN_PH LVS_LLKP_PH LVS_L0N_PH LVS_LN_PH LVS_LN_PH LVS_L0P_PH LVS_LP_PH LVS_LP_PH Single hannel T T V V Y V 0 Y V P P Y T U T Y T U0 T LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_REEN RT_RE LVS igital isplay Interface P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT J U J 0 0 W Y E V0 E0 0 F H U0 U TMS_TXN_PH TMS_TXP_PH TMS_TXN_PH TMS_TXP_PH TMS_TXN0_PH TMS_TXP0_PH TMS_LKN_PH TMS_LKP_PH UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V TMS_TRLLK TMS_TRLT TMS_HP TMS_TXN_PH TMS_TXP_PH TMS_TXN_PH TMS_TXP_PH TMS_TXN0_PH TMS_TXP0_PH TMS_LKN_PH TMS_LKP_PH TMS_TXN_PH R 0 TMS_TXP_PH TMS_TXN0_PH R 0 TMS_TXP0_PH TMS_TXN_PH R 0 TMS_TXP_PH TMS_LKN_PH R 0 TMS_LKP_PH R % R % R % RT_HSYN_PH RT_VSYN_PH _LK_PH _T_PH R R R0., R0.: K+/0.% Intel checklist recommand:.0k P resistor to 0.% R0 R0 0.% KOHM PH_RT_HSYN PH_RT_VSYN PH IREF V RT LK V RT T Y RT_HSYN Y RT_VSYN _IREF RT_IRTN IEXPEKM RT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 0 J F H E RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE RT_HSYN,RT_VSYN. kω ±0.% pulldown to : _IREF. onnected to : RT_ITRN. onnect to +V.: V SUSTeK OMPUTER IN. N PH_IEX()_P,LVS,RT KF Thursday, November, 00 ate: Sheet of.0

16 VS_Native[0,,] T0 VS_Native_IPU [,,] VS_PI [,,,] T0 T0 PI_INT# PI_INT# PI_INT# PI_INT# PI_REQ0# PI_REQ# PU_SELET#_R PI_REQ# PI_NT0# PI_NT# PI_NT# PI_NT# PI_INTE# PI_INTF# PI_INT# PI_INTH# PI_RST# PI_SERR# PI_PERR# PI_IRY# PI_PR PI_EVSEL# PI_FRME# U00E H0 0 N J 0 E H E0 0 0 M M F M0 M J K F0 0 K M J K L F J0 F M 0 H J0 /E0# /E# H /E# /E# PIRQ# H PIRQ# PIRQ# PIRQ# F REQ0# REQ#/PIO0 REQ#/PIO M REQ#/PIO F NT0# K NT#/PIO F NT#/PIO H NT#/PIO PIRQE#/PIO K PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO K PIRST# E SERR# E0 PERR# IRY# H PR F EVSEL# FRME# PI NVRM US NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP Y P V P P T T V E J J Y U V Y Y V F H J N0 P0 J0 L0 F M N H J E F H L M Strap information: PH_NV_LE: Strap Intel ntitheft Technology H ata Protection Enable NV_LE: Strap MI Termination voltage PH_NV_LE PH_NV_LE KOhm KOhm R R US_PN US_PP +.VS NV_LE: Strap Intel ntitheft Technology H ata Protection Enable. (H: enable) NV_LE: Strap MI Termination voltage KJR US_PN0 US_PP0 0 US port US_PN US_PP US port US_PN US_PP US port US_PN US_PP WiFi/WiMax US_PN US_PP amera 0 T (.) H ENLE L ISLE Recommand settings PI_INTE# PI_STOP# PI_IRY# PI_SERR# PI_INT# PI_INT# PI_INT# PI_INT# PI_LOK# PI_EVSEL# PI_PERR# PI_REQ# PU_SELET#_R PI_FRME# PI_TRY# PI_INTH# PI_REQ0# PI_INT# PI_INTF# PI_REQ# +VS RP0 0KOhm 0 RP0 0KOhm 0 RP0 0KOhm 0 RP0 0KOhm 0 RP0E 0KOhm 0 RP0F 0KOhm 0 RP0 0KOhm 0 RP0H 0KOhm 0 RP0 0KOhm 0 RP0 0KOhm 0 RP0 0KOhm 0 RP0 0KOhm 0 RP0E 0KOhm 0 RP0F 0KOhm 0 RP0 0KOhm 0 RP0H 0KOhm 0 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN +VSUS change to PI_LK to sync IS PI_PME#: Internal PU to suspend plane. LK_PI_F LK_KPI_PH 0 LK_EU R.,item L IPU T0 T0 RX0 R0 R0 T0 USRIS# USRIS O# O# O# O# O# O# USRIS_PN US_O0# US_O# R.Ohm % Place within 00 mils of IH VSUS_Native [,0,,0,,,,] O# O# O# O# O# O# RP0 RP0 RP0 RP0 RP0E RP0F RP0 RP0H 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0KOhm 0 0PF/0V 0 0PF/0V 0 0PF/0V 0 PI_LOK# PLOK# PI_STOP# PI_TRY# STOP# TRY# PI_PME# M PME# PLT_RST# PLTRST# LK_SPPI_R N LK_PI_F_R LKOUT_PI0 P LK_KPI_PH_R LKOUT_PI P LK_EU_R LKOUT_PI P LK_PI_R LKOUT_PI P LKOUT_PI IEXPEKM O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO N J F L E F T +VSUS NT0#,NT#: oot IOS Strap. oot IOS Strap PI_NT# PI_NT0# oot IOS Location 0 0 LP PI 0 Reserved 0 SPI (PH) NT#: swap override Strap/ Toplock swap override jumper Low=Enabled swap override/ Toplock swap override High=efault PLT_RST# R 0KOhm U0 V Y NSZ0PX_NL R UF_PLT_RST#,,,, check 其他 device 是否 reset 起來 Sampled on rising edge of PWROK. PI_NT0# R0 KOhm PI_NT# R KOhm PI_NT# R KOhm SUSTeK OMPUTER IN. N PH_IEX()_PI,NVRM,US KF Thursday, November, 00 ate: Sheet of.0

17 +VS POWER 按照提供的 default 值調節電壓 U00F VS_PI VS_PI_IPU.V_SEL SPIO Y MUSY#/PIO0 TH/PIO LKOUT_PIEN LKOUT_PIEP H H R 0KOhm VS_PI_IPU VS_PI_IPU VSUS_PO_IPU E_SMI# P_I P_I0 J F0 TH/PIO TH/PIO PIO MIS LKOUT_PIEN LKOUT_PIEP F F P_I0 P_I P_I VSUS_PI VSUS_PO_IP VS_PI VS_PI_IPU SPIO PIO PU_HOL_RST# V_VORE_PWR K T F LN_PHY_PWR_TRL/PIO PIO STP/PIO TH0/PIO 0TE LKOUT_LK0_N/LKOUT_PIEN LKOUT_LK0_P/LKOUT_PIEP U M M 0TE LK_PU_N_PH LK_PU_P_PH +VTT_PU R KOhm R KOhm R 0KOhm PIO :Enable VVRM,Low=disable. efault internal pull up. VS_PI VSUS_PO VSUS_PO_IPU VSUS_PI_IPU VS_PI 0 WLN_T_LE.V_SEL STP_PI# T PIO PH_VRM_EN Y H0 V M SLOK/PIO MEM_LE/PIO PIO PIO STP_PI#/PIO PIO PU PEI RIN# PROPWR THRMTRIP# 0 T E0 0 PM_THRMTRIP# H_PEI K_RST# H_PUPWR, R Ohm VS_PO STLKREQ# V STLKREQ#/PIO PI VS_PI VS_PI VORE_SEL PU_PWR_EN# STP/PIO STP/PIO TP TP W VS_PI VORE_SEL V SLO/PIO TP VS_PI P_I P STOUT0/PIO TP Y +VS VSUS_Native_IPU VSUS_Native VS_PI T T LK_REQ# LK_REQ# PIO H F PIELKRQ#/PIO PIELKRQ#/PIO STOUT/PIO TP TP TP Y V V 0KOhm RN 0KOhm RN VORE_SEL SPIO VS_PI VSUS_PI PH_TEMP_EN VTT_PH_SEL F STP/PIO PIO TP TP F M TP_PH T 0KOhm RN.V_SEL TP0 N TP0_PH T +VSUS +VS R R 0KOhm RN KOhm 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm PIO.V_SEL VORE_SEL SPIO VTT_PH_SEL E_SMI# LK_REQ# LK_REQ# PU_PWR_EN# STLKREQ# 0 E E F F H H H H J J J J J J0 J J E E VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ IEXPEKM NTF RSV TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP J K K M N M0 N0 H T P 0 TP_PH TP_PH INT_V# T T0 T IPU RN0 0KOhm RN0 0KOhm RN0 0KOhm RN0 0KOhm PH_TEMP_EN PU_HOL_RST# STP_PI# PIO R 0KOhm R 00KOHM PH_VRM_EN V_VORE_PWR SUSTeK OMPUTER IN. N PH_IEX()PU,PIO,MIS KF Thursday, November, 00 ate: Sheet of.0

18 +VTT_PH U00. S0 max VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[] H VORE[0] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VORE[] +VTT_PH_VPLL_EXP m S0 idlek +VTT_PH_VPLL_EXP VIO[] J +VTT_PH VPLLEXP +VTT_PH_V_EXP N0 VIO[] N VIO[] N VIO[] N VIO[] N VIO[] N VIO[0] J VIO[] J VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[] W VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[] E VIO[0] VIO[] VIO[] H VIO[] N0 VIO[] N +VS +VS_V VIO[] N +VFI_VRM R V_[] +VTT_PH_VPLL_FI T VVRM[] +VTT_PH +VTT_PH_VPLL_FI J VFIPLL M R0 VIO[] POWER V ORE PI E* FI RT LVS HVMOS MI NN / SPI V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VME_[] VME_[] VME_[] VME_[] +V E0 m S0 max E F F +VS_V_LVS H 00m S0 max H +.VS_VT_LV P m S0 max P T T +VS_V_IO m S0 max +.VS_VMI_VRM T +VTT_PU_V_MI T m S0 max U +V_NVRM_VPNN M m S0 max K K0 K K K M M M +VM_VPEP M m S0 max M P P +VTT_PH 0 0UF/.V +VTT_PH +VTT_PH_VPLL_EXP L0 /00Mhz +VTT_PH +VTT_PH_VPLL_EXP R0 +VTT_PH +VTT_PH_VPLL_FI +V +VS 0 0.0UF/V 0 UF/0V L0 /00Mhz 0.UF/V +VS_V_LVS +VS 0 0UF/.V 0 UF/0V 0 0UF/.V 0 0UF/.V 0 UF/0V 0 UF/0V L0 /00Mhz L0 0 +.VS 0UF/.V /00Mhz 0 UF/0V +.VS_VT_LV +VS_V_IO +VTT_PU_V_MI +V_NVRM_VPNN +VM_VPEP 0.0UF/V 0.UF/V UF/0V R R 0.UF/V R +VS R +VTT_PU +VTT_PH +.VS +VS R /0 0.UF/V R 0.0UF/V L0 /00Mhz UF/.V +VSUS +.VS Update /0 R.0 IEXPEKM R0 R0 H_SYN: Select VVRM.V or.v (IP) Low:.V High:.V +.VS +VTT_PH_.VS_.VS +VFI_VRM R R +.VS +.VS_VMI_VRM R0 R 0.UF/V 0.UF/V SUSTeK OMPUTER IN. N PH_IEX()_POWER, KF Thursday, November, 00 ate: Sheet of.0

19 +VTT_PH_V_LK U00J POWER +VTT_PH +VTT_PH R +.0VM_VUX m S0 max R +VTT_PH TP_PH_VSW 0.UF/V PRT +VTT_PH_.VS_.VS +VTT_PH +VTT_PH_SSV +VSST 0.UF/V+V.0_INT_VSUS Y +V_VPSUS +VS +VTT_PU_VPPU +V_RT m S0 max +.VM_VEPW 0.UF/V m +VTT_PH_V PL S0 max m +VTT_PH_V PL S0 max 0.UF/V +VS_VPORE m S0 max P P F F Y0 F F F V V V Y Y Y V U H J H F H F V P U U0 U V V Y T U VLK[] VLK[] VLN[] VLN[] PSUSYP VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[0] VME[] VME[] PRT VVRM[] VPLL[] VPLL[] VPLL[] VPLL[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] PSST PSUS VSUS_[] VSUS_[0] VSUS_[] VSUS_[] V_[] V_[] V_[] V_PU_IO[] V_PU_IO[] VRT IEXPEKM lock and Miscellaneous RT PU PI/PIO/LP ST PI/PIO/LP US H VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[0] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VIO[] VREF_SUS VREF V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VSTPLL[] VSTPLL[] VIO[] VVRM[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VME[] VME[] VME[] VME[] VSUSH V +VTT_PH_VUSORE V Y Y +VSUS_VPUS V m S0 max U U U P P N N M M L L J J H H F F E E U +VTT_PH V +VSUS_PH_VREFSUS F +VS_PH_VREF K +VS J +VS_VPPI L M N P U +VS +VTT_PH_VPLL K K +VTT_PH H +VTT_PH_V_ST +VPLLVRM T0 H 0 F F0 F H0 0 +VTT_PH +.0VM_OR_R Y +.0VM_OR_R Y +.0VM_OR_R +.0VM_OR_R 0mil trace +VSUS_H L0 +VTT_PH +VTT_PH +VPLLVRM +VSUS +VS +VSUS_VPUS L0 /00Mhz. S0 max 0 0UF/.V R 0.UF/V 0 0UF/.V R +V_VPSUS +VTT_PH_V_LK 0UF/.V +VTT_PH_.VS_.VS 0.UF/V +VTT_PU +VTT_PU_VPPU >m S0 max R.UF/.V 0.UF/V 0.UF/V 0 0.UF/V R0 0.UF/V 0 UF/.V 0.UF/V UF/0V +VSUS UF/0V 0 UF/0V 0 0.UF/V UF/0V UF/0V UF/0V UF/0V UF/0V +VSUS_PH_VREFSUS +VS_PH_VREF +VTT_PH_VPLL +VSUS_H UF/0V UF/0V 0UF/.V UF/0V +V_RT R 0.UF/V HNE LOTION NEXT 0UF/.V 0 TW +VSUS +VSUS +VS +VTT_PH L0 /00Mhz 0.UF/V R 0 0 TW R 0 +VSUS +VS +VTT_PH_V PL +VTT_PH_V PL +VTT_PH L0 /00Mhz R UF/0V 0UF/.V +VTT_PH_V PL +VTT_PH_V PL L0 0.UF/V UF/0V /00Mhz 0UF/.V SUSTeK OMPUTER IN. N PH_IEX()_POWER, KF Tuesday, November 0, 00 ate: Sheet of.0

20 ate: Sheet of Tuesday, November 0, 00 SUSTeK OMPUTER IN. N.0 KF 0 PH ate: Sheet of Tuesday, November 0, 00 SUSTeK OMPUTER IN. N.0 KF 0 PH ate: Sheet of Tuesday, November 0, 00 SUSTeK OMPUTER IN. N.0 KF 0 PH VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] P VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] VSS[] VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[0] J VSS[] T VSS[] J VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K0 VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[0] K VSS[] L VSS[] L VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M0 VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] M VSS[0] U0 VSS[] M VSS[] V VSS[] M VSS[] M VSS[] 0 VSS[] N VSS[] N0 VSS[] N VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] V VSS[] V VSS[] V0 VSS[] V VSS[0] V0 VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[0] W VSS[] F VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] U VSS[] N VSS[] 0 VSS[0] VSS[] V VSS[] U VSS[] M VSS[] M VSS[] N VSS[] H VSS[] VSS[0] H VSS[0] VSS[] VSS[] U00H IEXPEKM U00H IEXPEKM VSS[] Y VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] 0 VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[0] VSS[] H VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] E VSS[] E0 VSS[00] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E VSS[0] E0 VSS[0] E VSS[0] E VSS[0] F VSS[0] F VSS[0] F VSS[] VSS[] VSS[] VSS[] 0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[] 0 VSS[] VSS[] E VSS[] E VSS[0] E0 VSS[] E VSS[] E0 VSS[] E VSS[] E VSS[] E VSS[] E VSS[] E VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L0 VSS[] L VSS[] M VSS[] M VSS[] M0 VSS[] N VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P VSS[] P VSS[] P0 VSS[0] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] T VSS[0] T VSS[0] U0 VSS[0] U VSS[0] U VSS[0] U VSS[0] P VSS[0] V VSS[0] P VSS[0] V VSS[] V0 VSS[] V VSS[] V0 VSS[] V VSS[] V VSS[] V VSS[] E VSS[] E VSS[0] F VSS[] F VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] V VSS[] V VSS[] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y0 VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] P VSS[] P VSS[] VSS[] F VSS[] H VSS[] H0 VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] T VSS[] VSS[] T VSS[] VSS[0] Y VSS[] T VSS[] M VSS[] T VSS[] M VSS[] K VSS[] K VSS[] V VSS[] K VSS[] K VSS[] H VSS[0] H VSS[] J U00I IEXPEKM U00I IEXPEKM

21 R MOhm :isable 0:Enable FS Function X.Mhz _XIN PF/0V _XOUT PF/0V +VS L +V_LK PEREQ:PIEx0 & PIEx PEREQ:PIEx & PIEx & ST PEREQ:PIEx & PIEx & PIEx H L FIXE PLL (synchronous) PI/PIEX PLL(synchronize) /00Mhz 0.UF/V 0UF/.V c00_h Vxx min:.v max:.v I: mv 0.UF/V 0.UF/V 0.UF/V 0 /00Mhz 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V L +V_LK_V 0.UF/V +V_LK_V +V_LK _M_OT _M_OT# _PH_MI _PH_MI# _PH_ST _PH_ST# PEREQ# _REQ#_WLN FS _PI_S_R _M_R LK_EN _FSL _FSL U V MHz/FREERUN PI&PIEX_STOP# PEREQ# PU_STOP# PEREQ# REF0/FSL FS/PILK0 O_PEREQ# VPI X 0 ITP_EN/PILK_F0 X SEL_#/_MHz VREF 0 Vtt_Pwrd/P# ST V SLK FSL/US_MHz PUT_LR0 OTT_MHzLR PU_LR0 OT_MHzLR VPU FSL PUT_LR PIeT_LR0 PU_LR 0 PIe_LR0 RESET# PIeT_LR 0 PIe_LR V VPIEX PUITPT_LR/PIeT_LR PIeT_LR PUITP_LR/PIe_LR PIe_LR VPIEX PIeT_LR PIeT_LR PIe_LR PIe_LR STLKT_LR PIeT_LR STLK_LR PIe_LR 0 VPIEX ISLPRSLFT _M_LN_R +V_LK STP_PU# _FSL Ohm R _REQ#_LN _XIN _XOUT _XP _XP# Ohm R T T _FSL R0 0KOhm +V_LK _M_LN STP_PI# _M_PH SM_T_S,, SM_LK_S,, _PH_LK _PH_LK# FSL STP_PU# _M_R FSL R R FSL PU(MHZ) 0 0KOhm 0KOhm +V_LK _M_LN_R _FSL 0PF/0V 0PF/0V /EMI /EMI LK_EN# +VS R 0KOhm S Q N00 LK_EN R 00KOhm 0.UF/V _FSL R 0KOhm +V_LK R 0KOhm R 0KOhm 0 0 _REQ#_LN _REQ#_WLN PEREQ# _PI_S_R KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN +V_LK +V_LK _FSL R 0KOhm FS R R 0KOhm 0KOhm <Variant Name> SUSTek omputer IN. KF ISLPRS ate: Thursday, November, 00 Sheet of.0

22 place on LP_E bus Update /0 R.0 PIN R0 R0 /0 +V_E +VS 0 000PF/0V +V_E +VPLL +VS+V 0 0.UF/V K_RST# UF_PLT_RST# 00 0.UF/V,0,0,0,0 LP_0 LP_ LP_ LP_ ME_SusPwrnck 0 E_SPI_K E_SPI_O E_SPI_I E_SPI_E# Update /0 R.0, RN0 E_LP_0 0OHM 0 RN0 E_LP_ 0OHM RN0 E_LP_ 0OHM RN0 E_LP_ 0OHM LK_KPI_PH,0 LP_FRME#,,,, UF_PLT_RST# INT_SERIRQ O E_SMI# O E_SI# O 0TE O K_RST# O E_RST# R00 ME_SusPwrnck P0 0 R0 FSK R0 FSI 0 R0 FSE# 0 00 VSUS_ON KSO0 KSO KSO KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO PM_PWRTN# OP_S# KSI0 KSI KSI KSI KSI KSI KSI KSI VSUS_ON TP_LK TP_T SM0_LK SM0_T SM_LK SM_T THRO_PU PH_SPI_OV jonas Update /0 R.0 /0 R E_XIN E_XOUT PF U00 P0 FSK P FMISO FMOSI FSE# P PIN L0 P0 L P L PWM/P L PWM/P LPLK PWM/P LFRME# PWM/P LPRST#/WUI/P PWM/P SERIRQ PWM/P ESMI#/P ESI#/P RX/P0 0/P TX/P KRST#/P P WRST# RIN#/ PWRFIL#/KKOUT/LPRST#/P KSI0/ST# KSI/F# KSI/INIT# KSI/SLIN# KSI KSI KSI KSI KSO0/P0 KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/P KSO/K# KSO/USY KSO0/PE KSO/ERR# KSO/SLT KSO KSO KSO KSO/P KSO/P KK KKE PF0 PF PSLK/PF PST/PF PSLK/WUI0/PF PST/WUI/PF SMLK0/P SMT0/P SMLK/P SMT/P WUI/PF WUI/PF IT00EL 0 VSTY VSTY VSTY VSTY VSTY VSTY/PLL KMX LP FLSH ROM PS/ SMus N V V VSS VORE VSS VSS VSS VSS VSS VSS P0 TMRI0/WUI/P TMRI/WUI/P PWUREQ#/P RI#/WUI0/P0 RI#/WUI/P INT/P TH0/P TH/P L0HLT/WUI/PE0 WUI/PE WUI/PE WUI/PE PWRSW/PE WUI/PE LPP#/WUI/PE L0LLT/WUI/PE PIO P/I LKRUN#/WUI/PH0/I0 WUI/PH/I WUI/PH/I WUI/PH/I PH/I PH/I PH/I PI0 PI PI PI /WUI/PI /WUI/PI /WUI0/PI /WUI/PI PJ0 PJ /PJ /PJ /PJ /PJ O O O PWRLIMIT# PE0 NUM_LE# V_LERT# EPI EPI T0 T0 T0 T00 T0 PWR_LE#,0 H_LE# 0 H_FULL_LE# 0 L_L_PWM FN0_PWM TSEL_0 TSEL_ ME PRESENT PM_RSMRST# _IN_O# T_IN_O# PM_SUS# L_KOFF# FN0_TH PWR_SW# LI_SW#, PM_SUS# PM_LKRUN# H_EN SUS_E#,0,, SUS_E#,,,,0, P_LE# 0 SUS_PWR,, LL_SYSTEM_PWR VRM_PWR, PH_TEMP_ENLE PU_VRON, PM_PWROK VSET_E ISET_E PM_RSMRST# PWR_SW# 0 0.UF/V Update /0 R.0 Update /0 R.0 VRM_PWR LL_SYSTEM_PWR SUS_PWR 0 0.UF/V 0 0.UF/V LI_SW# 0 0.UF/V 0 0.UF/V 00 0.UF/V +V +V_E +VS +V_E E_ +V_E +V_E +VS +VS +VS +V_E For IT0 Power +V_E L00 00 /00Mhz 0.UF/V close to PIN JP UF/V 0.UF/V 0.UF/V RN00 _IN_O# 0KOhm RN00 T_IN_O# 0KOhm RN00 PWR_SW# 0KOhm RN00 LI_SW# 0KOhm Update /0 R.0 RN0 SM0_LK.KOhm RN0 SM0_T.KOhm RN0 SM_LK.KOhm RN0 SM_T.KOhm RN0 K_RST# 0KOhm RN0 0TE 0KOhm RN0 V_LERT# 0KOhm 0KOhm RN0 PH_TEMP_ENLE Update /0 R.0 For PU / P For E Reset FORE_OFF# RN0 TP_T.KOhm RN0 TP_LK.KOhm RN0.KOhm RN0.KOhm RN0 P_LE# 0KOhm RN0 NUM_LE# 0KOhm RN0 PWRLIMIT# 0KOhm RN0 0KOhm 00 0UF/.V close to PIN +VPLL JP UF/V +V JP E_ 0.UF/V close to PIN +V_E R0 0KOHM 00 TW R E_RST# 0 0.UF/V 00.UF/.V 00 0.UF/V E_ PM_SUS# 00KOhm PM_SUS# 00KOhm 00KOhm 00KOhm PM_RSMRST# R 0KOhm SUS_E# R0.KOhm SUS_E# R0.KOhm PU_VRON R 00KOHM VSUS_ON R 00KOHM For E Hardware Strap For imt pin name _PRESENT I/O ase ddress PM_S_STTE# S_STTE_ON Note: It can be programmable by E fireware PM_SLP_M# SLP_M_ON Share Memory E_WLN_PWR MP_PWR Note: It can be programmable by E fireware. _PRESENT LN_WOL_EN PP Enable +VM_P +.VM_+VMLK_P Note: efault Int. PullLow SUSPWR_K Update /0 R.0 For X'tal Note: load=.pf place close to E +V_E R0 0KOhm P0 E_XIN R0 E_XOUT R0 E_XIN 0MOhm X00.Khz If IT00 X and future version are used and internal clock is selected, please Mount R0 and R0 UnMount X00, 0, 0 0 PF/0V 0 PF/0V <Variant Name> SUSTeK OMPUTER IN. N lock iagram KF Thursday, November, 00 ate: Sheet of.0

23 TouchPad TP_L TP_R UF/0V +V_TP TP_L_SW TT_SWITH_P PF/0V TP_R_SW TT_SWITH_P PF/0V +VS R TP_LK TP_T TP_R TP_L FP_ON_P SIE 0 0 SIE TOUH_P 00 Keyboard onnector EMI Request K_ON SIE 0 0 SIE 0 0 KSO KSO KSO KSO KSO KSI KSI KSI KSI KSI KSI KSI0 KSI KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSO KSI KSI KSI KSI KSI KSI KSI0 KSI KSO KSO0 KSO KSO KSO KSO KSO KSO KSO KSO0 KSO KSO KSO KSO KSO KSI KSI KSI KSO KSI0 KSI KSI KSI KSO KSO0 KSO KSI KSO KSO KSO KSO KSO KSO0 KSO KSO PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V PF/0V N0 PF/0V N0 PF/0V N0 N0 PF/0V FP_ON_P 00 <Variant Name> SUSTeK OMPUTER IN. N lock iagram ustom KF ate: Thursday, November, 00 Sheet of.0

24 Main oard Thermal Policy PH_TEMP_EN R PH_TEMP_ENLE +VS Input (sensor) PU_OS#_O R0 0KOhm R0 +V R0 0KOhm UMKN Q0 FORE_OFF# Output (shut down),,,, UF_PLT_RST# Q0 UMKN +VTT_PU R0 RST_TRIP Q0 PMS0 Input (thermtrip) H_THRMTRIP# R0 OHM E +VSUSO +VS POWER OO ETETER PR0 00KOhm PR0 00KOhm PR0 00KOHM SUS_E#,, SUS_PWR P0 NWS SYSTEM_PWR Enable +VTT_PU_PWR +.V_PWR PL 00.VS_PWR PL 00 +VS SUS_E#,,,,0, O/ +VTT_PU_PWR, VRM_PWR PR Ohm +VS PR0 KOhm PR KOhm.KOHM PR PL 00 P0 H_VTTPWR LL_SYSTEM_PWR P0 NWS UMKN PQ0 PR0 0KOhm P0.UF/.V PQ0 UMKN FORE_OFF# TW 00KOhm PR0 TPT PT0 +VS Forceoff#_PWR_Thermal SUSTeK OMPUTER IN. N KF.0 Thursday, November, 00 ate: Sheet of

25 PU Thermal Sensor PU Thermal Sensor R00 0KOhm U0 PU_SENOR_SET SET V OT# HYST O/ Update /0 (R.0) 0TUF PU_OS#_O U0 under PU socket PU_SENSOR_HYST +VS_PUTM R R R % HYST=V : 0 degree HYST= : 0 degree +VS 0 0.UF/V PWM Fan Remove diode(+vs to ) for using wires PWM FN. 00 put besides J00. +VS +VS 00 0UF/.V + E00 UF/.V FN0_PWM FN0_TH 00 00PF/0V R00 0KOhm 00 00PF/0V FN SIE SIE WTO_ON_P 00000J SUSTeK OMPUTER IN ustom KF R ate: Thursday, November, 00 Sheet of.0

26 +VS Vout=0.*(+(.K/0.K)) +VS 0m 0.UF/V 0.UF/V lose to pin, P0 0UF/V /L_V R /L_V PU0 P_VSET EN N/SS/F VIN VOUT UPM00 /L_V PR0 0.KOHM % /L_V P0 /L_V 000PF/0V PR00 % /L_V.KOHM +VS_UIO PT0 TPT P0 0UF/.V P0 0.UF/V P0 0.UF/V P0 UF/V /L_V Place next to pin, _UIO 0 0UF/.V +VS +VS_MP L /00Mhz 0UF/.V UF/0V 0.UF/V Place next to pin, U 0 LQVR update /0 R.0 _UIO For EMI JP00 00 JP00 00 H_SPKL+ H_SPKL H_SPKR H_SPKR+ H_SPKL+ H_SPKL H_SPKR H_SPKR+ JP00 00 JP VS_MP +VS_UIO HNE 0 OHM _UIO _UIO Z_LK_U 0PF/0V OP_S# Z_RST#_U Z_SOUT_U Z_LK_U Z_SIN0_U Z_SYN_U Z_RST#_U 0 TW MP_P# Ohm R Z_SIN P_EEP +VS IPU 0 U V PIO0/MI_T PIO/MI_LK P# ST_OUT LK VSS ST_IN V_IO SYN RESET# PEEP LQVR SPIFO EP/SPIFO PV SPK_OUT_R+ SPK_OUT_R PVSS PVSS SPK_OUT_L SPK_OUT_L+ 0 PV V VSS Sense LINE_L LINE_R MI_L MI_R Sense JREF MONO_OUT MI_L MI_R LINE_L LINE_R 0 P N PVEE HPOUT_R HPOUT_L PVREF MI_VREFO_R 0 MI_VREFO MI_VREFO_L VREF VSS V _P _N _PVEE _UIO NLO MOT _PVREF_VMIREF MI_VREFOUT_R MI_VREFOUT V_LO_P VREF_OE +VS_UIO.UF/0V 0.UF/0V.UF/0V 0.UF/V _UIO _UIO MI_VREFOUT_R MI_VREFOUT update /0 R.0 R /L_V _PVREF_VMIREF _UIO R0 /L_V R /L_V V_LO_P 0UF/.V _UIO /L_V PIN,PIN MOIY MI_VREFOUT_L _J_MI R 0KOhm SENSE_ % MI_INT_L MI_INT_R _JREF R 0KOhm % MI_HP_R_ MI_HP_L_ UF/.V UF/.V _MI_HP_R _MI_HP_L INTERNL MI _UIO MI_INT_R UF/0V MI_IN_ MI_INT_L UF/0V 0.UF/V P EEP _UIO S_SPKR R S_SPKR P_EEP_ P_EEP.KOhm 0.UF/V R.KOhm <Variant Name> SUSTeK OMPUTER IN. N OE L KF Thursday, November, 00 ate: Sheet of.0

27 SPEKER FOR EMI UF/0V H_SPKR+_ON 00PF/0V /EMI H_SPKR+ H_SPKR H_SPKL+ H_SPKL H_SPKR+ H_SPKR H_SPKL+ H_SPKL R0 R R R UF/0V H_SPKR+_ON H_SPKR_ON H_SPKL+_ON H_SPKL_ON SPEKER_ON SIE SIE Wto_ON_P 0000P H_SPKR_ON H_SPKL+_ON H_SPKL_ON 00PF/0V 00PF/0V 00PF/0V /EMI /EMI /EMI HP and MI _J_MI MI_VREFOUT_L MI_VREFOUT_R _MI_HP_R _MI_HP_L R.KOhm OHM R OHM R R0.KOhm _MI_R_R _MI_L_R L0 L /00Mhz /00Mhz _MI_R_L _MI_L_L HP_MI 0 NP_N NP_N PHONE_JK_P R KOHM R KOHM 0 00PF/0V 00PF/0V 00PF/0V 000P _UIO Internal MI and MP +VS_UIO MI_VREFOUT MI_IN_ Q PMS0 R0 0OHM Q MMTL R00 00KOHM 00 UF/V R0.KOhm _SMI_L_ L /00Mhz _SMI_L_ E E 0.UF/V 0 UF/V R0.Ohm R0.Ohm R0 00KOHM R0 _UIO 0 0.UF/V Update /0 R.0 _UIO _UIO near LVS ON SUSTeK OMPUTER IN. N KF Thursday, November, 00 ate: Sheet of.0

28 KOhm R0 LN_REXT V LNXIN LNXOUT V RELX RF PH LN_N PH LN_P V PIE_TX_LN_P PIE_TX_LN_N PTXNX PIE_RX_LN_N PTXPX PIE_RX_LN_P 0.UF/V 0.UF/V V 0 U0 REXT VX XIN XOUT LX F VRE LKN LKP VH RXP RXN TXN TXP V V 0 0 VIN_ VIP_ V_ VIN_ VIP_ V VIN_ VIP_ V_ VIN_ VIP_ V LE LE0 VTX RSTN WKEN MP REQN SM_SL/LE R_N R_0N VO V VIO TESTN SM_S/R_LEN MIO MIO L_TRN L_TRP L_TRN L_TRP L_TRN L_TRP L_TRN0 L_TRP0 LN_LE T0 TPT LN_LE0 T0 TPT MIO0 MIO MIO VIO MIO MIO MIO MIO MIO VIO MIO MIO MIO0 MIO MIO S0 S S V S SM JMSLK R SLK 0 SWP V /EMI 0PF/0V S S SM SLK S0 S SWP: Internal Pulldown (IOL) SN: Internal Pullup (IH) SWP = Write protect SWP = 0 Writeable SN = No card SN = 0 ard inserted R_POWER_ON S_ON P_ P_ 0 S_SOKET_P 000N 0 SWP R_0N R_POWER_ON 0.UF/V R0 R0 MP UF_PLT_RST# V JMV0 0 0 UF_PLT_RST# 0 0.UF/V,,,, UF_PLT_RST# PIE_WKE# LKREQ_LN# PIE_WKE# MP LN_LE R_N R_0N V MIOR R_LEN R_POWER (>0mil) T0 TPT ard Insert: Pin.0 and Pin. are Shorted. ard not Insert: Pin.0 and Pin. are Opened. Write Protect: Pin. and Pin. are Opened. Write Enable: Pin. and Pin. are Shorted. +VSUS V +VSUS V JP0 RF 00 L0 RELX (>0mil).UH 0.UF/V (>0mil) V 0UF/.V 0 0.UF/V V 0 0.UF/V 0 0UF/.V 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V 0 0.UF/V R_POWER JP0 00 F0 0./V R_POWER_ON R_POWER_ON R0.KOhm R0.KOhm R_0N R_N 0KOhm RN 0KOhm RN 0KOhm RN 0KOhm RN SM SWP R0 KOhm MIOR _M_LN LNXIN Serial EEPROM V R Ohm 0PF/0V LNXOUT PF/0V X0 Mhz PF/0V 0.UF/0V V U0 0 V WP SL S T0NSHT R.KOhm R.KOhm LN_LE R_LEN SUSTeK OMPUTER IN. N LNR KF Thursday, November, 00 ate: Sheet of.0

29 Main oard, EI_LK_PH EI_LK,, EI_T_PH EI_T,, L_KEN_PH L_KEN,, L_VEN_PH L_VEN,, LVS_LLKP_PH, LVS_LLKN_PH LVS_LLKP, LVS_LLKN,, LVS_L0P_PH, LVS_L0N_PH LVS_L0P, LVS_L0N,, LVS_LP_PH, LVS_LN_PH LVS_LP, LVS_LN,, LVS_LP_PH, LVS_LN_PH LVS_LP, LVS_LN, SUSTeK OMPUTER IN. N _Neward KF Thursday, November, 00 ate: Sheet of.0

30 Main oard LP ebug Port, LP_0, LP_, LP_, LP_, LP_FRME# LK_EU +VS LP_0 LP_ LP_ LP_ LP_FRME# EU SIE 0 0 SIE ZIF_ON_P /EU 00S SUSTeK OMPUTER IN. N U_ebug KF Thursday, November, 00 ate: Sheet of 0.0

31 +VS +VS +VS L_VEN RN 00KOhm Q UMKN RN 00KOhm Q0 SIV LVS_+V_TE S Q UMKN 0 0.UF/V +VSL +VS_L L0 /00Mhz 0.UF/V 0 0UF/0V R0 UF/0V +VS_L PF/0V lose to connector LVS_+V_HRE RN 00KOhm LVS_+V_HR_TE S Q0 N00 L_L_PWM R L_L_PWM_ON LVS EI_LK EI_T,,,,0,, SUS_E# LI_SW# L_KEN L_KOFF# L L /00Mhz /00Mhz 0 TW 0 TW 0 00PF/0V LVS_EI_LK_ON LVS_EI_T_ON +VS_L 0 000PF/0V R0 KOhm L_EN RN 00KOhm 00PF/0V R0 KOhm L_EN_ON 000PF/0V update /0 r.0 L0 +VS LVS_LLKN 0 0PF/0V LVS_LLKP LVS_L0N LVS_L0P LVS_LN LVS_LP LVS_LN LVS_LP _UIO _SMI_L_ L0 _T_SYS PT0 PT TPT TPT /00Mhz /00Mhz 0.UF/V LVS_LLKN LVS_LLKP Max 0m R +VS NF0 amera 導入需 +VS R +VS UF/V LVS_+VS_EIP +VS_L LVS_EI_T_ON LVS_EI_LK_ON L_L_PWM_ON L_EN_ON US_M US_M+ _INV 0 0.UF/V 0 0 NP_N SIE SIE NP_N WTO_ON_ 0P 000 +VS update /0 r.0 amera US 0 VW_L US_M _SMI_L_ E00V0 US_PN US_PP RN0 RN0 US_M L0 /00Mhz US_M+ 0 VW_L US_M+ _UIO E00V0 SUSTeK OMPUTER IN. N Title LVS : & Inverter ON KF Thursday, November, 00 ate: Sheet of.0

32 Main oard RT_R RT_R_ LX0 RT_R_ON JP0 R0 0 0PF 0.0uH 0 0PF RT_ RT LX0 RT ON JP0 R0 0 0PF 0.0uH 0 0PF SU RT_ RT_HSYN RT_VSYN LX0 RT JP0 R R0 Ohm 0.0uH 0 0PF U0 HSYN_RT R0 Ohm Y RT_SW_+VS OE# V LVV R +VS U0 OE# V VSYN_RT R Ohm Y RT ON 0 0PF HSYN_ON PF/0V VSYN_ON RT_R_ON RT ON RT ON RE_RTN RE REEN_RTN REEN LUE_RTN LUE +V N 0 _SU_P 0V P_ P_ N S HSYN VSYN SL _T_ON HSYN_ON VSYN_ON _LK_ON _T_ON _LK_ON LVV PF/0V 0 R Ohm RT_R_ON RT ON +VS RT ON IP0Z E00V0 HSYN_ON 0 VSYN_ON 0 _LK_ON 0 0 _T_ON SUSTeK OMPUTER IN. N RT_Sub KF Thursday, November, 00 ate: Sheet of.0

33 , RT_VSYN_PH, RT_HSYN_PH RT_VSYN, RT_HSYN,, RT_R_PH, RT PH, RT PH RT_R, RT_, RT_, +VS 0 SS RT_+VS_ +VS _T_PH.KOhm RN _LK_PH.KOhm RN _T.KOhm RN _LK.KOhm RN _T_PH Q0 UMKN _T RX0 _T_ON _T_ON 0 PF/V +VS _LK_PH UMKN Q0 _LK RX0 _LK_ON 0 PF/V _LK_ON SUSTeK OMPUTER IN. N isplay Port KF Thursday, November, 00 ate: Sheet of.0

34 S Main oard Near ON J0 HMI_TXP RN0 /00Mhz L0 HMI_TXP_ON +VS F0 +VS_HMI_F 0./V SI0S Q0 +VS_HMI L0 +VS_HMI_ON /00Mhz HMI_TXN RN0 HMI_TXN_ON 0 0.UF/V +VS R 0KOhm 0 0UF/.V 0 0.UF/V HMI_TXP RN0 L0 /00Mhz HMI_TXP_ON 0.UF/V HMI_TXN RN0 HMI_TXN_ON HMI_TXP0 HMI_TXN0 HMI_LKP HMI_LKN RN0 /00Mhz L0 RN0 RN0 L0 /00Mhz RN0 HMI_TXP0_ON HMI_TXN0_ON HMI_LKP_ON HMI_LKN_ON +VS_HMI_ON HMI_SL_ON HMI_S_ON HMI_HP_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP_ON HMI_TXN_ON HMI_TXP0_ON HMI_TXN0_ON HMI_LKP_ON HMI_LKN_ON HMI_ON P_ 0 P_ 0 0 P_ P_ HMI_ON_P 0T SUSTeK OMPUTER IN. N TV_HMI KF.0 Thursday, November, 00 ate: Sheet of

35 Main oard +VS 0 UF/0V 0 0UF/.V 0 0.UF/V +VS hange to PS0 P0 P R.KOhm R0 0KOhm.KOhm R R0 0KOhm If using Parade PS0 Level Shifter, pin pin Recommended Equalization[P,P0]=00,d +VS TMS_HP TMS_TRLT TMS_TRLLK +VS P0 P R % Ohm R0 0KOhm R.KOhm 0 U0 V P0 P REXT HP S SL RT_EN# V PS0 0 OUT_+ OUT_ V OUT_+ OUT_ OUT_+ OUT_ V OUT_+ OUT_ IN_+ IN_ V IN_+ IN_ 0 IN_+ IN_ V IN_+ IN_ 0 TMS_TXP_PH TMS_TXN_PH TMS_TXP_PH TMS_TXN_PH TMS_TXP0_PH +VS TMS_TXN0_PH TMS_LKP_PH TMS_LKN_PH +VS.KOhm.KOhm.KOhm R R R HMI_N R 0KOhm N HMI_N N R 0KOhm V _EN R +VS HP_SINK 0 HMI_HP_ON S_SINK HMI_S_ON SL_SINK HMI_SL_ON V OE# OE#.KOhm RN.KOhm RN.KOhm R For PH From HMI on. Plug in HI. +VS_HMI OE# HMI_HP_ON +VS R0 0KOhm Q0 E PMS0 +VS TMS_TRLLK.KOhm RN TMS_TRLT.KOhm RN HMI_TXP HMI_TXN HMI_TXP HMI_TXN HMI_TXP0 HMI_TXN0 HMI_LKP HMI_LKN 0 0.UF/V SUSTeK OMPUTER IN. N TV_**** KF Thursday, November, 00 ate: Sheet of.0

36 Main oard SUSTeK OMPUTER IN. N FN_Fan & Sensor KF Tuesday, November 0, 00 ate: Sheet of.0

37 Main oard O O NP_N S S S S NP_N S S S S S S S S S S ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ML 0.0UF/V (00) XR 0% X0 0.0UF/V ML 0.0UF/V (00) XR 0% X 0.0UF/V ML 0.0UF/V (00) XR 0% X 0.0UF/V ML 0.0UF/V (00) XR 0% X 0.0UF/V ST_TXP ST_TXN ST_RXN ST_RXP NP_N NP_N P P P P P P P P P P P P T0 T0 0.UF/V 0 UF/.V +VS + E0 UF/.V ST_ON_P 00 H (st) H NP_N S S S S NP_N S S S S S S S S S S ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ ML 0.0UF/V (00) XR 0% X0 0.0UF/V ML 0.0UF/V (00) XR 0% X0 0.0UF/V ML 0.0UF/V (00) XR 0% X0 0.0UF/V ML 0.0UF/V (00) XR 0% X0 0.0UF/V ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 P P P P P P P P P P0 P P NP_N P P NP_N P P P P P P P P P P P0 P P P P P 0 0.UF/0V 0 0.UF/V 0 UF/.V +VS 0 0UF/0V + E0 UF/.V +VS ST_ON_P 0 SUSTeK OMPUTER IN. N X_H & O KF Thursday, November, 00 ate: Sheet of.0

38 Main oard US ports +V_US_ ombine power because these two ports are nearby. +V +V_US L0 /00Mhz F0./V R0.KOHM US_O0# + E0 UF/.V 0 0.UF/V US_P0 US_P0+ US P_ P_ 000 hange US PIN to R0 KOhm + E0 UF/.V 0 0.UF/V US_P US_P+ US P_ P_ update /0 r US_PP0 RNX0 US_P0+ /00Mhz LX0 US_PN0 RNX0 US_P0 0 I/O I/O +V_US_ V US_PP update /0 r.0 RNX0 US_P+ I/O I/O Z00S /00Mhz LX0 US_PN RNX0 US_P SUSTeK OMPUTER IN. N US_US Port * KF Thursday, November, 00 ate: Sheet of.0

39 H_PTH_V T_ON L_TRP0 L_TRN0 L_TRP L_TRN L_TRP L_TRN L_TRP L_TRN LK_PIE_WLN#_PH LK_PIE_WLN_PH PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN US_PN US_PP US_PN US_PP, LI_SW# SIE SIE NP_N NP_N SIE SIE SIE SIE H_V +V +.VS +VS +V_RT +V H_V_TE PWR_LE#,0 PWR_SW# US_O# LKREQ_WLN# WLN_ON UF_PLT_RST#,,,, +VSUS TO_ON_0P 0000 SUSTeK OMPUTER IN. N MINIR(WLN) KF Thursday, November, 00 ate: Sheet of.0

40 Main oard +VSUS harge LE ap. Lock LE WLN LE H_FULL_LE# H_LE# R0 0 H_LE HR_LE MER/REEN 00L00J +VS +VSUS R P_LER 0 R PWR_LER 0 P_LE REEN 00L00 PWR LE PWR_LE REEN 00L00 H LE P_LE# PWR_LE#, +VS R WLN_LER 0 WLN_T_LE WIFI_LE REEN 00L00 R0 00KOhm WLN_LEQ S Q0 N00 +VS R0 H_LER 0 H_LE ST_LE# REEN 00L00 SUSTeK OMPUTER IN. N LE_Indicator KF Thursday, November, 00 ate: Sheet of 0.0

41 Remove +.Vs is for TI FX Main oard +VS +VS +.VS +.VS +VTT_PH +VTT_PU +0.VS +VORE +VFX_ORE +V R0 R0 R0 R0 R0 R0 R R R R0 00KOhm +VS_ISHR +VS_ISHR +.VS_ISHR +.VS_ISHR +VTT_PH_ISHR +VTT_PU_ISHR +0.VS_ISHR +VORE_ISHR +VFX_ORE_ISHR MPWR_HR_EN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN Q0 UMKN,,,,0, SUS_E# Q0 UMKN +V +.V +V R0 R R0 00KOhm +V_ISHR +.V_ISHR PWR_HR_EN Q0 UMKN Q0 UMKN Q0 UMKN,0,, SUS_E# Q0 UMKN SUSTeK OMPUTER IN. N S_ischarge KF Thursday, November, 00 ate: Sheet of.0

42 Main oard attery onnector attery IN ETET For E pin protection, clamping=.v TT P_ 0 P_ TT_ON_P T_ON T00 T00 T0 T0 TON_SM_LK R00 TON_SM_T R00 TON_TS R UF/V T0 T0 T0 T0 00 T0 F.FU T0 T0 00 PF/0V 00 PF/0V For Q0Z0 rising time spec. 00 PF/0V SM0_LK SM0_T TS# TS# PR +V PR 00KOhm PR 00KOhm PQ UMKN PQ UMKN T_IN_O# P 000PF/0V update /0 r.0 SUSTeK OMPUTER IN. N _ & T onn. KF Thursday, November, 00 ate: Sheet of.0

43 Main oard LUETOOTH +VS +VS 0 0.UF/V T_ON 0 T_ON_ TW R0 0KOhm US_PP US_PN T0 T_Link_LE WTO_ON_P SIE SIE U0 000 SUSTeK OMPUTER IN. N T_luetooth KF Thursday, November, 00 ate: Sheet of.0

44 Main oard For PU H0 T H0 T H0 T H0 T H0 H H H H T _UIO H H H T H H H0 For 橢圓定位孔 H H H OX0OX0N H H H OX0OX0N H H 呼吸孔 H N SUSTeK OMPUTER IN. N ME_onn & Skew Hole KF Tuesday, November 0, 00 ate: Sheet of.0

45 Main oard Update EMI P 0 +VTT_PU +V +.V +VS _T_SYS +V +VS +VSUS 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V SUSTeK OMPUTER IN. N EMI KF Tuesday, November 0, 00 ate: Sheet of.0

46 daptor /_OK_IN 0W(V/.) EM0P0* _T_SYS M H:EM0N0V L:EM0N0V T T SP/.V/. _OK H_EN ISET_E VSET_E TSEL_0 TSEL IN_O# SWITH EM0P0 Switching _T_SYS Switch H_EN ISET_E VSUS_ON RT0*/ H:EM0N0V L:EM0N0V +VSUS +VSUS (./.) Linear VSET_E ELL_SEL0 SUS_E# EM0N0V +VS (./ ) urrent flow ELL_SEL Signal E VSUS_ON SUS_E# SUS_E# VR_ON SUS_PWR +V (0./ ) SUS_E# RT0*/ H:EM0N0V +VSUS UP0 EM0N0V SUS_E# UP.VS_PWR +V (0./ ) +.VS (/ ) +V (./ ) evice LL_SYS_PWR VRM_PWR VSUS_ON L:RJK0 SUS_PWR EM0N0V +VS (./ ) SUS_E# FORE_OFF# _IN_O# SUS_E# +VSUS UMN +V (0.0/0.0) harge pump +VTT_PU_PWR SUS_E# UMN +VS(0.0/0.0) VTT_PU_SEL SYSTEM_PWR RT0 H: RJK0* L: RJK0* +VTT_PU +VTT_PU (./ ) VTT_PU_SEL S +.V_SEL +.V_SEL VTT_PU_SEL VTT_PU_SEL +VTT_PH (/ ) +VORE_SEL +VORE_SEL VTT_PH_SEL SUS_E# EM0N0V +.VS (/ ) RT0 H: RJK0* +.V +.V (/.) VI(...0) PRSLVR PRSTP# SUS_E#.V_SEL.V_SEL L: RJK0* +.V_PWR SUS_E# UP +0.VS (/ ) PU PSI# LK_EN# P_MON VORE_SEL VORE_SEL RT H:RJK0* L:RJK0* LK_EN# I_MON +VORE (/.) VR_ON phase VRM_PWR VI(...0),PM_PRSLVR,PU_VRN,PSI# FX_VRON RT H: RJK0* L: RJK0* FX_PWR SYSTEM_PWR +VFX_ORE (/ ) VRM_PWR LL_SYS_PWR FORE_OFF# ST version :.g(0/0/) <Variant Name> SUSTeK OMPUTER IN Power_ FLOW ustom.0 Tuesday, November 0, 00 ate: Sheet of

47 S S S S PU0 RT0QW _T_SYS +V P0 UF/0V PL0 Irat= /00Mhz Power stage. I/P urrent: +VSUS Power stage. I/P urrent: +VSUS +VSUSO (./0.) +VSUS PJP0 MM_OPEN_MIL + PE0 00UF/.V PJP0 PJP0 PJP0 PL.UH Irat=. P 000PF/0V c00 PR Ohm P_+VSUS_SNU_S P_+VSUS_+VSUS_IN_S P0 0UF/V PQ0 EM0N0V 0.UF/V P0 PQ0 RJK0P00J0 P0 00PF/V PR0 0KOhm KOhm PR0 PR 0KOhm PR0 0KOhm P0 UF/V +V PU0 RT0QW P_+VSUS_YP_0 P_+VSUS_VO_0 0 P_+VSUS_F_0 P_+VSUS_ILIM_0 P_+VSUS_+VSUS_P_0 P_+VSUS_EN_0 P_+VSUS_H_0 P_+VSUS_PHSE_0 P 0.UF/V c00 P_+VSUS_OOT_0 P0 0UF/.V YP VOUT F ILIM POO EN UTE PHSE P_+VSUS_L_0 P_SUS_SEF_0 P_+VSUS_+VSUS_TON_0 N LO VIN N ENLO V TON REF OOT LTE PV SEF P LTE OOT 0 F ILIM VOUT SKIP# POO EN UTE PHSE P_+VSUS_+VSUS_REF_0 0 P_+VSUS_OOT_0 P_+VSUS_F_0 P_+VSUS_ILIM_0 P_+VSUS_VO_0 P_+VSUS_+VSUS_SKIPSEL_0 P_+VSUS_+VSUS_P_0 P_+VSUS_EN_0 P_+VSUS_H_0 P_+VSUS_PHSE_0 P0 0.UF/V c00 P0 UF/0V P_+VSUS_L_0 PR0 0KOhm PR0 0KOhm PR0 PR0 SUS_PWR,, KOhm P0 00PF/V P 0.UF/V.KOHM PQ0 P_+VSUS_+VSUS_IN_S EM0N0V PQ0 P_+VSUS_SNU_S P0 0UF/V c00 PJP0 PJP0 PL0 EM0N0V PR P 000PF/0V Ohm c00 r0_h.uh Irat=. + PE P UF/V UF/V (./.) PJP0 +VSUS MM_OPEN_MIL + PE0 00UF/.V PL0 _T_SYS Irat= /00Mhz +VSUSO I in = Vo*Io/( 0. * Vin) =.. Ripple urrent: I rip =. I spec=. pcs. ynamic: Ipeak=(vinvo)*/(L*Fsw)=. ESR / pcs =mohm V =.mv. Inductor Spec: I sat=0 I dc =. R= mohm. MOSFET Spec: Hside MOSFET: EM0N0V Rds(ON)= mohm (Vgs=. V) I cont = (T = ) I peak = (Pause <0 us) I in = Vo*Io/( 0. * Vin) =.0. Ripple urrent: I rip =.0 I spec=.. pcs ynamic: Ipeak=(vinvo)*/(L*Fsw)=. ESR / pcs = mohm V =.mv. Inductor Spec: I sat=0 I dc =. R= mohm. MOSFET Spec: Hside MOSFET: EM0N0V Rds(ON)= mohm (Vgs=. V) I cont = (T = ) I peak = (Pause <0 us) +VSUSO P 0.UF/V P P0 TSW P0 P 0.UF/V c00 P0 P_+VSUS_L_0 PT0 TPT +V PR P UF/0V PT0 TP_P_0 VSUS_ON PR PR MOhm P 0.UF/V P_+VSUS_OOT_0 P_+VSUS_OOT_0 P0 TW TPT TPT PT0 PT0 +VSUS TPT TPT PT0 PT0 TPT TPT PT PT +VSUSO TPT TPT PT PT Lside MOSFET: EM0N0V Rds(ON)= mohm (Vgs=. V) I cont = (T = ) I peak = (Pause <0 us) Lside MOSFET: RJK0P00J0 WPK Rds(ON)=. mohm (Vgs=. V) I cont = 0 (T = ) I peak = 0 (Pause <0 us) +VSUS 0.UF/V TSW 0.UF/V, VSUS_ON c00 PR MOhm P 0.UF/V +VSUS +VSUS TPT TPT PT0 PT0 +VSUSO TPT TPT PT PT ontroller +VSUS ontroller +VSUS P PF/0V PR 00KOhm PR KOhm +V +V PR0 00KOhm P_VE_EN_0 +V_E / 00m PU0 EN N/SS/F VIN VOUT P_VE_F_0 P 0PF/0V PR.KOhm P_VE_FJP_0 PJP0 PT TPT +VO TPT TPT PT0 PT0 TPT TPT PT0 PT. Voltage & urrent: +VSUS=.V. Frequency: fosc=khz. OP: Set PR0=0Kohm Iocp=.. Soft start time: Tss=ms.Inrush urrent: total = 00 uf I inrush= 0.. Voltage & urrent: +VSUS=V. Frequency: fosc=00khz. OP: Set PR=0Kohm Iocp=. Soft start time: Tss=ms 0.Inrush urrent: total = 00 uf I inrush= 0. P UF/0V P 0.UF/V UPM00 PR 0KOhm P 0UF/.V +VO TPT PT PJP0 TPT PT +V MM_OPEN_MIL SUSTek omputer IN Power_+SUS&+VSUS&+VSUS Size Project Name ustom KF Rev.0 Thursday, November, 00 ate: Sheet of

48 P0 NWS SYSTEM_PWR PR0 P0 0.UF/V Irat= PL0 +VTT_PU_PWR +VSUSO P0 UF/0V PR0.Ohm PR0 0KOhm % P_+VTT_PU_VOUT_0 P_+VTT_PU_V_0 P_+VTT_PU_F_0 PU0 bom PN: 000 P_+VTT_PU_TON_0 PU0 0 RT0PQW PU0 VOUT V F POO P_+VTT_PU_EN_0 TON EN/EM N OOT N P LTE RT0PQW P0 TW +VSUSO P0 P_+VTT_PU_OOST_0 UTE PHSE O 0 VP P_+VTT_PU_L_0 +VSUSO P_+VTT_PU_H_0 P_+VTT_PU_PHSE_0 P_+VTT_PU_O_0 P0 UF/0V 0.UF/V PJP0 PQ0 RJK0P00J0 PR0 PJP0 P_+VTT_PU_OR_0 KOhm PQ0 RJK0P00J0 S P_+VTT_PU_IN_S S S S PQ0 RJK0P00J0 PQ0 P0 000PF/0V c00 RJK0P00J0 P_+VTT_PU_SR_0 PR0 Ohm P0 0UF/V PL0 P0 0UF/V 0.UH Irat= PE0 P UF/V + 0UF/V c00 PE0 + 0UF/V /00Mhz PL0 Irat= /00Mhz + PE UF/V _T_SYS (./?) +VTT_PUO PJP0 PJP0 PJP0 MM_OPEN_MIL MM_OPEN_MIL PJP0 MM_OPEN_MIL MM_OPEN_MIL +VTT_PU +VTT_PH PR0 PJP0 0KOhm VTT_PU_SEL VTT_PU_SEL +VTT_PU % 0 0. % 0.0 Normal.0 +% PR0.KOhm PR KOhm 0PF/0V P0 PR KOhm UMKN PR PQ0 VTT_PU_SEL UMKN VTT_PU_SEL PR P 0KOhm 0.UF/V TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT TPT PT0 PT0 PT0 PT0 PT0 PT0 PT0 PT0 PT0 PT0 PT PT +VTT_PU +VTT_PUO PR.KOhm PQ0 P0 0.UF/V 0KOhm ontroller. Voltage & urrent: +VTT_PU:.0V0. Frequency: place to I Ton=.p*Rt(on)/Vin0=0.us Frequency=Vout/(Vin*Ton) =00KHZ. OP: P0 0.UF/V Set PR0=0KOhm Iocp=Rocp*0/Rds(on)=. Soft start time: SoftStar duration is.ms.inrush urrent: total = 0 uf I inrush= 0. Ipeak=. R=.mohm V=.mV. Inductor Spec: Hside and Lside MOSFET:RJK0P00JO WPK Rds(on)=.mOhm (Vgs=.V) Icont=0 (T=) Ipeak=0 (Pause<0us) <Variant Name> SUSTeK OMPUTER IN Power stage. I/P urrent: I in = Vo*Io/( 0. * Vin) =.. Ripple urrent: Iripple=.. ynamic: Isat=0 Idc= R=.mOhm. MOSFET Spec: Power_+VP ate: Thursday, November, 00 Sheet of.0

49 PU0 0 UP0U +VS +VSUSO SUS_E# P NWS PR P 0.UF/V P_+.VS_IN_S P_+.VS_VNTL_0 PR P P_+.VS_F_0 (/ ) TPT PT +.VS 0.UF/V +VS +.VS.VS_PWR,,,,0, SUS_E# P_+.VS_IN_S PL /00Mhz Irat= +VSUSO P_+.VS_VNTL_0 PU0 POK EN VIN NTL UP0U F VOUT REFIN P_+.VS_F_0 PR 0KOhm (/ ) TPT PT +.VS P 0.UF/V PU0 0 P0 0UF/.V PU0 POK EN VIN NTL UP0U F VOUT REFIN PR0 0KOhm P P 000PF/0V PR KOhm P 0UF/.V c00 P NWS PR P 0.UF/V PL /00Mhz Irat= PL /00Mhz Irat= P 0UF/.V PR P 000PF/0V PR.KOhm P 0UF/.V c00 UP0U <Variant Name> SUSTeK OMPUTER IN Power_+.V&+0.V ustom.0 Thursday, November, 00 ate: Sheet of

50 SUS#_PWR POWER SUS#_PWR POWER +.VO +VSUSO TPT TPT PT PT TPT TPT PT0 PT0 PQ S EM0N0V PQ0 S EM0N0V PR 00KOhm P 0.0UF/V ML/+/0% PR0 0KOhm TPT TPT PT0 PT TPT TPT PT0 PT0 P.UF/.V P0.UF/.V (/?) (./?) +.VS +VS +VSUSO TPT TPT PT PT PQ S EM0N0V P0 0.0UF/V ML/+/0% PR0 00KOhm % TPT TPT PT0 PT P0.UF/.V (./?) +V P0 0.0UF/V ML/+/0% +VSUSO +VSUS TPT TPT PT0 PT0,,,,, SUS_E# PQ0 S EM0N0V TPT PT0 P0 0.0UF/V ML/+/0% PQ0 K K E E K 0K UMN PR0 00KOhm % PR0 00KOhm % TPT TPT PT0 PT0 P0.UF/.V TPT PT0 (./?) +VS (0.0) +VS +VSUS,,, SUS_E# TPT PT PQ0 K K E E K 0K UMN PR0 00KOhm % +V (0.0) <Variant Name> SUSTeK OMPUTER IN Power_Load_ Switch ustom.0 Thursday, November, 00 ate: Sheet of 0

51 +VO PJP0 SL_JUMP PU_VRON, PJP0 SL_JUMP SUS_E#,,,,,0 PJP0 SL_JUMP SUS_E#,,0, PJP0 VSUS_ON, SL_JUMP PJP0 FX_VRON, SL_JUMP <Variant Name> SUSTeK OMPUTER IN Power_for_test ustom.0 ate: Thursday, November, 00 Sheet of

52 S S S S S S PM_PRSLPVR, PU_VRON VORE_SEL VORE_SEL VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI VORE_SEL LK_EN#, +VTT_PU VRM_PWR VORE_SEL +VS P_VORE_F_0 +VORE 0 0 VI00mV 0 PQ0 UMKN 0 PR 00 PSL0 PR0 0KOhm PSL0 PSL0 PSL0 PSL0 PSL0 PSL0 PSL0 PQ0 UMKN PR0 KOhm PQ0 UMKN VI0mV VI OHM PR 0KOhm % r00_h PR KOhm % r00_h VI+0mV P_VORE_V_0 P_VR_VI0 P_VR_VI P_VR_VI P_VR_VI P_VR_VI P_VR_VI P_VR_VI +VS PR0 KOhm PSL0 00 PQ0 UMKN P_VORE_MSET_0 0% % Normal +% PR 00KOhm % r00 0KOhm PR0 PR 0KOhm r00 +VS KOhm PR 0 PR P_VORE_TON_R PR0.Ohm r00_h PR0.KOhm I_MON TPT TPT TPT TPT TPT TPT TPT PT0 PT0 PT0 PT PT PT PT P_VORE_MSET_0 P_VORE_OSET_0 P0 UF/0V P_VORE_V_0 PR 0KOhm PR.KOHM P PJP0 PR0 P_VORE_R_0 P_VORE_VSEN_0 PM_PSI# VSSSENSE VSENSE PR KOhm N/ PR KOhm N/ PR0 KOhm N/ PR KOhm PR KOhm 0KOHM P_VORE_PRSLPVR_0 P_VORE_VRON_0 P_VORE_FS_0 P_VR_VI P_VR_VI P_VR_VI P_VR_VI P_VR_VI 0 0.0UF/V P 000PF/V PR KOhm N/ P 000PF/V +VTT_PU PU0 PJP0 P_VORE_POO_0 P_VORE_LKEN#_0 P_VORE_TON_0 P_VORE_ISEN_0 P_VORE_ISEN_N_0 POO 0 LKEN# V TON VRTT# NT OSET ISEN ISEN_N OOT PRSLPVR VRON FS M MSET VI RTQW VI VI VI VI VI VI0 PSI# OMP F VSEN R SOFT ISEN ISEN_N 0 P_VR_VI P_VR_VI0 P_VORE_PSI#_0 P_VORE_OMP_0 P_VORE_F_0 P_VORE_VSEN_0 P_VORE_R_0 P_VORE_SOFT_0 P_VORE_ISEN_0 P_VORE_ISEN_N_0 PR KOhm PR.KOhm P0 000PF/V PR0.KOhm P 0.0UF/V P0 0.UF/V P_VORE_TON_R P_VORE_OOT_0 UTE 0 PHSE P LTE PV LTE P PHSE UTE OOT P0 0.UF/V P PF/0V P PF/0V P_VORE_UTE_0 P_VORE_LTE_0 +VS P_VORE_LTE_0 P_VORE_UTE_0 P_VORE_OOT_0 PR PR 0 r00_h +VS P0 UF/0V c00 +VORE PJP0 P0 0.UF/V P 0.UF/V c00 P0 TW PR0 PU0 PQ0 RJK0P00J0 RTQW PQ0 RJK0P00J0 PQ0 RJK0P00J0 PQ0 RJK0P00J0 N/ PR0 Ohm P_VORE_SUR_0 P0 000PF/0V c00 P_VORE_PHSE_shape PQ0 RJK0P00J0 P_VORE_PHSE_shape PQ0 RJK0P00J0 P_VORE_SUR_0 PR Ohm P_VORE_IN_PHSE P0 PJP UF/V P0 UF/V PR0 P_VORE_ISEN_R_0 P0 P_VORE_ISEN_0 P_VORE_ISEN_N_0 P 000PF/0V c00 PJP P_VORE_ISEN_0 P_VORE_ISEN_N_0 P_VORE_IN_PHSE P_VORE_ISEN_R_0 PR P Power stage. I/P urrent: I in = Vo*Io/( 0. * Vin) =.. Ripple urrent: Iripple=.0 Vrip=.mV. ynamic: Ipeak= ESR=.mohm V=.mV. Inductor Spec: Idc=. Itemp=. R=.mOhm. MOSFET Spec: PL0 0.UH.KOhm Hside MOSFET: RJK0 Rds(on)=.mOhm (Vgs=.V) Icont=0 (T=) Ipeak=0 (Pause<0us). PU ML: *0uF UF/V lose to I PL0.KOhm 0.UH PE0 UF/V PE0 UF/V PJP0 _T_SYS Irat= PL0 /00Mhz Irat= PL0 Irat= 0.UF/V lose to I /00Mhz PJP0 PL0 /00Mhz Irat= PL0 /00Mhz () + PE0 0uF/V +VORE _T_SYS PT0 TPT PT0 TPT PT0 TPT PT0 TPT PT0 TPT PT0 TPT PT0 TPT + PE0 0uF/V Lside MOSFET: RJK0 Rds(on)=.mOhm (Vgs=.V) Icont= (T=) Ipeak=0 (Pause<0us) + PE0 0uF/V + PE0 0uF/V ontroller. Voltage & urrent: Vcore:.0V/. Frequency: M:Fsw=00*/RFS=00KHZ. OP: Vocset=*Ilim*Rsense Ilim=.*=. Slew rate: Slewrate=Iss/P0=00u/0nF=0mV/uS.Inrush urrent: total = 0 uf I inrush= 0..roop Resistance: Rdroop=R/R*0*Rsense=mohm PR PR PR PR KOhm KOhm KOhm KOhm N/ N/ N/ <Variant Name> SUSTek omputer IN. POWER_VORE Limy_li ustom KF Friday, November, 00 ate: Sheet of.0