JM50_R31_0822_4

Transcription

1 JM0 Ultrabook lock iagram Rev.0 VRM Page, L Panel PU nvidia NPL Page 0~ PE ep LV PU andy ridge Page ~ R MHz R O-IMM & Memory own Page ~ HMI Page Page HMI MI x FI 0 Miniard (HLF) WLN + T Touchpad Keyboard Page ebug onn. E NPEL FN Page 0 Page Page 0 LP PI ROM (M+M) Page PH Panther Point U.0 U.0 PIEx T Page 0~ 0 roadcom M0 Realtek RT0 Page Page 0 Miniard (FULL) (mt) Page igaln ardreader IN RJ Page Power +V_ORE +VFX_ORE ystem Page 0 peaker Page udio Jack (combo) Page zalia odec L ischarge ircuit Page Reset ircuit Page Page zalia & TT. onn. Page 0 kew Holes Page 0 MO amera Page luetooth U Port() Page Page U Port() Page harger Page 0 U Port() H O Page Page Page VTT R +.V +V +V_ORE harger etect Page Page Page Page Page Page Page Page 0 Page Load witch Page Power Protect Page -HW R iv.-n R ept. lock iagram Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

2 PH_PT PIO PH_PT PIO PIO 00 PIO 0 PIO [:] PIO 0 PIO 0 PIO 0 PIO 0 PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Use s ignal Name Internal & External Pull-up/down Power E NPEL E PIO P0 P P P P P P P P0 P P P P P P P P0 P P P P P P P P0 P P P P P P P PE0 PE PE PE PE PE PE PE PF0 PF PF PF PF PF PF PF P0 P P P PH0 PH PH PH PH PH PH PI0 PI PI PI PI PI PI PI PJ0 PJ PJ PJ PJ PJ Use s ignal Name M_U RE : M-us evice M-us ddress O-IMM x ( 0h ) O-IMM 0000x ( h ) PIE PIE PIE PIE PIE PIE PIE PIE T0 T T T T T N/ U 0 U Port () Minicard WLN N/ U U U Port () U.0 Port () U.0 U U Port () N/ U N/ LN U N/ N/ U N/ N/ U N/ U MO amera T H U WLN N/ U 0 ard Reader T O U N/ N/ U N/ N/ U N/ N/ ystem etting Joyoung_hianhg -HW R iv.-n R ept. JM0. Thursday, ugust, 0 ate: heet of

3 +VP +VP,,,0,,, +VP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN[:0] FI_TXP[:0] FI_FYN0 FI_FYN FI_INT FI_LYN0 FI_LYN +VP.Ohm % R00 P_OMP 0KOhm /LV R00 KOhm /ep R0 P_HP#_PH P_UXN_PH P_UXP_PH P_TXN0_PH P_TXN_PH P_TXP0_PH P_TXP_PH U00 M MI_RX#[0] P MI_RX#[] P MI_RX#[] P0 MI_RX#[] N MI_RX[0] P MI_RX[] P MI_RX[] P MI_RX[] K MI_TX#[0] M MI_TX#[] N MI_TX#[] R MI_TX#[] K MI_TX[0] M MI_TX[] P MI_TX[] T MI_TX[] FI_TXN0 U FI_TXN FI0_TX#[0] W FI_TXN FI0_TX#[] W FI_TXN FI0_TX#[] FI_TXN FI0_TX#[] W FI_TXN FI_TX#[0] V FI_TXN FI_TX#[] Y FI_TXN FI_TX#[] FI_TX#[] FI_TXP0 U FI_TXP FI0_TX[0] W0 FI_TXP FI0_TX[] W FI_TXP FI0_TX[] FI_TXP FI0_TX[] W FI_TXP FI_TX[0] T FI_TXP FI_TX[] FI_TXP FI_TX[] FI_TX[] FI0_FYN FI_FYN U FI_INT 0 FI0_LYN FI_LYN F ep_ompio ep_iompo ep_hp ep_ux# F ep_ux ep_tx#[0] ep_tx#[] E ep_tx#[] E ep_tx#[] ep_tx[0] ep_tx[] E0 ep_tx[] E ep_tx[] MI Intel(R) FI P PI EXPRE -- RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_OMP R00 %.Ohm PIEN_RXN[:0] 0 H PIEN_RXN J PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN 0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN H PIEN_RXN E PIEN_RXN K PIEN_RXN0 PIEN_RXP[:0] 0 K PIEN_RXP K PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP F PIEN_RXP PIEN_RXP PIEN_RXP H PIEN_RXP F PIEN_RXP K PIEN_RXP0 PIEN_TXN0 X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN H PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN0 K PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN J PIEN_TXN0 X0 0.UF/0V PIE_RXN H PIEN_TXN X0 0.UF/0V PIE_RXN M0 PIEN_TXN X0 0.UF/0V PIE_RXN F0 PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN J PIEN_TXN X0 0.UF/0V PIE_RXN0 F PIEN_TXP0 X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP E PIEN_TXP X00 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP0 K PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP E PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP0 X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K0 PIEN_TXP X0 0.UF/0V PIE_RXP 0 PIEN_TXP X00 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP X0 0.UF/0V PIE_RXP0 PIE_RXN[:0] 0 PIE_RXP[:0] 0 R. 0/0 E 0V HW R iv.-n R ept. PU()_MI,P,PE,FI Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

4 U00 +.V_VQ +.V_VQ,,0,,,,,0 H_N_IV# +VP H_PEI H_THRMTRIP# H_PM_YN H_PUPWR PM_RM_PWR 0KOhm UF_PLT_RT# T00 T00 Ohm % R00 H_PROHOT# Ohm N_R00_MIL_MLL R00 R00 R00 % N_R00_MIL_MLL R0.KOhm R00 TP_KTO#_R TP_TERR#_R H_PROHOT#_ R00 0V00000 H_PM_YN_R H_PUPWR_R VPWROO_R R. UF_PU_RT# F E PRO_ELET# PRO_ETET# TERR# PEI PROHOT# THERMTRIP# PM_YN UNOREPWROO M_RMPWROK REET# MI THERML PWR MNEMENT LOK R MI JT & PM LK LK# PLL_REF_LK PLL_REF_LK# LK_ITP LK_ITP# M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] PRY# PREQ# TK TM TRT# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] J H N N T0 F E N N L L J M0 L K E E H0 J J LK_EXP_P_R LK_EXP_N_R LK_P_P_R LK_P_N_R M_ROMP_0 M_ROMP_ M_ROMP_ LK_XP_ITP_P LK_XP_ITP_N XP_ebug XP_PRY# XP_PREQ# XP_TK XP_TM XP_TRT# XP_TI XP_TO R0 R0 R0 /LV R0 R0 R00 XP_REET# % % % XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM R00 T00 T0 /LV.Ohm 0 T00 T00 T00 T00 T00 T00 T00 T0 T0 T0 T0 T0 T0 T0 T0 T0 KOhm RN00 RN00 KOhm +VP /ep /ep PURMRT# LK_EXP_P LK_EXP_N LK_P_P LK_P_N R RM REET ystem Memory Impedance ompensation Huron River platform esign uide P. Table. Remove XP interface. 0VH VH V +V,0,,,,,,,,,0,,,,,,,,,0,,,,,,0,, +VU +VU,,,0,0,, +VP +VP,,,0,,, +V +V,,,,, R.0 PU/P for JT signals +VP XP_TM R0 Ohm XP_TI R0 Ohm XP_TO R0 Ohm XP_PREQ# R00 Ohm XP_TK R0 Ohm XP_TRT# R0 Ohm R0 E 0V R.0 0 andy ridge:r0 = 0 ohm (0V00000) Ivy ridge:r0 = 0 ohm (0V00000) PM_Y_PWR is the power good for +.V_VQ ifferent from EVERET R00 +VU PM_RM_PWR R0 N_R00_MIL_MLL R00 KOhm % +.V_VQ R0 0 %. Volt 0V00000 R0.KOhm % +VU 00 0.UF/0V U00 V Y Vcc=~. R0.KOhm RV-0 0.V/0m 00 0 UF/.V PM_PWROK,0, +.0V_PWR, R. R. add power reduction 0 VR_HOT# R0 If support power reduction with power good.. Mount U00, 00, 0, 00, R00, R0, R0, Unmount R00. hange R0 to kohm from 00ohm, change R00 to 0ohm from 0ohm - esign uide.0 page 0 R.0 0 Intel omments H_PROHOT# 00 PF/0V Q00 N00 THRO_PU THRO_PU 0 -HW R iv.-n R ept. PU()_LK,MI,JT Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

5 +.V +.V,,,,0, M Q[:0] M 0 M M M # M R# M WE# U00 M Q0 M Q _Q[0] J M Q _Q[] P M Q _Q[] L M Q _Q[] J0 M Q _Q[] J M Q _Q[] L M Q _Q[] L M Q _Q[] R M Q _Q[] P M Q0 _Q[] U M Q _Q[0] V M Q _Q[] R M Q _Q[] P M Q _Q[] T M Q _Q[] U M Q _Q[] M Q _Q[] M Q _Q[] M Q _Q[] M Q0 _Q[] M Q _Q[0] M Q _Q[] M Q _Q[] Y M Q _Q[] V M Q _Q[] R M Q _Q[] Y M Q _Q[] R M Q _Q[] M Q _Q[] U M Q0 _Q[] M Q _Q[0] M Q _Q[] M Q _Q[] R M Q _Q[] W M Q _Q[] M Q _Q[] M Q _Q[] R M Q _Q[] T M Q _Q[] Y M Q0 _Q[] M Q _Q[0] V M Q _Q[] M Q _Q[] Y M Q _Q[] M Q _Q[] U M Q _Q[] M Q _Q[] M Q _Q[] M Q _Q[] V M Q0 _Q[] P0 M Q _Q[0] P M Q _Q[] V M Q _Q[] T M Q _Q[] P M Q _Q[] P M Q _Q[] N M Q _Q[] N M Q _Q[] M Q _Q[] M Q0 _Q[] N M Q _Q[0] N M Q _Q[] M Q _Q[] K _Q[] _[0] F _[] _[] E _# _R# T _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] U V Y T0 U0 0 Y0 L M Q#0 R M Q# V M Q# T M Q# V M Q# Y M Q# T M Q# K M Q# J M Q0 R0 M Q Y M Q U M Q W M Q V M Q T M Q K M Q M 0 M E M M T M U M M T M Y M V M E M 0 0 M 0 M W M Y M U M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 T00 T00 T00 M IM0_#0 M IM0_OT0 M Q#[:0] M Q[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M 0 M M M # M R# M WE# U00 L _Q[0] L _Q[] N _Q[] R _Q[] K _Q[] K _Q[] N _Q[] R _Q[] U _Q[] T _Q[] V _Q[0] _Q[] U _Q[] R _Q[] Y _Q[] _Q[] E _Q[] _Q[] _Q[] F _Q[] F _Q[0] 0 _Q[] _Q[] E _Q[] F _Q[] E _Q[] E _Q[] E _Q[] E _Q[] _Q[] _Q[0] F _Q[] 0 _Q[] F _Q[] _Q[] F _Q[] _Q[] E _Q[] _Q[] E _Q[] F _Q[0] E _Q[] _Q[] Y0 _Q[] E _Q[] _Q[] _Q[] W _Q[] W _Q[] U _Q[] N _Q[0] N _Q[] U _Q[] U _Q[] N _Q[] R _Q[] K _Q[] L _Q[] _Q[] _Q[] M0 _Q[0] L _Q[] F _Q[] H0 _Q[] _[0] _[] T _[] V _# F0 _R# _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] Y R F E E T L V T0 K M V E E R K F E U0 0 V0 0 E0 E T V T U M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_#0 M IM0_# M IM0_OT0 M IM0_OT M Q#[:0] M Q[:0] M [:0] E 0V E 0V R.0 circuit: RM_RT# to memory should be high during R. add power reduction +.V R00 KOhm always support PWR Reduction Remove bypass R Q00 N00 R00, R_RMRT# KOhm PURMRT# R00 use k ohm esign uide 0. p0() lose to IMM,,0 RMRT_NTRL_PH R.0 / 00 0.UF/0V %.KOhm R00 -HW R iv.-n R ept. PU()_R Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

6 +VP +VORE +VP,,,0,,, +VORE,,0 U00F +VP +VORE E E E E E E F F F F F F F F H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 ORE UPPLY POWER PE N R ENE LINE VI QUIET RIL VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO_EL VPQE VPQE0 VILERT# VILK VIOUT V_ENE V_ENE VIO_ENE V_ENE_VIO F 0 J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 0 J J W W M N F N N +VIO_PU_F VP_EL 0 UF/.V H_PU_VILRT# H_PU_VILK H_PU_VIT V_ENE_R V_ENE_R 0 UF/.V 00 UF/.V 0 UF/.V R0 % R0 % R00 R0 0 UF/.V 00 UF/.V 0 UF/.V +VP lose to PU +VP 0 UF/.V 00 UF/.V 00 UF/.V +VP N_R00_MIL_MLL R00 % Ohm vx_c00_small +V +VP +VP +VP +VP 0V00000 R00 Ohm % P00 N_R00_0MIL_MLL P00 N_R00_0MIL_MLL +VP_ENE +VP_ENE 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 00 UF/.V VR_VI_LERT# 0 VENE VENE vx_c00_small 0 0UF/.V vx_c00_small 0 UF/.V vx_c00_small R0 0KOhm 00 0UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V vx_c00_small lose to VR VENE 0 VENE 0 vx_c00_small 00 0UF/.V vx_c00_small 00 0UF/.V vx_c00_small 0 UF/.V 0 UF/.V 00 0UF/.V P00 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V R00 00 UF/.V vx_c00_small 00 0UF/.V vx_c00_small.ohm % 00 0UF/.V VR_VI_LK 0 0 UF/.V +VP R.0 / lose to PU R00 % P00 lose to VR R00 % VR_VI_T 0 E 0V HW R iv.-n R ept. PU()_PWR Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

7 ecoupling guide from Intel P R0. +VFX_ORE uf * pcs 0uF * pcs uf * pcs +VFX_ORE uf * pcs 0uF * pcs uf * pcs(power request) +VP +.V +V +VP,,,0,,, +.V,,,,,0, +V +VFX_ORE raphics core voltage Voltage range: 0 -.V +.V +VFX_ORE +.V +.V,,,0, +VFX_ORE,0 +.V,,, +V_M_VREF +V_M_VREF 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 0 UF/.V U00 R Reference Voltage +V_M_REF 0mil +.V_VQ R. add power reduction 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V vx_c00_small 00 0UF/.V 00 UF/.V +V 0 0UF/.V vx_c00_small vx_c00_small V 0 0UF/.V VT_ENE VT_ENE PLL supply voltage ( + specification) vx_c00_small 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V vx_c00_small E00 0UF/V 0 0UF/.V vx_c00_small 0 UF/.V vx_c00_small 0 0UF/.V 0 UF/.V vx_c00_small 0 UF/.V 0 0UF/.V 0 vx_c00_small UF/.V P00 N_R00_0MIL_MLL P00 N_R00_0MIL_MLL 0 UF/.V 0 0UF/.V vx_c00_small 0 UF/.V MX:. T:. 0 UF/.V MX:0 vx_c00_small T: 0 0UF/.V 0 0UF/.V 0 UF/.V 0 0 E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y F L L N N0 N P P0 R R R U V V V V W0 VX VX0 VX VX M_VREF VX VX VX VX VX VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ0 VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ0 VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ0 VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX_ENE VX_ENE VPLL VPLL VPLL0 V V V V V V0 V V V V V V V V V V0 RPHI POWER ENE LINE.V RIL RIL ENE LINE QUIET RIL R -.V RIL VQ VQ0 VQ_ENE V_ENE_VQ V_ENE V_VI[0] V_VI[] Y J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 M N U0 +V_M_VREF V_EL0 V_EL hief River +V_M_VREF MX: hief River ecoupling guide from Intel (EE) +.V_VQ uf * 0pcs 0uF * pcs 0uF * pcs Filtered( Only) T00 T00 00 UF/.V vx_c00_small R00 0 UF/.V 0 0UF/.V R00 00 UF/.V 0 0UF/.V vx_c00_small +.V_VQ R00 KOhm R00 KOhm V_EL0 V_EL vx_c00_small V_ENE lose to PU 00 UF/.V 0 0UF/.V 0 0.UF/0V 00 UF/.V 0 0UF/.V vx_c00_small 00 UF/.V vx_c00_small +V_EL0 +V_EL L L H H 00 UF/.V 0 0UF/.V R., 0/0 0 0UF/.V vx_c00_small L H L H 0 UF/.V 00 UF/.V vx_c00_small 00 0UF/.V V 0.V 0.V 0.V 0.V 0 UF/.V 0 0UF/.V vx_c00_small >00 ns +.V_VQ 0 UF/.V JP00 MM_OPEN_MIL V_EL0 V_EL +VP +.V > 0 U_E# R.0 00 Intel omments Processor I/O supply voltage for R ( + specification) R. add power reduction E00 0UF/V R00 KOhm R00 KOhm IMX_VQ +.V_VQ +.V_VQ Power ood (U00 pin ) +0.V R00 KOhm R00 KOhm E 0V ecoupling guide for (EE) +V uf * pcs 0uF * pcs -HW R iv.-n R ept. PU()_FX_PWR Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

8 ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. PU()_. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. PU()_. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. PU()_. JM0 Joyoung_hianhg V U00H 0V E V U00H 0V E V V V V V V V V 0 V V0 V V00 V V V 0 V V V V0 V V V V V V V V 0 V V0 V V V 0 V V V E V E V F V F V F V0 F V F V F0 V F V F V F V F V F V F V F V 0 V V V V V V0 V H V H V0 J V J V J0 V J V J V J0 V J V J V J V J V0 J V J V K V K V L0 V L V L V L V L V L V L V0 L V0 L0 V0 L V0 L V0 L V0 M V0 M0 V0 M V0 M V00 M0 V M V M V0 M V M V M V M V M V N V N V N V0 N V N V N V N0 V N V N V N0 V N V P0 V0 P V P V P V R V R V R V R V R V R V R V0 T V T V T V T V T V T V T V U V U V U V0 U V U V U V V V V V V V V V V0 V V V V V0 W V W V W V W V Y V Y V Y0 V Y V Y V Y V0 Y V Y V Y V Y V Y V V V V V V V0 V V V V V V V V V0 V V V V 0 V V V V V V E V V NTF U00I 0V E V NTF U00I 0V E V V V V V V V V V0 V0 V V V 0 V 0 V V V0 V V V V V 0 V V V 0 V V V V E V E V0 E V E V E0 V F V F V F V F V F V0 F0 V F V V V V V H0 V H V H V0 H V H V H V H V J V J V J V K V K V K V K V0 L V L0 V L V L V L0 V L V L V L V L V0 P V0 P V0 P V0 P V0 P V0 P V0 P V0 R V0 R0 V0 R V00 R V T V T V T0 V T V T V T V T V T V0 U V U V V0 V V V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF E V_NTF E V_NTF V_NTF0 V_NTF V_NTF0 V_NTF V_NTF E V_NTF E V0 M V M V M V N V N V N V N V N V0 N V N V N0 V N V N V N V N V N V N V N V L V M V W V W V W V W V W V W V Y V0 Y V Y V Y V M

9 F strapping information: F[]: PIE tatic Numbering Lane Reversal- F[] is for the x - : (efault) Normal Operation, Lane # definition matches sockect pin map definition - 0: Lane Numbers Reversed F[]: Embedded isplayport etection - : (efault) isabled ; No Physical isplay Port attached to Embedded isplayport - 0: Enabled ; n external isplay Port device is connected to the Embedded isplay Port F[:]: PI Express Port ifurcation traps - : (efault) x - 0 : x, x - 0 : Reserved - 00 : x, x, x F[]: PE EFER TRININ - : (efault) PE Train immediately following xxreet de assertion - 0: PE Wait for IO training F F F F F R00 R00 R00 % KOhm % KOhm % KOhm Joyoung R.0 T0 T00 T0 T00 T0 T00 T0 T0 T00 T00 T00 T00 T00 T00 T00 T00 T0 T0 T0 T0 T0 R. 0/0 F0 F F F F F F F F F F0 F F F F F F F V_VL_ENE V_VL_ENE VX_VL_ENE VX_VL_ENE V_IE_ENE hief River R_WR_VREF0 R_WR_VREF0 PROEOR RIVEN Vref PTH W TUFFE Y EFULT: For ifim testing R0~ R0 close to pin < inch R. 0 R00 +VFX_ORE +VORE R_WR_VREF0 Q00 UMKN IMM0_VREF_Q VX_VL_ENE V_VL_ENE R0 0 % VX_VL_ENE,,0 RMRT_NTRL_PH R00 R0.Ohm % R0.Ohm % R_WR_VREF0 IMM_VREF_Q R0 % KOhm R00 R00 % KOhm % /ep KOhm T0 T0 0 H H K K F L F L H K H K F H K V T Y Y U U E E F E U00E F[0] F[] F[] F[] F[] F[] F[] F[] F[] F[] F[0] F[] F[] F[] F[] F[] F[] F[] V_VL_ENE V_VL_ENE VX_VL_ENE VX_VL_ENE V_IE_ENE RV RV RV RV RV RV RV RV RV RV RV0 RV RV RV0 RV RV RV RV RV0 RV RV RV REERVE RV RV RV RV RV RV RV RV RV RV RV RV RV RV RV RV RV RV0 _TET TET TET TET TET TET TET TET TET TET TET TET_E _TET_E _TET TET TET TET TET TET_E _TET TET_E _TET_ E N L L L M M U W P T K H M M N0 E E E E E 0V R00 R0.Ohm % R0.Ohm % % KOhm R0 0 % V_VL_ENE Q00 UMKN -HW R iv.-n R ept. PU()_RV Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

10 PU XP connector heck onnector PH XP connector -HW R iv.-n R ept. PU_PH_XP Joyoung_hianhg ustom JM0 ate: Thursday, ugust, 0 heet 0 of.

11 +VORE hief River ecoupling guide from Intel P R0. +VORE.uF * pcs uf * pcs vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small.uf/.v.uf/.v.uf/.v.uf/.v.uf/.v.uf/.v vx_c00_small vx_c00_small vx_c00_small hief River +VORE.uF * pcs uf * pcs (power request) UF/.V UF/.V UF/.V UF/.V 0 UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V 0 UF/.V UF/.V UF/.V -HW R iv.-n R ept. PU EOUPLIN Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

12 F_VREF_0_M F_VREF_Q0_M M IM0_LK_R#0 M IM0_LK_R0 M R# M # M WE# M M M 0 M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M Q M R# M # M WE# M M M 0 M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M Q M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M Q M R# M # M WE# M M M 0 M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M Q M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M Q M R# M # M WE# M M M 0 M R# M # M WE# M M M 0 M IM0_OT0 M 0 R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M R# M # M WE# M M M 0 M R# M # M WE# M M M 0 M IM0_OT0 M 0 M Q# R_RMRT# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M M M 0 M M IM0_OT0 M IM0_#0 M R# M # M WE# M IM0_KE0 M M M M M M M 0 M 0 M M M M M M M F_VREF_0_M F_VREF_Q0_M M M Q# M Q M M 0 M IM0_KE0 M IM0_LK_R0 M Q M Q#0 M Q M M WE# M M M M IM0_LK_R#0 M M M Q M Q0 M M M IM0_#0 M Q M M # M 0 M M M 0 M M M R# M Q M M IM0_OT0 M Q0 M R_RMRT# M Q M Q +0.V,, +.V,,,,0, M [:0] M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M R# M WE# M # M IM0_#0 M IM0_OT0 R_RMRT#, M Q#[:0] M Q[:0] M Q[:0] M [:0] +V_VREF_Q_IMM0, +V_VREF IMM0, +0.V +.V +.V +.V +.V +0.V +.V F_VREF_Q0_M F_VREF_0_M +0.V +.V +.V +.V +.V +.V +.V ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. R()_O-IMM0. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. R()_O-IMM0. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 -HW R iv.-n R ept. R()_O-IMM0. JM0 Joyoung_hianhg Memory own H Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near OIMM 0 place close to balls 0 Near Memory ontroller Follow design guide 0 /.. Place each cap close to each VrefQ or Vref ram all R. /0 RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V R 0V0000 0OHM R 0V0000 0OHM RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V R0 R0 RN0 Ohm RN0 Ohm U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/V 0.UF/V RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# R0 R0 R0 R0 RN0 Ohm RN0 Ohm 0 0.UF/0V 0 0.UF/0V RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# 0 UF/.V 0 UF/.V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# RN0 Ohm RN0 Ohm V PF/V V PF/V RN0 Ohm RN0 Ohm R 0V0000 0OHM R 0V0000 0OHM RN0 Ohm RN0 Ohm UF/.V UF/.V R0 R0 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm R0 R0 R0 R0 0UF/.V 0UF/.V RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V R0 R0 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# RN0 Ohm RN0 Ohm R0 R0 RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0UF/.V 0 0UF/.V U0 0V00000 EJ0E-J-F U0 0V00000 EJ0E-J-F Q0 Q Q Q Q Q Q# VREFQ E Q E Q E Q E R# F K F OT # K# KE VREF J V V V V V F V F V J V J V L V0 L V N V N V V V V V V K V K V M V M N N F N F N H N H J N # H WE# H REET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VQ VQ VQ VQ VQ VQ VQ VQ E VQ E M/TQ NU/TQ# RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm 0UF/.V 0UF/.V

13 +.V +.V,,,,0, +.V +.V Layout Note: Place these caps near O IMM +0.V +0.V +0.V,, + E0 +V +V_VREF IMM +V 0,,,,,,,,,0,,,,,,,,,0,,,,,,0,, +V_VREF IMM, 0UF/V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V UF/.V UF/.V UF/.V 0 UF/.V +V_VREF_Q_IMM +V_VREF_Q_IMM, M [:0] M Q[:0] +.V +.V M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# 0 0PF/0V 0PF/0V PLE LOE TO OIMM J0 M 0 M 0 M M M M M 0 M M M M 0 0 M 0/P M M /# M 0 M M IM0_LK_R 0 K M IM0_LK_R# 0 K# M IM0_LK_R0 0 K0 M IM0_LK_R#0 0 K0# M IM0_# R0 # M IM0_#0 0# M IM0_OT 0 OT M IM0_OT0 OT0 M WE# WE# M R# 0 R# M # R0 # M M 0 M M IM0_KE KE M IM0_KE0 KE0 +V R0 0KOhm 0 Mus lave ddress: H P0 0 take care if can't boot or issue M Q M Q[:0] M Q# Q M Q#[:0] M Q Q# M Q# Q M Q Q# M Q# Q M Q Q# M Q# Q M Q Q# M Q# Q M Q Q# M Q# Q M Q Q# M Q# Q M Q0 Q# M Q#0 Q0 0 Q#0 M 0 M M M should connect to directly M esign uide.0 P. () M M M M0 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0~ ~ ~ ~ ~ 0~ ~ ~ Layout Note: Place these caps near O IMM Reserve 0 0.UF/V T0 +V_VREF IMM +V_VREF_Q_IMM PM_EXTT#0_IM_.UF/.V.UF/.V 0 0.UF/V 0.UF/V 0.UF/V J0 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V EVENT# TET N N VREF VREFQ V V V V V0 V V V V V V V V V0 V V V V V0 V V V V V0 V V V V V0 V V V V V0 V NP_N NP_N VTT VTT VP 0 0.UF/V +0.V 0.UF/V Frank 00 VREF and VREFQ need to separate It follow EVERET and Intel spec. 0 0.UF/V +V.UF/.V,, M_LK_,, M_T_ P0 P0 R00 M_LK H R00 M_T H 0 00 L REET# 0 R_RMRT#, R_IMM_0P V0RM000 R_IMM_0P V0RM000 H:.mm PETRON OMPUTER IN R()_O-IMM Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

14 R Vref +.V +V_VREF IMM0 +V_VREF_Q_IMM0 +.V,,,,0, +V_VREF IMM0, +V_VREF_Q_IMM0, M: Fixed O-IMM VREF_Q +.V +V_VREF_R +V_VREF IMM0 R KOhm +V_VREF IMM +V +VU +V,,,,, +VU,,, +V +V,0,, 0 0.UF/V R KOhm R For R_VREF command & address. +.V efault M +V_VREF_Q_IMM0 R KOhm +V_VREF_Q_IMM R.0 R KOhm 0 0.UF/V IMM0_VREF_Q R0 IMM_VREF_Q M R0 M: Processor enerated O-IMM VREFQ New Requirement If support M :. Mount R0,R0,R0,R0,R0,R,0. Un mount R0,R0 -HW R iv.-n R ept. R()_/Q Voltage Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

15 R.-- PETRON OMPUTER IN VI ontroller Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

16 RT battery,0 T00 +RTT +RTT +V PR. R00 KOhm +V_RT 00 +RT_T V/0. 00 UF/0V +V_RT +V +V +VU_OR +V_RT, R.0 elete +RTT +V,,,0,,,,0,,, +V,,,,,,,,,0,,,,,,,,,0,,,,,,0,, +VU_OR,,,,,, +VTT_PH_VIO +VTT_PH_VIO, +V_RT RTRT# R delay should be ms~ms R00 % 0KOhm 00 UF/0V JRT00 L_JUMP Request by for MO clear function MO ettings lear MO Keep MO JRT00 hunt Open (efault) 00 PF/0V RT_X_ X00.KHZ P00 R00 0MOhm U00 R00 R00 MOhm % 0KOhm TPM ettings 00 UF/0V lear ME RT Registers Keep ME RT Registers Intel. esign uide, page 0 JRT00 hunt JRT00 L_JUMP Open (efault) INTVRMEN: Integrated U.0V VRM Enables Low: Enable External VRs High:Enable Internal VRs PH_INTVRMEN R00 % 00KOhm T0 00 T0 T0 +V_RT 00 Frank add 00 for EMI request, Z_LK_U Z_YN_U _PKR Z_RT#_U Z_IN0_U Z_OUT_U R. 0/ IO PF/0V T0 T0 0KOhm % R00 00 PF/0V T00 T00 T00 P00 P00 P00 P0 RT_X RT_X RT_RT# RT_RT# M_INTRUER# PH_INTVRMEN Z_LK Z_YN Z_RT# Remove TP Z_IN_U Z_IN_U Z_OUT R00 near R00 H_OK_EN# RREER_REET PH_JT_TK_UF K N L T0 K E N J RTX RTX RTRT# RTRT# INTRUER# INTVRMEN H_LK H_YN PKR H_RT# H_IN0 H_IN H_IN H_IN H_O RT IH H_OK_EN#/PIO H_OK_RT#/PIO JT_TK T LP T FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP E NN_PH_RQ#0 K NN_LP_RQ# V erial Interrupt Request M M P P M0 M P P0 H H 0 F F Y Y R.0 Y Y T0 T0 R.0 LP_0 0,, LP_ 0,, LP_ 0,, LP_ 0,, LP_FRME# 0,, INT_ERIRQ 0,, T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP T_RXN T_RXP T_TXN T_TXP H H O mt isolate schematic for Z _YN and OUT follow EIH T00 T00 T00 PH_JT_TM PH_JT_TI PH_JT_TO H K H JT_TM JT_TI JT_TO JT TIOMPO TIOMPI TROMPO Y Y0 T_OMP R00 %.Ohm +VTT_PH_VIO TOMPI T_OMP R0 %.Ohm +VTT_PH_VIO PI_LK T PI_LK TRI H RI_T R0 % PI_#0 PI_# PI_I PI_# Y T V PI_0# PI_# PI_MOI PI TLE# T0P/PIO P V T0P R0 0KOhm T_LE# T0 +V PI_O U PI_MIO TP/PIO P _IT0 OUR_POINT_E 0V R. /0 R.0 For JT to pull high and low. Remove JT schematic trap information: Pull High +V _PKR: No reboot strap Low: isable (efault) High:Enable _PKR R00 KOhm +V INT_ERIRQ R0 0KOhm Z_OUT:.Flash descriptor security: ampled Low: in effect. ampled High: override Z_OUT R0 KOhm +VU_OR T0P R0 0KOhm.Z_OUTwhich sample high on the rising edge of PWROK Will also disable Intel ME. Z_YN: On ie PLL VR voltage selector Low:.V (efault) High:.V note : R has no strap Hrron River Platform chematic esign hecklist (0 page ) Z_YN R0 KOhm VVRM use +.V in mobile +VU_OR PETRON OMPUTER IN PH()_T,IH,RT,LP Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of 0.

17 Frank 0_dd U.0 and ard Reader PIE and LKRQ Frank 0_dd PIE and LKRQ in Port. +V +VTT_PH_OR +VU_OR +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, +VTT_PH_OR,, +VU_OR 0,,,,,, Joyoung R.0 PIE_RXN_R PIE_RXP_R PIE_TXN_R PIE_TXP_R PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RXN_mT PIE_RXP_mT PIE_TXN_mT PIE_TXP_mT UF/V 0.UF/V 0.UF/V 0.UF/V PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_WLN_ PIE_TXP_WLN_ J V U E F Y J V U U00 PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp MU MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T E H EXT_I# L RMRT_NTRL_PH_R R ML0_LK ML0_T R.0 / /NON_ EXT_I# 0, L RMRT_NTRL_PH,,0 T T LK_UF_PYLK_N RN0 0KOhm LK_UF_PYLK_P RN0 0KOhm LK_UF_EXP_N RN0 0KOhm LK_UF_EXP_P RN0 0KOhm LK_UF_OT_N RN0 0KOhm LK_UF_OT_P RN0 0KOhm LK_UF_K_N RN 0KOhm LK_UF_K_P RN 0KOhm LK_UF_REF R 0KOhm LOK TERMINTION for FIM efault power-on mode is I. PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN R. remove /nimt remark LK_PIE_R# LK_PIE_R 0 T0 T0 T0 T0 T0 T0 T0 T0 P P 0.UF/V 0.UF/V LK_REQ0# PIE_TXN_LN_ PIE_TXP_LN_ PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_U0_ PIE_TXP_U0_ F E Y H Y J U V 0 J0 Y0 0 E W Y Y0 Y J PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp LKOUT_PIE0N LKOUT_PIE0P PI-E* 00MHz PIELKRQ0#/PIO LKOUT_PIEN 00MHz LKOUT_PIEP LOK ontroller MLLERT#/PHHOT#/PIO MLLK/PIO MLT/PIO L_LK Link L_T L_RT# PE LKRQ#/PIO 00MHz LKOUT_PE N LKOUT_PE P 00MHz LKOUT_MI_N LKOUT_MI_P E M M T P0 M0 V U MLLERT# ML_LK ML_T LK_REQ_PE_# LK_PIE_PE#_PH_L LK_PIE_PE_PH_L R0 R0 N_R00_0MIL_MLL N_R00_0MIL_MLL R.0 ML_LK ML_T LKREQ_PE# 0 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 LK_EXP_N LK_EXP_P To E R.0 /0 R.0 / R. RM reset TRL +VU_OR EXT_I# R 0KOhm L_ RN0.KOhm _ RN0.KOhm RMRT_NTRL_PH_R R0 0KOhm ML0_LK RN0.KOhm ML0_T RN0.KOhm ML_LK RN0.KOhm ML_T RN0.KOhm MLLERT# R 0KOhm **UNTUFF** LK_PIE_mT#_PH LK_PIE_mT_PH LK_PIE_WLN#_PH LK_PIE_WLN_PH LK_REQ_mT# LK_REQ_R# LK_REQ_WLN# LK_PIE_LN# LK_PIE_LN LK_REQ_LN# P0 P0 P0 P0 P P R0 /NON_mT P0 P0 P0 T T LK_REQ# LK_REQ# LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ_PE_# T T T LK_PH_R_N LK_PH_R_P LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# M V0 Y Y Y Y L V V L 0 E V0 V T PIELKRQ#/PIO 0MHz LKOUT_P_N LKOUT_P_P LKOUT_PIEN 00MHz LKOUT_PIEP 00MHz LKIN_MI_N PIELKRQ#/PIO0 LKIN_MI_P LKOUT_PIEN 00MHz LKIN N LKOUT_PIEP LKIN P PIELKRQ#/PIO OUR_POINT_E MHz LKIN_OT_N LKIN_OT_P LKOUT_PIEN 00MHz LKOUT_PIEP 00MHz LKIN_T_N PIELKRQ#/PIO LKIN_T_P.MHz LKOUT_PIEN 00MHz REFLKIN LKOUT_PIEP MHz PIELKRQ#/PIO LKIN_PILOOPK LKOUT_PE N 00MHz XTL_IN LKOUT_PE P XTL_OUT PE LKRQ#/PIO XLK_ROMP LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO M M F E J0 0 E K K K H V V Y LK_P_N LK_P_P LK_UF_EXP_N LK_UF_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P LK_UF_OT_N LK_UF_OT_P LK_UF_K_N LK_UF_K_P LK_UF_REF XTL_IN XTL_OUT XLK_OMP R0 0.Ohm LK_P_N LK_P_P LK_PI_F +VIFFLKN MOhm R Joyoung R.0 modify LK_REQ -MHz is required in:. FIM. TM for PH isplay lock gereration in Integrated raphics platforms P 0 0PF/0V X0 MHZ 0 XTL_OUT_ 0PF/0V PH LKREQ etting: Not connected to device. R.0 0 +VU_OR LK_REQ0# R0 0KOhm **UNTUFF** LK_REQ# R 0KOhm **UNTUFF** LK_REQ# RN0 0KOhm LK_REQ_PE_# RN0 0KOhm LK_REQ# R 0KOhm **UNTUFF** onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +V Eric Fang to lan hien on //00 LK_REQ# Remove XP. V V K K K LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO LKOUT_ITPXP_N 00MHz LKOUT_ITPXP_P 0V FLEX LOK LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO K F H K R.0 / YRM00 YRM0 YRM0 YRM0 R.0 Modify RM trap PIN +V +V +V +V LK_REQ# LK_REQ# LK_REQ# LK_REQ# R R R R 0KOhm 0KOhm +VU_OR 0KOhm 0KOhm Joyoung R.0 add PIO Table for on board RM trap. On oard RM etting PIO PIO PIO PIO XXXX On oard RM etting No on board RM Micron MHz Elpida MHz Elpida MHz 00 Micron MHz Hynix MHz T ommon efinition MHz ommon efinition 00MHz 0 Elpida 00MHz R 0KOhm R 0KOhm R 0KOhm / R 0KOhm / R 0KOhm /E R 0KOhm /M\H R 0KOhm /M\00 R 0KOhm /E\H YRM00 YRM0 YRM0 YRM0 LK_REQ_PE_# R0 0KOhm LK_REQ_PE_# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm PH()_PIE,LK,M,PE Joyoung_hianhg PETRON OMPUTER IN JM0. Thursday, ugust, 0 ate: heet of

18 +VU_OR +VU_OR 0,,,,,, +V +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, U00 +VTT_PH_OR +V +VTT_PH_OR, +V,0,,,0,,,,0,,, MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP E0 0 E 0 J J0 W W0 V Y Y0 Y U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT J Y E H J 0 F E J0 H W FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT +V_RT +VU +VU +VU +V_RT 0, +VU,,,0,0,, +VU,,, +VU,,, J MI_ZOMP FI_FYN0 V FI_FYN0 +VTT_PH_OR R0 %.Ohm MI_OMP_R MI_IROMP FI_FYN 0 FI_FYN R0 % RI_PY H MIRI FI_LYN0 V FI_LYN0 FI_LYN 0 FI_LYN Remove UK#. R.0 dd XP_REET# dd ME_PWROK.,0, PM_RMRT# has pull down 0k ohm in E PM_PWROK Y_PWROK PM_YRT#_R R0 0 ME_PWROK R PM_PWROK_R L0 N PWROK ULK/PIO ULK 0 0 PM_RM_PWR 0 PM_RMRT# ME_UPWRNK R.0 0 PM_PWRTN# dd PM_PWRTN#_R 0 0 UK# +V ME PREENT T0 T0 R U_PWR_K_R /NON_ R0.V/0. 0 R. 0/ R R R / R 0KOhm R. 0/ R. 0/ TLOW# RI# UK#_R PM_RMRT_R U_PWR_K_R K P L K E0 ystem Power Management WOVREN PH_PROK PIE_WKE# PM_U_TT# LP_# R 00KOhm % R 00KOhm % R. 0/ R R R. 0/ _PREENT_R H0 LP_W#_R R PREENT/PIO LP_U# E0 0 UK# Y_REET# Y_PWROK PWROK RMPWROK RMRT# UWRN#/UPWRNK/PIO0 PWRTN# TLOW#/PIO RI# WVRMEN PWROK WKE# LKRUN#/PIO U_TT#/PIO LP_#/PIO LP_# LP_# LP_# PMYNH LP_LN#/PIO E N 0 H F 0 P K R +V_RT WOVREN - On ie W VR Enable HIH - Enabled(EFULT) ; LOW-isabled /NON_ PM_RMRT_R E_RT# 0, / R. IO, 0/ LN_WKE# 0, T0 T0 PM_LKRUN# 0, PM_U# 0 PM_U# 0 R.0 ME_PM_LP_M# 0 LP_U# 0, H_PM_YN R.0 ME_PM_LP_LN# 0 R.0 0V OUR_POINT_E Y_PWROK for PH R. Remove some P in P +VU PM_PWROK U0 V ELY_VR_N_LL_Y Y Vcc=~. Y_PWROK +VU_OR RI# R 0KOhm R.0 TLOW# PIE_WKE# R 0KOhm R KOhm R.0 +V PM_LKRUN# R0 0KOhm ME_PM_LP_M# R 0KOhm PM_PWROK R 0KOhm ME_UPWRNK R 0KOhm R. /0 ME PREENT R 0KOhm ME_PM_LP_LN# R 0KOhm PETRON OMPUTER IN PH()_FI,MI,Y PWR Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

19 +V +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, +V L_KEN_PH L_VEN_PH P0 P0 J M U00 L_KLTEN L_V_EN VO_TVLKINN VO_TVLKINP P P L_TRL_LK.KOhm RN0 L_TRL_T.KOhm RN0 EI_LK_PH.KOhm RN0 EI_T_PH.KOhm RN0 Pull up.k ohm in bus for LV. Remove LV net name and add port. L_KLT_TRL EI_LK_PH EI_T_PH R.0 R0 R0 LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH P0.KOhm L_TRL_LK L_TRL_T LV_I LV_V LV_VREF P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV igital isplay Interface VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y isplay Port isplay Port VO R0 % KOhm N P T T M0 M M T T RT_LUE RT_REEN RT_RE RT LK RT T RT_HYN RT_VYN _IREF RT_IRTN RT P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M T T H F E F E J HMI LK_PH HMI T_PH HMI_HP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN0_PH HMI_TXP0_PH HMI_LKN_PH HMI_LKP_PH isplay Port OUR_POINT_E 0V RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE RT_HYN,RT_VYN. -kω ±0.% pull-down to : _IREF. onnected to : RT_ITRN. onnect to +V.: V isplay Port isable: (For discrete graphic). N: LL LV isable: (For discrete graphic). N: LV_T [:0], LV_T# [:0], LV_LK, LV_LK#, LV_T [:0], LV_T# [:0], LV_LK, LV_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to : VccLV,VccTX_LV PETRON OMPUTER IN PH()_P,LV,RT Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

20 +V +VU +V +VU,,,0,0,, +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, V_PWRON R +VU Frank P0 is removed in EIH. T_O_# has short pin in EIH. **UNTUFF** R. add Zero Power O **UNTUFF** **UNTUFF** R +V R R R R U0 V Y NLV0KR PU_HOL_RT# PU_PWR_EN PU_PWR_EN is active high 0KOhm 0KOhm 0KOhm 0KOhm R0 0KOhm R U_E# 0,,, MP_PWR_TRL# T_O_# EXTT_NI_RV0_PH EXTT_NI_RV_PH PU_PWR_EN PU_PWR_EN U_RX_N U_RX_N U_RX_P U_RX_P U_TX_N U_TX_N U_TX_P U_TX_P T_O_# P0 P0 +V R00 T0 R00 PU_PWR_EN_R T0 R.0 00 T0 R. 00 T0 T0 T0 T R0 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 KOhm U_RX_N U_RX_P U_TX_N U_TX_P INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PU_HOL_RT#_R PU_ELET# _IT PU_PWM_ELET# TP_OVR MP_PWR_TRL# T_O_# EXTT_NI_RV0_PH EXTT_NI_RV_PH PI_PME# J H J H H K K N0 H H M M Y K L M0 Y 0 E 0 E J 0 E0 F 0 V U Y0 0 U Y V W0 K0 K H E0 E F 0 K0 U00E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP RV U0 port RXN TP U0 port RXN TP U0 port RXN TP U0 port RXN TP U0 port RXP TP U0 port RXP TP0 U0 port RXP TP U0 port RXP TP U0 port TXN TP U0 port TXN TP U0 port TXN TP U0 port TXN TP U0 port TXP TP U0 port TXP TP U0 port TXP TP U0 port TXP TP0 PIRQ# PIRQ# PIRQ# PIRQ# REQ#/PIO0 REQ#/PIO REQ#/PIO NT#/PIO NT#/PIO NT#/PIO PI OUR_POINT_E PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PME# U RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP0N UP0P UPN UPP UPN UPP UPN UPP URI# URI Y V U T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 0 E0 0 0 L K E NV_ROMP U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_I +V +VU_OR +V +.V R T T +V,,,, +VU_OR 0,,,,,, +V,,, +.V,,,,0, 0 R. 0 R. U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN0 U_PP0 U_PN U_PP : R=. ohm for E. R T T T0 T % %.Ohm.Ohm U PORT U P00 U P0 U P0 U P0 U P0 U P0 U P0 U P0 U P0 U P U P U P +VU_OR Touch Panel External.0/.0 External Main External Main T Mini PIE (mt) ebug Port amera WiFi 0 LK_TPM LK_PI_F LK_KPI_PH LK_EU PLT_RT# :R0=00ohm for E. Ohm Ohm Ohm Ohm T0 R R0 R0 R LK_TPM_R LK_PI_F_R LK_KPI_PH_R LK_EU_R LK R H H J K H0 PLTRT# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI MHz O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO K0 L O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 Remove O# to XP. 0 0PF/0V 0 0PF/0V Reserved for Wireless team 0V R R /HRU0 Place within 00 mils of PH R /RU0 U_O# R. add O# pin for add U port U_O# R U_O0# _IT0,_IT : oot IO trap oot IO trap _IT _IT0 0 0 oot IO Location LP TP_OVR: swap override trap/ Top-lock swap override jumper Low=Enabled swap override/ Top-lock swap override **UNTUFF** **UNTUFF** PU_PWM_ELET# PU_ELET# PU_HOL_RT#_R PU_PWR_EN_R R0 0KOhm R 0KOhm R 0KOhm R KOhm +V U0 V +V This ignal has a weak internal pull-up. 0 _IT0 _IT0 0 0 Reserved (NN) Reserved PI (PH) ampled on rising edge of PWROK. R KOhm High=efault TP_OVR R KOhm PLT_RT# Y Vcc=~. 0V R R 0KOhm UF_PLT_RT#,0,,,,,0 _IT R.0 dd _IT signal. R KOhm PETRON OMPUTER IN PH()_PI,NVRM,U Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

21 +V +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, +VU +VU,,,,0,0,, +VU_OR +VU_OR 0,,,,,, +V +V R.0 TPN_INT# Remove RIT_PH_PIO0_R to XP JM0_T 0/0 /TPN R T0 PIO0 PIO PU_HP_INTR# PIO T H E U00F MUY#/PIO0 TH/PIO TH/PIO TH/PIO TH/PIO TH/PIO TH/PIO0 TH/PIO 0 0 T_O_PWRT T0 T0 T0 R. add Zero Power O T_O_PWRT **UNTUFF** **UNTUFF** **UNTUFF** R.0 / /HR_IO R 0KOhm R 0KOhm / dd PM_LNPHY_EN dd HOT_LERT#_R. LN_LPWR 0, EXT_MI# P0 P0 R00 U0_EXT_MI# PM_LNPHY_EN HOT_LERT#_R PU_PRNT# 0 U PIO LN_PHY_PWR_TRL/PIO PIO TP/PIO 0TE PEI RIN# P U P R. /0 Frank 000 H_THRMTRIP# is not connected pull up resister but EIH does not. H_PEI_R R Ohm R 0TE 0 H_PEI H_PEI_E 0 RIN# 0 /R R 0KOhm R 0KOhm /NON_ P_I0 P_I PU_PWROK has 00 ms software delay, no hardware delay requirement Reserve PH_PIO dd T_O_PRNT#_R and FI_OVRVLT., PU_PWROK T PU_PWROK O_ON R.0 00 R. hange WLN_ON to WLN_ON_PH R Frank 0, RF_ON 0 EE define PIO for ROOM LN chip. T0 T_O_PRNT#_R R. add Zero Power O T_PWR_EN#_R R.0 / O_ON WLN_LE PIO WLN_ON_R TP_PI# T_O_PRNT#_R FI_OVRVLT P_I0 P_I 0 T E E P K K V M N M TH0/PIO LOK/PIO PIO/MEM_LE PIO PIO TP_PI#/PIO PIO TP/PIO TP/PIO LO/PIO TOUT0/PIO PIO PU/MI PROPWR THRMTRIP# INIT_V# F_TV T_V T_V T_V T_V N_ Y Y0 T Y H K H0 K0 P PM_THRMTRIP# INIT_V# NV_LE % R T0 R0 KOhm T ignal isable uideline T_V[:] should pull down to esign uide 0. () R0.KOhm +.V H_PUPWR H_THRMTRIP#, R.0 H_N_IV# 0,, T_ON T_ON R V TOUT/PIO Vss_NTF **UNTUFF** **UNTUFF** **UNTUFF** EXT_MI# U0_EXT_MI# PM_LNPHY_EN O_ON Joyoung R.0 mount if suppot O RIN# has pull high at E side PU_HP_INTR# PU_PWROK R R R R R R KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm +VU_OR +V dd RIT_TEMP_REP#_R. R.0 Intel omments Joyoung R.0 Joyoung R. remove /nimt remark R.0 R. 0/ T PH_LERT# T T_LE Frank R NO T module, but the PIO control pin will conntact to page. It supports combo card. Frank 00 No WLN LE,so PIO pin change test point Frank 00 RIT_TEMP_REP#_R change net name RIT_TEMP_REP# and contact to E(follow I0) Frank 0 Remove T_ET#_R to XP Frank 0 Remove PLL_OVR_EN and T_PWR_EN#_R to XP Frank 0 Remove FI_OVRVLT to XP Frank 0 Remove RIT_TEMP_REP#_R to XP V E E F F TP/PIO PIO Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF H H J J J J J J E E F F Unused PIO OUR_POINT_E 0V PIO0 R 0KOhm **UNTUFF** **UNTUFF** TP_PI# WLN_LE PIO #0 hecklist PU_PWROK PIO R 0KOhm R 0KOhm R 0KOhm R0 0KOhm 00KOhm R JM0_T 0/ +V +V R % KOhm FI_OVRVLT FI TERMINTION VOLTE OVERRIE - PIO (FI_OVRVLT) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT R0 00KOhm MI TERMINTION VOLTE OVERRIE - PIO (T_O_PRNT#) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT T_O_PRNT#_R R 00KOhm R0 0KOhm Joyoung R.0 +V R. add Zero Power O PU_PRNT# PU_PRNT# R /UM 0KOhm R 0KOhm WLN_ON_R R KOhm PLL ON IE VR ENLE HIH - ILE (EFULT) LOW - ENLE Joyoung R.0 for IO detect Panel +V PIO PIO R R /LV /ep 0KOhm 0KOhm PETRON OMPUTER IN PH()_PU,PIO,MI Joyoung_hianhg JM0 Thursday, ugust, 0 ate: heet of.

22 +.0V,,, +VTT_PH_VIO 0, +VTT_PH_OR, +.V,,,0, +.V,,, +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, +VP,,,,0,,, +VFI_VRM +V_V_ +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO +VTT_PH_VIO +V_V +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR +VFI_VRM +.V +V_V_IO +VM_VPPI +VIO_PU_V_MI +.0V +VTT_PH_OR +VFI_VRM +V +V_NVRM_VPNN +.V +.0V +VTT_PH_VIO +VTT_PH_OR +.V +.V +V +VFI_VRM +VTT_PH_OR +VIO_PU_V_MI +VTT_PH_OR +VP +V_V_ +V_V_ +V_V_ +VFI_VRM +VTT_PH_OR_VLKMI +.V +V +V +.V_VTX_LV +V_V_LV +VTT_PH_V +VTT_PH_VIO +V +VU_OR ate: heet of Thursday, ugust, 0 PETRON OMPUTER IN PH()_POWER,. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 PETRON OMPUTER IN PH()_POWER,. JM0 Joyoung_hianhg ate: heet of Thursday, ugust, 0 PETRON OMPUTER IN PH()_POWER,. JM0 Joyoung_hianhg m +VTT_PH_VPLL_EXP.=0m+.+. +VTT_PH_V_EXP 0m VVRM use +.V in mobile H_YN should pull high to +VU m R. R.0 elete +VTT_PH_V +VTT_PH_VPLL_EXP +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_FI +V_V +V_V_IO +V +V_V_LV +VM_VPPI +V_NVRM_VPNN +.V_VTX_LV +VIO_PU_V_MI +VTT_PH_OR_VLKMI R.0 R.0.. R.0 Intel omments R.0 Intel omments Frank 000 EVERT remove.v and +VTT_PH_OR Frank 00 Follow Everest. 0m m/=.m./=m./*=. m/=.m m m/*pin=m./=m m/=.m 0m m/=.m 0m m/=.m R. /0 R. /0 R. /0 R.0 / P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL POWER V ORE MI VIO RT LV FI FT / PI HVMO U00 OUR_POINT_E 0V POWER V ORE MI VIO RT LV FI FT / PI HVMO U00 OUR_POINT_E 0V Vccore Vccore Vccore Vccore Vccore F Vccore F Vccore Vccore Vccore Vccore0 Vccore Vccore Vccore J Vccore J Vccore J VccFTERM J VccFTERM J VccIO N VccIO N VccIO N VccIO P VccIO0 P VccIO T VccIO N VccIO N VccIO P VccIO P Vcc U VccTX_LV M VccTX_LV M VccLV K VccVRM T VccVRM P VccPLLEXP J VccFIPLL VccIO N VccTX_LV P VccTX_LV P Vss U VssLV K VccIO P Vcc V Vcc V Vcc H VccFTERM VccFTERM VccMI T0 VccIO N VccIO N Vccore J Vccore J VccPI V VcclkMI VccMI U0 0 0UF/0V 0 0UF/0V L0 kohm/00mhz L0 kohm/00mhz 0 UF/.V 0 UF/.V 0.0UF/V 0.0UF/V UF/.V UF/.V 0PF/0V 0PF/0V 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL R0 R0 0 UF/.V 0 UF/.V U00H OUR_POINT_E 0V U00H OUR_POINT_E 0V V V V V V V V V V0 V V V V V V V V V V0 0 V V V V V V V V V V0 V V V V 0 V V V V V F0 V F V V F V F V F V0 F V F V F V F V F V F V F V F V F V0 F V V V V V H V H V H V H V H0 V0 H V H V H V J V J V J V K V K V0 K V K V K V K V K V L V L V L V L V L V0 L V L V L V L V L V M V M V M V00 M V0 M V0 M V0 M V0 N V0 N V0 N V0 N V0 P V0 P V P V P0 V P V P V P V P V P V R V0 R V T V T V T V T V T V T V T0 V T V T V T V T V U V U0 V V V V0 V V V V0 V0 V V V V V V V V W V W V W V W V W V W V0 W V W V W V W0 V W V V V Y V Y V Y V0 V E V V P V0 H V F V V V J V J V E V T V0 T V0 M V L V L L0 kohm/00mhz L0 kohm/00mhz R R 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0PF/0V 0PF/0V UF/.V UF/.V 0 UF/.V 0 UF/.V R0 N_R00_0MIL_MLL R0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL R R UF/.V UF/.V 0.0UF/V 0.0UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL 0.0UF/V 0.0UF/V P0 N_R00_0MIL_MLL P0 N_R00_0MIL_MLL 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small L0 kohm/00mhz L0 kohm/00mhz

23 Y Y Y Y F E E E0 F0 F F F0 F F F F F0 F F0 F H H H H H0 H H H H H H H 0 E E 0 H H H H H H0 H H F Frank 000 R0 is un-mounted and L0 is mounted in EIH +V_V_ U00I V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V 0V OUR_POINT_E R0 R.0 Intel omments L0 kohm/00mhz V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V 0 0UF/0V H K K K K K L L L0 L L L L M P M M M M0 M M M M M M M N P0 N P P T P0 P P P R R T T T T W T T T V V V V V V V V V V W W W W W Y Y Y Y Y Y N J E0 H T P M P P E J +V_V_LKF 0 UF/.V +VTT_PH_VIO +VTT_PH_V PL +VTT_PH_V PL +.0VM_OR +.0VM_OR +VTT_PH_OR +VTT_PH_V PL +VTT_PH_OR +VTT_PH_OR +VTT_PH_OR +VU_OR +V +VTT_PU_VPPU P0 R0 /NON_ R0 R. 0/ / Frank 000,,,0 is mounted in EIH P N_R00_0MIL_MLL UF/.V R. /0 R0 0 UF/.V 0 UF/.V L0 0 0UF/0V R0 R0 N_R00_MIL_MLL +VTT_PH_VIO R.0 Intel omments UF/.V R0 0 UF/.V 0 UF/.V kohm/00mhz 0 UF/.V +V_RT +VTT_PH_OR R.0 Intel omments 0.UF/.V 0.UF/V UF/.V L0 L0 0 0.UF/V +VTT_PH_OR kohm/00mhz kohm/00mhz +VTT_PH_VLK +VPW PH_VW 0 +V_V_LKF T m/=.m 0.UF/V +VPLL_PY_PH H P L./=m N_R00_0MIL_MLL +VPLL_PY +VU 0m/=0m L R.0 Intel omments 0.0/*0= m UF/.V +VFI_VRM +VTT_PH_V PL +VTT_PH_V PL R0 0 UF/.V +VIFFLK +VTT_PH_OR_V UF/.V UF/.V R. 0/ Link UF/.V UF/.V +VRTEXT 0.UF/V VT +V.0VM_OR_VU +VU_ +VU_ +V m/=.m 0.UF/V u m m./=m F 0m F F +VIFFLKN R. /0 0.UF/V UF/.V m m m T V W W W W W W W N Y F V T V J R. /0 JP0 MM_OPEN_MM JP0 U00J Vcclk VccW_ cpusyp Vcc VccPLLMI VccIO cpus VccW VccW VccW VccW VccW VccW VccW VccW VccW VccW0 VccW VccW VccW VccW VccW VccW VccW VccW VccW VccW0 cprt VccVRM VccPLL VccPLL VccIO VccIFFLKN VccIFFLKN VccIFFLKN Vcc cpt cpus cpus V_PRO_IO VccRT +VU_OR 0m +VU_OR POWER lock and Miscellaneous PU RT OUR_POINT_E T PI/PIO/LP U MI H R.0 +.0V VccIO VccIO VccIO VccIO0 VccIO Vccus Vccus Vccus Vccus Vccus VccIO VREF_us cpus Vccus VREF Vccus Vccus Vccus Vccus 0 Vcc Vcc Vcc Vcc VccIO VccIO VccIO VccIO VccPLLT VccVRM VccIO VccIO VccIO VccW VccW VccW VccusH Frank MM_OPEN_MM 00 Follow Everest +V_V_ +V_RT JP0 +V m +.0V +VTT_PH_OR +VTT_PH_VIO MM_OPEN_MM +VIFFLKN +VFI_VRM +V +V_V_ +VP +VU +V +VU_OR +VU N./*= m P P T T T T V V P m +VU_OR_VPU R. 0/ Line up./=m T +VUPLL +VTT_PH_VIO P0 N_R00_0MIL_MLL M m N N P m N0 N P0 P W T J F H H F K +V_UU PH_V 0 PH_V PH_V m/*pin=.m m/=.m m/=.m 0mil trace 0m +VTT_PH_VUORE +VU_OR_VPU +VU_OR_VPU Fm/=.m T V T P 0.UF/V R.0 Intel omments Frank 00 Remove Remove +.0VM. UF/.V UF/.V +V_VPORE./*= 0.m +V_RT 0, +V,0,,0,,,,0,,, +.0V,,, +VTT_PH_OR, +VTT_PH_VIO 0, +V_PH_VREF N_R00_MIL_MLL UF/.V +VTT_PH_OR_VPLL_T +VFI_VRM./*= m JP0 MM_OPEN_MM P0 R. 0/ Link +.0VM_OR.0 +VTT_PH_VIO_T P0 +VTT_PH_VIO_V_T N_R00_0MIL_MLL N_R00_MIL_MLL UF/.V R.0 Intel omments 0.0/*= 0m 0.UF/V P0 P0 P0 0 UF/.V N_R00_MIL_MLL N_R00_MIL_MLL 0.UF/V +VU_PH_VREFU kohm/00mhz 0UF/0V +VU_OR +.0VM_OR +VIFFLKN +VFI_VRM +V,0,,,,,,,,0,,,,,,,,,0,,,,,,0,, +V_V_ +VP,,,,0,,, +VU,,, +V,,,,,0,,,0,, +VU_OR 0,,,,,, +VU,,,,0,0,, PETRON OMPUTER IN +VTT_PH_VIO +VU_OR +VTT_PH_VIO +VTT_PH_VIO +VU_OR_VPZU P +VU_OR Frank 000 N_R00_MIL_MLL is uf in EIH. R.0 elete +VTT_PH_VUORE +VTT_PH_VIO_T +VTT_PH_OR_VPLL_T +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_OR_V +VPLL_PY +VTT_PH_VIO_V_T +V_V_LKF +V_VPORE +V_VPPI +VTT_PU_VPPU +VU_OR +VU_PH_VREFU +V_PH_VREF +VU_OR_VPZU +VU_OR_VPU +VTT_PH_OR +VU_OR +VU_OR Frank 000 Remove short pins but EIH does not. +V +V +V_V_ PH()_POWER, 0.UF/V UF/.V P0 JM0 0.UF/V L0 0 V/0. R 0 UF/.V 0 V/0. R 0 N_R00_0MIL_MLL Joyoung_hianhg Thursday, ugust, 0 ate: heet of.