zy5_0512a_reve

Transcription

1 PU ORE ISL PGE ZY SYSTEM LOK IGRM N ORE.V PGE N RUN.V PGE R II SMR_VTERM.VSUS(TPSREGR) PGE SYSTEM POWER ISL PGE INT or EV selector Resistor RII-SOIMM PGE RII-SOIMM PGE RII /00 MHz RII /00 MHz Lion Sabie SG Processor P (upg)/w PGE,,, M Griffin PU THERML SENSOR PGE PU Fan PGE SYSTEM HRGER (ISL) PGE ISHRGER /.V_S,.V,.V PGE 0 LVS PGE MXM onnector PGE PI-Express X LVS RT HMI HT LINK NORTH RIGE & SOUTH RIGE PI-E X Mini PI-E ard (Wireless LN) PGE X Mini PI-E ard (TV TUNER) US.0 x PGE X Express ard (NEW R) US.0 Ports x X ard reader JMicron JM-LGEZ0 X LN roadom PIE-LN M/ (0/00/GigaLN) PGE PGE 0 PGE RJ/RJ PGE LE OK LN/VG/VI/US/UIO PGE SNTLVPWR Switch PGE TSV0RHUR Switch PGE ST - H PGE ST0 MPM US.0 RT VI- HMI ST - H PGE O(PT) PGE ST ST mm X mm, pin G PI US.0 Ports luetooth x PGE x PGE x PGE Fingrprinter x PGE LE OK US x PGE RT PGE LE OK PGE HMI ONN. PGE.MHz PGE,,,0,,, H ard us PMI O Micro OZ0TN LP zalia udioontroller RealTek L/ PGE M. PGE PGE P STK UP Keyboard PGE IR PGE K (WPE0G) PGE udio mplifier Int MI LYER : TOP LYER : S LYER : IN LYER : IN LYER : V LYER : Touch SPI Pad ROM PGE PGE LE OK UIO PGE Speaker SPIF/Phone Jack Line in MI Jack Quanta omputer Inc. PROJET : ZY Size ocument Number Rev lock iagram Monday, May, 00 ate: Sheet of

2 HT_RX#[..0] HT_RX#[..0] HT_TX[..0] HT_RX[..0] HT_RX[..0] HT_TX#[..0] HT_TX[..0] HT_TX#[..0] HOLE0 *PU_HOLE HOLE *PU_HOLE HOLE *PU_HOLE HOLE0 *PU_HOLE HOLE *H-P HOLE *H-P HOLE *H-P HOLE *H-P PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE ONNETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE HOLE *MINI_HOLE HOLE *MINI_HOLE HOLE *H-P HOLE *H-P HOLE *H-P HOLE *H-P HT_PU_UPLK0 HT_PU_UPLK#0 HT_PU_UPLK HT_PU_UPLK# VLT_RUN HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX#.u/.V_ HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# REV: Modify HT_PU_WNLK0 HT_PU_WNLK#0 HT_PU_WNLK HT_PU_WNLK#.V 0 ohm() VLT_RUN Note:on MP,(HT=.V) and PU(HT=.V) and therefore cannot be connected to the same HT power rail. O MOIFY 0/,LEX HT_PU_UPTL0 HT_PU_UPTL#0 HT_PU_UPTL HT_PU_UPTL# NO STU for HT VLT_RUN thlon Sg Processor Socket SOKET PIN HT_PU_WNTL0 HT_PU_WNTL#0 HT_PU_WNTL HT_PU_WNTL# HOLE HOLE HOLE HOLE *MXM_HOLE *MXM_HOLE *MXM_HOLE *MXM_HOLE HOLE HOLE HOLE HOLE *M_HOLE *M_HOLE *MXM_HOLE *MXM_HOLE.u/.V_ HOLE HOLE *NONP_HOLE LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT ONNETE IRETLY TO OWNSTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS P *EMIP HOLE *O_HOLE *H-P HOLE *FN_HOLE HOLE *H_HOLE R */F_ HOLE Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin HT I/F ate: Monday, May, 00 Sheet of *H-P 0P_ HOLE HOLE *MINI_HOLE HOLE *MINI_HOLE E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P J J J K U VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L HT LINK VLT_0 VLT_ VLT_ VLT_ L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L E E E E W W V U U U T R Y W V V V U T T Y W Y Y L FJHS00_0 HOLE HOLE *O_HOLE *H_HOLE 0.u/.V_ HOLE0 *H_HOLE 0P_ *H-P HOLE HOLE *H_HOLE *H-P N P P P R */F_ L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L thlon Sg SOKET PIN R R T R P *EMIP L FJHS00_0.u/.V_.u/.V_ HOLE *H-P

3 E V_VTT_SUS_PU IS ONNETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE Processor R Memory Interface SMR_VTERM SMR_VTERM MEM:T M Q[0..] M Q[0..] M Q0 M Q0 PLE THEM LOSE TO U M Q M_T0 M_T0 G M Q M Q M_T M_T F M Q PU WITHIN ".VSUS M Q M_T M_T H 0 M Q VTT VTT W0 0 MEM:M/TRL/LK M Q M_T M_T G M Q VTT VTT 0 G M Q M_T M_T H 0 M Q VTT VTT 0 E M Q M_T M_T H 0 M Q VTT VTT 0 R./F_ M Q M Q M_ZP VTT 0 R M_T M_T M Q M_T M_T E F0 M Q M_ZN MEMZP.VSUS E0 PU_VTT_SUS_F M Q M Q MEMZN VTT_SENSE Y0 K/F_ M_T M_T H T R./F_ M Q0 M_T M_T E M Q0 MEM_M_RESET# PU_M_VREF M Q M_T0 M_T0 E M Q T0 H RSV_M MEMVREF W 0 M Q M_T M_T H M Q MEM_M_RESET# M Q M_T M_T E M Q M OT0 T M0_OT0 RSV_M T M Q M Q M OT V R M_T M_T F 0 M OT0 M0_OT M Q M_T M_T M Q T U M OT M_OT0 M0_OT0 W M OT0 M Q M Q T V M_OT M0_OT W K/F_ M_T M_T G.u/0V_ 000p_ M OT 0 M OT0 M Q M_T M_T G M Q M_OT0 Y T M Q M_T M_T M Q M S#0 T0 M0_S_L0 M Q M_T M_T M Q M S# U M S#0 M S#0 M0_S_L M0_S_L0 V M Q0 M_T M_T E0 M Q0 T0 U0 M S# M S# M_S_L0 M0_S_L W 0 M S#0 M Q M_T0 M_T0 E M Q T V0 M_S_L M_S_L0 U T 0 M Q M_T M_T F M Q M Q M_T M_T M Q M KE0 J M_KE0 M_KE0 J M KE0 M Q M_T M_T M Q M KE J0 M_KE M_KE H M KE E M Q M_T M_T F0 E M Q M Q M_T M_T F M Q T N M_LK_H M_LK_H P T G M Q M_T M_T H M Q T N0 M_LK_L M_LK_L R T G M Q M_T M_T J M Q M LKOUT E M_LK_H M_LK_H M LKOUT M Q M_T M_T E M Q M LKOUT# F M_LK_L M_LK_L M LKOUT# M Q0 M_T M_T E M Q0 M LKOUT Y M_LK_H M_LK_H F M LKOUT G M Q M_T0 M_T0 H0 M Q M LKOUT# M_LK_L M_LK_L F M LKOUT# G P M Q M_T M_T H M Q T0 M_LK_H M_LK_H R T P0 M Q M_T M_T Y M Q T M_LK_L M_LK_L R T M [0..] M Q M_T M_T M Q M [0..] M 0 N M 0 M Q M_T M_T M Q M M_0 M_0 P E M0 M M Q M_T M_T M Q M M_ M_ N N M M Q M_T M_T W M Q M M_ M_ P M M M Q M_T M_T W M Q M M_ M_ N M M M Q M_T M_T Y M Q M M_ M_ N E L0 M M Q0 M_T M_T M Q0 M M_ M_ L M M M Q M_T0 M_T0 Y0 M Q M M_ M_ N L M M Q M_T M_T 0 M Q M M_ M_ L E0 L M M Q M_T M_T M Q M M_ M_ M F0 K M M Q M_T M_T M Q M 0 M_ M_ K F R M 0 M Q M_T M_T M Q M M_0 M_0 T F L M M Q M_T M_T M Q M M_ M_ L 0 K0 M M Q M_T M_T M Q M M_ M_ L 0 V M M Q M_T M_T Y M Q M M_ M_ W K M M Q M_T M_T M Q M M_ M_ J E K M M Q0 M_T M_T W M Q0 M_ M_ J M Q M_T0 M_T0 W M Q M S#0 M Q M_T M_T Y M Q M S#0 R0 M_NK0 M_NK0 R F M S# M Q M_T M_T Y M Q M S# R M_NK M_NK U M Q M_T M_T M Q M S# J M_NK M_NK J M S# F M Q M_T M_T F M Q M Q M_T M_T M Q M RS# R M_RS_L M_RS_L U M RS# F M Q M_T M_T M Q M S# T M_S_L M_S_L U M S# M Q M_T M_T M Q M WE# T M_WE_L M_WE_L U M WE# M Q M_T M_T Y Y M Q M Q0 M_T M_T W E M Q0 M Q M_T0 M_T0 F M Q M Q M_T M_T M Q thlon Sg SOKET PIN F M Q M_T M_T M Q M_T M_T thlon Sg Processor Socket SOKET PIN M QS0 M QS0 M QS#0 M_QS_H0 M_QS_H0 G M QS#0 M LKOUT M LKOUT M QS M_QS_L0 M_QS_L0 H M QS M QS# M_QS_H M_QS_H G M QS# M QS M_QS_L M_QS_L G M QS.p_NPO_ M QS# M_QS_H M_QS_H.p_NPO_ M QS# M QS M_QS_L M_QS_L M QS M LKOUT# M LKOUT# F PLE LOSE TO PROESSOR PLE LOSE TO PROESSOR M QS# M_QS_H M_QS_H G E M QS# M QS M_QS_L M_QS_L G M QS M LKOUT WITHIN. INH M LKOUT WITHIN. INH M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F M QS M QS# M_QS_H M_QS_H 0 F M QS#.p_NPO_ M QS M_QS_L M_QS_L 0.p_NPO_ E M QS M QS# M_QS_H M_QS_H Y M QS# M LKOUT# M LKOUT# M QS M_QS_L M_QS_L W F M QS M QS# M_QS_H M_QS_H W E M QS# M_QS_L M_QS_L W To reverse SOIMM socket M M[0..] M M0 M M M M M M M M M M M M M M E E U M_M0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_M M_M M_M M_M E E F Y Y M M0 M M M M M M M M M M M M M M M M[0..] To normal SOIMM socket SMR_VTERM 0 0.u/.V_.u/.V_.u/.V_.u/.V_ u/.V_.u/.V_.u/.V_.u/.V_ 000P_ 0 000P_ 000P_ 000P_ 0P_ 0 0P_ 0P_ 0P_ M QS[0..] M QS0 M QS M QS M QS M QS M QS M QS M QS thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN M QS0 M QS M QS M QS M QS M QS M QS M QS M QS[0..] M QS#[0..] M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#[0..] Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin RII MEMORY I/F Monday, May, 00 ate: Sheet of E

4 THLON ontrol and ebug.vsus.v LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LONG. PU_V_RUN L LMPG0SN_ PU_V_RUN.VSUS If M SI is not used, the SI pin can be left unconnected and SI should have a 0-Ω (±%) pulldown to VSS. R 0_ R0 0_ R *0_ R *K/F_ 0 Ohm PU_SI PU_SI PU_LERT PU_SI PU_SI PU_THERMTRIP# PU_THERMTRIP#.VSUS R00 00_ R 0_ R0 00_ Q MMT0 SYS_SHN#,0 00u/.V_.u/.V_.u/.V_ 00p/0V_.VSUS PU_LKP PU_LKN PU_LKP PU_LKN 00P_ place them to PU within." VLT_RUN 00P_ R /F_ PU_V_RUN Keep trace from resisor to PU within 0." keep trace from caps to PU within." PU_LKIN_S_P PU_LKIN_S_N R R./F_./F_ PU_HT_RESET# PU_HT_PWRG PU_HT_LTSTOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_HTREF0 PU_HTREF F F F0 F F E R P U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM M W F W W PU_SV_R PU_SV_R PU_THERMTRIP# PU_PROHOT# PU_MEMHOT# PU_THERM PU_THERM connect to PU VIO power F PU_PROHOT#.VSUS R 00_ R.VSUS R 0_ *0_ HEK MP thermal Q MMT0 E_PROHOT# MP_PROHOT#.VSUS HTPU_PWRG HTPU_STOP# HTPU_RST# R 0_ R 0_ R 0_ R 00_.VSUS R 00_.VSUS R 00_ PU_HT_PWRG PU_HT_LTSTOP# PU_HT_RESET# 0.u/0V_ REV: Modify connect to PU ORE power F REV:E Modify by M.VSUS R0 00_ R 00_ T T T T T T0 T T T PU_V0_F_H PU_V0_F_L PU_V_F_H PU_V_F_L PU_RY PU_TMS PU_TK PU_TRST# PU_TI PU_TEST_TSTUP PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_SINGLEHIN R 0_ PU_TEST_NLOGIN PU_TEST_IERKMON T F E Y G0 F H0 G E E F E E F V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV W Y H G E0 E J H E F K H H PU_REQ# PU_TO PU_TEST_H_PLLHRZ_P PU_TEST_L_PLLHRZ_N PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_NLOG_T PU_TEST0_NLOGOUT PU_TEST_IG_T PU_VIO_F_H PU_VIO_F_L V_N_F_H V_N_F_L PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N T T0 connect to PU VN power F route as differential as short as possible testpoint under package T T T T T T T T T PU_SV_R PU_SV_R PU_MEMHOT# R 0_ R 0_.VSUS R *00_ VI Override ircuit.vsus Q *MMT0 PUMEMHOT# connect to PU ORE power controlier R K_ R K_ R *0_ Serial VI lock SV Serial VI ata SV dd pull up.vsus R 00_ thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN HTPU_PWRG R 0_ R *0_ R *0_ PG_IN PU_LT_REQ#_PU PU H/W MONITOR /0/0' Reserve 0 ohm for PU thermal issue on -test V R R *0_ PU_THERM /F_ PU_THERM 0 mil trace / 0 mil space 00P_ MIL V_THM 0.u/0V_ R 0_ ddress H U V XN XP -OVT G -LT SMT SMLK HTPU_REQ# HTPU_REQ# V R 0K_ To S GPIO THERM_LERT# Q N00E KSMT KSMLK V R 0K_ To FN PUFN#_ON V Rev:E dd R by M esign guide 0 V_0 on /. R0.K_ V R.K_ Q N00E Q N00E N_MT N_MLK.VSUS PU_TEST_SINGLEHIN R *00_ PU_TEST_PLLTEST R0 *00_ PU_TEST_PLLTEST0 R0 *00_ PU_TEST_P R0 *00_ PU_TEST_P0 R *00_ PU_TEST_TSTUP R 00_ PU_TEST_SNEN R 00_ PU_TEST0_SNLK R 00_ PU_TEST_SNLK R 00_ PU_TEST_SNSHIFTEN R *00_ PU_TEST_SNSHIFTEN R *00_ Need heck with nvidia PU_HT_RESET#.VSUS R *0_.VSUS V R *0K_ Q *MMT0 R0 *0_ R *0_ R *0_ R *K/F_ R 00_ H_HTPU_RST# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO VFIX MOE SV SV Voltage Output(PU Power) 0 0.V 0.V 0.0V 0.V HT ONNETOR.VSUS T T T T T T T N *SP-00-0-P-LV HT RSV RSV0 REQ_L RY 0 TK TMS TI TRST_L TO 0 V_PRO_IO_ V_PRO_IO_RESET_L KEY H_HTPU_RST# Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin TRL & EUG ate: Monday, May, 00 Sheet of 0 0

5 E PROESSOR POWER N GROUN UF VSS VSS J VSS VSS J PU_ORE0 PU_ORE VSS VSS J0 VSS VSS J PU_ORE0 UE VSS VSS0 J VSS VSS J VSS VSS J G V0_ V_ P VSS VSS K H V0_ V_ P0 VSS VSS K J V0_ V_ R VSS0 VSS K J 0u_V_.u/.V_ 0P_ V0_ V_ R VSS VSS K u/.v_.0u/v_ J V0_ V_ R VSS VSS K J V0_ V_ R VSS VSS K K V0_ V_ T VSS VSS K K0 V0_ V_ T VSS VSS0 L K V0_ V_ T VSS VSS L K PU_ORE V0_0 V_0 T0 VSS VSS L0 L V0_ V_ T VSS VSS L L V0_ V_ T VSS VSS L L V0_ V_ U VSS0 VSS L L V0_ V_ U E VSS VSS L 0 L V0_ V_ U E VSS VSS M 0u_V_ L.u/.V_.0u/V_ 0P_ V0_ V_ U E VSS VSS M 0u_V_ u/.v_ M V0_ V_ U E VSS VSS M V0_ V_ V E VSS VSS0 M M V0_ V_ V E VSS VSS N M0 V0_0 V_0 V0 E VSS VSS N N V0_ V_ V VSS VSS N0 N V0_ V_ V VSS VSS N N PU_VN_ORE V0_ V_ W VSS0 VSS N V_ Y VSS VSS P PU_VN_ORE K VN_ V_ VSS VSS P M VN_ V_ VSS VSS P P VN_ VSS VSS P T VN_ VIO Y.VSUS VSS VSS00 P V 0 VN_ VIO V VSS VSS0 R u/.v_ u/.v_ VIO V u/.v_ VSS VSS0 R0.VSUS H VIO VIO V VSS VSS0 R J VIO VIO V VSS VSS0 R K VIO VIO U VSS0 VSS0 T K VIO VIO T VSS VSS0 T K VIO VIO0 T VSS VSS0 T K VIO VIO T VSS VSS0 T L VIO VIO T VSS VSS0 T M VIO VIO R VSS VSS0 T M VIO VIO P VSS VSS U M VIO0 VIO P VSS VSS U M EOUPLING ETWEEN PROESSOR N IMMs VIO VIO P VSS VSS U N VIO VIO P VSS VSS U0 VSS0 VSS U E PLE LOSE TO PROESSOR S POSSILE VSS VSS U F thlon Sg SOKET PIN VSS VSS U F VSS VSS U.VSUS thlon Sg F VSS VSS V F Processor Socket VSS VSS0 V F VSS VSS V SOKET PIN F VSS VSS V F VSS VSS V F 0 0 VSS VSS V F.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.0u/V_.0u/V_ VSS0 VSS V.u/.V_.u/.V_ 0P_ H VSS VSS W H VSS VSS Y H VSS VSS Y H VSS VSS N J VSS M Sg Griffin upg thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Top View F Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin PWR & ate: Monday, May, 00 Sheet of E

6 E E MEM_SMLK MEM_SMT M Q0 M Q MEM_SMT M M 0 M M M M M M Q MEM_SMLK M M 0 M M M M M M Q M Q0 M Q M MVREF_IM M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q MVREF_IM MEM_SMLK M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M0 M Q MVREF_IM M Q M M M M M M M M M M M QS0 M M M M M QS M QS M QS M QS M QS M QS M QS M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M 0 M Q M Q M M Q M M Q M M M Q M Q M M Q M M Q M Q M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS0 M QS M Q M M M Q M Q M M M Q M Q0 M Q M M 0 M M Q M M Q M Q M Q M Q M M Q M Q0 MEM_SMT M Q M Q M Q M Q M Q M Q M S# M OT0 M S#0 M M M KE0 M OT M S# M WE# M S# M RS# M KE0 M OT0 M S# M RS# M S# M 0 M S#0 M S# M M S# M OT M 0 M S# M M M M S#0 M M S#0 M M M WE# M M M M M M M M M 0 M M M M M M 0 M M M M KE M M KE M M MEM_SMT MEM_SMLK MSM_T MSM_LK.VSUS V V SMR_VTERM.VSUS SMR_VTERM V V.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VREF V SMR_VTERM V V M [0..] M KE0 M KE M RS# M S# M WE# M S#0 M S# M OT0 M Q[0..] M LKOUT M LKOUT# M LKOUT M LKOUT# M OT M S# M S# M S#0 M QS#[0..] M QS[0..] M M[0..] M LKOUT M LKOUT# M LKOUT M LKOUT# M OT0 M KE0 M KE M OT M [0..] M S# M S#0 M S# M QS#[0..] M QS[0..] M M[0..] M RS# M S# M WE# M Q[0..] M S#0 M S# Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Monday, May, 00 ZY REVERSE (H=.) REVERSE (H=.) M suggestion : 00 XR 0.U each R-Pack between.vsus and SMR_VTERM M suggestion : 00 XR for each R-pack NEE UT R K/F_ R K/F_ RP X_ RP X_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ RP X_ RP X_ RP X_ RP X_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ *0u/0V_ *0u/0V_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_.u/0V_ T T T T R _ R _.u/0v_.u/0v_ R0 _ R0 _.u/0v_.u/0v_ RP0 X_ RP0 X_.u/0V_.u/0V_.u/0V_.u/0V_ R _ R _ Q *N00E Q *N00E.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ U_ U_ RP X_ RP X_ RP0 X_ RP0 X_.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 R 0_ R 0_ RP X_ RP X_.u/0V_.u/0V_ *.U/0V_ *.U/0V_ *.U/0V_ *.U/0V_ T T T0 T0 R K/F_ R K/F_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_ RP X_ RP X_.U/.V_.U/.V_.u/0V_.u/0V_.u/0V_.u/0V_.U/.V_.U/.V_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_ RP *.K_PR RP *.K_PR *0u/0V_ *0u/0V_ RP X_ RP X_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H. R _ R _ *0U *0U.u/0V_.u/0V_ T T R _ R _.u/0v_ 0.u/0V_ 0.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_ R *0_ R *0_.u/0V_.u/0V_.u/0V_.u/0V_ R _ R _ *0U *0U.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ 00.u/0V_ 00.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ *0u/0V_ *0u/0V_ RP X_ RP X_ Q0 *N00E Q0 *N00E RP X_ RP X_ R _ R _ T T *.U/0V_ 0 *.U/0V_ 0 R _ R _ 0U/.V_ 0U/.V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ R 0_ R 0_.u/0V_.u/0V_ R 0_ R 0_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H..u/0V_.u/0V_ R0 _ R0 _.u/0v_.u/0v_ *0u/0V_ *0u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ R0 _ R0 _ RP X_ RP X_.u/0V_ 0.u/0V_ 0 RP X_ RP X_ RP X_ RP X_.u/0V_.u/0V_ *.U/0V_ *.U/0V_.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ R 0K_ R 0K_ *.U/0V_ *.U/0V_.u/0V_.u/0V_ 0U/.V_ 0U/.V_ RP X_ RP X_.u/0V_.u/0V_ RP X_ RP X_ 0.u/0V_ 0.u/0V_ RP X_ RP X_

7 HT_TX[..0] HT_RX[..0] HT_TX#[..0] U FG-NVII-MP :JMP0T00 :JMP0T0 HT_RX#[..0] HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# F G H J J K K L G F L K L K J K E F G H J L K E E HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N SE OF HT HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N K J K L K L L K K L K L H J L0 M0 G H F G H J E F E F G 0 0 E F HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_PU_WNLK0 HT_PU_WNLK#0 HT_PU_WNLK HT_PU_WNLK# J H L K HT_MP_RX_LK0_P HT_MP_RX_LK0_N HT_MP_RX_LK_P HT_MP_RX_LK_N HT_MP_TX_LK0_P HT_MP_TX_LK0_N HT_MP_TX_LK_P HT_MP_TX_LK_N K J G H HT_PU_UPLK0 HT_PU_UPLK#0 HT_PU_UPLK HT_PU_UPLK# V V_PLL L0 TI00U00_ REV: Modify NV FE: HTMP_OMP_V ONNET TO.V_HT_PLL.U/.V_ m m HT_PU_WNTL0 HT_PU_WNTL#0 HT_PU_WNTL HT_PU_WNTL# PU_THERMTRIP# MP_PROHOT#.u/0V_.V_N.V_N.V_N.V_HT_PLL L 0 L 0 R R R 0m R0 0_ PU_THERMTRIP# MP_PROHOT# V_PLL TI00U00_.U/.V_.V_HT_PLL.u/0V_ TI00U00_.U/.V_.V_PLL_PU.u/0V_ PU_SVREF *.K/F_ MP_TERM_J REV: Modify 0/F_ HTMP_OMP_VM.u/0V_ H G R 0/F_ HTMP_OMP_L G HT_MP_RXTL0_P HT_MP_RXTL0_N HT_MP_RXTL_P HT_MP_RXTL_N THERMTRIP#/GPIO_ PROHOT#/GPIO_0.V_LL_HT.V_PLL_HT.V_PLL_PU HT_MP_OMP_V HT_MP_OMP_ PU_SVREF LK00_TERM_ HT_MP_TXTL0_P HT_MP_TXTL0_N HT_MP_TXTL_P HT_MP_TXTL_N HT_MP_REQ# HT_MP_STOP# HT_MP_RST# HT_MP_PWRG LKOUT_00MHZ_P LKOUT_00MHZ_N LKOUT_MHZ.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_ K0 J0 0 L M K Y Y Y V V W W HTPU_REQ# LKOUT_MHz.V_HT_ U_.V_HT_ U_ U_ U_ T HT_PU_UPTL0 HT_PU_UPTL#0 HT_PU_UPTL HT_PU_UPTL# HTPU_REQ# HTPU_STOP# HTPU_RST# HTPU_PWRG PU_LKP PU_LKN.u/.V_ u/.v_ L TI00U00_.u/.V_.u/.V_ u/.v_.v_n L PY00T_ 00m.V_N 0m.VSUS MP_PROHOT# R 00_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP HyperTransport us ate: Monday, May, 00 Sheet of

8 PEG_RXP[:0] PEG_RXN[:0] PEG_TXP[:0] PEG_TXN[:0] U FG-NVII-MP V_S R *0K_ [TV] [NEW R] PIE_WKE# [MINI R] [Giga LN],, PIE_WKE# PE0_PRSNTX# MXM_ON# PIE_RXP PIE_RXN MINI_LKREQ# PIE_RXP PIE_RXN TV_LKREQ# PIE_RXP PIE_RXN LN_LKREQ# PIE_RXP PIE_RXN NEW_LKREQ# PPE#.V_N T T T R0 0 EV^0_ S PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_WKE# PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX# MINI_LKREQ# TV_LKREQ# R 0_ LN_LKREQ# R 0_ NEW_LKREQ# PPE#_.V_PLLPE_SS F G F F 0 0 F F F F H H H H H H K K K K K K J J0 K K0 H U U0 U U L L0 W W M M U U N N U U N0 N R U P P0 T V P P U V0 PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE_WKE#/GPIO_ PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PEE_LKREQ#/GPIO_ PEE_PRSNT# PE_RX_P PE_RX_N PEF_LKREQ#/GPIO_ PEF_PRSNT# PE_RX_P PE_RX_N PEG_LKREQ#/GPIO_ PEG_PRSNT# SE OF PIE PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PEE_REFLK_P PEE_REFLK_N PE_TX_P PE_TX_N PEF_REFLK_P PEF_REFLK_N PE_TX_P PE_TX_N PEG_REFLK_P PEG_REFLK_N.V_PE_ 0 0 E E0 F F0 G G0 H H0 H H R R0 M M T T M M T T0 M M T T M0 M T T P P T T P P P R W _PEG_TXP0 _PEG_TXN0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP0 _PEG_TXN0 _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN PIE_TXP_ PIE_TXN_ LK_PIE_MINI_R LK_PIE_MINI#_R PIE_TXP_ PIE_TXN_ LK_PIE_TV_R LK_PIE_TV#_R PIE_TXP_ PIE_TXN_ LK_PIE_LN_R LK_PIE_LN#_R PIE_TXP_ PIE_TXN_ LK_PIE_NEW R LK_PIE_NEW_#_R 00m.V_PE PE0_REFLK_P R _ PE0_REFLK_N R _.u/0v_ PEG_TXP0.u/0V_ PEG_TXN0.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP0.u/0V_ PEG_TXN0.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_ PEG_TXP.u/0V_ PEG_TXN.u/0V_.u/0V_ R _ R _ 0.u/0V_.u/0V_ R0 _ R0 _.u/0v_.u/0v_ R _ R _ 00.u/0V_.u/0V_ R0 _ R0 _ LK_PIE_MXM LK_PIE_MXM# L 0_ PIE_TXP PIE_TXN LK_PIE_MINI LK_PIE_MINI# PIE_TXP PIE_TXN LK_PIE_TV LK_PIE_TV# PIE_TXP PIE_TXN LK_PIE_LN LK_PIE_LN# PIE_TXP PIE_TXN LK_PIE_NEW_ LK_PIE_NEW_#.V_N [MXM] [MINI R] [TV] [Giga LN] [ard Reader] [NEW R] For EMI LK_PIE_MINI LK_PIE_MINI# REV: Modify 0m.V_N POWER connect to LL_HT LK_PIE_MXM LK_PIE_MXM# 0 0 *0P_ *0P_ *0P_ *0P_ L0 0m.u/.V_.U/.V_.V_PLLPE_SSU L MLG00NJ_.V_PLLPE.U/.V_.u/0V_ V_PLL V_PLL REV: Modify MLG00NJ_ PE_LK_OMP V.u/0V_ R *.K/F_ <00mil R0 R P0.V_PLL_PE_SS.V_PLL_PE N/.V_PLL_PE N/.V_PLL_PE_SS PE_LK_OMP Remove R for Nvidia suggest..v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_ PE_RST0# PE_RST# W V V W Y Y Y Y W Y W Y W0 W 0m.V_PE R *0_.u/0V_ U_ U_ u/.v_.u/0v_.u/0v_.u/0v_ U_ PIE_RST0#,.u/.V_ u/.v_ u/.v_ ( For MXM, LN,ard Reader ) dd 0R resistor, The resistor should only be stuffed for MP PIE_RST# ( For New card, WL,TV ) L0 u/.v_ PY00T_.V_N LK_PIE_NEW_ LK_PIE_NEW_# LK_PIE_LN LK_PIE_LN# *0P_ *0P_ *0P_ *0P_ Internal K to.v R0 *K_ MINI_LKREQ# LK_PIE_TV LK_PIE_TV# *0P_ *0P_ R R R R *K_ *K_ *K_ *K_ NEW_LKREQ# PPE#_ TV_LKREQ# LN_LKREQ# Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP PI-Express us ate: Monday, May, 00 Sheet of

9 REQ0# MXM_PWR_EN [..0] INT# MXM_PWR_EN REQ0# REQ# REQ# REQ# INT# INT# INT# INT# E0 G0 J0 M E L K J J H G F E G E J K L G J E H F L J K U FG-NVII-MP PI_REQ0# PI_REQ#/FNRPM PI_REQ#/GPIO_0/RS_SR# PI_REQ#/GPIO_/RS_TS# PI_REQ#/GPIO_/RS_SIN# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INTW# PI_INTX# PI_INTY# PI_INTZ# MP SE OF PI PI_GNT0# PI_GNT#/FNTL PI_GNT#/GPIO_/RS_TR# PI_GNT#/GPIO_/RS_RTS# PI_GNT#/GPIO_/RS_SOUT# PI_E0# PI_E# PI_E# PI_E# PI_EVSEL# PI_FRME# PI_IRY# PI_PR PI_PERR#/GPIO_/RS_# PI_SERR# PI_STOP# PI_PME#/GPIO_0 PI_RESET0# PI_RESET# PI_RESET# PI_LK0 PI_LK PI_LK PI_LK PI_LK PI_LKIN F0 H0 K0 L0 F K K F K L J H J J K K GNT0# EVSEL# FRME# IRY# PR PERR# SERR# STOP# PI_PME# PIRST_R# R PIRST# PIRST# T T *^_ GNT0# E0# E# E# E# EVSEL# FRME# IRY# PR PERR# SERR# STOP# PI_PME# PIRST# PI_LK R R *^_ PLK_PM PI_LK T PI_LK T PI_LK T PI_LK R _ PI_LKIN L:match to within 000 = Length of PI feedback and onboard devices = V INT# INT# TRY# REQ0# MXM_PWR_EN REQ# REQ# IRY# V LKRUN# MXM_ON# PI_PME# SERIRQ PI/LP PULL-UP 0 0 RP RP For OZ0 LOK YPSS LP_LK_E.KX_0PR.KX_0PR R R0 R R.K_.K_ *.K_ *.K_ INT# INT# PERR# EVSEL# REQ# SERR# STOP# FRME# V_S V *P_ V V V TRY# TRY# K PI_TRY#,, LKRUN# MXM_ON# SERIRQ MXM_ON# R T LRQ#0 SERIRQ 0K_ F0 L K K K J L L J K L J J L K G0 PI_LKRUN#/GPIO_ LP_RQ#/GPIO/FNRPM LP_RQ0#/GPIO_0 LP_SERIRQ IE_T_P0/WUS_T0 IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P IE_T_P IE_T_P0 IE_T_P IE_T_P IE_T_P IE_T_P IE_T_P IE LP LP_FRME# LP_PWRWN#/GPIO_/EXT_NMI# LP_RESET0# LP_RESET# LP_0 LP_ LP_ LP_ LP_LK0 LP_LK IE_R_P0/WUS_STOP IE_R_P/WUS_RX_EN IE_R_P/WUS_TX_EN IE_S_P#/WUS_PHY_RESET# IE_S_P# IE_K_P# L G E H J K J LFRME#_ LP_P# LP_RST0# LP_RST# L0_ L_ L_ L_ LP_LK_E_R R _ T R _ T R0 _ R0 _ R0 _ R0 _ R _ LP_LK_EUG R R _ LFRME#,, LP_RST_E#, L0, L, L, L, LP_LK_E LP_LK_EUG LP_LK_EUG R *P_ PI_LKIN *P_ Reserve EMI solution V R R R.K_ 0K_.K_ PREQ K IE_INTR H0 PIORY K0 L0 LE_ET_P F IE_REQ_P/WUS_PLK IE_INTR_P/WUS_PHY_TIVE IE_RY_P/WUS_T_EN IE_IOR_P#/WUS_SERIL_T LE_ET_P/GPIO_ IE_IOW_P#/WUS STTUS IE_OMP_PV IE_OMP_ J0 M K IE_OMP_V R IE_OMP_V_ /F_ V R K_ R /F_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP PI/LP/IE ate: Monday, May, 00 Sheet of

10 U FG-NVII-MP R R0 0K_ 0K_ LN_RXER LN_OL LN_RS 0 0 E F G J0 J RGMII_RX0/MII_RX0 RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RXLK RGMII_RXTL/MII_RXV MII_RXER/GPIO_ MII_OL/MSM_T MII_RS/MSM_LK SE OF LN.V_UL_RMGT.V_UL_RMGT RGMII_TX0/MII_TX0 RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TXLK/MII_TXLK RGMII_TXTL/MII_TXEN L N J K L L H K R 0K_ V_UL.V_UL m m m.v_ul R 0K_ LN_INT N RGMII/MII_INTR/GPIO.V_PLL_M_UL MII_OMP_PV MII_OMP_ RGMII/MII_M RGMII/MII_MIO RGMII/MII_PWRWN#/GPIO_ UF_MHZ MII_RESET# MII_VREF K0 L0 MIO R G H0 RGMII_VREF R 0K_ 0K_ R /F_ RG RSET K.0u/V_RG VREF RG RSET RG VREF RG RE RG GREEN RG LUE RT_RE RT_GRN RT_LU RT_RE RT_GRN RT_LU m.v_n L TI00U00_.u/0V_ E H.V_PLL_ISP N E F.U/.V_ REV: Modify TV RSET TV VREF.V_PLL_ISP TV_XTLIN TV_XTLOUT S RG HSYN RG VSYN _LK0 _T0.V_RG_ G H G H E V.u/0V_ RT_HSYN RT_VSYN RTLK RTT L TI00U00_ m V 0 0.u/.V_.u/.V_ RT_RE R 0/F_ RT_GRN R 0/F_ RT_LU R 0/F_.V_N FOR UM ONLY Remove R,R 00m HMILKP HMILKN HMITX0P HMITX0N HMITXP HMITXN HMITXP HMITXN V REV: Modify 0m.V L 0m V L_LON L_V_ON V.V_PLLPE_SS TI00U00_ R0 R R R R0 R00.u/.V_.u/0V_ *.K_ *.K_ T.u/0V_.u/0V_ MP_GPIO MP_GPIO HMI_TXP_ HMI_TXN_.u/0V_ HMI_TX0P_ K.u/0V_ HMI_TX0N_ J.u/0V_ HMI_TXP_ M0.u/0V_ HMI_TXN_ L0.u/0V_ HMI_TXP_ K0.u/0V_ HMI_TXN_ J0 *0K_ HP_ROM_SLK *0K_ HP_ROM_ST K_ HPLUG_ET E *0K_ HMI_HP L L 0_.u/.V_ *U_.V_IFP.u/0V_ L TI00U00_.U/.V_.V_PLL_IFPP.u/0V_.u/0V_ m U0 R0 K/F_.V_P_V H HMI_RSET HMI_VPROE U T E E L M K K GPIO_/FERR/SYS_SERR/IGPU_GPIO_* GPIO_/NFERR/SYS_PERR/IGPU_GPIO_* L_KL_TL L_KL_ON L_PNEL_PWR HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX0_P/ML0_LNE_P HMI_TX0_N/ML0_LNE_N HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX_P/ML0_LNE0_P HMI_TX_N/ML0_LNE0_N UX_H0_P UX_H0_N HPLUG_ET HPLUG_ET.V_IFP.V_IFP.V_IFP_HV.V_HMI_PLL_HV.V_PLL_P.V_P_V HMI_RSET HMI_VPROE 0 Remove,R *.U/0V_ for Nvidia suggest. FLT PNEL.V_TV_ TV RE TV GREEN TV LUE IFP_TX_P IFP_TX_N IFP_TX0_P IFP_TX0_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N _LK _T _LK _T IFP_RSET IFP_VPROE F E0 E 0 0 J J E E F0 F G0 G H H0 L J L K 0 V INT_TXLOUT INT_TXLOUT- INT_TXUOUT INT_TXUOUT- HMILK HMIT IFP_RST IFP_VPROE Remove,R for Nvidia suggest. T T T T m R *.0u/V_ *K/F_ INT_TXLLKOUT INT_TXLLKOUT- INT_TXLOUT0 INT_TXLOUT0- INT_TXLOUT INT_TXLOUT- INT_TXLOUT INT_TXLOUT- INT_TXULKOUT INT_TXULKOUT- INT_TXUOUT0 INT_TXUOUT0- INT_TXUOUT INT_TXUOUT- INT_TXUOUT INT_TXUOUT- INT_LVS_EILK INT_LVS_EIT HMILK HMIT REV: Modify [LVS] HMILK HMIT R R 0K_ 0K_ V / NV FE HEK IT. HMI_HP HMI_HP REV: Modify Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP LN and Graphics ate: Monday, May, 00 Sheet 0 of

11 UE FG-NVII-MP REV: Modify [ST H ] [ST H ] [ST O] ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP REV: Modify.0u/V_ST_TXP0_.0u/V_ST_TXN0_.0u/V_ST_TXP_.0u/V_ST_TXN_.0u/V_ST_TXP_.0u/V_ST_TXN_ T T T T ST_TXP ST_TXN ST_RXN ST_RXP E E G G E E G G H H G G F F L L K L J J K K ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST SE OF US US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N RSV RSV RSV RSV RSV RSV U U U U U U V V W W W W W W Y Y USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP0 USP0- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP USP- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP 0 USP- 0 USP USP- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP USP- VSUS MINI R * MINI R * LUETOOTH REV: Modify INT LEFT US R REER INT LEFT US Fingerprint EXT US * ocking EXT US * NEW R REV: Swap Modify US PULL-OWN USP0- USP0 RN USP- RN USP USP- USP RN0 USP USP- RN USP RN USP- USP RN USP- USP RN0 USP- USP RN USP- USP RN USP- USP0 RN USP0- USP RN USP- KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ 0m.V_N 0m m 0m R 0_.V_N.V_N.V_N.V_SP_ 0u/.V_ ST_LE# L MLG00NJ_.V_PLL_SP_V.u/0V_.U/.V_ L MLG00NJ_.u/0V_.U/.V_.V_PLL_SP_SS L TI00U00_ 0.u/0V_.V_PLL_LEG 0.U/.V_ 0 0u/.V_.u/.V_ W V P E E E E.u/0V_.u/0V_.u/0V_ 0 ST_LE#/GPIO_.V_PLL_SP_V.V_PLL_SP_SS.V_PLL_LEG.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_ US_O0#/GPIO_ US_O#/GPIO_ US_O#/GPIO_ US_O#/GPIO_/MGPIO_ US_O#/GPIO_/MGPIO_.V_PLL_US.V_US_UL.V_US_UL T T T T T P Y Y USO#0 USO# USO# USO# USO#.V_US_PLL 0.u/0V_.u/.V_.V_US_UL R R R R R0 L 0K_ 0K_ 0K_ 0K_ 0K_ TI00U00_ L m.u/0v_.u/0v_ V TI00U00_ V_S 0m USP USP- RN USP USP- RN USP USP- RN USP USP- RN.V_N KX_ KX_ KX_ KX_.V_N L PY00T_ 0m.u/.V_.u/.V_.u/0V_.u/0V_.V_SP_ ST_THRM.u/0V_ R.K/F_ 0 0 E0 J.V_SP_.V_SP_.V_SP_ ST_TERMP US_RIS_ T US_RIS_ R /F_ REV: Modify Ohm for MP checklist 0 000p_ 000p_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP ST and US ate: Monday, May, 00 Sheet of

12 V V_S PE_RESET_MXM# Z_SIN0 Z_SIN Z_SIN PU LEGY PULL-UP R R R R MXM_RUNWORK need to onnect from MXM card GTE0 RIN# KSMI# SIO_PME# T0 MXM_PRESENT# T MXM_RUNPWROK GTE0 RIN# E_SI# KSMI# SM_INTRUER# MP_LI# PMU PULL-UP R R R0 R R *0K_ *0K_.K_ 0K_ *0K_ *0K_ *0K_ *0K_ *0K_ R PE_RESET_MXM_R# EV^0_ RSTTN# RI# MP_GPIO PM_TLOW# NSWON# PU V for KSMI# & SIO_PME#,0/0 LEX T MP_GPIO P MXM_PRESENT# N MP_GPIO R MXM_RUNPWROK M PE_RESET_MXM_R# M0 R0 0_ MP_GPIO K K SIO_PME# M P RI# P L MP_LI# PM_TLOW# M P N0 V W W0 Y0 0 W Y UF FG-NVII-MP H_ST_IN0/GPIO_ H_ST_IN/GPIO_/MGPIO_0 H_ST_IN/GPIO_/MGPIO_ GPIO_/PWRN_OK/SPI_S GPIO_/NMI/PS_LK0 GPIO_/SMI#/PS_T0 GPIO_/SI/PS_LK GPIO_/INIT#/PS_T GPIO_/SUS_STT/LMTR_EXT_TRIG# 0GTE/GPIO_/FNTL KRRSTIN#/GPIO_/FNRPM SIO_PME#/GPIO_/SPI_S EXT_SMI#/GPIO_ RI#/GPIO INTRUER# LI# LL# FI_RSV0 FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV SE OF H MIS H_OK_EN#/GPIO_ H_OK_RST#/GPIO H_ST_OUT/GPIO_ H_ITLK H_RESET# H_SYN/GPIO_ SLP_S# SLP_RMGT# SLP_S# MP_VI0/GPIO_ MP_VI/GPIO_ MP_VI/GPIO_ SPKR SM_LK0 SM_T0 SM_LK/MSM_LK SM_T/MSM_T SM_LERT#/GPIO_ THERM#/GPIO_ R P R H H H K E G E F F K MP_GPIO MP_GPIO Z_SOUT Z_ITLK Z_RESET# Z_SYN SUSR# R 0_ SLP_RMGT# T SUSR# R0 0_ VORE.I0_R R_PPE# R_WKE# PSPK R R T T T T T R 0_ R 0_ MSM_LK MSM_T SM_LERT# H Z_SOUT Z_SYN Z_RESET# Z_ITLK REV:E Modify by NV EMI Solution *K_ *K_ PLK_SM PT_SM Z_SOUT Z_SYN Z_RESET# Z_ITLK R 0_ SUS# SUS# REV: Modify R0 _ R _ R *EV^_ R _ R _ R *EV^_ R _ R _ R *EV^K_ L NQ00T-Y-N_ L NQ00T-Y-N_ L *NQ00T-Y-N_ PSPK PLK_SM,, PT_SM,, MSM_LK MSM_T THERM_LERT# Z_SOUT_UIO Z_SOUT_M Z_SOUT_MXM Z_SYN_UIO Z_SYN_M Z_SYN_MXM Z_RESET#_UIO Z_RESET#_M Z_RESET#_MXM Z_ITLK_UIO Z_ITLK_M Z_ITLK_MXM 0P_ 0P_ 0P_ 0P_ H_SOUT_R, LFRM# (IOS) 00 LP (EFULT) 0 PI IOS 0 SPI IOS RESERVE (SPI) MP_SPKR (oot MOE) 0 USER TLE (EFULT) SFE TLE SPI_O, SPI_LK (SPI LOK) 00 MHz 0 MHz 0 MHz MHz V_S V_S V_S STRPPING H_RESET# (LN) 0 MII RGMII (EFULT) H_SYN_R (SIO LOK) 0.MHz (EFULT) MHz V V V V R R R00 R R R R R R R R0 R R R 0K_ *0K_ *.K_.K_ *.K_.K_ *0K_ 0K_ *0K_ 0K_ 0K_ *0K_ *0K_ 0K_ Z_RESET# Z_SOUT PSPK Z_SYN LFRME#,, MP_SPI_O MP_SPI_LK.VSUS NSWON# elay 0ms RTRST# after S powerok RSMRST#, PWROK_E, HWPG_.V,0 HWPG_.V, PU_OREPG U_ R _ PWRTN# RSTTN# R0 P M L T0 M P M PWRTN# RSTTN# RT_RST# PWRG_S PWRG MEM_VL MP_VL/HT_VL PU_VL THERM_SI/GPIO_/MSM_LK THERM_SI/GPIO_/MSM_T THERM_LERT#/GPIO_/PWR_LE# FNRPM0/GPIO_0 FNTL0/GPIO_ FNTL/GPIO_ F F F MP_GPIO R 00_ MP_GPIO0_I0 MP_GPIO_I MP_GPIO_I PU_SI PU_SI.VSUS PU_SI R *00_ PU_SI R *00_ confirm by n-vidia FE 0/ V T V R R0 R R P_ P_ *K_ *K_ *0K_ K_ Y MHZ MP_TI MP_TO MP_TMS MP_TRST# MP_TK XTL XTL U T T U T H H JTG_TI JTG_TO JTG_TMS JTG_TRST# JTG_TK XTLIN XTLOUT MPV_EN/HTV_EN PUV_EN SPI_S0/GPIO_0 SPI_LK/GPIO_ SPI_I/GPIO_ SPI_O/GPIO_ SUS_LK/GPIO_ UF_SIO_LK N M K K M J P J HTV_EN PU_VRON MP_GPIO0 MP_SPI_LK MP_SPI_O SUS_LK_R SIO_LK T T T HTV_EN,0 PU_VRON REV: elete T0 Strap pin only MP_TRST# MP_TO MP_TI MP_TMS MP_TK N 0 0 *NV_JTG P_ LK_KX LK_KX H H XTLIN_RT XTLOUT_RT TEST_MOE_EN PKG_TEST P P0 TESTMOE_EN R *0M_ Y.KHz R K_ P_ SM/I PULL-UP PLK_SM R0.K_ PT_SM R.K_ SM_LERT# R0.K_ MXM_PRESENT# R 00K_ V_S MSM_LK MSM_T MXM_RUNPWROK R R R REV: Modify.K_ V.K_ K_ HP -WIRE ROM PE_RESET_MXM_R# R *0K_ U VPU :Z timing issue, modify to P : HNGE P FROM 0.U TO U FOR ELY HT_VL V_S R R 0K_ 0K_ R R *0K_ *0K_ R0 IV^0K_ MP_GPIO0_I0 MP_GPIO_I MP_GPIO_I R0 EV^0K_??? HEK M I M/ I for "/" VPU I0 I I M/ " 0 0 X 0 0 " 0 0 " U 0 " ual ore PU & MXM 0 " ual ore PU & UM " Single ore PU & UM R PLK_SM PT_SM *0K_ SL S HP_WP WP R 0 V HP^TS00 HP^0K_ Quanta omputer Inc. PROJET : ZY HP^.u/V_ Size ocument Number Rev MP H/SM/PMU/GPIO/RT Tuesday, May, 00 ate: Sheet of

13 .V_UL V_UL VRT RT_HG RT_HG RT_HG VRT_ RTRST# VRT_ SM_INTRUER# RTRST#.V_S V_S V N_ORE VRT VPU VPU VRT V_UL.V_UL Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER/ Monday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER/ Monday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : MP POWER/ Monday, May, 00 ZY MP POWER PLNE/ & YPSS 0MIL RT 0MIL 0MIL 0.V~.0V 0m change footprint from 00 to 00 m 0m 0m 0m L G M M N U0 U M L H P L J V M M N N0 G R M E G F F E G J F M T0 U J J E T P G G N 0 J T H E N Y E Y J J J U N M R R U H M P T N R E J P Y T Y J T F J V E 0 F0 F V G0 G J E0 J J L E E N J V0 E E P H F R R N H G L N F M N V R M W J T T SE OF FG-NVII-MP UH SE OF FG-NVII-MP UH u/.v_ u/.v_ u/.v_ u/.v_ u/0v_ u/0v_ u/0v_ u/0v_.u/.v_.u/.v_.u/0v_.u/0v_ H00H H00H.u/0V_.u/0V_ U_ U_.u/0V_.u/0V_.u/0V_.u/0V_ H00H H00H.u/0V_.u/0V_.u/.V_.u/.V_.u/0V_.u/0V_.u/0V_.u/0V_ U/.V_0 U/.V_0 R M/F_ R M/F_ R0 K/F_ R0 K/F_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ U_ U_.u/0V_.u/0V_ 0.u/.V_ 0.u/.V_ R.K/F_ R.K/F_ N RT_ONN N RT_ONN R 0_ R 0_.u/.V_.u/.V_ G *SHORT P G *SHORT P 0.u/0V_ 0.u/0V_ R 0K_ R 0K_ R 0_ R 0_.u/0V_.u/0V_.u/0V_.u/0V_ Q MMT0 Q MMT0 U_ U_ *.u/0v_ *.u/0v_.u/.v_.u/.v_ R K_ R K_ R 0_ R 0_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ N.V_UL N.V_UL V0.0V.0V 0.0V W.0V.0V.0V.0V.0V W.0V.0V.0V.0V V.0V.0V U.0V Y.0V W.0V0 Y.0V U.0V U.0V Y0.0V.0V.0V V.0V Y.0V Y0.0V W0.0V V.0V0.0V N.V_VT L.V_UL L.V_UL H.V F.V G.V J.V R J G G R H R M K N H V L P L V F F M E H F M M V F Y G N R V E U E M Y E H PWR/ SE OF UG FG-NVII-MP PWR/ SE OF UG FG-NVII-MP.u/0V_.u/0V_.u/0V_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_ *.u/v_ *.u/v_.u/0v_.u/0v_ R 0K_ R 0K_

14 N,, MXM_PWREN MXM_PWREN MXM_T MXM_LK MXM_PWR_EN.V V Q EV^FS V PWREN#.V_MXM Q EV^FN_NL V_MXM EV^0u/V_0 R0 EV^K_ Q EV^N00E Q EV^N00E Q EV^N00E VTHM_T VTHM_LK MXM_PWREN MXM_PWREN MXM_PWREN R EV^K_ VG_THERM# R *EV^00K_.V V PWREN# Q EV^FN_NL.V_MXM Q EV^FN_NL R V_MXM VG_THERM# *EV^00K_ G S Q0 EV^O LVS_ULK# LVS_ULK LVS_UTX0# LVS_UTX# LVS_UTX# LVS_UTX# LVS_UTX0 LVS_UTX LVS_UTX LVS_UTX LVS_LLK# LVS_LLK LVS_LTX0# LVS_LTX# LVS_LTX# LVS_LTX# LVS_LTX0 LVS_LTX LVS_LTX LVS_LTX LVS_PPEN LVS_LEN LVS_L_RGHT _LK _T VG_HSYN VG_VSYN VG_RE VG_GREEN VG_LUE _LK _T MXM_ EV^0.U/XR/0V_ TV_Y/HTV_Y/TV_VS TV_/HTV_Pr TV_VS/HTV_Pb THERM# SM_T SM_LK EV^MXM_TYPEII LVS RT TV VI / HMI VI- VI- EV^0u/V_0 EV^0.U/XR/0V_ HMI_VI LK# / VI LK# 0 HMI_VI LK / VI LK 0 HMI_VI TX0# / VI TX0# HMI_VI TX# / VI TX# HMI_VI TX# / VI TX# HMI_VI TX0 / VI TX0 HMI_VI TX / VI TX HMI_VI TX / VI TX HMI_VI HP / VI HP 0 *EV^0u/V_0 _LK 0 _T P_L# / IGP/VI LK# P_L / IGP/VI LK P_L# / IGP/VI TX0# P_L# / IGP/VI TX# P_L0# / IGP_/VI TX# P_L / IGP/VI TX0 P_L / IGP/VI TX P_L0 / IGP_VI TX 0 0 P_HP / VI HP/ H_SI / IGP_RSV H_SO / IGP_RSV IGP_RSV / IGP P_UX#/VI T/IGP P_UX/VI LK/IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP RSV RSV IGP_RSV / RSV IGP_RSV / RSV H_LK / RSV H_SYN / RSV RUNPWROK /TT# VI HP VI HP SIN_MXM R R0 R0 HEK IT R R R *EV^0_ EV^0_ *EV^S *EV^0K_ V EV^00K_ EV^00K_ EV^_ MXM_RUNPWROK IN Nvidia MXM VG R NEE TI MXM VG R NO NEE Q EV^N00E Q EV^TYU 0K K R0 V Z_SIN Z_SOUT_MXM Z_ITLK_MXM Z_SYN_MXM PWROK_E, Z_RESET#_MXM, EV^0.U/XR/0V_ V,0. V,. EV^0u/.V_ EV^.u/V_ EV^000p_.V,0. EV^u/0V_ EV^.u/V_ EV^000p_.V,. *EV^00u/.V_ EV^0u/0V_ EV^0u/0V_ EV^.u/V_ dd H for MXM, 0/ lex EV^0K_ EV^0u/V_0 EV^u/0V_ EV^.u/V_ IN, SPIF_MXM 0 0 MXM_ V_MXM V_MXM 0.V_MXM.V_MXM N PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN H_RST# / SPIF / EV^MXM_TYPEII LK_REQ# PEX_RST# PEX_REFLK# PEX_REFLK PEX_RX0# PEX_RX# 0 PEX_RX# 0 PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX0# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX0 PEX_RX PEX_RX 0 PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX0 PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_TX0# PEX_TX# PEX_TX# 0 PEX_TX# 00 PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# 0 PEX_TX# PEX_TX0# PEX_TX# PEX_TX# PEX_TX# 0 PEX_TX# PEX_TX# PEX_TX0 0 PEX_TX PEX_TX 0 PEX_TX 0 PEX_TX PEX_TX 0 PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX0 0 PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX 0 P P PRSNT# PRSNT# R *EV^0_ LK_PIE_MXM# LK_PIE_MXM PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP R PE0_PRSNTX_R R PE_RESET_MXM# PIE_RST0#, LK_PIE_MXM# LK_PIE_MXM PEG_RXN[:0] PEG_RXP[:0] PEG_TXN[:0] PEG_TXP[:0] EV^0_ MXM_PRESENT# PE0_PRSNTX# *EV^0_ Q EV^N00E REV:E change to PMOS V_ON MXM_PWR_EN MXM_PWR_EN MXM_RUNPWROK U EV^TSH0FU MXM_RUNPWROK Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MXM Monday, May, 00 ate: Sheet of

15 RT V V V_RT R0 0 V.u/0V_ OK_INSERT_V LVS amera VG_RE_SYS VG_GRN_SYS VG_LU_SYS RT_RE RT_GRN RT_LU V _PWR V R.K_.u/0V_ *0_.u/0V_ RT_R RT_G RT_ HMILK_ HMIT_ OK_INSERT_V RT_RE RT_GRN RT_LU OK_INSERT_V _L Q TEU R 0/F PWR L_ON RT_RE RT_GRN RT_LU _PWRON# R 0_ mil V _POWERON U SE EN# 00 0p_ U V_SYN V_ YP V_VIEO VIEO_ VIEO_ VIEO_.u/V_ R 0/F_ U SE EN#, M_HMI_LK V RT_SENSE# VSYN HSYN M_HMI_T RTLK RTT RTLK_R RTT_R REV: Modify footprint for -test V u/V_0 EZ^SNTLVPWR 0p_ SYN_OUT SYN_OUT SYN_IN SYN_IN _IN _IN _OUT _OUT V R REV: MOIFY R 0/F_ EZ^SNTLVPWR N M00 R0 R0 R L_ON0X Q L L L VG_RE_SYS VG_RE_OK VG_GRN_SYS VG_GRN_OK VG_LU_SYS VG_LU_OK *NZ^0_ *NZ^0_ *NZ^0_ 0u/V_0 *0_ V 0p_ O0 VG_RE_SYS VG_GRN_SYS VG_LU_SYS L_V RIGHTNESS RN 0_PR L V_RT NHW *LWHN00SQL _L.u/V PWR V_RT VG_RE_OK VG_GRN_OK VG_LU_OK INT_TXULKOUT 0 INT_TXULKOUT- 0 INT_TXUOUT0 0 INT_TXUOUT0-0 INT_TXUOUT 0 INT_TXUOUT- 0 INT_TXUOUT 0 INT_TXUOUT- 0 RT_R RT_G RT_ INT_LVS_EIT 0 INT_LVS_EILK 0 RT_SEN# HS_0/S HS_/S HS_/S HS_/S HS_0/S HS_/S HS_/S HS_/S VSYN_ HSYN_ ONTRST INT_LVS_EILK INT_LVS_EIT R HMILKN HMILKP HMITX0N HMITX0P HMITXN HMITXP HMITXN HMITXP HS_MS HS_0/S HS_/S HS_/S HS_/S HS_SEL_IN HMILKP_ HMILKN_ HMITXP_ HMITXN_ HMITXP_ HMITXN_ HMITX0P_ HMITX0N_ HMILK HMIT RT_SEN# RIGHTNESS OK_INSERT_V HMILKN_ HMILKP_ HMITX0N_ HMITX0P_ HMITXN_ HMITXP_ HMITXN_ HMITXP_ HMILK_ R0 HMIT_ R HMI_HP_ RT_VSYN_OK RT_HSYN_OK M_HMILK M_HMILK# M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# OK_HMILK OK_HMILK# OK_HMITX OK_HMITX# OK_HMITX OK_HMITX# OK_HMITX0 OK_HMITX0# HS_SEL_IN 0 L_V_ON RT_VSYN 0 0 RT_HSYN 0 V_RT 0p_ 0p_ acklight ontrol.k_ V RTLK 0 R R0.K_.K_.K_ V V RTT 0 R EZ^0_ RT_LK_OK R0 EZ^0_ RT_T_OK R V 0mil OK_HMI_LK OK_HMI_T SE L LM0SN 0. LM0SN 0. R0.u/.V_ FUN US 0 H US R LM0SN 0. R0 R 0p_ 0K_ R 0_.u/V_ 0p_ MIL V *0_.u/.V_ M00-0 have internal ohm R _ RIGHTNESS L EI SMus PU HMI V R R R R V 0 0p_ R _ R R R0 R 0 V V R R SEL_IN H L MS H EZ^H00H HMILKN HMILKP HMITX0N HMITX0P HMITXN HMITXP HMITXN HMITXP HMILK HMIT HMI_HP R.u/0V_.u/V_ *.K_ *.K_ *.K_ *.K_ EZ^0_ EZ^0_ EZ^0_ EZ^0_ EZ^.K_ *0_ HS_MS FUN R0 *0_ N RT 0K_ OK (port ) M (port ) FUN I ONTROL R L OK (port ) 00 0p_ R *0_ R 0_ R R R K_ R 0_ R 0_.u/V_ *0_ *0_ *0_.u/V_ R0 U R R 0p_ R 0_ 0 U SL S HP OE# I_EN# RT_EN# P0 P REXT PRE TEST TEST V V V V V V V V EZ^0_ EZ^0_ V V REV: HNGE I LK LK LK LK- SL/S S/S MS 0 0/S /S /S /S TEST_OUT SEL_OUT N TEST_IN SEL_IN.K_.K_ SHELL 0 Shield - Shield Shield 0- K K Shield K- E Remote N LK T V HP ET SHELL IN_ IN_- IN_ IN_- IN_ IN_- IN_ IN_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- V[] V[] V[] V[] V[] V[] V[] V[] [] [] [] [] [] [] [] [] [] [0] OE EZ^PIHMI 0 SL_SINK S_SINK HP_SINK 0 0 PERIOM_PIVPLS *0U R.u/V_ R EZ^.K_ V V 000p_.u/V_ EZ^S V *S EZ^0_ 0K_ 0K_.u/V_ OK_HMILK OK_HMILK# OK_HMITX OK_HMITX# OK_HMITX OK_HMITX# OK_HMITX0 OK_HMITX0#,,,,,, V R *.K_ L_ON V V 0.u/V_ PT_SM MXM_T PLK_SM MXM_LK.u/V_ NHW V M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# M_HMILK M_HMILK# M_HMI_LK M_HMI_T HMI_HP_ R R R R OK_HMILK OK_HMITX OK_HMITX OK_HMITX0 R 00K_ 0.u/V_ OK_HMILK R OK_HMITX R OK_HMITX R OK_HMITX0 R Q PTTT L_LON.u/V_ *0_ EZ^0_ *0_ EZ^0_ R 00K_ V VPU LVS_LON R 00K_ HMI_HP_ V V OK_HMILK# OK_HMITX# OK_HMITX# OK_HMITX0# V L# Q N00E LON# HMIT HMILK LONG 0K_ L_ON V M_HMI_LK M_HMI_T HMI_HP_ LV mil R _ M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# M_HMILK M_HMILK# HMILKN_ HMILKP_ HMITX0N_ HMITX0P_ HMITXN_ HMITXP_ HMITXN_ HMITXP_ HMIT_ HMILK_ mil Q O0 LISHG REV : R Modify connect to U pin0; add R connect from U pin to U Pin L. H00H Q *N00E R 0_ EZ^00/F_ OK_HMILK# EZ^00/F_ OK_HMITX# EZ^00/F_ OK_HMITX# EZ^00/F_ OK_HMITX0# *EZ^.P/V_ *EZ^.P/V_ *EZ^.P/V_ *EZ^.P/V_ 0 Q *N00E N R 0_ R 0K_ USP USP- USP- USP USP- USP INT_TXLOUT0 INT_TXLOUT0- INT_TXLOUT INT_TXLOUT- INT_TXLOUT INT_TXLOUT- INT_TXLLKOUT INT_TXLLKOUT LK LK- HMI ONN R *.K_ Q N00E 0K_ Q N00E Q EZ^N00E R *00K_ R *.K_.0u/V_ R Q N00E S R Q TEU S OK_INSERT_V Q0 SS Q EZ^SS K_ V E_FPK# OK_VI_HP V V RN RN RN RN L 0_ U *Rlamp0M_G 0 0 V U *Rlamp0M_G 0 0 V RN U R V 000p_.u/V_ *Rlamp0M_G 0 0 Monday, May, 00 ate: Sheet of MP_LI# LI#, 0K_ *NZ^0_PR *NZ^0_PR *NZ^0_PR *NZ^0_PR mil.0u/v_ 0 L_V HMI_HP_ 000p_ *NZ^0_PR M_HMI_LK M_HMI_T HMI_HP_ M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# M_HMILK M_HMILK# M_HMILK# M_HMILK M_HMITX0# M_HMITX0 M_HMITX# M_HMITX M_HMITX# M_HMITX M_HMI_T M_HMI_LK Quanta omputer Inc. PROJET : ZY Size ocument Number Rev LVS/RT/TVOUT//VI u/.v_ REV: Modify 0 000p_ *.U/0V_

16 To NEW-R & EXT. US,, PT_SM,, PLK_SM, USON# USP- USP USP- USP USP- USP USP0- USP0 0m.V PT_SM PLK_SM USON# USP- USP USP- USP USP- USP USP0- USP0 VPU N. m V V_S NEW R_ON0X PIE_RST# PPE# NEW_LKREQ# LK_PIE_NEW_# LK_PIE_NEW_ PIE_RXN PIE_RXP PIE_TXN PIE_TXP Fingerprint REV: Modify footprint for -test REV: Modify V RN VSUS L V R *0_ R 0_ 0_PR *LWHN00SQL N Finger_H. luetooth VPU VPU 0mil T_POWER VSUS R R Q O0.u/.V *_ N0 T_POWERON# U RN USP USP 0_PR USP- IR_V USP- L IR US_T_P.u/V_ *LWHN00SQL T_LE L 0mil USPWRP USPWR N TI00G RN *0_PR USP- USP- USP USP, USON# L 0p_ 0u/.V_X. REV: Modify SYUIN_US INT. US IR IRRX_ 0u/0V_ u/0v_ USON# VPU Q0 OE# V Y *NSZPX R 0_ U RTPF IN OUT IN OUT OUT EN# - O# VPU R 0mil USPWR *.K/F_ IRRX PPE#_E R 0_ PPE# REV: Modify LWHN00SQL.u/.V_ u/0v_.u/v_ USPWRP MINI-R V_MINI R 0_ V_MINI_ N _.V _.Vaux _.V _.V _.Vaux _.V V_MINI_ R 0_ V_MINI USP- USP RN L *0_PR LWHN00SQL USP- USP N0 SYUIN_US 0p_ USP USP- USP USP- 0 REV: Modify PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_TV LK_PIE_TV# TV_LKREQ# USP USP- RF_LE# R 0_ R 0_ R 0_ PIE_WKE_WL_R_# R 0_ RF_LE#_ USP_ USP-_ MINI_SMT MINI_SMLK PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_TV LK_PIE_TV# WKE_WL_#.V 0 USP USP- _LE_WPN# _LE_WLN# _LE_WWN# _US US_- _SM_T _SM_LK _PETp0 _PETn0 _PERp0 _PERn0 _PERST# _REFLK _REFLK- _LKREQ# _WKE# _LE_WPN# _LE_WLN# _LE_WWN# _US US_- _SM_T _SM_LK 0 _PETp0 _PETn0 _PERp0 _PERn0 0 _PERST# _REFLK _REFLK- _LKREQ# _WKE# RF_LE#_ USP0_ USP0-_ MINI_SMT MINI_SMLK PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_MINI LK_PIE_MINI# WKE_WL_# PIE_WKE_WL_R_# R 0_.V R 0_ R 0_ RF_LE# USP0 USP0- PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_MINI LK_PIE_MINI# MINI_LKREQ# V R 0_ V for WWN card is. V_MINI.u/.V_.V V.u/.V_ R0 0_.u/.V_.u/.V_ 00m, mil V_TV-R REV: Modify.u/V_ MLVG00R MLVG00R MLVG00R MLVG00R R0 0_ V_MINI_.u/V_.u/V_.u/V_ V.u/V_ R0 0K_ V_MINI_.u/V.V _.V _.V _.V _.V _.V.u/V_.u/V_.u/.V_.u/.V_.u/V_,, PT_SM Q N00E MINI_SMT,,,,,, LFRME# L L L L0 ebug, LP_RST_E# LP_LK_EUG R 0_ R *0_ R00 *0_ R *0_ R0 *0_ R0 R0 V_MINI *0_ *0_ R0 0_ TV use V LFRME#_R_ L_R_ L_R_ L_R_ L0_R_ LP_RST_E#_R_ LP_LK_EUG_R_ V_MINI_R_ 0 N N N N N N -Link_RST -Link_T -Link_LK N N N N N N 0 N N -Link_RST 0 -Link_T -Link_LK N N V_MINI_R_ LFRME#_R_ L_R_ L_R_ L_R_ L0_R_ LP_RST_E#_R_ LP_LK_EUG_R_ R R 0_ R *0_ R *0_ R *0_ R *0_ R R *0_ *0_ *0_ V_MINI LFRME#,, L, L, L, L0, ebug LP_RST_E#, LP_LK_EUG,, PIE_WKE# VSUS Q *TEU R.K_ PIE_WKE_WL_R_#,, PLK_SM V R R *0_ *0_ R0 0K_ Q N00E MINI_SMLK RF_EN V_TV-R R *0_ R0 0_ TV use V.u/V RF_EN V_TV-R_R_ N N _W_ISLE# _T_HLK _T_T _W_ISLE# N N _T_HLK _T_T SP@QUSR-00-0N_P _RF_EN V_TV-R_R_ *.u/v_ R0 0_ R *0_ RF_EN REV: Modify V_TV-R RF_EN *0P_ R *_ PITOR on Module LP_LK_EUG For EMI ouble Stack MINI R MOULE '' TV card MOULE '' Wireless card Quanta omputer Inc. PROJET : ZY Size ocument Number Rev NEW&MINI&TV R/US/T/IR Monday, May, 00 ate: Sheet of

17 V ST N ST_H S S S S S S S S S V R 0_ S S S0 0 S S S S S S S S S S0 0 S S O (ST) N - - P V V 0 M --L_Serial_T ST_RXN_ ST_RXP_ ST_P V_O V_O R 00 ST_TXN0 ST_RXN0_ ST_RXP0_ K_.VST VST.VST ST_RXN0_ VN VP VST VN VP VST ST_TXP0 H H ST_RXP0_ REV:E add ES ST_RXN H H ST_RXP 00mil 00mil.0u/V_.0u/V_ 0 R 0_ VST u/.V_.u/.V_.u/V_ U M-0SO H H.0u/V_.0u/V_ V 0.u/V_ ST_TXP ST_TXN ST_RXN ST_RXP 0 ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 0.0u/V_.0u/V_ TP ONN FN V.u/.V_.u/.V_.u/V_ TPT TPLK R0 0K_ ST V Q N00E N ST_H S S S S S S S S S R R R 0_ V S S S0 0 S S S S S S S S S S0 0 S S R 0K_.K_ L L V ST_RXN_ ST_RXP_.VST 00mil VST 00mil VST 0 00u/.V_.u/.V_.K_ V K0LL 0m K0LL 0m EV^S S ST_TXP R 0_.u/V_.VST VG_THERM# PUFN#_ON U M-0SO H H.0u/V_.0u/V_ V.u/V_ 0p_ 0 R 0_.u/V_ TP_V TPT_R TPLK_R 0p_ ST_TXN V ST_TXP ST_TXN ST_RXN ST_RXP 00 0.u/.V_.u/.V_.u/V_ 0.0u/V_.0u/V_ mil N TOUHP_M REV: Modify R 0K_ LE SUSLE# PWR_V R 0_ VPU PWRLE# LE_/O REV: Modify *PESV0SL_ES REV: Modify TLE# ST_LE# To Power/ REV: Modify NSWON# *PESV0SL_ES To Switch/ *PESV0SL_ES LE *PESV0SL_ES LE V R 0K_ NSWON# MX0 MX MX MX MY0 MY NUMLE# PSLE# PWRLE# SUSLE#, LI# RF_LE# T_LE MX MX MX MX MX MY0 RE_KEY VPU V Power LE attery LE TLE0# LE_G/O *PESV0SL_ES R NSWON# MX0 MX MX MX MY0 MY NUMLE# PSLE# ST_LE#_R PWRLE# SUSLE# LI# T_V VSUS V Power/Suspend: lue/ mber *0_ ST_LE#_R U TSH0FU V N RF_LE# T_LE MX MX MX MX MX MY0 RE_KEY 0 0 R 0_ REV: Modify N SW-0P FUNTION_P REV: Modify VPU R0 0_ 0 0u/.V_.u/V_.u/V_.u/V_ 00u/.V_ U *M-0SO ST_TXP H H ST_TXN VN VP V_O ST_RXN H H ST_RXP REV:E add ES.u/V_.u/.V_ PUFN# V U0 VO FON# VSET G G pin have internal PU to u/.v_ FNSIG TH_FN_POWER 0 MIL.0u/V_ 000p_ 0 FN_TRL N FN Quanta omputer Inc. PROJET : ZY Size ocument Number Rev H/O/LE/SW/TP/FN ate: Monday, May, 00 Sheet of