Quanta R7X - Schematics.

Transcription

1 +V/+V S +.V PG. PG. PU ore RL harge PG. +.VS/+.V PG.~ PG. PG. is-harge PG. +VGORE PG. +. VG PG. +.V/+./ + VG PG. / K LNE K ITE TP PG. SOIMM Max. G RTS RX M SYSTEM IGRM PG. SOIMM Max. G PG. PI-E x H O LNE PI-E x LNE ard Reader ROM PG. PG. WLN T OMO PG. PG. FN PG. R L hannel ST ST LN US. RTLEH PORT ccelerometer PG. SMUS PG. PG. PG. PG. MT/s MT/s R L hannel LP TPM SL (option) M mm X mm P RIHLN pin upg TP W P UMI PG.~ M FH OLTON M.mm X.mm PG. P pin FG TP.W PG.~ UIO OE L-G PI-E x ep (.Gb/s) I (.Gb/s) P RT US. PORT, PG. US. P Port M US. Ports X PG. PORT, US. Ports PG. Speaker Sun XT mm X mm bit M package W ep OMO JK HP/MI IGITL MI PG. PG. PG. PG.~ R MHz VRM Mxx or GHz Mxx PORT PG.~ RELTEK R P to LVS onverter PGE Webcam PORT LVS Interface PG. PORT Touch Screen (option) PG. ep LVS HMI RT PG. PG. PG. PG. Stackup TOP GN IN IN V OT PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom LOK IGRM ate: Tuesday, March, Sheet of

2 TO WLN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_RXP_WLN PIE_RXN_WLN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN +.V_VP / For omal. PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN R /F_ UF PI EXPRESS P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN P_GFX_RXP P_GFX_TXP P_GFX_RXN P_GFX_TXN Y P_GFX_RXP P_GFX_TXP Y Y P_GFX_RXN P_GFX_TXN Y Y P_GFX_RXP P_GFX_TXP Y W P_GFX_RXN P_GFX_TXN W W P_GFX_RXP P_GFX_TXP W W P_GFX_RXN P_GFX_TXN V W P_GFX_RXP P_GFX_TXP V V P_GFX_RXN P_GFX_TXN V V P_GFX_RXP P_GFX_TXP V U P_GFX_RXN P_GFX_TXN U U P_GFX_RXP P_GFX_TXP U U P_GFX_RXN P_GFX_TXN T U P_GFX_RXP P_GFX_TXP T T P_GFX_RXN P_GFX_TXN T T P_GFX_RXP P_GFX_TXP T R P_GFX_RXN P_GFX_TXN R R P_GFX_RXP P_GFX_TXP R R P_GFX_RXN P_GFX_TXN P R P_GFX_RXP P_GFX_TXP P P P_GFX_RXN P_GFX_TXN P P P_GFX_RXP P_GFX_TXP P N P_GFX_RXN P_GFX_TXN N N P_GFX_RXP P_GFX_TXP N N P_GFX_RXN P_GFX_TXN M N P_GFX_RXP P_GFX_TXP M M P_GFX_RXN P_GFX_TXN M M P_GFX_RXP P_GFX_TXP M P_GFX_RXN P_GFX_TXN E E P_GPP_RXP P_GPP_TXP P_GPP_RXN P_GPP_TXN P_GPP_RXP P_GPP_TXP P_GPP_RXN P_GPP_TXN P_GPP_RXP P_GPP_TXP P_GPP_RXN P_GPP_TXN P_GPP_RXP P_GPP_TXP P_GPP_RXN P_GPP_TXN G G G P_UMI_RXP P_UMI_TXP G G P_UMI_RXN P_UMI_TXN F G P_UMI_RXP P_UMI_TXP F F P_UMI_RXN P_UMI_TXN F F P_UMI_RXP P_UMI_TXP F E P_UMI_RXN P_UMI_TXN E E P_UMI_RXP P_UMI_TXP E P_UMI_RXN P_UMI_TXN P_ZVP G H P_ZVP P_ZVSS GRPHIS GPP UMI-LINK Richland PU PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PEG_TXP_ PEG_TXN_ PIE_TXP_ PIE_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ UMI_TXP_ UMI_TXN_ P_ZVSS R *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ UM can remove.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_.u/v_ /F_ PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PEG_TXP PEG_TXN PIE_TXP_WLN PIE_TXN_WLN TO WLN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN PEG X HT+ onnector for ebug only +V R *_/S R K/F_ +.V R K/F_ / For omal. VI Override ircuit SV SV OOT VOLTGE VFIX_+V =V/GN VFIX_+V =OPEN..,, PU_RST# PU_PWRG PU_RST# PU_PWRG U GN Y V Y PU_RST_L_UF PU_PWROK_UF LVGGW MV, remove it for cost down J PU_TI PU_TK PU_TMS PU_TRST# PU_REQ# RY RY RY close to HT debug HEER R R R R R K/F_ / For omal. R R R K/F_ K/F_ K/F_ K/F_ *K_ *K_ *K_ Reserve for debug +.VSUS +.VSUS PU_TEST PU_TEST TP PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_TEST PU_TEST PU_RST_L_UF PU_LT_RST_HTP# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO PU_PWROK_UF RY RY RY HT ONN --p-l SV SV SV SV PU_PWRG PU_PWRG have pull up ohm to +.V on page Rd R Re R Rf R *_/S *_/S *_/S PU_SV PU_SV PU_PWRG_SVI_REG PU_SV PU_SV PU_PWRG_SVI_REG PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom PU /(PIE/UMI/GPP/HT) ate: Tuesday, March, Sheet of

3 Place close to PU within " Soldermask openings for all bottom side vias/tps under FS Reserved for M suggest Reserved / For omal. M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M +M_ZVIO +MEMVREF_PU +MEMVREF_PU M S# M S# M S# M M M M M M M M M M M M M M M M M S# M S# M S# M M M M M M M M M M M M M M M M M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M KE M KE M OT M OT M S# M S# M RS# M RST# M S# M WE# M EVENT#, M LKP M LKN M LKP M LKN M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M LKP M LKN M LKP M LKN M RS# M OT M OT M S# M RST# M WE# M EVENT# M KE M KE M S# M S# M Q[..] M Q[..] M [:] M [:] R_VTTREF,, +.VSUS,,,,,,, +VS,,,,,,,,,,,, M M[..] M M[..] M S# M S# M S# M S# M S# M S# +MEMVREF_PU +.VSUS +.VSUS +.VSUS +.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RX N PU /(R MEM I/F) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RX N PU /(R MEM I/F) ustom Tuesday, March, Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RX N PU /(R MEM I/F) ustom Tuesday, March, P/V_ P/V_ R K/F_ R K/F_ MEMORY HNNEL Richland PU U M_ZVIO W M_VREF W M_EVENT_L T M_RESET_L H M_WE_L W M_S_L W M_RS_L V M_S_L M_S_L V M_OT M_OT Y M_KE H M_KE H M_LK_L R M_LK_H R M_LK_L T M_LK_H T M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L E M_QS_H E M_QS_L H M_QS_H J M_QS_L H M_QS_H G M_QS_L H M_QS_H G M_M M_M M_M M_M M_M F M_M E M_M J M_M E M_NK L M_NK U M_NK U M_ L M_ L M_ M_ L M_ M M_ U M_ M M_ N M_ N M_ N M_ N M_ P M_ P M_ R M_ U M_T Y M_T M_T M_T Y M_T M_T M_T Y M_T M_T M_T M_T Y M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T Y M_T M_T Y M_T M_T M_T M_T E M_T M_T M_T M_T M_T F M_T E M_T H M_T F M_T G M_T G M_T E M_T G M_T H M_T G M_T E M_T G M_T H M_T J M_T F M_T H M_T F M_T H M_T H M_T G M_T J M_T E M_T F M_T H M_T E M_T F M_T F M_T H M_T J M_T H M_T J M_T E M_ R P/V_ R K/F_.U/V_ R K/F_ MEMORY HNNEL Richland PU U M_EVENT_L T M_RESET_L J M_WE_L V M_S_L V M_RS_L V M_S_L Y M_S_L V M_OT Y M_OT W M_KE J M_KE J M_LK_L P M_LK_H P M_LK_L R M_LK_H R M_QS_L G M_QS_H H M_QS_L G M_QS_H G M_QS_L F M_QS_H G M_QS_L G M_QS_H G M_QS_L M_QS_H M_QS_L M_QS_H E M_QS_L M_QS_H E M_QS_L M_QS_H M_M M_M H M_M G M_M F M_M M_M M_M M_M M_NK K M_NK T M_NK U M_ K M_ K M_ W M_ K M_ L M_ U M_ L M_ M M_ M M_ M M_ M M_ N M_ N M_ P M_ P M_ T M_T F M_T E M_T F M_T G M_T M_T G M_T M_T G M_T M_T F M_T G M_T G M_T H M_T E M_T E M_T F M_T M_T M_T M_T M_T H M_T E M_T H M_T E M_T E M_T H M_T F M_T G M_T G M_T F M_T H M_T G M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T M_T M_T M_T M_T M_T M_T E M_T M_T M_T P/V_ R *_ R./F_

4 Thermal FH_THERMTRIP# +.VSUS Q METR-G R K/F_ PU_THERMTRIP# THERMTRIP# shutdown temperature 度 R K/F_ MEKV- METR-G Q R EPWROK K/F_ +V TP TP TP TP / For omal, close to PU. E_WRST# EPWROK, Place caps with PU < inch route PIE as ohm +/- % FH_PROHOT# H_PROHOT# PU_PROHOT# 可可可 input or output 可 Low 時 PU 會會 P - STTE R R *_/S *_/S to E reserve only P/V_ U NLOG/ISPLY/MIS EP_TXP.U/V_ INT_eP_TXP_ L EP_UXP EP_TXN.U/V_ INT_eP_TXN_ L P_TXP P_UXP P_TXN P_UXN EP_UXN P output to ep to LVS converter EP_TXP.U/V_ INT_eP_TXP_ K E PU_P_UXP_.U/V_ PU_P_UXP EP_TXN.U/V_ INT_eP_TXN_ K P_TXP P_UXP PU_P_UXN_.U/V_ P_TXN P_UXN E PU_P_UXN TP K SVO_LK EP_UXN R SVO_LK TP K P_TXP P_UXP SVO_T P_TXN P_UXN SVO_T HMI isplay port power.v min.v max :.v TP J E TP J P_TXP P_UXP P_TXN P_UXN E isplay port power.v min.v max :.v PU_P_UXP R.U/V_ PU_P_TXP_ H F PU_P_TXP.U/V_ PU_P_TXN_ H P_TXP P_UXP PU_P_UXN R PU_P_TXN P_TXN P_UXN F.U/V_ PU_P_TXP_ H G PU_P_UXP_ R PU_P_TXP P output to Hudson-M.U/V_ PU_P_TXN_ H P_TXP P_UXP PU_P_TXN P_TXN P_UXN G PU_P_UXN_ R for VG translator interface.u/v_ PU_P_TXP_ G EP_HP PU_P_TXP EP_HP,.U/V_ PU_P_TXN_ G P_TXP P_HP FH_VG_HP PU_P_TXN P_TXN P_HP E FH_VG_HP HMI_HP_ON HMI_HP_ON.U/V_ PU_P_TXP_ F P_HP PU_P_TXP.U/V_ PU_P_TXN_ F P_TXP P_HP E PU_P_TXN P_TXN P_HP F +.VSUS.U/V_ PEG_HMI_TXP P_HP G L _TX_HMI+.U/V_ PEG_HMI_TXN L P_TXP PU_LVS_LON _TX_HMI- P_TXN P_LON / HMI change to P for omal. PU_ISP_ON PU_LVS_LON PU_ISP_ON.U/V_ PEG_HMI_TXP P_IGON L PU_PST_PWM _TX_HMI+ P output to PEG_HMI_TXN PU_PST_PWM.U/V_ L P_TXP P_VRY_L _TX_HMI- P_TXN P_UX_ZVSS R /F_ R HMI connector.u/v_ PEG_HMI_TXP K P_UX_ZVSS *./F TX_HMI+.U/V_ PEG_HMI_TXN K P_TXP _TX_HMI- P_TXN TEST note --HMI P&N can not swap M PU_TEST M_TEST.U/V_ PEG_HMI_TXP J TEST N TP PU_TEST _TX_HMI+.U/V_ PEG_HMI_TXN J P_TXP TEST F PU_TEST_P TP _TX_HMI- P_TXN TEST TP G PU_TEST_P M_TEST ONNETION T LK_PU_P E TEST H TP PU_TEST_P R LK_PU_P Note: LK_PU_HLKP/N is MHZ SS LK_PU_N LKIN_H TEST J TP PU_TEST_P./F_ LK_PU_N LKIN_L TEST F TP PU_TEST PU_TEST LK_P_P TEST G PU_TEST LK_P_P PU_TEST Note: LK_P_NSSP/N is MHZ non-ss LK_P_N ISP_LKIN_H TEST J PU_TEST_SNLK LK_P_N ISP_LKIN_L TEST To M HT H PU_TEST_SNLK TP TP SV TEST PU_TEST_H SV SV SV TEST_H E PU_TEST_L TP SV TP PU_TEST_H +.V R *K/F_ SV TEST_L TP R *_/S PU_SVT_R TEST_H L M PU_TEST_L PU_SVT SVT TEST_L TP / For omal. PU_SI G TEST_H P R PU_SI H SI TEST_L K M_TEST MTIVE_L controls +.V R _ SI TEST entry and exit from the PU_RST# F TEST_H T N PU_TEST_L, PU_RST# sleep and power states PU_PWRG RESET_L TEST_L PU_TEST, PU_PWRG +.V R _ PWROK TEST PU_PROHOT# W FSR R K/F_ +VS PU_TEST PU_THERMTRIP# E PROHOT_L FSR MTIVE_L MTIVE_L PU_LERT +.VSUS R K/F_ F THERMTRIP_L MTIVE_L R *K/F_ LERT_L +.V P PU_THERM R K/F_ +.VSUS SI PU_TEST TP PU_TI H TEST R PU_THERM PU_TEST PU_TI PU_TO J TI TEST TP PU_TEST_SNLK PU_TO PU_TK F TO M internal test only PU_TEST_SNLK PU_TK PU_TMS G TK PU_TEST_H PU_TMS change to short-pad PU_TRST# F TMS Y PU_TRST# FSR signals is for detect PU TYPE and protect it. PU_RY G TRST_L RSV_ PU_RY FSR PU this pin is N. / For omal. PU_REQ# H RY RSV_ Y PU_REQ# REQ_L RSV_ FSR PU this pin is LOW K VSS_SENSE RSV_ can remove it at MP R *_/S PU_V_RUN_F_L VP_F_H VSS_SENSE VP_F_H PU_VN_RUN_F_H VP_SENSE PU_VN_RUN_F_H VIO_F_H VN_SENSE VIO_F_H PU_V_RUN_F_H VIO_SENSE PU_V_RUN_F_H VP_F_H V_SENSE VR_SENSE PU_PROHOT# ISPLY PORT +.V R *K/F_ +.VSUS R K/F_ VRHOT reserve for leakage current verify R / For omal. *_/S PU_PROHOT# dd R for verify this solution,,,, MLK MT EP_UXP R *K/F_ LVS EP_UXN R *K/F_ +V EP_UXP R.K_ VG MLK MT Q METR-G +.VSUS R K/F_ Q METR-G MEKV- PU_TEST / For omal. TEST PU FOR INTERNL TEST P FOR USTOMER / For omal. R *_ R K/F_ R.K_ K/F_ K/F_.K_.K_ R R R R R PU_SI PU_SI +V /F_ K/F_ K/F_ K/F_ K/F_ /F_ +.VSUS +.VSUS R /_ R */_ +.V Q *MENE GPU_OVT# MEKV- ISPLY PORT ISPLY PORT JTG TRL SER. LK SENSE Richland PU TEST ISPLY PORT MIS. RSV R K/F_ R K/F_ THERMTRIP# R _ GPU_PWROK,,, FH_THERMTRIP# THRM_LERT_HW# MEKV- SI change from R to iode for solve +VS leakage VG TEMP_ FIL function is active Hi +V,,,,,,,,,,,,,,,,,,,, +.V, +.V,,,,,, +VS,,,,,,,,,,, +VPU,,,,,, +.VSUS,,,,,,, PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom PU /(isplay/misc) ate: Tuesday, March, Sheet of

5 PIN NME V VN PU POWER TLE NET NME +V_ORE +VN_ORE VOLTGE +.V?? EMI suggestion +V_ORE VIO VP +.VSUS +.V_VP +.V +.V E P/V_ E *P/V_ E *P/V_ VR V +.V +.V_VR +.V_V.U/V_ +.V +.V / For omal. U/.VS_ / For omal. +VN_ORE / For omal. +VN_P. Up to VIO.U/V_ R U/.V_.U/V_ U/.VS_.U/V_ +.V_VP VP = *_/S U/.V_ P/V_ P/V_.U/V_ U/.VS_ U/.V_ P/V_.U/V_ U/.V_ P/V_.U/V_ +.V_VP U/.V_ +VN_ORE +.VSUS / For omal. U/.V_.U/V_ P/V_ +V_ORE U F H V_ J V_ J V_ P V_ P V_ J V_ J V_ J V_ K V_ K V_ K V_ M V_ K V_ V V_ V V_ V V_ F V_ L V_ V V_ W V_ T V_ Y V_ V_ V_ V_ R V_ P V_ K V_ H V_ M V_ V_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ E VN_ E VN_ VN_ VN_ H K VIO_ J VIO_ K VIO_ K VIO_ L VIO_ L VIO_ L VIO_ M VIO_ M VIO_ M VIO_ N VIO_ N VIO_ N VIO_ P VIO_ P VIO_ P VIO_ VIO_ VIO_ H H VP H VP H VP H VP VP V V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_ VN_P VN_P VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VR VR VR VR R T H G U W W W W W E L Y M N N T T U U Y Y Y F F F L E K K T T U U U Y T R R R V V V W W W Y G G H H H +V_ORE U/.V_ U/.V_.U/V_ Maximum Ispike Maximum INspike +VN_ORE +VN_P +.VSUS U/.VS_ / For omal. EOUPLING between PROESSOR and IMMs cross VIO and VSS split / For omal. If the VSS plane is cut to create a VIO plane, ceramic capacitors are connected across the VIO and VSS plane split as follows VR =. ( Up to ) +.V_VR_ U/.V_ U/.V_ U/.VS_.U/V_ U/.VS_ U/.V_ U/.V_ U/.V_ P/V_ +.VSUS U/.VS_ U/.V_.U/V_ R U/.VS_ U/.VS_ P/V_ U/.VS_.U/V_.U/V_ U/.VS_ *_/S U/.VS_.U/.V_ +.V.U/V_ P/V_.U/.V_.U/V_ P/V_.U/.V_.U/.V_ UE J L VSS_ VSS_ R VSS_ VSS_ W VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ VSS_ F VSS_ VSS_ H VSS_ VSS_ H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ VSS_ E VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ F VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ G VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ J VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ K VSS_ VSS_ VSS_ VSS_ L VSS_ VSS_ L VSS_ VSS_ M VSS_ VSS_ F VSS_ VSS_ V VSS_ VSS_ V VSS_ VSS_ W VSS_ VSS_ W VSS_ VSS_ W VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ K VSS_ VSS_ F VSS_ VSS_ G VSS_ VSS_ H VSS_ VSS_ J VSS_ VSS_ VSS_ Richland PU E E E M N N N R R T T U U U U V E E E E E E F F F F F F F F G G H H H H H P W P E K W.U/.V_.U/.V_ P/V_ P/V_ Richland PU.U/.V_.U/V_ P/V_ P/V_ P/V_ +.V L PYT-Y-N(,) V=. +.V_V.U/.V_.U/V_ P/V_ PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom PU /(POWER/GN) ate: Tuesday, March, Sheet of

6 remove PIE_RST# from M recommend U TP PIE_RST# TP RI# R PIE_RST#/GEVENT# USLK/M_M_M_OS G W RI#/GEVENT# US_ROMP_S R.K/F_ SUS# T SPI_S#/GE_STT/GEVENT# US_ROMP SUS# SUS# W SLP_S# H SUS# NSWON# J SLP_S# US_FSP/GPIO NSWON# FH_PWRG N PWR_TN# US_FSN H FH_PWRG PWR_GOO OLTON-M H TP FH_TEST T Part of US_FSP/GPIO +V / For omal. TP FH_TEST T TEST US_FSN H FH_TEST V TEST/TMS H SM_RUN_LK TP R.K_ GEVENT# internal pull Hi.K to +V E_GTE E TEST US_HSP E_GTE to R SMUS GEVENT# internal pull Hi.K to +V E_RIN# G GIN/GEVENT# US_HSN G E_RIN# R.K_ SM_RUN_T TP FH_PME# R KRST#/GEVENT# K GEVENT# internal pull Hi.K to +V SIO_EXT_SMI# PME#/GEVENT# US_HSP +VS SIO_EXT_SMI# GEVENT# internal pull Hi.K to +VS GEVENT# T LP_SMI#/GEVENT# US_HSN J R *_/S SIO_EXT_SI# SYS_RST# U LP_P#/GEVENT# G USP+ USP+ R *K_ PIE_WKE# no need to pull PIE_WKE# K SYS_RESET#/GEVENT# US_HSP USP-, PIE_WKE# USP- Left side US ombo./.. Hi resistor from check list *P/V_ V WKE#/GEVENT# US_HSN F J SYS_RST# FH_THERMTRIP# R IR_RX/GEVENT# K USP+ FH_THERMTRIP# USP+ SYS_RST# internal GEVENT# internal pull Hi K to +VS W_PWRG USP- +V R K/F_ F THRMTRIP#/SMLERT#/GEVENT# US_HSP USP- Left side US ombo./.. *SOLERJUMPER- W_PWRG US_HSN K K pull up RSMRST# U RSMRST# RSMRST# US_HSP LK_REQ# internal pull Hi.K to +V LK_PIE_REQ# G US_HSN LK_PIE_REQ# LK_REQ# internal pull Hi.K to +V PIE_LKREQ_LN# E LK_REQ#/ST_IS#/GPIO E PIE_LKREQ_LN# E LK_REQ#/ST_IS#/GPIO US_HSP USP+ USP- amera US F SMRTVOLT/ST_IS#/GPIO US_HSN F +VS H LK_REQ#/ST_IS#/GPIO USP+ G ST_IS#/FNOUT/GPIO US_HSP TP USP- TP R K/F_ SL R *_/S FH_GPIO F ST_IS#/FNIN/GPIO US_HSN Z_SPKR SM_RUN_LK SPKR/GPIO H,, SM_RUN_LK R K/F_ S SM_RUN_T SL/GPIO US_HSP,, SM_RUN_T SM_PH_LK T S/GPIO US_HSN G SM_PH_LK R.K_ SL SM_PH_T R SL/GPIO SM_PH_T LK_REQ# internal pull Hi.K to +V PIE_LKREQ_WLN# G S/GPIO US_HSP PIE_LKREQ_WLN# S LKREQ# G LK_REQ#/FNIN/GPIO US_HSN R.K_ LL# Not Implemented,left unconnected. TP LL# J LK_REQ#/FNOUT/GPIO F This pin is used to TP SMRTVOLT G IR_LE#/LL#/GPIO US_HSP SM_PH_LK power down VG VG_P V SMRTVOLT/SHUTOWN#/GPIO US_HSN E R.K_ R *_/S VG_POWER_OWN regulators when RT TP GE_LE W R_RST#/GEVENT#/VG_P USP+ R.K_ SM_PH_T Y GE_LE/GPIO US_HSP no connected SPI_HOL# USN- V SPI_HOL#/GE_LE/GEVENT# US_HSN GE_LE/GEVENT# USP+ R *.K_ FH_THERMTRIP# TP F GE_STT/GEVENT# US_HSP LK_REQG#/GPIO/OSIN/ILEEXIT# US_HSN USP- WLN Min-ard *.U/V_ TP M US_HSP PIE_LKREQ_WLN# R LINK/US_O#/GEVENT# US_HSN R *K/F_ TP O_PLUGIN# T US_O#/IR_TX/GEVENT# E O_PLUGIN# USP+ R K/F_ NSWON# GEVENT# internal pull Hi.K to +VS O_#_FH P US_O#/IR_TX/GEVENT# US_HSP O_#_FH USP- Right side US. onnector F US_O#/IR_RX/GEVENT# US_HSN E TP R *K/F_ O_#_FH GEVENT# internal pull Hi.K to +VS / For omal. TP FH_JTG_TK P US_O#/_PRES/TO/GEVENT# USSS_LRP R K/F_ TP FH_JTG_TI J US_O#/TK/GEVENT# USSS_LRP USSS_LRN For Zero O +FH_V SSUS_S reserve TP FH_JTG_RST# T US_O#/TI/GEVENT# USSS_LRN R K/F_ US_O#/SPI_TPM_S#/TRST#/GEVENT# US_SS_TXP US_SS_TXN R *K/F_ Z_LK_R Z_SOUT_R Z_ITLK US_SS_RXP H audio TP Z_SIN Z_SOUT US_SS_RXN US. Not Implemented: left unconnected. interface is Z_SIN Y Z_SIN/GPIO TP +V_S voltage Z_SIN_R Y Z_SIN/GPIO US_SS_TXP TP Z_SIN_R Y Z_SIN/GPIO US_SS_TXN TP Z_SYN_R Z_SIN/GPIO E Z_RST#_R E Z_SYN US_SS_RXP Z_RST# US_SS_RXN F To zalia F US_TX+ TP K US_SS_TXP J PS_T/S/GPIO US_SS_TXN G US_TX- TP Z_SOUT_R R _ J PS_LK/E/SL/GPIO H Z_SOUT_UIO SPI_S#/GE_STT/GPIO US_SS_RXP US_RX+ US_RX- Z_SYN_R R _ US_SS_RXN G Z_SYN_UIO T_OMO_OFF# T_OMO_OFF# J US_TX+ Z_LK_R R _ PSK_T/GPIO US_SS_TXP IT_LK_UIO US_TX- VG_RST PSK_LK/GPIO US_SS_TXN H VG_RST Z_RST#_R R _ VG_ON_S PSM_T/GPIO J Z_RST#_UIO VG_ON_S PSM_LK/GPIO US_SS_RXP US_RX+ US_RX- Z_SIN US_SS_RXN K Z_SIN F E KSO_/GPIO H SL F KSO_/GPIO SL/GPIO G S KSO_/GPIO S/GPIO G SL SL of a TSI-capable PU's E KSO_/GPIO SL_LV/GPIO G S thermal bus,pulled up to LK_REQ# already KSO_/GPIO S_LV/GPIO E PU_VIO. Resistor value Pure UM can remove internal pull up.k J KSO_/GPIO E_PWM/E_TIMER/GPIO H H KSO_/GPIO E_PWM/E_TIMER/GPIO J E_PWM verified in the relevant PU E_PWM LKREQ# G KSO_/GPIO E_PWM/E_TIMER/WOL_EN/GPIO H design guide. VG_REQ *MEKV- KSO_/GPIO E_PWM/E_TIMER/GPIO No need for GPIO K KSO_/GPIO K KSO_/GPIO EMEE KSI_/GPIO K KSO_/GPIO TRL KSI_/GPIO F KSO_/GPIO KSI_/GPIO F KSO_/GPIO KSI_/GPIO E KSO_/X/GPIO KSI_/GPIO KSO_/X/GPIO KSI_/GPIO KSO_/X/GPIO KSI_/GPIO F KSO_/X/GPIO KSI_/GPIO H UIO PI / WKE UP EVENTS GPIO US O US MIS US. US. US. olton-m PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom FH /(GPIO/US/Z) ate: Tuesday, March, Sheet of

7 , LN_PIE_RST# GPU_RST# Place these PIE coupling cap close to FH TO LN TO LN R_PIE_RST# MINI_PIE_RST# PIE_TXP_R PIE_TXN_R PIE_TXP_LN PIE_TXN_LN Pure UM can remove PIE_RXP_R PIE_RXN_R PIE_RXP_LN PIE_RXN_LN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_RXP UMI_RXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN UMI_TXP UMI_TXN LK_P_P LK_P_N PIE_RXP_R PIE_RXN_R PIE_RXP_LN PIE_RXN_LN change to shortpad LK_PU_P LK_PU_N LK_VG_P LK_VG_N *P/V_ LK_PIE_WLN LK_PIE_WLN# LK_PIE_RP LK_PIE_RN RP *X LK_VG_FH_P LK_VG_FH_N Note: LK_FH_SRP/N is MHZ SS Note: LK_PIE_TRVISP/N is MHZ non-ss Note: LK_P_NSSP/N is MHZ non-ss Note: LK_PU_HLKP/N is MHZ SS Note: LK_PIE_VGP/N is MHZ SS Note: GPP_LK(:)P/N is MHZ SS capable LK_PIE_LNP LK_PIE_LNN +.V_PIE_VR PH_XTL_IN P/V_ P/V_ P/V_.U/V_.U/V_ +.V_KV *P/V_ *P/V_ R _ PIE_RST# E R * RST# PIE_RST# _RST#.U/V_ UMI_RXP_ E.U/V_ UMI_RXN_ E UMI_TXP.U/V_ UMI_RXP_ UMI_TXN.U/V_ UMI_RXN_ UMI_TXP.U/V_ UMI_RXP_ UMI_TXN.U/V_ UMI_RXN_ UMI_TXP.U/V_ UMI_RXP_ UMI_TXN.U/V_ UMI_RXN_ UMI_TXP UMI_TXN UMI_RXP UMI_RXN UMI_RXP Y UMI_RXN Y UMI_RXP Y UMI_RXN Y UMI_RXP UMI_RXN R /F_ PIE_LRP_FH F R K/F_ PIE_LRN_FH F PIE_LRP PIE_LRN.U/V_ PIE_TXP_R_ V PIE_TXN_R_ V GPP_TXP.U/V_ PIE_TXP_ W GPP_TXN PIE_TXN_ W GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_RXP W GPP_RXN V GPP_RXP V GPP_RXN W GPP_RXP W GPP_RXN W GPP_RXP GPP_RXN RP RP RP RP RP R _ R _ R R change to shortpad R _ Y *MHZ R *_ K/F_ TP *M/F_ TP LK_LRN_FH *X/S LK_P_FH_P LK_P_FH_N *X/S LK_PU_FH_P LK_PU_FH_N *X/S LK_WLN_FH_P LK_WLN_FH_N LK_PIE_RP_FH LK_PIE_RN_FH *X/S LK_PIE_LNP_FH LK_PIE_LNN_FH TP X LK_FLEX_M M_X M_X F J UE LK_LRN G G PIE_RLKP PIE_RLKN R T ISP_LKP ISP_LKN H H ISP_LKP ISP_LKN T T PU_LKP PU_LKN J K SLT_GFX_LKP SLT_GFX_LKN H H GPP_LKP GPP_LKN J K GPP_LKP GPP_LKN F F GPP_LKP GPP_LKN E E GPP_LKP GPP_LKN M M GPP_LKP GPP_LKN M M GPP_LKP GPP_LKN N N GPP_LKP GPP_LKN R R GPP_LKP GPP_LKN N R GPP_LKP GPP_LKN M_M_M_OS M_X M_X olton M OLTON-M Part of PI EXPRESS INTERFES LOK GENERTOR PI LKS PILK PILK/GPO PILK/GPO PILK/GPO PILK/M_OS/GPO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO E# E# E# E# FRME# EVSEL# IRY# TRY# PR STOP# PERR# SERR# REQ# REQ#/GPIO REQ#/LK_REQ#/GPIO REQ#/LK_REQ#/GPIO GNT# GNT#/GPO GNT#/S_LE/GPO GNT#/LK_REQ#/GPIO LKRUN# LOK# PI INTERFE LPLK LPLK L L L L LFRME# LRQ# LRQ#/LK_REQ#/GPIO SERIRQ/GPIO PU S PLUS LP S_ORE_EN RTLK INTRUER_LERT# VT_RT_G PIRST# INTE#/GPIO INTF#/GPIO INTG#/GPIO INTH#/GPIO M_TIVE# PROHOT# PU_PG LT_STP# PU_RST# K_X K_X F F F G F J L G L H J L N N J L L M J K N G M J L K N G E E F H H E N J N G K L F E H M H G G F M K H F E E E G E E G F G G H F F E PI_LK PI_LK PI_LK PIRST#_L PI_ PI_ PI_ PI_ PI_ HUSON_MEMHOT#_R FH_GPIO LKRUN# TRVIS_EN# EL_INTH# LP_LK LP_LK L L L L LFRME# LRQ# LRQ# SERIRQ MTIVE_L FH_PROHOT# PU_PWRG_R PU_STOP# PU_RST# K_X K_X S_ORE_EN LK_RT INTRUER_LERT# +V_RT MIL R _ P/V_ R TP TP TP TP *_ TP TP TP R *_ R _ R _ PI_LK PI_LK PI_LK K_RST# PI_SERR# LKRUN#, EL_INTH# LP_LK LP_LK K_RST# PI_ PI_ PI_ PI_ PI_ GPU_PWROK,,, TP SPI_WP LK_PI_TPM INTRUER_LERT# Left not connected (FH has -kohm internal pull-up to VT). MIL LK_PI_TPM MIL dd R for support TPM function S_ORE_EN is necessary to connect enable pin of +VPU/+VPU regulator for S+ mode implementation MIL change to short-pad K_X MTIVE_L *P/V_ FH_PROHOT# R *_/S USE GROUN GUR FOR K_X N K_X PU_PWRG, TP PU_RST#, LT_STP# let is N from schematic recommend for OS +V noise issue MV change to reserve R */F_ +VRT_ R *_ +VRT LK_M_EUG L,, L,, LK_M_K L,, L,, LFRME#,, K_X TP TP SERIRQ, FH PROHOT#--- (input.v threshold ) When it isasserted, it can generate SI or R SMI to OS/IOS *M_.u/V_ TP LK_RT TP +V_RT.U/V_ +V_RT *P/V_ U/.V_ E E E *P/V_ P/V_ P/V_ R _ Y *.KHZ *MEKV- *P/V_ *MEKV- MIL MIL N -L R *K/F_ +VRT_ +T +VPU +T LKGEN_RT_X PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom FH /(PI/PI/LK) ate: Tuesday, March, Sheet of

8 I I I I I ONFIG - Level OM Item U VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ K VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_ M VSS_ M VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P VSS_ R VSS_ R VSS_ R VSS_ R VSS_ T VSS_ T VSS_ T VSS_ VSS_ N VSSN_HWM K VSSXL H VSSPL_SYS olton M OLTON-M Part of GROUN T VSS_ T VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ U VSS_ V VSS_ V VSS_ V VSS_ W VSS_ W VSS_ W VSS_ W VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_ F VSS_ F VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_ J VSS_ K VSS_ K VSS_ L VSS_ M VSS_ M VSS_ N VSS_ N VSS_ N VSS_ N VSS_ VSSPL_ T VSSN_ L VSSNQ_ K VSSIO_ N R EFUSE UM ST H ST O GPIO internal pull Hi.K to +V GPIO internal pull Hi.K to +V GPIO internal pull Hi.K to +V GPIO internal pull Hi.K to +V GPIO internal pull Hi.K to +V GPIO internal pull Hi.K to +V +.V_V_ST / For omal. +V SIE_PORT_I PLE ST OUPLING PS LOSE TO HUSON-M/M ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP PLE ST_L RES VERY LOSE TO LL OF HUSON-M/M Integrated lock Mode: Leave unconnected. dd GPIO for G-sensor LE control R R R ST_LE# RF_OFF# TP T_OMO_EN# O_PWR _LE# R K/F_ K/F_ /F_ SIE_PORT_I ST_TXP ST_TXN ST_TXP ST_TXN ST_LRP ST_LRN */F_ ST_LE# R K/F_ R K/F_ F G SIE_PORT_I U K M ST_TXP ST_TXN L N ST_RXN ST_RXP N L ST_TXP ST_TXN H J ST_RXN ST_RXP J H ST_TXP ST_TXN M K ST_RXN ST_RXP H J ST_TXP ST_TXN N L ST_RXN ST_RXP L N ST_TXP ST_TXN J H ST_RXN ST_RXP N L ST_TXP ST_TXN K M ST_RXN ST_RXP L N N N L L N N H H N N J J N N F F ST_LRP ST_LRN ST_T#/GPIO ST_X ST_X olton M OLTON-M SERIL T TEMP( - ) Temp Monitor Not Implemented -KΩ % pull-up to +VS or -KΩ % pull-down Samsung S R SPI ROM VG RF_OFF# H T_OFF# M FNOUT/GPIO T_OMO_EN# J FNOUT/GPIO FNOUT/GPIO HW O_PWR K MONITOR N FNIN/GPIO L FNIN/GPIO FNIN/GPIO TEMPIN K TEMPIN K TEMPIN/GPIO TEMPIN K TEMPIN/GPIO TEMPIN M TEMPIN/GPIO TEMPIN/TLERT#/GPIO R K/F_ VG MINLINK GE LN Part of L S_LK/SLK_/GPIO N S_M/SLO_/GPIO J S_#/GPIO H S_WP/GPIO K S_T/STI_/GPIO M S_T/STO_/GPIO H S_T/GPIO J S_T/GPIO GE_OL GE_RS GE_MK GE_MIO W GE_RXLK H GE_RX F GE_RX E GE_RX GE_RX G GE_RXTL/RXV GE_RXERR GE_TXLK F GE_TX G GE_TX E GE_TX GE_TX GE_TXTL/TXEN GE_PHY_P GE_PHY_RST# GE_PHY_INTR W V SPI_I/GPIO V SPI_O/GPIO V SPI_LK/GPIO T SPI_S#/GPIO V ROM_RST#/SPI_WP#/GPIO M VG_HSYN/GPO N VG_VSYN/GPO M VG S/GPO N VG SL/GPO K VG RSET V UX_VG_H_P UX_VG_H_N V U UXL T ML_VG_LP ML_VG_LN T T ML_VG_LP ML_VG_LN T R ML_VG_LP ML_VG_LN R P ML_VG_LP ML_VG_LN P ML_VG_HP/GPIO N VIN/GPIO M VIN/GPIO L VIN/STI_/GPIO N VIN/STO_/GPIO P VIN/SLO_/GPIO P VIN/SLK_/GPIO M VIN/GE_STT/GPIO M VIN/GE_LE/GPIO G N H N N G N L N +VS VG_RE VG_GREEN VG_LUE R R R R R L L M *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ Vender MI WINON Socket GE_PHY_INTR SPI_SI SPI_SO SPI_LK SPI_S# FH_SPI_WP FH_RT_R FH_RT_G FH_RT_ VG REST UXL VG_HP SIE_PORT_I SIE_PORT_I SIE_PORT_I OR_I OR_I OR_I OR_I OR_I Size M M EMI P/N VIN ( - ) Voltage Monitor Not Implemented -KΩ % pull-up to +VS or -KΩ % pull-down OR_I OR_I OR_I OR_I OR_I R R SPI_LK E *P/V_ R R R E_IOS_S# E_IOS_SPI_LK_I E_IOS_WR# E_IOS_R# TP TP TP TP TP R R R R R R R KEZN KEFPN FHSFS HMISO FH_SPI_WP IT need TP size test point *_/S *_/S *_/S HSYN_OM VSYN_OM T LK PU_P_UXP PU_P_UXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN PU_P_TXP PU_P_TXN *K/F_ FH_VG_HP K/F_ K/F_ K/F_ K/F_ K/F_ K/F_ /F_ /F_ +VS R R R R R R HMISO SPI_HOL# RT_R RT_G RT_ +FH_VN R R K/F_ FH_VG_HP ual +VS R place close to PH FH_RT_R FH_RT_G FH_RT_ +FH_VN ML +V FH SPI ROM VG Hot-plug ual Reserve for support quad read hange U V from +V to +VS for M G. U *_/S SPI_S# *_/S SPI_LK E# V *_/S SPI_SO SK *_/S SPI_SI SI SO HOL# *_/S SPI_WP WP# VSS *_/S *MXLMI-G *K/F_ R +V R FH_VG_HP R K/F_ Q NW--F SPI_WP *_/S SPI_HOL# R R R +V.U/V_ R /F_ /F_ *_ +VS R VG_HP Reserve for debug R K/F_ Q /F_ NW--F VG_HP K/F_ R K/F_ IS Hynix N no supprot side port R R R K/F_ K/F_ *K/F_ SIE_PORT_I R SIE_PORT_I R SIE_PORT_I R *K/F_ *K/F_ K/F_ PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom FH /(ST/VG/GN/SPI) ate: Tuesday, March, Sheet of

9 +V +V NOTE : LO_P stepping : will install nf cap stepping : will let it to N +V L PYT-Y-N(,) L PYT-Y-N(,) L PYT-Y-N(,).U/.V_.U/.V_ +VPL_.V +V TRE WITH >=mil TRE WITH >=mil +FH_VN ML.U/.V_ *.U/V_ *.U/V_.U/V_ +.V_VIO VQ--.V I/O power.u/v_ U/.VS_ M chipset need to connect to GN M remove +VPL SYS +VPL VPL US_S : US PHY PLL analog power +V_V_US m +FH_VN R +VPL_.V +FH_VPL ML R L PYT-Y-N(,).U/V_.U/V_ *_ +FH_VPL SSUS_S +FH_VPL SUS_S +FH_VPL PIE +FH_VPL ST +FH_VPL SUS_S U/.V_ m m m m m m m m PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. U *P/V_ +LO_P M LO_P +FH_VN m V VN ML -- UMI.V analog power VPL +FH_VN ML m Y V VN ML_ V VN ML_ V VN ML_.U/V_ U/.V_.U/.V_.U/V_ VN ML_.U/.V_.U/V_ VIO_GE_S_ VIO_GE_S_ OLTON-M Part of VIO PIGP_ E VIO PIGP_ VIO PIGP_ G VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ VIO PIGP_ H V VPL SYS U VPL T VPL ML L VN VPL SSUS_S H VPL US_S G VPL PIE VPL ST VIO GE_S MIN LINK VR GE_S_ VR GE_S_ PI/GPIO I/O GE LN LKGEN I/O PI EXPRESS SERIL T ORE S m for M +.V_VR m for M VR-- S/ ORE power T TRE WITH >=mil VR +.V T VR T VR U VR U.U/V_.U/V_ U/.V_ U/.V_ U/.V_ VR V VR V VR V VR Y +.V_KV VR m VN LK-- Internal clock H VN LK_ Generator I/O power J TRE WITH >=mil L VN LK_ +.V K HKF-T VN LK_ L VN LK_ M VN LK_ N U/.V_ U/.V_.U/V_.U/V_ U/.VS_ VN LK_ N VN LK_ P VN LK_ +.V_PIE_VR m VN PIE --PIE/UMI analog power TRE WITH >=mil L VN PIE_ +.V Y HKF-T VN PIE_ E VN PIE_ VN PIE_.U/V_.U/V_ U/.V_ U/.V_ U/.VS_ VN PIE_ +.VS VN PIE_ F VN PIE_ G +.V_V_ST VN PIE_ m VN ST--ST PHY analog/io power TRE WITH >=mil L VN ST_ +.V Y HKF-T VN ST_ VN ST_ VN ST_ if support US U/.V_ U/.V_.U/V_.U/V_ U/.VS_ VN ST_. wake up VN ST_ should be VN ST_ change pull hi VN ST_ to S power VN ST_ VN ST_ +VS Reserve for VN L leakage current issue VPL SYS_S : System lock Gen PLLs analog power L PYT-Y-N(,) +VPL_.V VN HWM_S -- Hardware monitor interface I/O power L PYT-Y-N(,).U/.V_ +VN_.V_HWM.U/V_ VN US_S : US PHY I/O analog power VN US_S : US PHY PLL analog power VR US_S : US PHY core power +.VS +.VS M chipset need to stuff for support US. M chipset need to connect to GN M remove if support Modem wake up should be change pull hi to S power +VS +VS L PYT-Y-N(,) R L *_ L PYT-Y-N(,) U/.V_.U/.V_ PYT-Y-N(,) +.VS +FH_V SSUS_S R R *_/S M chipset need to stuff for support US. +FH_VPL SSUS_S M chipset need to stuff for support US..U/V_.U/V_ L PYT-Y-N(,) L PYT-Y-N(,).U/V_ *_/S.U/V_ U/.V_ +V_V_US TRE WITH >=mil m +FH_VN US_S.U/V_.U/V_ m.u/.v_ TRE WITH >=mil.u/v_ m +FH_VR US_S TRE WITH >=mil m +FH_VN SSUS_S_R VN SSUS_S : US. PHY PLL analog power U/.V_ +FH_VR SSUS_S VR SSUS_S : US. PHY core power +V U/.V_ U/.V_ R U/.V_.U/V_ U/.V_ *_/S VIO_Z_S -- H udio Interface I/O power +VIO_Z U/.V_ U/.V_.U/V_ m.u/.v_.u/v_ G H VN US_S_ J VN US_S_ K VN US_S_ K VN US_S_ M VN US_S_ M VN US_S_ N VN US_S_ N VN US_S_ M VN US_S_ N VN US_S_ M VN US_S_ VN US_S_ U U VN US_S_ VN US_S_ T T VR US_S_ VR US_S_ P M VN SSUS_S_ N VN SSUS_S_ P VN SSUS_S_ P VN SSUS_S_ VN SSUS_S_ N N VR SSUS_S_ P VR SSUS_S_ M VR SSUS_S_ VR SSUS_S_ olton-m US POWER.V_S I/O US SS m N VIO S_ L VIO S_ M VIO S_ V VIO S_ V VIO S_ Y VIO S_ Y VIO S_ W VIO S_ VXL S VR S_ VR S_ VPL SYS_S VN HWM_S m VG_POWER_OWN TRE WITH >=mil +VN_.V_HWM m VIO_Z_S +VIO_Z Trace width >= mil VG will power down when RT no insert VG_P is generated from FH VG_POWER_OWN R.K_ +VIO_.V VIO S--.v S I/O power.u/.v_ m VXL S-- MHZ XTL IO power G +VXL_.V VR_._S--.V S ore power m N +VR_.V +.VS M TRE WITH >=mil m J +VPL_.V U/.V_.U/.V_ M *.U/V_ +VLW U/.V_ U/.V_ R K_ +FH_VG_PWR_EN Q MENE U/.V_.U/V_ U/.V_ U/.V_ +V +VS if support US. wake up should be change pull hi to S power This circuit is for switch and UMI analog power +FH_VN L PYT-Y-N(,) +.V *.U/V_ Q PMVEN Q PMVEN +VN ML L PYT-Y-N(,).U/.V_ L +FH_VN R m Max m Max +V,,,,,,,,,,,,,,,,,,,, +.V +VS,,,,,,,,,,, +.VS, Size ocument Number Rev +VLW,, ustom N FH /(POWER) R PYT-Y-N(,) +VS.U/.V_ +FH_VN R +FH_VPL ML *_/S +FH_VN ML.U/.V_.U/V_.U/.V_ PROJET : RX Quanta omputer Inc..U/V_.U/V_ ate: Tuesday, March, Sheet of

10 STRPS PINS OVERLP OMMON PS WHERE POSSILE FOR UL-OP RESISTORS. EUG STRPS +V +VS +VS +VS PI_LK PI_LK PI_LK LP_LK PI_LK PI_LK PI_LK LP_LK R K/F_ R K/F_ R *K/F_ R K/F_ PI_ PI_ PI_ PI_ PI_ FH has K Internal Pull Up for PI_[:] PI_ PI_ PI_ PI_ PI_ TP TP TP TP TP remove reserve pull low resistor reserve test point only. LP_LK LP_LK E_PWM E_PWM LK_RT LK_RT PI_ PI_ PI_ PI_ PI_ R *K_ R K/F_ R K/F_ R K/F_ R.K_ R *.K_ PULL HIGH USE PI PLL ISLE IL UTORUN USE F PLL USE EFULT PIE STRPS ISLE PI MEM OOT EFULT EFULT EFULT EFULT EFULT REQUIRE STRPS PULL LOW YPSS PI PLL ENLE IL UTORUN YPSS F PLL USE EEPROM PIE STRPS ENLE PI MEM OOT PI_LK PI_LK PI_LK LP_LK LP_LK E_PWM LK_RT PULL HIGH LLOW PIE Gen EFULT USE EUG STRP non_fusion LOK MOE M internal E ENLE LKGEN ENLE EFULT LP ROM S PLUS MOE ISLE EFULT PULL LOW FORE PIE Gen IGNORE EUG STRP EFULT FUSION LOK MOE EFULT E ISLE EFULT LKGEN ISLE SPI ROM EFULT S PLUS MOE ENLE FH PWRG SI reserve for M G +VS +V PU_VRM_PG, EPWROK T R *K/F_ *.U/.V_ R K/F_ FH_PWRG PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom FH /(Strap &PWRG) ate: Tuesday, March, Sheet of

11 M M[..] R R K_ K_,,,, M [:] M S# M S# M S# M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# SM_RUN_LK SM_RUN_T M OT M OT M M M M M M M M M M M M M M M M M QSP[:] M QSN[:] M M M M M M M M M M M M M M M M IMM_S IMM_S SM_RUN_LK SM_RUN_T M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# P R SRM SO-IMM (P) Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q[:] +VREF_Q +V, M EVENT# M RST# R *_/S +VREF_. R +V M EVENT# +VREF_Q +VREF_ +.VSUS *K_ JIM V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P R SRM SO-IMM (P) R-IMM_H=._ST VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN +.V_R_VTT R-IMM_H=._ST Place these aps near So-imm. +.VSUS +.V_R_VTT U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ *U/.V_ U/.VS_ U/.VS_.U/V_ U/.VS_.U/V_ *.U/V_.U/V_ *.U/V_.U/V_.U/V_ E.U/V_ E P/V_ E P/V_ EMI E.U/V_.U/V_ EMI request +VREF_.U/V_ +V.U/.V_ P/V_ *.U/V_ *.U/V_ E *.U/V_ R SI stuff +VREF_ R K_ R SI change from short pad to *R *_ R_VTTREF,, K_ +.VSUS +V,,,,,,,,,,,,,,,,,,,, +.V,,,,,,, +VPU,,,,,, +.VSUS,,,,,,, +.V_R_VTT, +VREF_Q.U/V_ P/V_ PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom R IMM-ST (.H) ate: Tuesday, March, Sheet of

12 +V R R M M[..].K_ K_,,,, M [:] M S# M S# M S# M S# M S# M LKP M LKN M LKP M LKN M KE M KE M S# M RS# M WE# SM_RUN_LK SM_RUN_T M OT M OT M M M M M M M M M M M M M M M M M QSP[:] M QSN[:] M M M M M M M M M M M M M M M M IMM_S IMM_S M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P /# S# S# K K# K K# KE KE S# RS# WE# S S SL S OT OT M M M M M M M M QS QS QS QS QS QS QS QS QS# QS# QS# QS# QS# QS# QS# QS# P R SRM SO-IMM (P) R-IMM_H=._ST Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q[:],,,, MLK MT +V +VREF_Q M EVENT# M RST# R +VREF_ Q R R *_/S. +V M EVENT# +VREF_Q +VREF_ +.VSUS SLK_G *.K_ +V *.K_ S_G JIM V V V V V V V V V V V V V V V V V V VSP N N NTEST EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS P R SRM SO-IMM (P) R-IMM_H=._ST VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTT VTT GN GN R Thermal Sensor +.V_R_VTT Place these aps near So-imm. +.VSUS +.V_R_VTT U/.VS_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ *U/.V_.U/V_ *U/.V_.U/V_ U/.VS_.U/V_ *.U/V_.U/V_ *.U/V_.U/V_ E P/V_ E P/V_ +VREF_Q E P/V_ E P/V_.U/V_ R for WiMX +.VSUS +VREF_ K_ SI stuff SI change from short pad to *R R R *_ K_ +.VSUS +.VSUS R_VTTREF,,, *NW M EVENT# +V M EVENT# R SLK_G S_G PM_EXTTS#_E *K_ U SLK S LERT# OVERT# *GPU V XP XN GN *.U/V_ R_THERM *P/V_ R_THERM +V Q *METR-G +V EMI P/V_ R +VREF_Q.U/.V_ *.U/V_ *.U/V_ +VREF_.U/V_ P/V_ *.U/V_ P/V_ E P/V_ E EMI P/V_ E *P/V_ *P/V_ K/F_ R K/F_ +VREF_Q *.U/.V_ +.V_R_VTT, +.VSUS,,,,,,, +VPU,,,,,, +V,,,,,,,,,,,,,,,,,,,, PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom R IMM-ST (.H) ate: Tuesday, March, Sheet of

13 PRT F U PEG_TXP PEG_TXN Y PIE_RXP PIE_RXN PIE_TXP PIE_TXN Y Y _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN Y W PIE_RXP PIE_RXN PIE_TXP PIE_TXN W W _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN W V PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN V U PIE_RXP PIE_RXN PIE_TXP PIE_TXN U U _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN U T PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN T R PIE_RXP PIE_RXN PIE_TXP PIE_TXN T T _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN R P PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN PEG_TXP PEG_TXN P N PIE_RXP PIE_RXN PIE_TXP PIE_TXN P P _PEG_RXP _PEG_RXN *.U/V_ *.U/V_ PEG_RXP PEG_RXN For Mars /Sun N pin : N,M,M,L,L,K,K,J,J H,H,G,G,F,F,E N M M L L K K J PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PIE_RXP PIE_RXN PI EXPRESS INTERFE PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN N N N N L L L L FOR Mars / Sun N pin : N,N,N,N,L,L,L,L,K,K J,J,K,K,H,H J H PIE_RXP PIE_RXN PIE_TXP PIE_TXN K K H G PIE_RXP PIE_RXN PIE_TXP PIE_TXN J J G F PIE_RXP PIE_RXN PIE_TXP PIE_TXN K K F E PIE_RXP PIE_RXN PIE_TXP PIE_TXN H H Mars/ Sun Only : Stuff Ra Ra R *.K/F_ +.V_VG LK_VG_P LK_VG_N LOK PIE_REFLKP PIE_REFLKN o not install for Mars/ Sun, check M can del? R Ra *K/F_ H TEST_PG LIRTION PIE_LR_TX PIE_LR_RX Y Y PIE_LRP PIE_LRN R R Rb *.K/F_ *K/F_ Rc +.V_VG PEGX_RST# PERST Install k for Mars / Sun MHz (+/-ppm) input frequency, -.V single-ended swing *SUN_M_XT SUN_M_XT +V_ELY MRS/SUN change for leakage issue Ra.K GPU_RST# VG_RST R *_ GPU_HIN_RST# *UHGG-L-R U *.U/V_ R PEGX_RST# *K_ Rb Rc n/a K,,,,,,,,,,,,,,,,,,,,,,,, +V +V +.V_VG +.V_VG PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom SUN_PIE_Interface ate: Tuesday, March, Sheet of

14 PS IT=>IT [:] PS IT=>IT [:] Vendor Hynix Mx * Micron Mx * Samsung Mx * Vendor Only for Test Vendor P/N HTGFFR- MTJMJT-G:K KWGE- Vendor P/N Hynix Mx * HTGFR- Micron Mx * MTJMH-G:E Samsung Mx * KWG-H QI P/N (TOP /S),, KMZTW KMGSTL KMGGT QI P/N KPGWTW KPZSTL KPZT For Sun only : For Mars / Sun : R/W/R/R/U: N pin For Sun only : / /J /K: N pin P /V /T /R /W / U /P : N pin +V_ELY R R GPUT_LK GPUT_T *.K_ *.K_ SI stuff R R *_ *_ P P GENLK_LK GENLK_VSYN J K R U P W R R U U W P W U R W U T V N V T R W U P V T R W U P MUTI GFX GENLK_LK GENLK_VSYN SWPLOK SWPLOK VPNTL_MVP_ VPNTL_MVP_ VPNTL_ VPNTL_ VPNTL_ VPLK VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ VPT_ U PRT F P P P TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN TXP_PP TXM_PN U V T R U V T R R T V U R T T U U V T R U V T R U T T R For Mars / Sun : P to Port: all N pin +V_ELY +V_ELY R R R R R R R R SI stuff R *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ *K/F_ GPIO LKREQb *K/F_ *K_ GPIO R */F_ ase on M check list GPU_TRST GPU_PROHOT# GPU_TI GPU_TMS GPU_TK TEMP_FIL VG_LERT_ SI add TEMP FIL circuit for SUN XT ccess to SMus ans S/SL is mandatory on all designs dd test points on SMus and S/SL for debug R *.K_ +V_ELY R *.K_ GPIO change to shortpad GPU TT GFX_ORE_NTRL P FOR SUN GPIO N PIN : J/ K / K / M / N / J/ H / H / J K/ H / N / K / K / L/ M P P GFX_ORE_NTRL P P P P GFX_ORE_NTRL GFX_ORE_NTRL TEMP_FIL GFX_ORE_NTRL P P P P P P P P GPU_PROHOT# P P R GPUT_LK_ GPUT_T_ GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HMI_HP GFX_ORE_NTRL GFX_ORE_NTRL VG_LERT_ HP TEMP_FIL GFX_ORE_NTRL GPIO GPIO GPIO LKREQb R *_/S *_ GENERI J H K J H H N H J K J H J K L M M M K G N M L J K N G G J K J K J H H SMLK SMus SMT SL I S GENERL PURPOSE I/O GPIO_ GPIO_ GPIO_ GPIO TT GPIO_ GPIO LON GPIO ROMSO GPIO ROMSI GPIO ROMSK GPIO_ GPIO_ GPIO_ GPIO HP GPIO PWRNTL_ GPIO_ GPIO THERML_INT GPIO HP GPIO TF GPIO PWRNTL_ GPIO_ GPIO ROMS LKREQ GPIO_ GPIO_ GENERI GENERI GENERI GENERI GENERIE_HP GENERIF_HP GENERIG_HP P TXP_PP TXM_PN TXP_PP TXM_PN R VSSN# G VSSN# VSSN# HSYN VSYN RSET V VSSQ VI VSSI N# N# N# N# N# N# N# N# N# N_TSVSSQ PS_ U V T R E F E E V U F G F M *_ *_ *_ GPU_HSYN_OM GPU_VSYN_OM R *_ *_ *_ *_ FOR MRS: / E / VSSN to GN FOR SUN : / E / N pin FOR SUN : R/R/R -->N FOR SUN : R/R/R/R/R -->N FOR SUN N PIN : / E / / / / E PS_ R R R */F_ R R R R P TP P P P +.V_V_Q +V F/ / / / P P E_ Mars: stuff +.V_VG R */F_ K HP MLPS PS_ PS_ TP For Sun Nc: R, R, Thermal Solution(lose to GPU) R */F_ *.U/V_ +.V_VREFG P H L VREFG PX_EN O PS_ PS_ G PS_ PS_ P P IT => IT PS => +.V_VG +.V_VG *.U/V_ U, GPUT_LK SLK V +V_ELY, GPUT_T GPU_THERM S XP VG_LERT_ *_ R VG_LERT_ LERT# XN +V_ELY R *K/F_ *P/V_ OVERT# GN GPU_THERM GPU_OVT# *G-P(h) Main:L G-P(h) nd:l EM--ZL-TR(h) Reserve for Power Play +.V_TSV GFX_ORE_NTRL R *.K/F_ *HKFT.V(m TSV) GFX_ORE_NTRL R *.K/F_ +.V_VG Rc L GFX_ORE_NTRL R *.K/F_ GFX_ORE_NTRL R *.K/F_ *U/.V_ *U/V_ *.U/V_ GFX_ORE_NTRL R *.K/F_ Ra GFX_ORE_NTRL R *K_ +V_ELY Rb GFX_ORE_NTRL R *K_ For Mars: Stuff Ra, Rc=> V.V GFX_ORE_NTRL R *K_ For Thems: Stuff Ra, Rb, Na Rc=> V.V +V_ELY R *.K/F_ TESTEN P R *K/F_ GPU_TRST P GPU_TI P GPU_TK P GPU_TMS P GPU_TO P GPU_THERM GPU_THERM GPIO GPIO P +.V_TSV EUG TESTEN M JTG_TRST N JTG_TI K JTG_TK L JTG_TMS M JTG_TO THERML F PLUS G MINUS K GPIO FO L TS_ J TSV J TSVSS *SUN_M_XT SUN_M_XT /UX LK T UXP UXN LK T UXP UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN LK_UXP T_UXN VGLK VGT M N M L M L N M L M L M N M K K J J change to shortpad For Mars / Sun:N pin L, M, L, M, N, M, K, K +.V_VG L L nalog Power V m *_/S igital Power. VI m *_/S *U/.VS_ *U/.VS_ *U/.V_ *U/.V_ +.V_V_Q *.U/V_ *.U/V_ +V PS => PS => PS => R *.K_ PS_ R *K_ +.V_VG R *_ PS_ R *.K/F_ PS_ *.U/V_ PS_ *.U/.V_ R *.K_ no stuff R *K_ *.U/.V_ +.V_VG R *.K/F_ R *.K/F_ *.U/V_ For Sun Only :N pin L, M, M, N, N, M, L,, M, J, J,,,,,,,,,, +.V_VG +.V_VG +V_ELY +.V_VG +.V_VG +V_ELY PROJET : RX Quanta omputer Inc. Size ocument Number Rev N SUN_Main & GN ustom ate: Tuesday, March, Sheet of

15 For Mars/ Sun hange La, Lb ead to ohm +.V_VG La change to shortpad +.V_VG +.V_VG +.V_VG +.V_VG Lb.V(m PLL_V) L L L L L.V(m PLL_V) *_/S *_/S *HKF-T *U/.V_ *U/.V_ *U/.V_ *U/.V_ *HKF-T *U/.V_ +.V_PLL_ isplay Phase Lock Loop Power PLL_ m +.V_PLL_ +.V_PLL_V PLL_V m *U/.V_ *U/.V_ *U/.V_ +.V_PLL_V PLL_SS +.V_MPLL_ MPLL_ m +.V_MPLL_ +.V_SPLL_ SPLL_ m +.V_SPLL_ +.V_SPLL_V SPLL_V m *U/.V_ *U/.V_ *TUN(,.) *.U/V_ *.U/V_ *.U/V_ *.U/V_ *.U/V_ +.V_PLL_ +.V_SPLL_V SPLL_SS R R Ra *_ Rb *_ Memory Type R GR M N N M N N F F SPLL_ SPLL_V SPLL_SS N_XTL_ N_XTL_SS *SUN_M_XT reserve Ra, Rb for future SI H H PLL_ PLL_V PLL_SS MPLL_ MPLL_ -MHz (± ppm) crystal connected to XTLIN/XTLOUT, or -MHz (. V) oscillator connected to XTLIN. -MHz (. V) oscillator connected to XO_IN, and -MHz (. V) oscillator connected to XO_IN. (y default, this clock should not be spread since internal spreading is used.) PRT F PLLS/XTL UI SUN_M_XT XTLIN XTLOUT XO_IN XO_IN LKTEST LKTEST V U W W K L EVG-XTLI EVG-XTLO LKTEST LKTEST R *M_ P *.U/V_ ebug only, for clock observation, if not needed, NI R *./F_ route ohms single-ended/ ohms diff and keep short change from X_IN for M suggestion *P/V_ change to XTI_IN for M suggestion R *_ R *P/V_ Y * *_ *.U/V_ R *./F_ GPU_XTL_IN PIE_VSS E PIE_VSS F PIE_VSS F PIE_VSS G PIE_VSS G PIE_VSS H PIE_VSS H PIE_VSS H PIE_VSS J PIE_VSS J PIE_VSS K PIE_VSS K PIE_VSS K PIE_VSS L PIE_VSS L PIE_VSS M PIE_VSS M PIE_VSS N PIE_VSS N PIE_VSS P PIE_VSS P PIE_VSS P PIE_VSS R PIE_VSS T PIE_VSS T PIE_VSS T PIE_VSS U PIE_VSS U PIE_VSS V PIE_VSS V PIE_VSS W PIE_VSS W PIE_VSS Y PIE_VSS Y PIE_VSS F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN F GN G GN G GN H GN J GN J GN J GN J GN K GN K GN L GN L GN L GN L GN L GN L GN M GN M GN M GN N GN N GN N GN N GN N GN N GN N GN R GN R GN R GN R GN R GN R GN R GN R GN T GN T GN T GN T GN T GN T GN T GN U GN U GN U GN U GN U GN U GN U GN U GN V GN V GN V GN V GN V GN V GN W GN W GN Y GN Y GN Y GN Y GN Y GN Y GN PRT F GN UF GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN E GN E GN F GN F GN F GN F GN G GN G GN G GN G GN G GN G GN H GN J GN J GN J GN J GN J GN K GN K GN K GN L GN L GN L GN L GN L GN L GN L GN L GN L GN L GN M GN M GN M GN N GN N GN N GN N GN N GN P GN P GN P GN R GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN E GN E GN F GN F VSS_MEH VSS_MEH W VSS_MEH W Mars/Sun G is nc pin SUN_M_XT,,, +.V_VG +.V_VG PROJET : RX Quanta omputer Inc.,,,, +.V_VG +.V_VG Size ocument Number Rev N ustom SUN_XTL Tuesday, March, ate: Sheet of

16 PRT F LVS ONTROL UG VRY_L IGON K J Fo Mars only: F, G: N pin Fo Mars only: N, P: N pin TXLK_UP_PFP TXLK_UN_PFN K L ONFIGURTION STRPS -- SEE EH TOOK FOR STRP ETILS LLOW FOR PULLUP PS FOR THESE STRPS N IF THESE GPIOS RE USE, THEY MUST NOT ONFLIT URING RESET TXOUT_UP_PFP TXOUT_UN_PFN J K STRPS MLPS GPIO PIN ESRIPTION OF EFULT SETTINGS efault Setting LVTMP TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP_PFP TXOUT_UN_PFN TXOUT_UP TXOUT_UN TXLK_LP_PEP TXLK_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP_PEP TXOUT_LN_PEN H J G H F G P R W U R U MLPS_ISLE TX_PWRS_EN TX_EEMPH_EN IF_GEN_EN_ IF_VG IS N PS_[] PS_[] PS_[] PS_[] GPIO FO GPIO GPIO GPIO GPIO Enable MLPS, N for Thames/Whistler/Seymour : Enable MLPS, disable GPIO PINSTRP : isable MLPS, enable GPIO PINSTRP Transmitter Power Savings Enable : % Tx output swing : Full Tx output swing PIE Transmitter e-emphasis Enable : Tx de-emphasis disabled : Tx de-emphasis enabled PIE Gen Enable (NOTE: RESERVE for Thames/Whistler/Seymour) : GEN not supported at power-on : GEN supported at power-on VG ontrol : VG controller capacity enabled : VG controller capacity disabled (for multi-gpu) TXOUT_LP_PEP TXOUT_LN_PEN TXOUT_LP TXOUT_LN SUN_M_XT P R N P Fo Sun Only : ll N pin ROMIFG[:] PS_[..] GPIO[:] Serial ROM type or Memory perture Size Select If GPIO =, defines memory aperture size If GPIO, defines ROM type Kbit MP (ST) Mbit MP (ST) - Mbit MP (ST) Mbit MP (ST) Mbit MP (ST) Kbit PmLV (hingis) - Mbit PmLV (hingis) +V_ELY IOS_ROM_EN PS_[] GPIO Enable external IOS ROM device : isabled : Enabled GPIO GPIO R *K_ U[] U[] N N HSYN VSYN - No audio function udio for P only - udio for P and HMI if dongle is detected udio for both P and HMI HMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. XX E_IS PS_[] GENLK_VSYN Enable E function. Reserved for Thames/Whistler/Seymour : isabled : Enabled Reserve for future SI NOTE: LLOW FOR PULLUP PS FOR THE RESERVE STRPS UT O NOT INSTLL RESISTOR IF THESE GPIOS RE USEE, THEY MUST KEEP LOW N NOT ONFLIT URING RESET RESERVE RESERVE RESERVE RESERVE PS_[] PS_[] N N GENLK_LK GPIO GPIO GENERI Reserved Reserved Reserved Reserved (for Thames/Whistler/Seymour only) GPIO GPIO Ra R Rb R *K_ *K_ U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] U_PORT_ONN_PINSTRP[] PS_[] PS_[] PS_[] N N N STRPS TO INITE THE NUMER OF UIO PLE ISPLY OUTPUTS = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = usable endpoints = all endpoints are usable Thems : stuff Ra=> disable MLPS, support GPIO only Mars : stuff Rb=> enable MLPS, support MLPS only Power Up/own Sequence +VG_ORE V +VG_ORE VI +.V_VG VR +.V_VG VR +.V_VG +.V_VG VR V_T ms ms PROJET : RX Quanta omputer Inc. Size ocument Number Rev N ustom SUN_LVS / STRP Tuesday, March, Sheet ate: of

17 For Mars: stuff +.V_VG I/O power for the memory interface. ISRETE: Stuff U/.VS_ UM: Stuff _ ISRETE: Reserve U/.VS_ UM: Stuff _ +.V_VG change to shortpad +V_VG GR MHz *U/.V For Sun: N L,,,,,, L L *U/.V_ *U/.VS L *_ *U/.V_ *U/.VS_ *U/.VS_ *U/.VS_ *_/S *_/S *U/.V_ *U/.V_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.VS_ *U/.V_ *U/.VS_ *U/.VS_ VR m VR m Reserve for rop ISRETE: Reserve U/.VS_ UM: Stuff _ *U/.V_ *U/.VS_ *U/.V_ Route as differential pair and connect to the VSEN and RTN pins of the VR through a decoupling and termination circuit. *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.VS +.V_V_T *U/.V_ *U/.V_ +VR VGPU_ORE_SENSE VSS_GPU_SENSE *U/.V_ *U/.VS_ *U/.V_*.U/V_ *U/.V_*.U/V_ TP *U/.V_ +V_ELY *.U/V_ F G J K L G G G G G G G H J J K K K L L L L L L M N P R U U Y Y F F G G F F G G F F F F G G G F G H VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR VR MEM I/O LEVEL TRNSLTION V_T V_T V_T V_T VR VR VR VR VR VR VR VR VR VR VR VR I/O VP VOLTGE SENESE F_V F_VI F_GN *SUN_M_XT UE PRT F SUN_M_XT PIE O ORE ISOLTE ORE I/O N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR N_PIE_VR W N_PIE_VR Y N_IF_V V N_IF_V W PIE_ PIE_V G PIE_V G PIE_V H PIE_V H PIE_V J PIE_V J PIE_V L PIE_V M PIE_V N PIE_V R PIE_V T PIE_V U IF_V N IF_V T V V V V V V V V V V V V V V V V V V V V V V F V F V F V G V G V H V H V H V M V N V R V R V R V R V T V T V T V T V U V U V U V U V U V V V V V V V V V V V Y V Y V Y V Y V Y V Y VI VI VI VI VI VI VI M VI M VI M VI M VI N VI N VI N VI N VI N VI R VI R VI R VI T VI T VI V VI Y IF_V *.U/V_ *U/.V_ *U/.V_ Ra R *_ Rb R *_ +VG_ORE *U/.V_ *U/.V_ *.U/V_ *U/.V_ *U/.VS_ *U/.VS_ *U/.V_ *.U/V_ *.U/V_ *.U/V_ *U/.V_ *U/.V *U/.V_ *U/.VS_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ +VG_ORE +VG_ORE *U/.V_ *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ *U/.VS_ *U/.V_ ISRETE: Stuff U/.VS_ UM: Stuff _ +.V_VG PIe igital Power Supply PIE_V (GEN.) PIE_V (GEN.) *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V *U/.V_ *U/.V_ Reserve for rop + *U/.V_ *U/.V_ *u_.v_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.V_ +.V_VG *U/.V_ *U/.V_ *U/.V_ *U/.V_ *U/.VS_ *U/.V_ *U/.V_ *U/.V_ +.V_VG *U/.VS_ ISRETE: Stuff U/.VS_ UM: Stuff _ IF_V *U/.VS_ *U/.V_ *U/.V_,,, +.V_VG,,, +.V_VG,,,, +.V_VG +V_VG, +VG_ORE *U/.VS_ +.V_VG +.V_VG +.V_VG +V_VG +VG_ORE Support O Mode Note.. No O Support :IF_V shorts with V (Install Ra) PX_EN =, for Normal Operation PX_EN =, for O MOE. O Support: Refer to the O reference schematics/pplication note for detail about IF_V Rail if O is Supported (Uninstall Ra) PROJET : RX Quanta omputer Inc. Size ocument Number Rev N SUN_Power & O ustom ate: Tuesday, March, Sheet of