EMI LOOPS FILTERING EMI ferrite noise suppressors

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1 (HighSpeedBoardDesign) (HIGHSPEEDBOARDDESIGN) vs vs STUB TS

2 EMI LOOPS FILTERING EMI ferrite noise suppressors

3 (HighSpeedBoardDesign) 66MHz 2MHz MHz a) b) a 4.5ns pld mach 5ns plds edge rate pcb boardinghouse crosstalk 1 VCC AC VCC *5 ICs 5.V 5V Line noise 1a 1b 3

4 voltage 1.1 power buses (power planes) vs a b 2a +5V 2b 4

5 2 3 IC 2 IC 2mA 4A V 5V 4.5V 2a U9 U uf-1uf.1uf-.1uf 1uf 6hz 1mhz harmonics.1u AC 3a 3b a) b) 3 ESR (ESL) 5

6 f R = 1 LC 4a FR a b 4 band-reject filter high-frequency-reject filter. 1u 5 ESL ESR ESL FR 1MHz 6 1MHZ swtching >uf 5 ESK ESR FR FR ESL 4b ESL ESL 6

7 1 1 ESL 6 CG.1uF.1uF.1uF 7 7

8 ESL 7 X7R CG X7R CG 8a VCC VCC chip leads a) b) 8 VCC VCC 8b lead extension routing VCC 8

9 connected internally VCC VCC decoupled AC 9a 9b VCC 9c a) Vcc b) c) AC 9 AC A B 9

10 1 Vcc Vcc vs 1 2a

11 1.3.1 (cuts) gaps connectors device sockets VME a 13b 13c 13 11

12 spike DAC, 14 Jumper planes

13 Bus AC

14 18 Z tpd Z AC driver Z L Z = 2-1 C L = C = L C t pd = L C (strpeline) microstrip ( 19) 19 C L Z t PD 6 4h Z = ln Ω ε t R.67 πω (.8 + ) w t = 1.17 ε ns / ft PD t PD C = 1 pf / ft Z L = Z C ph / ft 2 R

15 h Z = ln Ω ε w + t tpd = ε r +.67 ns/ ft t PD C = 1 pf / ft Z L = Z C ph / ft 2 r 2-4 ε r epoxy-laminated fiberglass ε r 5 FR4 ε 4.3 ~4.5 r t 1 oz 1mil w 8 15 mil 8 mil 15 mil 1 mil h 3 mil εr w 1 mil t 1mil h 3 mil ε 5 r 2-4 Z = ln = 67.5Ω t = = 1.75 ns/ ft PD 1.75 C = 1 = 26.1 pf / ft 67.5Z L = = ph ft /

16 Z t PD CL / in memory banks 4pF 12pF 5pF 5 pf CL = = 12 pf / ft 2-5 1ft.5in 12in Z 67.5Ω = = 28.34Ω 12 pf / ft pf / ft 12 pf / ft tpd = 1.75 ns/ ft 1+ = 4.14 ns/ ft 26.1 pf / ft Z 16

17 ZL, 2 ZL ZL Z t R t t R /t the load reflects the new transition, 17 swing 4 22 t / τ 4 R t R τ 8 t R microstrip line t 5ns( bipolar technology ) 1ns R CMOS 2 t R t t R

18 2 tr 5ns t 5nS R tr 1nS 1 t R tr / τ = Z Z L numerical indicatior K R K R = Z Z L L Z + Z

19 : 1 KR Z open load : KR = = 1 + Z Z shorted load : KR = = 1 + Z KR Z 3 Ω 15Ω 1kW 1kW CMOS CMOS PAL PALCE16V8.2V 24mA 8 Ω 5 Ω Z CMOS what happens on the HIGH to LOW transition. VOL.2V Zs : Zs 8.3 I = 24mA Ω / OL 1k Ω Z 67 Ω K 1. K R 8.3 K 67 R = V.2V Z voltage divider (.2V.35 V) Zo (.2V.35 V) 5 V = = = 2.84V Zo + Zs Vs = 3.5V = 3.5V 2.84V =.66V V R VL 2.84V 19

20 V L 3.5V 2.19V VS Vs.66V KR V S V = = 2.21V R V =.66V 2.84V =.35V S : V = = 2.24V L ns/ft 5ns/ft 2

21 t PD 3ns/ft 6 1.5ns 13.5ns 24 a) b) a) RT RT = Z = Z V BLAS VCC b) c) d) R 1 R 2 RT C T = Z R R = Z 1 2 e) Vcc Z S Drive R 2 ( ) R1 + R2 a) b) c) d) e) R T Z 21

22 ZL = Z Z = Z L PAL CMOS 1kW bipolar 1kW 25 Z Z Z Z L Z Z L 25a R Z L S S current drain HIGH-output 5 Ω 48mA f 1 = = 254MHz π 1.25ns IOH 3.2mA V OH Vcc I I OL OH CMOS CMOS devices designed for board-level applications I OL 24mA V OL 25b 2 thevenin V TH Vcc R = R + R R R thevenin R 1 2 TH = R + R 1 2 Vcc V V 25c OH OL 3v 5v 5w, 3v DC AC 22

23 sinking sourcing respond to the transitions RC series RC 25d Z 1pF AC DC driver DC loading effect AC Zs Z 25e Zs Z Zs Z 26a,b R L Z + R = Z S L 27a 27b 23

24 59 Ω 68 Ω 9 Ω transition (.2V 3.5 V) Zo (.2V 3.5 V) 67Ω V = = = 1.65V ZS + Zo+ 59Ω 8Ω+ 67Ω+ 59Ω V = 3.5V + = 3.5V 1.65V = 1.85V S V V = 3.5V + = 3.5V 1.65V = 1.85V S V -1.65V Zs Z R V 1.85V-1.65V=.2V T S VL.2V V S.2V 3ns 27 driver Z t PD DRAM DRAM R Zs Z swing T VOL 2Ω V (.2V 3.5 V) Zo (.2V 3.5 V) 67Ω VS = 3.5V + = 3.5V + = 1.17V Z + Zo+ 2Ω 8Ω+ 67Ω+ 2Ω S memory swamp out TTL PALCE16V8 8 Ω 5 Ω S 24

25 KR Z via 29 9 stripline micro-strip 25

26 2.5.2 stub Ts stub Ts 3a stub Ts main line stub Ts stub termination Z 3a stub 3b stub 3. Crosstalk

27 31 Z voltage spike Z Zs Z L ZL 32. trace ends tap 1/4 27

28 λ = 1 1 vel Period = t freq tpd PD the highest significant frequency harmonic of interest 1/ π t R t 1.25 R = ns 1 PAL16R8-4 fmax = = 255MHz 1.25nS π 4.14ns/ft λ t in λ = = 11.4in 255MHz ns ft 4.14 ft 11.4 λ / 4 = = 2.81in 4 transformer 33 ( 34a) 34b 34c PD 28

29 3.2.1 L LP LS 33b coincide auto-transformer 35a, c VME / 36 Zs Is Is Is terminating Rin R T RT 3 15 Rin Rin Zs Zs Rin line impedance (terminated) λ /

30 5. 4 EMI EMI (glitch) FCC VDE CCITT EMI 4.1 loops (antennae) EMI filtering EMI EMI (ferrite ceramics) high-frequency suppressors EMI EMI the line load EMI EMI feedthrough L -Circuit, π -Circuit, T -Circuit 37a L-Circuit 37b the line load PI-Circuit 37c PI the line load T-Circuit T 37d 3

31 the line load LC insertion loss ferrite noise suppressors 38a 38b 39 4 Z + Z + Z loss( db) = 2LOG1 Z + Z S L F S L 31

32 Zs Z Z L F DC Vcc edge rate a 41b 1/ π t L 1/ π t f 1/ π t f 1/ π t f 32

33 t F 1/ π t L 1/ 1/ π t R or π F PAL16R8-4 2ns 1.25ns 1 f = 254MHz 1.25ns = π 254MHz regulatory agencies EMI 8MHz ground crosstalk 33

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Microsoft Word - AUCOL_2007JUN19_BOE_BAB_SAF_INF_POT_TA_999.doc EMI / EMC 设计秘籍电子产品设计工程师必备手册目录一 EMC 工程师必须具备的八大技能二 EMC 常用元件三 EMI/EMC 设计经典 85 问四 EMC 专用名词大全五产品内部的 EMC 设计技巧六电磁干扰的屏蔽方法七电磁兼容 (EMC) 设计如何