te2_intel_uma_ramp_boi_ok

Transcription

1 P STK UP LYER : TOP LYER : TE lock iagram LYER : IN LYER : IN LYER : V LYER : OT INT_LVS US-0 L/ on. P ST - H P RIII-SOIMM RIII-SOIMM P, Re-river P ual hannel R III 00/0/ MHZ R SYSTEM MEMORY rrandale (UMVG) rpg P,,,, FI MI PI-E Graphics Interfaces INT_RT INT_HMI daughter board P HMI Level Shift P RT on. HMI on. P US on. ardreader US- SIM R. ST - O EST on. daughter board P luetooth on. P P P US- US- US- US- ST 0 ST ST US.0 (Port0~) MI(x) FI MI ST PI-E Ibex Peak-M US RT PH P,,, 0, PI-Express PIE- PIE- PIE- PIE- US-0 US- G WLN P P Giga/0/00 Lan P K0 POWER SYSTEM ISL RT0 UP UP RT0 ISL RT P P P P P P P0 P P ardreader on. IN P US on. P US- TTERY P zalia IH LP LP NVRM V_ORE.V.VSUS VTT.0V M on. udio odec P MI JK HP SPK on. P P P P Port- Port- FN P K/ on. P HLL Sensor P E SPI Flash P Touch Pad / on. P P Power / on. P.V.V_S VPU V_S V VPU V_S V SMR_VTERM SMR_VREF Quanta omputer Inc. PROJET : TE Size ocument Number Rev lock iagram Wednesday, March 0, 00 ate: Sheet of

2 LOK Gen V L [LK] PY00T-0Y-N_ 0m(0mils) Pin// Sligo =>.V (L000000) Sligo0 =>.V (LSP0000) V_K0_V VIO_LK 0m(0mils) L PY00T-0Y-N_.0V.V L [] LK_PH_M 0.U/0V_X 0 *0.U/0V_X 0.U/0V_X R _ *P/0V_ 0m(0mils) *0.U/0V_X 0 *0.U/0V_X.V_K0_V R *0@0_ XTL_OUT XTL_IN PU_SEL GT_SM GLK_SM 0 U0 V_ V_REF V_OT_. V_SR_. V_PU_. XTL_OUT XTL_IN REF_0/PU_SEL S SL VSS_OT VSS_ VSS_ST VSS_SR VSS_PU VSS_REF V_SR_I/O V_PU_I/O OT_ OT_# M M_SS SR_/ST 0 SR_#/ST# SR_ SR_# *PU_STOP# PU_ 0 PU_# PU_0 PU_0# KPWRG/P# REFLK_R REFLK#_R LK_VG_M_R LK_VG_M#_R REFSSLK_R REFSSLK#_R PIE_GPLL_R PIE_GPLL#_R IS_PU_STOP# *0U/.V_X LK_UF_LK_P_R LK_UF_LK_N_R LK_UF_LK0_P_R LK_UF_LK0_N_R R VR_PWRG_LKEN TP TP 0U/.V_X RP RP RP 0K_ RP 0.U/0V_X 0.U/0V_X R R V *short_pr *_ *_ *short_pr *short_pr *short_pr *P/0V_ LK_UF_REFLKP [] LK_UF_REFLKN [] LK_UF_REFSSLKP [] LK_UF_REFSSLKN [] LK_UF_PIE_GPLLP [] LK_UF_PIE_GPLLN [] LK_UF_LKP [] LK_UF_LKN [] SLGSPVTR LK RYSTL LK PU_SEL LK I LK POWERGOO hange to VPU (follow R) V V R VPU R 0K_ VR_PWRG_LKEN Y XTL_IN XTL_OUT.MHZ_0 P/0V_N P/0V_N *0K_ PU_SEL R 0K_ [,,0] ST N00_00M Q R 0K_ GT_SM R GT_SM [,] [0] VR_PWRG_K0# Q N00_00M R 00K/F_ V 0K_ PU_SEL PU =MHz (default) 0 PU=00MHz [,,0] SLK N00_00M Q0 GLK_SM GLK_SM [,] Size ocument Number Rev LOK GENERTOR Quanta omputer Inc. PROJET : TE ate: Friday, March, 00 Sheet of

3 [] MI_TXN0 [] MI_TXN [] MI_TXN [] MI_TXN [] MI_TXP0 [] MI_TXP [] MI_TXP [] MI_TXP [] MI_RXN0 [] MI_RXN [] MI_RXN [] MI_RXN [] MI_RXP0 [] MI_RXP [] MI_RXP [] MI_RXP.GT/s data rate [] FI_TXN[:0] FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN [] FI_TXP[:0] FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP [] FI_FSYN0 [] FI_FSYN [] FI_INT [] FI_LSYN0 [] FI_LSYN U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] F MI Intel(R) FI FI_INT FI_LSYN[0] FI_LSYN[] I,U_F_rPG,RP0 PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_OMP PEG_RIS K J J G G F F E 0 J H H F G E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K G0 G F E R R./F_ 0/F_ [] HWPG R [,,0,,] *short_ R *short_ PLTRST# U [0] XP_TLK V [] [0] H_PEI PM_SYN H_PWRGOO H_TERR# R0 H_PURST#_R R XP_TMS R XP_TI_R R XP_PREQ# R R R HWPG_ TSH0FU(F) R0 R0 R0 R0 TP TP TP TP TP TP TP TP0 TP TP.K/F_ R H_TERR# H_PROHOT#_ PU_PM_THRMTRIP# H_PURST#_R PM_RM_PWRG VTT./F_ *_ *_ *_ *_ *_ R0 K/F_ U 0/F_ H_OMP T 0/F_ H_OMP OMP T./F_ H_OMP OMP G./F_ H_OMP0 OMP T OMP0 H SKTO# H_VTTPWRG PU_PLTRST# 0/F_ H_VTTPWRG R K/F_ K T N K P L N N K M M L J K K J J H K H JTG MPPING XP_TI_R XP_TO_M XP_TI_M XP_TO_R TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_0 SM_RMPWROK TPPWRGOO VTTPWRGOO RSTIN# XP_TRST# R _ MIS LOKS THERML PWR MNGEMENT PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] I,U_F_rPG,RP0 Ra R0 0_ Rb R *0_ Rc R0 0_ Rd R *0_ Re R 0_ R MIS JTG & PM LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# R0 T0 E F L M N N P T P N P T T R R P N LK_REFSSLKP_R LK_REFSSLKN_R R_RMRST#_ SM_ROMP_0 SM_ROMP_ SM_ROMP_ PM_EXT_TS#0 PM_EXT_TS# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO_R XP_TI_M XP_TO_M Processor hot [0] R0 R R R R0 R R R H_PROHOT# Thermal Trip 00/F_./F_ 0/F_ 0K_ *short_ *short_ 0K_ *short_pr VTT LK_PU_LKP [0] LK_PU_LKN [0] TP TP LK_PIE_GPLLP [] LK_PIE_GPLLN [] LK_REFSSLKP [] PLL_REF_SSLK LK_REFSSLKN [] Only for UM R 0_ VTT PM_EXTTS#0 [] PM_EXTTS# [] VTT TP SYS_RESET# [] VTT R0 _ H_PROHOT#_ If R no stuff must change R0 to 0 ohm [,] MPWROK R *0_ R *0_ for S power reduction.vsus [,0] ELY_VR_PWRGOO Q N00_00M [0] R_RMRST#_PH R K_ Scan hain (efault) STUFF -> Ra, Rc, Re NO STUFF -> Rb, Rd VTT R0 R R *00K_ 0 0.U/0V_X Q R *0_ R_RMRST# [,] PU Only GMH Only STUFF -> Ra, Rb NO STUFF -> Rc, Rd, Re STUFF -> Rd, Re NO STUFF -> Ra, Rb, Rc PU_PM_THRMTRIP# R *./F_ K_ Q MMT0--F_00M SYS_SHN# 00K_ SYS_SHN# [] SS_NL_0.M R_RMRST#_ R 0_ PM_THRMTRIP# PM_THRMTRIP# [0].V_PUVQ V_S R K_ R 0K/F_ R 0K/F_ Q N00_00M Q FV0N_NL_00M.V_PUVQ_PG [] V_S R 0K/F_ V_S U R0 TSH0FU(F).K/F_ R 0/F_ R *short_.vsus PU FN TRL PM_RM_PWRG [] TEMP_LERT# [0,] TEMP_LERT# Q V m(0mils) V U.U/.V_X VIN VO PUFN#_ON_R_ N00_00M /FON [] VFN VSET GPU 0mils TH_FN_POWER 0U/.V_X V R 0K_ [] FNSIG FNSIG 0.0U/V_X *0.0U/V_X N 0-000L FNPWR =.*VSET PM_RM_PWRG: Never drive hight before R voltage ramp to stable R *.K/F_ PM_RM_PWRG R *K/F_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER /(HOST&PEX) Tuesday, March 0, 00 ate: Sheet of

4 UURNLE/LRKSFIEL PROESSOR (R) [] M Q[:0] U M Q0 0 M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] M Q S_Q[] 0 M Q S_Q[] 0 M Q S_Q[] E0 M Q S_Q[] M Q S_Q[] M Q S_Q[] F0 M Q0 S_Q[] E M Q S_Q[0] F M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] H0 M Q S_Q[] G M Q S_Q[] K M Q S_Q[] J M Q0 S_Q[] G M Q S_Q[0] G0 M Q S_Q[] J M Q S_Q[] J0 M Q S_Q[] L M Q S_Q[] M M Q S_Q[] M M Q S_Q[] L M Q S_Q[] L M Q S_Q[] K M Q0 S_Q[] N M Q S_Q[0] P M Q S_Q[] H M Q S_Q[] F M Q S_Q[] K M Q S_Q[] K M Q S_Q[] F M Q S_Q[] G M Q S_Q[] J M Q S_Q[] J M Q0 S_Q[] J0 M Q S_Q[0] J M Q S_Q[] L0 M Q S_Q[] K M Q S_Q[] K M Q S_Q[] L M Q S_Q[] K M Q S_Q[] L M Q S_Q[] N M Q S_Q[] M0 M Q0 S_Q[] R M Q S_Q[0] L M Q S_Q[] M M Q S_Q[] N M Q S_Q[] T M Q S_Q[] P M Q S_Q[] M M Q S_Q[] N M Q S_Q[] M M Q S_Q[] T M Q0 S_Q[] T M Q S_Q[0] L M Q S_Q[] R M Q S_Q[] P S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F M M0 M M H M M M M M G M M M M M N0 M M N M M M QSN0 F M QSN J M QSN N M QSN H M QSN K M QSN P M QSN T M QSN M QSP0 F M QSP H M QSP M M QSP H M QSP K0 M QSP N M QSP R M QSP Y M 0 W M M M V M M V T M M Y M U M M 0 T M U M G M T M V M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M M[:0] [] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to on So-IMM side for larkfield design only M QSN[:0] [] M QSP[:0] [] M [:0] [] [] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U S_Q[0] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] F S_Q[0] F S_Q[] S_Q[] F S_Q[] F S_Q[] G S_Q[] H S_Q[] G S_Q[] J S_Q[] J S_Q[] G S_Q[0] G S_Q[] J S_Q[] J S_Q[] J S_Q[] K S_Q[] L S_Q[] M S_Q[] K S_Q[] K S_Q[] M S_Q[0] N S_Q[] F S_Q[] G S_Q[] J S_Q[] K S_Q[] G S_Q[] G S_Q[] J S_Q[] H S_Q[] K S_Q[0] K S_Q[] M S_Q[] N S_Q[] K S_Q[] K S_Q[] M S_Q[] M S_Q[] P S_Q[] N S_Q[] T S_Q[0] N S_Q[] N S_Q[] N S_Q[] T S_Q[] T S_Q[] N S_Q[] P S_Q[] P S_Q[] T S_Q[] T S_Q[0] P S_Q[] R0 S_Q[] T0 S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M E M M0 M M H M M K M M H M M L M M R M M T M M M QSN0 F M QSN J M QSN L M QSN H M QSN L M QSN R M QSN R M QSN M QSP0 E M QSP H M QSP M M QSP G M QSP L M QSP P M QSP R M QSP U V T V M 0 M M M R M T R M M R M R M R M M 0 P M R F M M P M N M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M OT0 [] M OT [] M M[:0] [] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to on So-IMM side for larkfield design only M QSN[:0] [] M QSP[:0] [] M [:0] [] [] M S#0 [] M S# [] M S# U S_S[0] S_S[] S_S[] [] M S#0 [] M S# [] M S# W R S_S[0] S_S[] S_S[] [] M S# [] M RS# [] M WE# E S_S# S_RS# E S_WE# I,U_F_rPG,RP0 [] M S# [] M RS# [] M WE# S_S# Y S_RS# S_WE# I,U_F_rPG,RP0 Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER /(R) ate: Friday, February, 00 Sheet of

5 VI PSI# VI VI0 VI VI IH_PRSTP# VI VI TP_VSS_SENSE_VTT VTT_SENSE ISENSE VI VI VI0 VI IH_PRSTP# VI PSI# VI VI MIN VTT_ VTT_ GFXVR_EN VSENSE [0] VSSSENSE [0] PSI# [0] IH_PRSTP# [0] H_VI0 [0] H_VI [0] H_VI [0] H_VI [0] H_VI [0] H_VI [0] H_VI [0] ISENSE [0] MIN [,,] MINON_ON_G [,,] GFXVR_VI_0 [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] GFXVR_VI_ [] V_XG_SENSE [] VSS_XG_SENSE [] GFXVR_IMON [] GFXVR_PRSLPVR [] GFXVR_EN [] VTT VTT VTT.V VXG V_ORE VTT VTT VTT V_ORE.VSUS.V_PUVQ.V_PUVQ V.V_PUVQ V_ORE VXG Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Tuesday, March 0, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Tuesday, March 0, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Tuesday, March 0, 00 TE VTT Rail Values are uburndal VTT=.0V H_VTTVI=Low,.V H_VTTVI=High,.0V HFM_VI : Max.V LFM_VI : Min 0.V for S power reduction /maximum (mils) VI for UM R *K_ R *K_ POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF I,U_F_rPG,RP0 POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF I,U_F_rPG,RP0 ISENSE N VTT_SENSE PSI# N VI[0] K VI[] K VI[] K VI[] L VI[] L VI[] M VI[] M PRO_PRSLPVR M VTT_SELET G V_SENSE J VSS_SENSE_VTT V G V G V G V G V G V G0 V G V G V G V0 G V F V F V F V F V F V F0 V F V F V F V0 F V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V Y V Y V Y V Y V Y V Y0 V Y V Y V Y V0 Y V V V V V V V V V V V V0 V V V V V V V0 V V U V U V U V U V U V U0 V U V U V U V0 U V R V R V R V R V R V R0 V R V R V R V0 R V P V P V P V P V P V P0 V P V P V P V00 P VTT0_ F0 VTT0_ E0 VTT0_ 0 VTT0_ 0 VTT0_ Y0 VTT0_ W0 VTT0_ U0 VTT0_0 T0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ H VTT0_ H0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ G VTT0_0 G VTT0_ G VTT0_ G VTT0_ F VTT0_ F VTT0_ F VTT0_ F VTT0_ E VTT0_ E VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VSS_SENSE J VTT0_ J VTT0_ J 0U/.V_X 0U/.V_X.U/.V_X.U/.V_X *0U/V_P_Eb *0U/V_P_Eb 0U/.V_X 0U/.V_X 0 0U/.V_X 0 0U/.V_X R *K_ R *K_.U/.V_X.U/.V_X 0U/.V_X 0U/.V_X U/.V_X U/.V_X 0U/.V_X 0U/.V_X 0 0U/.V_X 0 0U/.V_X R K_ R K_ R *K_ R *K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X 0.U/0V_X 0.U/0V_X R *00K_ R *00K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0 0U/.V_X 0 0U/.V_X U/.V_X U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X *0.0U/0V_X *0.0U/0V_X Q O_. Q O_. R 0_ R 0_ R *0_ R *0_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R *K_ R *K_ *0.0U/0V_X *0.0U/0V_X R *0_ R *0_ 0U/.V_X 0U/.V_X TP TP POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG I,U_F_rPG,RP0 POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG I,U_F_rPG,RP0 GFX_VI[0] M GFX_VI[] P GFX_VI[] N GFX_VI[] P GFX_VI[] M GFX_VI[] P GFX_VI[] N GFX_VR_EN R GFX_PRSLPVR T GFX_IMON M VXG_SENSE R VSSXG_SENSE T VXG T VXG T VXG T VXG T VXG R VXG R VXG R VXG R VXG P VXG0 P VXG P VXG P VXG N VXG N VXG N VXG N VXG M VXG M VXG M VXG0 M VXG L VXG L VXG L VXG L VXG K VXG K VXG K VXG K VXG J VXG0 J VXG J VXG J VXG H VXG H VXG H VXG H VTT_ J VTT_ J VTT_ H VTT_ K VTT_ J VTT_0 J VTT_ J VTT_ H VTT_ G VTT_ G VTT_ G VTT_ F VTT_ E VTT_ E VQ J VQ F VQ E VQ E VQ VQ VQ VQ Y VQ W VQ0 W VQ U VQ T VQ T VQ P VQ N VQ N VQ L VQ H VTT0_ P0 VTT0_0 N0 VTT0_ L0 VTT0_ K0 VPLL L VPLL L VPLL M VTT_ J VTT_ J0 VTT_ J VTT_ H VTT_ H0 VTT_ H U/.V_X U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R0 *short_ R0 *short_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0 *0U/V_P_Eb 0 *0U/V_P_Eb 0 U/.V_X 0 U/.V_X 0U/.V_X 0U/.V_X 0 *0U/.V_X 0 *0U/.V_X R K_ R K_ U/.V_X U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R *K_ R *K_ R K_ R K_ U/.V_X U/.V_X 0 U/.V_X 0 U/.V_X R *K_ R *K_ TP TP 0U/.V_X 0U/.V_X 0 *0U/V_P_Eb 0 *0U/V_P_Eb 0 *0U/V_P_Eb 0 *0U/V_P_Eb R 00/F_ R 00/F_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R K_ R K_ Q MN0K-_00M Q MN0K-_00M 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R 00/F_ R 00/F_ 0 0U/.V_X 0 0U/.V_X 0 0U/.V_X 0 0U/.V_X R *K_ R *K_ 0U/.V_X 0U/.V_X *0.0U/0V_X *0.0U/0V_X 0 0U/.V_X 0 0U/.V_X 00 0U/.V_X 00 0U/.V_X R0 *short_ R0 *short_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R0 *K_ R0 *K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X TP TP R *K_ R *K_ R K_ R K_ 0U/.V_X 0U/.V_X *0U/.V_X *0U/.V_X 0U/.V_X 0U/.V_X *0U/V_P_Eb *0U/V_P_Eb *0U/V_P_Eb *0U/V_P_Eb R0 K_ R0 K_ 0U/.V_X 0U/.V_X 0.0U/V_X 0.0U/V_X 0.U/0V_X 0.U/0V_X

6 UURNLE/LRKSFIEL PROESSOR () UH T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 VSS VSS E VSS E VSS E VSS E VSS E0 VSS E VSS E VSS E VSS E VSS0 E VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS00 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 0 VSS0 Y VSS0 Y VSS0 Y VSS0 W VSS W VSS W VSS W VSS W VSS W0 VSS W VSS W VSS W VSS W VSS0 W VSS V0 VSS U VSS U VSS U VSS T VSS T VSS T VSS T VSS T VSS0 T0 VSS T VSS T VSS T VSS T VSS T VSS R0 VSS P VSS P VSS P VSS0 N VSS N VSS N VSS N VSS N VSS N0 VSS N VSS N VSS N VSS N VSS0 N VSS M0 VSS L VSS L VSS L VSS L VSS L VSS L VSS K VSS K VSS0 K0 UI K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS G VSS G VSS G0 VSS G VSS G VSS G VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS T VSS_NTF T R *short_ VSS_NTF R R *short_ VSS_NTF R *short_ VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS I,U_F_rPG,RP0 I,U_F_rPG,RP0 NTF UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) [] R_VREF_Q0 [] R_VREF_Q TP R R *0_ *0_ FG0 FG FG FG TP_RSV_R TP_RSV_R UE J S_IMM_VREF H S_IMM_VREF M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV G RSV G RSV E RSV E0 RSV RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ J RSV J RSV H RSV K RSV L RSV R RSV_NTF_ J RSV J RSV P RSV_NTF_0 RESERVE I,U_F_rPG,RP0 RSV_NTF_ T RSV_NTF_ T RSV_NTF_ R RSV L RSV L RSV P0 RSV P RSV L RSV0 T RSV T RSV P RSV R RSV_NTF_ T RSV_NTF_ T RSV_NTF_ P RSV_NTF_ R RSV R RSV_TP_ E RSV_TP_0 F KEY RSV RSV RSV_R R RSV J RSV_R R RSV H RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ G RSV_TP_ E RSV_TP_ V RSV_TP_ V RSV_TP_ N RSV_TP_ RSV_TP_0 RSV_TP_ W RSV_TP_ W RSV_TP_ N RSV_TP_ E RSV_TP_ VSS P For iscrete only FG0 R FG R FG R FG R *0_ *0_ TP *.0K/F_.0K/F_ *.0K/F_ *.0K/F_ The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k /- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. FG (isplay Port Presence) FG0 (PI-Epress onfiguration Select) FG (PI-Epress Static Lane Reversal) 0 isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation FG[ :0 ] - PI_Epress onfiguration Select Enabled; n external isplay port * = x PEG device is connected to the Embedded * 0= x PEG isplay port ifurcation enabled Lane Numbers Reversed -> 0, -> Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER / () ate: Tuesday, March 0, 00 Sheet of

7 INTVRMEN - Integrated SUS.V VRM Enable High - Enable Internal VRs RT_ELL RT_ELL [] [0,] [0,] Y.KHZ_0 PEEP Z_SIN0_UIO TP TP0 TP [0] P/0V_ PH_GPIO TP SPI_SI_R P/0V_ R R0 RT_RST# SRT_RST# M_ SM_INTRUER# 0K_ PH_INVRMEN TP R 0M_ Z_ITLK Z_SYN Z_RST# Z_SOUT PH_JTG_TK PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# SPI_LK_R SPI_S0#_R SPI_S# SPI_SI_R SPI_SO RT_X RT_X IEX PEK-M (H,JTG,ST) 0 P 0 G0 F0 E F H J0 M K K J J V Y Y V U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN Ibex-M OF 0 RT H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN IH H_SIN H_SIN H_SO H_OK_EN# / GPIO (V) H_OK_RST# / GPIO (V_S) JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IbexPeak-M_Rev_0 JTG SPI FWH0 / L0 FWH / L LP FWH / L FWH / L FWH / LFRME# LRQ0# (V) LRQ# / GPIO SERIRQ ST ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# (V) ST0GP / GPIO (V_S) STGP / GPIO F K K K K H H H H F F F F H H F F F F T Y V ST_TXN_ ST_TXP_ ST_OMP ST_LE# R R L0 [,] L [,] L [,] L [,] LFRME# [,] LRQ# [] 0 R 0K_ 0K_ V 0.0U/V_X 0.0U/V_X./F_ V V R 0K_.0V SERIRQ [,] ST_RXN0 [] ST_RXP0 [] ST_TXN0 [] ST_TXP0 [] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP [] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP [] ST_LE# [] [] [] V H O EST RT_HSYN RT_VSYN [] LVS_RIGHT [] LVS_IGON [] LVS_PWM [] L_EILK [] L_EIT R 0K_ R 0K_ [] [] [] [] [] [] [] [] L_TXLLKOUT- L_TXLLKOUT L_TXLOUT0- L_TXLOUT- L_TXLOUT- TP L_TXLOUT0 L_TXLOUT L_TXLOUT TP [] [] [] [] [] TP RT_LU RT_GRE RT_RE RT_LK RT_T R 0_ R0 0_ R T T Y Y L_TRL_LK L_TRL_T V LVS_IG P LVS_VG P LVS_VREFH T LVS_VREFL T V V Y V 0 Y V P P Y T U T Y T U0 T RT_LU RT_GRE RT_RE V V RT_HSYN_R Y RT_VSYN_R Y K/ IREF IEX PEK-M (LVS,I) U L_KLTEN Ibex-M SVO_TVLKINN L_V_EN OF 0 SVO_TVLKINP L_KLTTL SVO_STLLN SVO_STLLP L LK L T SVO_INTN SVO SVO_INTP L_TRL_LK L_TRL_T SVO_TRLLK SVO_TRLT LV_IG LV_VG P_UXN P_UXP LV_VREFH P_HP LV_VREFL P_0N LVS-- P_0P LVS_LK# P_N LVS_LK P_P P_N LVS_T#0 P_P LVS_T# P_N LVS_T# P_P LVS_T# P_TRLLK LVS_T0 P_TRLT LVS_T LVS_T P_UXN LVS_T P_UXP P_HP LVS-- LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN RT igital isplay Interface ISPLY PORT ISPLY PORT ISPLY PORT P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P J G J G F H T T G J U J G 0 0 W Y E V0 E0 0 F H U0 U T J0 G0 J G F H E TP TP INT_HMI_SL [] INT_HMI_S [] P_UXN R 0K_ P_UXP R00 0K TMS_T# _TMS_T _TMS_T# _TMS_T _TMS_T0# _TMS_T0 _TMS_LK# _TMS_LK Port-_HP [] V IbexPeak-M_Rev_0 [RT] RT TTERY VPU (0mils) (0mils) R_VRT H0H-0PT_00M H0H-0PT_00M RT_ELL (0mils) Port LVS Port Port Strap L T SVO_TRLT P_TRLT How to enable Port? PU to.v with.k/- % PU to.v with.k/- % PU to.v with.k/- % How to disable Port? N N N [UM] R0 R R0 R R EMI _TMS_T _TMS_T *short_ LVS_VREFH LVS_VREFL.K/F_ LVS_IG 0/F_ RT_LU 0/F_ RT_GRE 0/F_ RT_RE HM@.P/0V TMS_T# HM@.P/0V TMS_T# R K_ RT_N0 (0mils) R0 U/0V_X.K/F_ R.K/F_ (0mils) VPU Port ep P_TRLT FG[] PU to.v with.k/- % P to directly N N _TMS_T0 _TMS_LK HMI _TMS_T _TMS_T# HM@.P/0V TMS_T0# HM@.P/0V TMS_LK# HM@0.U/0V_X HM@0.U/0V_X TMS_T [] TMS_T# [] Q MMT0--F_00M R _TMS_T _TMS_T# 0 HM@0.U/0V_X HM@0.U/0V_X TMS_T [] TMS_T# [] N -T-0-K0 RT_N0 (0mils).K/F_ R K/F TMS_T0 _TMS_T0# _TMS_LK _TMS_LK# HM@0.U/0V_X HM@0.U/0V_X HM@0.U/0V_X HM@0.U/0V_X TMS_T0 [] TMS_T0# [] TMS_LK [] TMS_LK# [] For UIO [] Z_RST#_UIO [] Z_SOUT_UIO [] [] Z_SYN_UIO IT_LK_UIO.0V R *_ PH_JTG_TMS R0 _ Z_RST# R0 _ Z_SOUT *0P/0V_ RESET JUMP RT_ELL R0 _ Z_SYN *0P/0V_ R 0K_ R0 _ Z_ITLK P/0V_N RT_ELL n R delay circuit with a time delay in the range of ms to ms should be provided U/.V_X RT_RST# G *SHORT_ P M byte SPI ROM SPI_SO SPI_SI_R SPI_LK_R SPI_S0#_R R 0_ R 0_ R 0_ R 0_ SPI_SO_R SPI_SI SPI_LK SPI_S0# U SO SI SK E V SPI_HOL# HOL WP VSS SPI_WP# R R0.K/F_.K/F_ V PH PM HM HM/PM QM/QS M M M R *_ PH_JTG_RST# R *_ PH_JTG_TI R *_ PH_JTG_TO R _ PH_JTG_TK R 0K_ U/.V_X SRT_RST# G *SHORT_ P WQVSSIG 0.U/0V_X Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (ST,H,LP) Wednesday, March 0, 00 ate: Sheet of

8 IEX PEK-M () UI Y VSS[] VSS[] H VSS[0] VSS[0] H VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L G VSS[0] VSS[0] L VSS[] VSS[] L VSS[] VSS[] L0 0 VSS[] VSS[] L VSS[] VSS[] M 0 VSS[] VSS[] M VSS[] VSS[] M0 VSS[] VSS[] N VSS[] VSS[] M VSS[] VSS[] M VSS[0] VSS[0] M 0 VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] N VSS[] VSS[] P VSS[] VSS[] 0 VSS[] VSS[] P VSS[] VSS[] P0 VSS[0] VSS[0] P H VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P E VSS[] VSS[] R E VSS[] VSS[] R E0 VSS[] VSS[] T E VSS[] VSS[] T E0 VSS[] VSS[] T E VSS[00] VSS[00] T E VSS[0] VSS[0] T E VSS[0] VSS[0] T E VSS[0] VSS[0] U0 E VSS[0] VSS[0] U E0 VSS[0] VSS[0] U E VSS[0] VSS[0] U E VSS[0] VSS[0] P F VSS[0] VSS[0] V F VSS[0] VSS[0] P F VSS[0] VSS[0] V G VSS[] VSS[] V0 G VSS[] VSS[] V G VSS[] VSS[] V0 G0 VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[0] VSS[0] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V VSS[] VSS[] V 0 VSS[] VSS[] V VSS[] VSS[] W E VSS[] VSS[] W E VSS[] VSS[] Y E0 VSS[0] VSS[0] Y E VSS[] VSS[] Y E0 VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y0 E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y F VSS[0] VSS[0] Y F VSS[] VSS[] P G0 VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] P G VSS[] VSS[] T G VSS[] VSS[] G VSS[] VSS[] T G0 VSS[] VSS[] G VSS[0] VSS[0] Y G VSS[] VSS[] T F VSS[] VSS[] M H VSS[] VSS[] T H0 VSS[] VSS[] M H0 VSS[] VSS[] K H VSS[] VSS[] K H VSS[] VSS[] V H VSS[] IbexPeak-M_Rev_0 PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ0# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_RQ# SMLERT# SML0LERT# SM_LK_ME0 SM_T_ME0 SMLLERT# MLK MT SLK ST PEG_LKREQ# MLK MT Q V_S Q R R 0K_ 0K_ V N_MLK [] N_MT [] G [] PIE_RXN [] PIE_RXP [] PIE_TXN [] PIE_TXP [] PIE_RXN [] PIE_RXP WLN [] PIE_TXN [] PIE_TXP LN G WLN [0] PIE_RXN [0] PIE_RXP LN [0] PIE_TXN [0] PIE_TXP [0] LK_PIE_LN# [0] LK_PIE_LN [0] PIE_LK_REQ# [] LK_PIE_G# [] LK_PIE_G [] PIE_LK_REQ# [] LK_PIE_MINI# [] LK_PIE_MINI [] PIE_LK_RQ# TP TP TP TP TP TP TP TP TP TP TP TP PIE_RXN PIE_RXP 0.U/0V_XPIE_TXN_ 0.U/0V_XPIE_TXP_ V_S R0 0K_ TP R *0K_ TP R 0K_ TP R 0K_ TP R 0K_ R 0K_ R0 0K_ R.K_ PIE_LK_REQ0# R.K_ TP0 R 0K_ TP R0.K_ R0.K_ PIE_LK_REQ# R.K_ R.K_ TP TP0 R 0K_ PIE_LK_REQ# N00_00M N00_00M 0 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X PIE_LK_REQ# PIE_LK_REQ# PIE_LK_RQ# TP TP PIE_LK_REQ# PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ IEX PEK-M (PI-E,SMUS,LK) U G0 PERN J0 PERP F PETN H PETP W0 PERN 0 PERP 0 PETN 0 PETP PIE_RXN U0 PIE_RXP PERN T0 PIE_TXN_ PERP U PIE_TXP_ PETN V PETP PERN PERP PETN E PETP F PERN H PERP G PETN J PETP PERN W PERP PETN PETP T PERN U PERP U PETN V PETP G PERN J PERP G PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P IbexPeak-M_Rev_0 Ibex-M OF 0 PI-E* P PIELKRQ0# / GPIO M (V_S) LKOUT_PIEN M LKOUT_PIEP U PIELKRQ# / GPIO (V) K LKOUT_PEG N K LKOUT_PEG P P PEG LKRQ# / GPIO (V_S) SMus (V_S) SMLERT# / GPIO SMLK SMT (V_S) SML0LERT# / GPIO0 SML0LK SML0T (V_S) SMLLERT# / GPIO (V_S) SMLLK / GPIO (V_S) SMLT / GPIO ontroller Link PEG (V_S) PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P From LK UFFER lock Flex L_LK L_T L_RST# XTL_IN XTL_OUT SMLERT# H SLK ST J SML0LERT# SM_LK_ME0 G SM_T_ME0 M SMLLERT# E0 MLK G MT T T T LKOUT_P_N / LKOUT_LK_N T LKOUT_P_P / LKOUT_LK_P T LKIN_MI_N W LKIN_MI_P LKIN_LK_N P LKIN_LK_P P LKIN_OT_N F LKIN_OT_P E L_LK L_T L_RST# H PEG_LKREQ# N N L_LK [] LK_PIE_GPLLN [] LK_PIE_GPLLP [] LK_UF_PIE_GPLLN [] LK_UF_PIE_GPLLP [] LK_UF_LKN [] LK_UF_LKP [] L_T [] L_RST# [] LK_REFSSLKN [] LK_REFSSLKP [] SLK [,,0] ST [,,0] LK_UF_REFLKN [] LK_UF_REFLKP [] M LKOUT_PIEN M LKOUT_PIEP LKIN_ST_N / KSS_N H LK_UF_REFSSLKN [] LKIN_ST_P / KSS_P H LK_UF_REFSSLKP [] N PIELKRQ# / GPIO0 (V) H R 0_ LKOUT_PIEN REFLKIN P LK_PH_M [] H LKOUT_PIEP *P/0V_N LK_PI_F PIELKRQ# / GPIO (V_S) LKIN_PILOOPK J LK_PI_F [] M LKOUT_PIEN M XTL_IN LKOUT_PIEP XTL_IN H XTL_OUT XTL_OUT H M PIELKRQ# / GPIO (V_S) XLK_ROMP XLK_ROMP F.0V R 0./F_ J0 LKOUT_PIEN J LK_FLEX0 R 0K_ LKOUT_PIEP (V) LKOUTFLEX0 / GPIO T V LK_FLEX T (V_S) (V) LKOUTFLEX / GPIO P H LK_FLEX T PIELKRQ# / GPIO (V) LKOUTFLEX / GPIO T LK_R_ (V) LKOUTFLEX / GPIO N0 LK_R_ [] Placement close R M/F_ TP TP Y MHZ_0 P/0V_N P/0V_N P/0V_N Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (PIE, SMUS, K) ate: Wednesday, March 0, 00 Sheet of

9 [0] GNT0# [0] GNT# [0] GNT# V TP0 R PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# REQ0# REQ# REQ# REQ# PIRQE# PIRQF# PIRQG# INTH#.K_ PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# IEX PEK-M (PI,US,NVRM) UE H0 0 N J 0 E H E0 0 0 M M F M0 M J K F0 0 K M J K L F J0 G F M 0 H J0 /E0# G /E# H /E# G /E# G PIRQ# H PIRQ# PIRQ# PIRQ# Ibex-M OF 0 PI F REQ0# REQ# / GPIO0 (V) REQ# / GPIO (V) M REQ# / GPIO (V) F GNT0# K GNT# / GPIO (V) F GNT# / GPIO (V) H GNT# / GPIO (V) PIRQE# / GPIO K (V) PIRQF# / GPIO (V) PIRQG# / GPIO (V) PIRQH# / GPIO (V) K PIRST# E SERR# E0 PERR# IRY# H PR F EVSEL# FRME# PLOK# STOP# TRY# NVRM US NV_E#0 Y NV_E# NV_E# P NV_E# NV_QS0 V NV_QS G NV_Q0 / NV_IO0 P NV_Q / NV_IO P NV_Q / NV_IO T NV_Q / NV_IO T NV_Q / NV_IO NV_Q / NV_IO V NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO E NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO J NV_Q / NV_IO J NV_Q / NV_IO G NV_LE NV_LE Y NV_ROMP NV_LE NV_ROMP R USP0- [] USP0 [] TP TP0 USP- [] USP [] USP- [] USP [] USP- [] USP [] USP- [] USP [] TP TP0 TP TP USP- [] USP [] USP- [] USP [] USP0- [] USP0 [] TP TP TP TP USP- [] USP []./F_ luetooth ard Reader SIM WLN TP M PME# US_O0# PLT_RST-R# (V_S) O0# / GPIO N US_O# PLTRST# (V_S) O# / GPIO0 J US_O# [] PLK_EUG R _ LK_M_LP_R (V_S) O# / GPIO F N US_O# TP LKOUT_PI0 (V_S) O# / GPIO L P USO# USO# [,] TP LKOUT_PI (V_S) O# / GPIO E P US_O# [] LK_PI_F LK_PI_F_R (V_S) O# / GPIO G R _ LKOUT_PI P USO#_ USO#_ [,] R _ LK_PI_E LKOUT_PI (V_S) O# / GPIO0 F SI# [] PLK_ P LKOUT_PI (V_S) O# / GPIO T SI# [] NV_R# U V NV_WR#0_RE# Y NV_WR#_RE# Y NV_WE#_K0 V NV_WE#_K F USP0N H USP0P J USPN USPP USPN N0 USPP P0 USPN J0 USPP L0 USPN F0 USPP G0 USPN 0 USPP 0 USPN M USPP N USPN USPP USPN H USPP J USPN E USPP F USP0N USP0P USPN G USPP H USPN L USPP M USPN USPP US_IS R00 USRIS# USRIS US US G EST PLT_RST-R# R *00K_ R V_S *0_ 0.U/0V_X V_S IEX PEK-M (MI,FI,GPIO) U FI_RXN0 FI_TXN0 [] [] MI_RXN0 MI0RXN Ibex-M FI_RXN H FI_TXN [] [] MI_RXN J MIRXN OF 0 FI_RXN FI_TXN [] [] MI_RXN W0 MIRXN FI_RXN J FI_TXN [] [] MI_RXN J0 MIRXN FI_RXN FI_TXN [] FI_RXN E FI_TXN [] [] MI_RXP0 MI0RXP FI_RXN FI_TXN [] [] MI_RXP G MIRXP FI_RXN FI_TXN [] [] MI_RXP 0 MIRXP [] MI_RXP G0 MIRXP FI_RXP0 FI_TXP0 [] FI_RXP F FI_TXP [] [] MI_TXN0 E MI0TXN FI_RXP FI_TXP [] [] MI_TXN F MITXN MI FI FI_RXP G FI_TXP [] [] MI_TXN 0 MITXN FI_RXP W FI_TXP [] [] MI_TXN E MITXN FI_RXP FI_TXP [] FI_RXP FI_TXP [] [] MI_TXP0 MI0TXP FI_RXP FI_TXP [] [] MI_TXP H MITXP [] MI_TXP 0 MITXP [] MI_TXP MITXP FI_INT J FI_INT [] FI_FSYN0 F FI_FSYN0 [] FI_FSYN H FI_FSYN [] NV_LE [0] H FI_LSYN0 [].0V R0./F_ MI_OMP MI_ZOMP FI_LSYN0 J F MI_IROMP FI_LSYN G FI_LSYN [] *./F_ System Power Management [] SYS_RESET# SYS_RESET# T SUS# [] SYS_PWROK R *short_ SYS_RESET# SLP_S# P M SUS# [] R *short_ SYS_PWROK SLP_S# H R *short_ PWROK K SLP_M# MEPWROK SLP_M# K TP RSV_IH_LN_RST# TP N 0 TP LN_RST# [] PM_RM_PWRG SUS_PWR_K_R [] RSMRST# RSMRST# RMPWROK (V_S) SUS_PWR_N_K / GPIO0 M _PRESENT RSMRST# (V_S) PRESENT / GPIO P LKRUN# LKRUN# [] [] NSWON# NSWON# (V) LKRUN# / GPIO Y P RSV_SUS_ST# PWRTN# (V_S) SUS_STT# / GPIO P TP (V_S) SUSLK / GPIO F SLP_S# TP (V_S) PM_RI# SLP_S# / GPIO E F PM_TLOW# TP [,0] PIE_WKE# PIE_WKE# RI# (V_S) TLOW# / GPIO J WKE# [] PM_SYN J0 PMSYNH (V_S) SLP_LN# / GPIO F TP U TSH0FU(F) Q IbexPeak-M_Rev_0 R 00K/F_ N00_00M PLTRST# [,,0,,] RSMRST# RSV_IH_LN_RST# REQ# PIRQE# PIRQF# LKRUN# PIRQG# SYS_RESET# PM_RI# PM_TLOW# PIE_WKE# SUS_PWR_K_R _PRESENT NSWON# R R R R R R0 R R R R R0 R R R 0K_ 0K_.K_.K_.K_.K_.K_ K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ V V_S V_S 0.U/0V_X IbexPeak-M_Rev_0 [] SUS_PWR_K SUS_PWR_K_R P/0V_N P/0V_N P/0V_N R *0_ [,0] ELY_VR_PWRGOO [,] MPWROK SYS_PWROK U TSH0FU(F) R V_S USO#_ US_O# US_O# US_O# RP.KX 0 V RP SI# US_O0# PI_IRY# PI_SERR# PI_PIRQ# US_O# PI_STOP# PI_FRME# USO# PI_PIRQ# REQ# V_S PI_PIRQ# 0 V.KX V RP0 REQ# PI_EVSEL# INTH# PI_TRY#.KX 0 PI_PLOK# PI_PERR# REQ0# PI_PIRQ# V R 00K_ 0K_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (PI,ONFI,US,MI) ate: Wednesday, March 0, 00 Sheet of

10 IEX PEK-M (GPIO,VSS_NTF,RSV) IEX PEK-M () [] EST_N# [] R_RMRST#_PH [,] TEMP_LERT# OR_I OR_I GPIO OR_I GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO EST_N# GPIO GPIO GPIO OR_I TEMP_LERT# GPIO GPIO GPIO OR_I OR_I GPIO Y J F0 K T F Y V P F H0 H F M V V 0 E E F F H UF MUSY# / GPIO0 (V) TH / GPIO (V) TH / GPIO (V) TH / GPIO (V) GPIO (V_S) V_S GPIO MIS LN_PHY_PWR_TRL / GPIO (V_S) 0GTE GPIO (V_S) STGP / GPIO (V) LKOUT_LK0_N/LKOUT_PIEN TH0 / GPIO (V) LKOUT_LK0_P/LKOUT_PIEP SLOK / GPIO (V) PEI GPIO (V_S) GPIO (V_S) STGP / GPIO (V) STGP / GPIO (V) STOUT0 / GPIO (V) PIELKRQ# / GPIO (V_S) STOUT / GPIO (V) STGP / GPIO (V) GPIO (V_S) PIELKRQ# / GPIO (V_S) GPIO (V_S) STP_PI# / GPIO (V) STLKREQ# / GPIO (V) SLO / GPIO (V) VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ IbexPeak-M_Rev_0 Ibex-M OF 0 NTF PU RSV LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP RIN# PROPWRG THRMTRIP# TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ H H F F U M M G0 T E0 0 W Y Y V V F M N J K K M N M0 N0 H T P 0 H H H J J J J J J0 J J E E GTE0 PH_PEI_R RIN# PH_THRMTRIP#_R RIN# GTE0 TEMP_LERT# GPIO R TP TP TP TP TP R R R R GTE0 [] LK_PU_LKN [] LK_PU_LKP [] H_PEI [] RIN# [] H_PWRGOO []./F_ PM_THRMTRIP# [] R0./F_ VTT V 0K_ 0K_ 0K_ 0K_ UH VSS[0] VSS[0] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] M VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[00] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] VSS[] VSS[0] 0 VSS[] VSS[0] VSS[] VSS[0] VSS[0] VSS[0] VSS[] VSS[] U VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] VSS[] E VSS[] VSS[] F VSS[] VSS[] Y VSS[0] VSS[0] H VSS[] VSS[] U VSS[] VSS[] F VSS[] VSS[] P VSS[] VSS[] N VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[] VSS[] F VSS[0] VSS[0] G VSS[] VSS[] G VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] H VSS[] VSS[] V VSS[] VSS[] H VSS[] VSS[] H VSS[0] VSS[0] H VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J0 VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[] VSS[] J VSS[0] VSS[0] T VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] M VSS[] VSS[] N VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] IbexPeak-M_Rev_0 K0 K K K K K K K K K K L L M M0 M M M M M0 M M M M M M M U0 M V M M 0 0 N N0 N P P P P P P R R T H T T T T T V V V0 V V0 V V V V V V V W W W F W W W0 W Y Y Y SPKR [,] [,] GNT#/ GPIO PH_GPIO GNT0#, GNT# SPI_MOSI [] NV_LE PH Strap Pin onfiguration Table [] PEEP [] H_OK_EN #/GPIO SPI_SI_R 0 = efault Mode (Internal weak Pull-down) = No Reboot Mode with TO isabled NV_LE GNT# 0 = efault Mode (Internal weak Pull-down) = No Reboot Mode with TO isabled 0 = Top lock Swap Mode = efault Mode (Internal pull-up) [] [] R GNT0# GNT# 0 0 GNT0# GNT# oot IOS Strap PI_GNT0# GNT# 0 0 R R 0K_ *K/F_ R *K_ R R *0K_ JP R *0K/F_ *SHORT P *K/F_ *K/F_ V.V V oot IOS Location LP Reserved (NN) PI SPI GPIO GPIO GPIO GPIO R R R00 R0 0K_ *0K_ *0K_ 0K_ GPIO GPIO GPIO R0 R R 0K_ 0K_ 0K_ GPIO = Enabled 0 = isabled (efault) GPIO R 0K_ V_S GPIO R *0K_ GPIO GPIO R R 0K_ 0K_ EST_N# GPIO GPIO GPIO R R R R0 0K_ 0K_ 0K_ 0K_ GPIO This signal has a weak internal pull up. NOTE: This signal should not be pulled low GPIO R K_ V_S OR I SETTING oard I UM SKU VG SKU W/ M W/O M W/ HMI W/O HMI W/O G W/ G " " W/O T W/ T I H L I H L I H L I H L I H L I H L V V R R 0K_ OR_I 0K_ OR_I PUS# [] T_etect# [] V V V V R0 *0K_ OR_I R0 0K_ R HM@0K_ R M@0K_ OR_I OR_I OR_I R0 *HM@0K_ R *M@0K_ R 0K_ R *EV@0K_ GPIO 0 = Intel ME rypto Transport Layer Security (TLS) cipher suite with no confidentiality = Intel ME rypto Transport Layer Security (TLS) cipher suite with confidentiality GPIO R *0K_ 0 = isables the VccVRM. Need to use on-board filter circuits for analog rails. = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. This signal has a weak internal pull-up. Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (GPIO & Strap) Wednesday, March 0, 00 ate: Sheet of 0

11 V =m(mils).0v V R R H0KF-T_. *0_ V_LO V 0U/.V_X.V.0V R [,,,,] *short_vfi_vrm V.LN_VPLL_FI *short_.0v_vpll_fi Reserve for clear RT Power MINON VORE =.(0mils) UG POWER *short_ R.0V_VORE_IH 0 U/.V_X VORE[] VORE[] Ibex-M.U/.V_X VORE[] OF 0 VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[] H.0V VORE[0] H VORE[] H0 VORE[] H VORE[] J0 VORE[].0V *short_ J VORE[] R0 0m(mils) V ORE.0V_PH_VPLL_EXP K R R0 VIO[] TP V.LN_VPLL_EXP J VPLLEXP *short_0 *short_0 N0 VIO[] N V.S_V_EXP VIO[] N.U/.V_X VIO[] N VIO[] N U/.V_X VIO[] N *0U/V_P_Eb VIO[0] J 0 U/.V_X VIO[] J VIO[] T U/.V_X VIO[] T VIO[] U 0 U/.V_X VIO[] U VIO[] V 0.U/0V_X VIO[] V VIO[] PI E* W 0.U/0V_X VIO[] W VIO[0] 0 0.U/0V_X VIO[] VIO[] VIO[] VIO[] VIO =.0(0mils) VIO[] VIO[] VIO[] VIO[] E VIO[] E VIO[0] G VIO[] G VIO[] H *0.U/0V_X VIO[] N0 VIO[] N VIO[] V R0 *short_ V_VGG N V_[] R TP m(mils) V 0 *0.U/0V_X U SHN VO T J M VIN *G VVRM[] VFIPLL VIO[] SET FI IbexPeak-M_Rev_0 RT LVS HVMOS MI V[] V[] VSS_[] VSS_[] VLVS VSS_LVS VTX_LVS[] VTX_LVS[] VTX_LVS[] VTX_LVS[] V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] NN / SPI VME_[] VME_[] VME_[] VME_[] *0U/.V_X E0 E F F H H VLVS R VMI.V_VME_SPI R0 V_LO P VTX_LVS P T T V_V_GIO 0.0U/V_X V V *short_ V.V.V.V VTT.0V V_S.0V.0V V VTT RT_ELL.0V V_ = 0.(0mils) V_PU >m(mils).v VIO =.0(0mils) VSUS_ = 0.(0mils) VRT= m(mils) VLK PSUSYP 0.U/0V_X VLVS= m(mils) VLN = 0.(0mils) R 0.U/0V_X V_ = 0.(0mils) VVRM= m(mils) *short_ VPNN= m(mils) m(mils) VME_= m(mils) R *0_ 0U/.V_X 0.U/0V_X T.S_VMI_VRM R0 T U M M P P R *.K/F_ 0.U/0V_X *short_ R 0.uh 0M 0U/.V_X 0.U/0V_X 0.0U/V_X R U/.V_X *short_ *short_ M K K0 K V_NVRM_VQ R *short_ K K 0.U/0V_X M M M *short_.0v_vepw VME =.(00mils) VMI= m(mils) L R R 0U/.V_X 0U/.V_X U/.V_X VRTEXT 0.U/0V_X V.LN_INT_VSUS 0.U/0V_X V_S_VPUS R0 0 0.U/0V_X.0V_VUSORE VREF_SUS R 00/F_ V_S H0H-0PT_00M V_S U/.V_X 0uh 00MV.LN_V PL U/.V_X VPLL[] *0U/.V_P_Eb VPLL[] VREF R 00/F_ V R *short_ VREF K H0H-0PT_00M V V.LN_V PL VPLL[] U/.V_X VPLL[] PI/GPIO/LP U/.V_X R *short_.0v_ssv H VIO[] J V_VPPI V 0 U/.V_X V_[] J R *short_ VIO[] H U/.V_X VIO[] V_[] L F VIO[] V_[0] M H 0.U/0V_X U/.V_X VIO[] V_[] N F 0.U/0V_X VIO[] V_[] P V_[] U 0.U/0V_X VSST V_[] V PSST R *short_ V_S_VPSUS 0.U/0V_X R TP *short_ U/.V_X U/.V_X *short_ V_VPORE 0.U/0V_X R *short_ VTT_VPPU.U/.V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X P UJ P VLK[] Y0 PSUSYP.0V_VUX F VLN[] F F F F V V V Y Y Y V U VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[] VME[0] VME[] VME[] POWER lock and Miscellaneous Y PSUS PI/GPIO/LP P VSUS_[] U VSUS_[0] U0 VSUS_[] U VSUS_[] VLK[] VLN[] VME[] PRT VVRM[] V V_[] V V_[] Y V_[] T V_PU_IO[] U V_PU_IO[] VRT PU RT Ibex-M 0 OF 0VIO[] V VIO[] V VIO[] Y VIO[] Y US VSUS_[] V VSUS_[] U VSUS_[] U VSUS_[] U VSUS_[] P VSUS_[] P VSUS_[] N VSUS_[] N VSUS_[] M VSUS_[0] M VSUS_[] L VSUS_[] L VSUS_[] J VSUS_[] J VSUS_[] H VSUS_[] H VSUS_[] G VSUS_[] G VSUS_[] F VSUS_[0] F VSUS_[] E VSUS_[] E VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] VSUS_[] ST VIO[] VREF_SUS VVRM[] U V F VSTPLL[] K VSTPLL[] K T0.0V_VUSORE R 0 U/.V_X 0 0.U/0V_X V.LN_VPLL *0.0U/0V_X VREF_SUS< m VREF< m R0 TP *short_.v V_ST R *short_ VIO[] H.0V VIO[0] H U/.V_X VIO[] 0 VIO[] F VIO[] VIO[] F0 VIO[] F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[0] *short_ *short_.0v V_S VIO =.0(0mils) VME =.(00mils) V_S.V_S VSUSH= m(mils) R0 R *short_ V._._H_IO *0_ U/.V_X L0 VSUSH H IbexPeak-M_Rev_0 VME[] VME[] VME[] VME[] Y Y.0V_VEPW Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (POWER) ate: Tuesday, March 0, 00 Sheet of

12 M 0 M M M M M M 0 M M M M M M M M M M M0 M M M M M M M M M M M M M M M QSP0 M QSN0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q IMM0_S0 IMM0_S SMR_VREF_Q0 SMR_VREF_IMM PM_EXTTS#0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP M QSP M QSP M QSP M QSP M QSP SMR_VREF_Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# [] M WE# [] M QSP[:0] [] M QSN[:0] [] M M[:0] [] M OT0 [] M OT [] M Q[:0] [] GLK_SM [,] GT_SM [,] R_VREF_Q0 [] MINON_ON_G [,,] R_RMRST# [,] PM_EXTTS#0 [] SMR_VREF_IMM [].VSUS V SMR_VTERM SMR_VTERM.VSUS SMR_VREF_Q0 V.VSUS SMR_VTERM SMR_VREF_IMM.VSUS.VSUS.VSUS SMR_VREF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Wednesday, March 0, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Wednesday, March 0, 00 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Wednesday, March 0, 00 TE SO-IMM SP ddress is 0X0 SO-IMM TS ddress is 0X0 Place these aps near So-imm0. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% for S power reduction R0 *0_ R0 *0_ R 0K/F_ R 0K/F_ R *short_ R *short_.u/.v_x.u/.v_x.u/.v_x.u/.v_x Q N00_00M Q N00_00M R0 _ R0 _.U/.V_X.U/.V_X U/.V_X U/.V_X R 0K/F_ R 0K/F_.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X 0 *0.0U/0V_X 0 *0.0U/0V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT U/.V_X U/.V_X R K/F_ R K/F_ U/.V_X U/.V_X R *0K/F_ R *0K/F_ R *K/F_ R *K/F_ *0U/.V_P_Ea *0U/.V_P_Ea 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X R K/F_ R K/F_ 0 U/.V_X 0 U/.V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0P/0V_X 0P/0V_X *0.0U/0V_X *0.0U/0V_X 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q.U/.V_X.U/.V_X *0.0U/0V_X *0.0U/0V_X *0.U/0V_X *0.U/0V_X.U/.V_X.U/.V_X 0.U/.V_X 0.U/.V_X R 00K/F_ R 00K/F_.U/.V_X.U/.V_X 0 *0.0U/0V_X 0 *0.0U/0V_X *0.0U/0V_X *0.0U/0V_X R *0K/F_ R *0K/F_

13 [] M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# [] M WE# V [,] GLK_SM [,] GT_SM [] M OT0 [] M OT [] M M[:0] SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X [] M QSP[:0] [] M QSN[:0] R0 R M 0 M M M M M M M M M M 0 M M M M M K/F_ IMM_S0 0K/F_ IMM_S M M0 M M M M M M M M M M M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM 0 0/P /# 0 S0# S# K0 K0# K K# KE0 KE S# RS# WE# S0 S SL S OT0 OT M0 M M M M M M M QS0 QS QS QS QS QS QS QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q0 M Q M Q M Q M Q M Q M Q M Q[:0] [] [] R_VREF_Q [] PM_EXTTS# [,] R_RMRST# R *0_.VSUS V SMR_VREF_Q [] SMR_VREF_IMM R 00K/F_ JIM V V V V V V V V V 00 V0 0 V 0 V V V V V V V VSP N N NTEST EVENT# 0 RESET# VREF_Q VREF_ P00 R SRM SO-IMM (0P) VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS RSK-00-TP VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VTT VTT SMR_VTERM Place these aps near So-imm. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% RSK-00-TP.VSUS SMR_VREF_IMM SMR_VTERM.U/.V_X 0.U/0V_X U/.V_X.U/.V_X.U/.V_X.U/.V_X U/.V_X 0 *0.0U/0V_X U/.V_X.VSUS.U/.V_X U/.V_X 0.U/.V_X.U/.V_X 0.U/0V_X SMR_VREF_Q 0.U/0V_X.U/.V_X.U/.V_X R K/F_ SMR_VREF_Q.VSUS 0.U/0V_X 0.U/0V_X V R K/F_ 0.U/0V_X *0.0U/0V_X *0U/.V_P_Ea 0.U/0V_X.U/.V_X 0.U/0V_X *0.0U/0V_X *0.0U/0V_X 0 *0.U/0V_X *0.0U/0V_X Quanta omputer Inc. PROJET : TE Size ocument Number Rev R IMM- ate: Wednesday, March 0, 00 Sheet of

14 HMI onn HMI Level Shift UM only [HM] V U TMS_LK TMS_LK# INT_HMI_SL INT_HMI_S V V R IHM@.K/F_ R *IHM@.K/F_ R IHM@.K_ R *IHM@.K_ SR0 R0 IHM@.K_ R IHM@0_ R0 *IHM@0_ R *IHM@.K_ SR R IHM@0K_ R IHM@0_ R *IHM@.K_ V R IHM@.K_ HMI_LF_HPOUT _EN OE# OE# Q IHM@N00_00M R IHM@0K_ R *IHM@0K_ *IHM@0_ V [] TMS_T [] TMS_T# [] TMS_T [] TMS_T# [] TMS_T0 [] TMS_T0# [] TMS_LK [] TMS_LK# [] INT_HMI_SL [] INT_HMI_S R0 TMS_T TMS_T# TMS_T TMS_T# TMS_T0 TMS_T0# TMS_LK TMS_LK# INT_HMI_SL INT_HMI_S HMI_LF_HPOUT OE# _EN O_ SR0 SR O_ EQ_0 EQ_ OUT_ OUT_- 0 OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- IN_ IN_- IN_ IN_- IN_ IN_- IN_ IN_- SL S HP OE# _EN 0 N(O_) SR0 SR N(O_) N(EQ_0) N(EQ_) IHM@PIVPLSRZE SL_SINK S_SINK HP_SINK 0 V[] V[] V[] V[] V[] V[] V[] 0 V[] [] [] [] [] [] [] [] [] [] [0] HMITXP HMITXN HMITXP HMITXN HMITX0P HMITX0N HMILK HMILK- HMI_LK HM_T HMI_ON_HP V 0.(0mils) Slew Rate ontrol Function SR SR0 Rise/Fall Time 0ps ps 0ps 0ps Reserve R R R0 R0 *IHM@0_ *IHM@0_ *IHM@0_ *IHM@0_ O_ O_ EQ_0 EQ_ [] Port-_HP Port-_HP Q IHM@N00_00M IHM@0_ R0 IHM@00K_ R HMI_LF_HPOUT R IHM@00K_ IHM@0.U/0V_X 0 IHM@0.0U/V_X V IHM@0.U/0V_X IHM@0.0U/V_X For EMI close to connector HMITXN R *HM@00_ HMITXP HMITXN R *HM@00_ HMITXP HMITX0N R *HM@00_ HMITX0P HMILK- R *HM@00_ HMILK HMI_LK HM_T *HM@P/0V_ *HM@P/0V_ V R R HMITXP HMITXN HMITXP HMITXN HMITX0P HMITX0N HMILK_R HMILK-_R HM@.K_ HMI_LK HM@.K_ HM_T V HMI_ON_HP N SHELL 0 Shield - Shield Shield 0-0 K K Shield K- E Remote N LK T V HP ET SHELL lose to HMI ONN HMITXP HMITXN HMITXP HMITXN HMILK HMILK- HMITX0P HMITX0N RP RP RP RP HMITXP HMITXN *LPSN00HLL(0,0.) HMITXP HMITXN *LPSN00HLL(0,0.) HMILK_R HMILK-_R HM@LPSN00HLL(0,0.) HMITX0P HMITX0N *LPSN00HLL(0,0.) HM@-0-L V 0mils HM@RSX0M-0_ 0 *HM@0U/.V_X F HM@FUSEV_POLY--V HMI_LK HM_T V HMI_ON_HP ES 0 0 _/ *HM@Rlamp0P HM@0.U/0V_X HMI_LK HM_T V HMI_ON_HP Size ocument Number Rev HMI ONN Quanta omputer Inc. PROJET : TE ate: Wednesday, March 0, 00 Sheet of

15 [] L POWER SWITH [LS] HLL SENSOR&K LIGHT SWITH [HSR] V VPU R 00K_ V USP0_L R *short_ USP0-_L R *short_ F *SM0P00TF *SSMLPT_ R *short POWER 0.(0mils) 0U/.V_X Q *000P/0V_X *O_ V *0.U/0V_X USP0 [] USP0- [] R0 *.K POWERON [] Q *TEU--F_0M [] LVS_IGON 0 00P/0V_X R 00K_ VPU R 00K_ Q PTTT_00M V R 0K_ Q N00_00M LON# LONG 0.0U/V_X V Q0 ME0_ LV R _ LISHG.(mils) L 0_ Q N00_00M 0 0.U/0V_X LV 0.0U/V_X 0U/.V_X R K_ 0.U/0V_X ISPON [] ISPON Q RSX0M-0_ RSX0M-0_ E_FPK# [] TEU--F_0M LI# MR PT- Q *N00_00M LI# [] V R *0K_ Q *N00_00M R0 00K_ LVS_RIGHT [] L Panel Module [LS] VIN V L_EILK 0. (0mils) R 0_ R R FOR EMI L_EIT L_K_POWER 0U/V_0X.K_.K_ V 000P/0V_X L_EILK L_EIT 0. (0mils) LV 0.U/V_X 0.U/V_X [] [] MI_LK MI_IN [] [] [] [] [] [] [] [] L_EILK L_EIT L L LV V LV L_EILK L_EIT LVS_VJ ISPON L_K_POWER USP0_L USP0-_L _POWER LMPGSN(0,000M) LMPGSN(0,000M) P/0V_N P/0V_N N RT [RT] [] RT_RE [] RT_GRE [] RT_LU US for RT OR [US].V I(max):0. Power:0.W VPU 0 mils LM0SN_00M L RE_L LM0SN_00M L GREEN_L LM0SN_00M L ULE_L P/0V_N.P/0V_N.P/0V_N.P/0V_N.P/0V_N.P/0V_N 0 mils *0.U/0V_X U/0V_X U GPU IN OUT IN OUT OUT [] US_EN# EN# R - O# V V VPU VPU U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0 mils V [] RT_LK [] RT_T V [] RT_VSYN [] RT_HSYN [] RT_SENSE# USPWR L_TXLOUT0- L_TXLOUT0 L_TXLLKOUT- L_TXLLKOUT L_TXLOUT- L_TXLOUT L_TXLOUT- L_TXLOUT L_TXLOUT0- L_TXLOUT0 [] L_TXLLKOUT- [] L_TXLLKOUT L_TXLOUT- L_TXLOUT L_TXLOUT- L_TXLOUT [] USP 0 [] USP- *0K_ V_S 0U/.V_X RE_L GREEN_L ULE_L N 0 0 [] LVS_PWM R 0_ p-l *P/0V_N *P/0V_N 0 *0.U/V_X *0.U/V_X [] ONTRST R *0_ LVS_VJ 0.U/0V_X [,] USO# Quanta omputer Inc. PROJET : TE Size ocument Number Rev L/LE Panel/ ate: Tuesday, March 0, 00 Sheet of

16 MINI ard Slot# (WiFi) [WLN] V_S V WIMX_P L Q PY00T-0Y-N_ *O_ Intel module use S power for.v Other module keep V for.v V_S R *.K_ Q *TEU--F_0M PLTRST# WMX_P [] [] R0 PIE_LK_RQ# 00K_ [] [] [] [] [] [,] [] PLK_EUG L_RST# L_T L_LK WIMX_P Q T_EN# SERIRQ LRQ# R 0_ R R R R R R R *N00_00M Q T *0_ [] [] *0_ *0_ *0_ [] [] [] [] SERIRQ_debug LRQ# debug PLTRST#_debug PLK debug *0_ L_RST#_WLN *0_ PLTRST#_PIE *0_ L_LK_WLN N00_00M PIE_TXP PIE_TXN PIE_RXP PIE_RXN LK_PIE_MINI LK_PIE_MINI# WLN_WKE# 0.(0mils) N N -Link_RST -Link_T -Link_LK N N PETp0 PETn0 PERp0 PERn0 N N REFLK REFLK- LKREQ# T_HLK T_T WKE# 000-.V 0.V LE_WPN# LE_WLN# N N 0 US_ US_- SM_T SM_LK 0.V.Vaux PERST# W_ISLE# 0 N N N N 0 N.V.V.V WIMX_P.(0mils) WL_SMT WL_SMLK PLTRST# RF_EN LFRME#_PIE L_PIE L_PIE L_PIE L0_PIE V_S 0.(0mils) USP [] USP- [] RF_EN [] R *0_ R *0_ LFRME# [,] R *0_ L [,] R *0_ L [,] R *0_ L [,] L0 [,] V_S 0.U/0V_X [,,0] ST 0.0U/V_X 0 0.U/0V_X WIMX_P WIMX_P.V 0U/.V_X Q *N00_00M R 0_ RP *.KX WL_SMT WIMX_P WIMX_P R R *0K_ *0K_ [,,0] SLK WL_SMLK 0.U/0V_X 0 0.U/0V_X 0.U/0V_X 0 0U/.V_X [,0] PIE_WKE# Q *N00_00M Q R 0_ *N00_00M V_S R *0K_ MINI ard Slot# G [MG].V_G V_G SIM R V_G.V_G.(0mils) 0 G@0.0U/V_X G@0.U/0V_X G@0.U/0V_X G@0U/.V_X V_S V_G V_S R Q G@O_ G@.K_ 0 *G@0.0U/V_X *G@0.U/0V_X *G@0U/.V_X [] PIE_TXP [] PIE_TXN [] PIE_RXP [] PIE_RXN.V.V_G 0.(0mils) R *G@0_ [] LK_PIE_G [] LK_PIE_G# [] PIE_LK_REQ# PIE_WKE# G_WKE# N N -Link_RST -Link_T -Link_LK.V.V PEE# PETp0 PETn0 PERp0 RERn0 MM_T MM_M REFLK REFLK- LKREQ# T_HLK T_T WKE#.V 0.V LE_WPN# LE_WLN# LE_WWN# PUS# 0 US_ US_- SM_T SM_LK 0.V.Vaux RESET# W_ISLE# 0 UIM_VPP UIM_RST UIM_LK UIM_T 0 UIM_PWR.V.V PLTRST# G_EN UIM_VPP UIM_RST UIM_LK UIM_T UIM_PWR PUS# [0] USP0 [] USP0- [] PLTRST# [,,0,,] G_EN [] 0 *G@00P/0V_N JSIM UIM_LK UIM_T UIM_RST UIM_VPP UIM_PWR 0 G@-0N G@0.U/0V_X USP [] USP- [] Q *G@N00_00M 000- V_G R *G@0K_ Q G_P [] G@TEU--F_0M Quanta omputer Inc. PROJET : TE Size ocument Number Rev MINI R(WLN/G/SIM ard) Friday, March, 00 ate: Sheet of

17 E-ST [ES] ST H Re-driver I EST_V EST_V V.V R R *0_ *0_ EST_V 0.(0mils) *0.0U/V_X *0.U/V_Y [] ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP Place close 0 0 EST_V [0] EST_N# *0.0U/V_X *0.0U/V_X *0.0U/V_X *0.0U/V_X R R ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ *0_ *0_ EN Mode V 0 V 0 V _P V U O I I- O- O O- I- I _EM _EM *PIEQXSTZE ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ R R R R *00_ *00_ EST_V EST_V 0.0U/V_X 0.0U/V_X 0.0U/V_X 0.0U/V_X Place close ST_TXP ST_TXN ST_RXN ST_RXP R0 *0_ *0K_ *0K_ ST_TXP ST_TXN ST_RXP ST_RXN R 0_ R 0_ R 0_ R 0_ ST_TXP_ ST_TXN_ ST_RXP_ ST_RXN_ EST ONN USPWR Shield V - Shield N ST_RXP ST_RXN ST_TXN ST_TXP ST_RXP ST_RXN ST_TXP ST_TXN R_USP- R_USP *00U/.V_P_Eb R_USP- R_USP 0 *EG00V0H *EG00V0H *EG00V0H *EG00V0H *EG00V0H *EG00V0H [] USP [] USP- USP USP- R_USP R_USP- Shield Shield Q-R0-H USPWR *VPORT 00 0K-V0 US M SIE RP LPSN00HLL(0,0.) [] USP [] USP- USP_ USP-_ VPU.V I(max):0. Power:0.W 0 mils [] US_EN#0 *0.U/0V_X 0 mils U/0V_X U GPU IN OUT IN OUT OUT EN# - O# R *0K_ 0 mils V_S USPWR 0U/.V_X RP LPSN00HLL(0,0.) 0 mils USPWR USP-_ USP_ *VPORT 00 0K-V0 *00U/.V_P_Eb 00MR00SZL N USP-_ *EG00V0H USP_ *EG00V0H [,] USO#_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev TP/SW/EST/USudio/LE ate: Wednesday, March 0, 00 Sheet of

18 ST O [O] N RXP RXN TXN TXP ST_RXN_ ST_RXP_ 0.0U/V_X 0.0U/V_X ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP [] V R 0_0 Q *O_ 0.(0mils) V_O V P V V 0 RSV SLS-EG R K_ V_O 00 *0.U/0V_X *0.U/0V_X.(00mils) 0 0.U/0V_X 0.U/0V_X 0U/.V_X *00U/.V_P_Eb R *.K_ O_EN [] Q *TEU--F_0M ST H [H] N RXP RXN TXN TXP ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 [] ST H Re-driver I ST_TXP0 ST_TXP0 V.V R 0_ R *0_ H_V H_V V 0 V 0 V V 0.(0mils) U 0.0U/V_X ST_TXP0_ ST_TXP0_ 0.0U/V_X I O H_V 0 0.0U/V_X 0 0.U/V_Y ST_TXP0.V.V.V 0 V V V RSV V 0 V V ST-HL0 0.(0mils) V_H 0.U/0V_X 0.U/0V_X 0U/.V_X R *short_ *00U/.V_P_Eb [] [] [] ST_TXN0 ST_RXN0 ST_RXP0 V ST_TXN0 ST_RXN0 ST_RXP0 0.0U/V_X 0.0U/V_X 0.0U/V_X Place close H_V ST_TXN0_ ST_RXN0_ ST_RXP0_ R 0_ I- O- O EN Mode _EM PIEQXSTZE EST Re-driver ypass _P I- O- I _EM ST_TXN0_ ST_RXN0_ ST_RXP0_ R 0K_ R R R0 0K_ *00_ *00_ H_V H_V Place close ST_TXN0 ST_RXN0 ST_RXP0 Quanta omputer Inc. Size ocument Number Rev H/O/M 0.0U/V_X 0.0U/V_X 0.0U/V_X PROJET : TE Wednesday, March 0, 00 ate: Sheet of