te4_0120_uma_v3_ramp_bom

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1 P STK UP LYER : TOP LYER : LYER : IN TE lock iagram LYER : V LYER : IN LYER : IN LYER : LYER : OT ST - H P RIII-SOIMM RIII-SOIMM P, Re-river P ual hannel R III 00/0/ MHZ R SYSTEM MEMORY rrandale (UMVG) rpg P,,, FI MI PI-E Graphics Interfaces INT_LVS INT_RT INT_HMI daughter board P US-0 L/ on. P RT on. HMI on. P ST - O P ST 0 ST ST FI MI MI(x) PI-E PI-Express US on.(right) ardreader P ardreader on. IN P daughter board P SIM R. P US on.(left) P US on.(left) P US- US- US- US- US- US.0 (Port0~) TTERY P zalia US RT IH Ibex Peak-M PH P, 0,,, LP LP NVRM PIE- PIE- PIE- US-0 US- G WLN P P Giga/0/00 Lan P K0 POWER SYSTEM ISL PMTR RT0L G0RU RT ISLHRTZ-T G V_ORE.V.VSUS VTT.0V P P P P P P0 P P.V M on. udio odec Port- P0 MI JK HP SPK on. P0 P0 P0 P0 Port- FN P K/ on. P HLL Sensor P E SPI Flash P Touch Pad / on. P P Power / on. P.V_S VPU V_S V VPU V_S V SMR_VTERM SMR_VREF Quanta omputer Inc. PROJET : TE Size ocument Number Rev lock iagram Friday, November, 00 ate: Sheet of

2 PGE Table of ontents ESRIPTION POWER PLNE VIN VOLTGE 0V~V ONTROL SIGNL Power States TIVE IN S0~S 0 Schematic lock iagram Front Page lock Gen - Processor S Power Reduction - PH RT - RIII SO-IMM HMI comm part L Panel RT & RT US SWITH HLL SENSOR&K LIGHT SWITH MINI ard (Wi-Fi & WIMX) MINI ard nd MINI ard nd US.0 ST O Main ST H & nd ST H 0 odec (X0) theros LN IN ard reader E NPEL INT Keyoard & K/ LE Power TP board Power SW HOLE LE / EMI harger (ISL) System V/V (PMTR) R.V(RT0L)/.0VSUS VTT/.0V (G0RU) 0 VXG_ORE RT FOR UM V_ORE(ISLHRTZ-T).V (G)/ischarge VRT V V_S V_HP VPU V V_S VPU WIMX_P.V.V.V_SUS V_ORE VTT.0V VXG PLNE udio_ Shield_.0V~.V.V.V.V.V V V V.V.V.V.V.0V.0V PGE 0 0 LL MIN_ON S_ON MIN_ON / Insert enable MIN_ON S_ON / Insert enable WMX_P for WLN MIN_ON MIN_ON SUSON VRON MIN_ON MIN_ON MPWROK S0~S S0 S0~S S0 S0 S0 S0~S S0~S S0 S0 S0~S S0 S0 S0 S0 ISL0_ 0 Quanta omputer Inc. PROJET : TE Size ocument Number Rev POWER STGE N OI-FUNTION Friday, November, 00 ate: Sheet of

3 LOK Gen V L [LK] PY00T-0Y-N_ 0m(0mils) Pin// Sligo =>.V (L000000) Sligo0 =>.V (LSP0000) 0.0V VIO_LK 0m(0mils) V_K0_V L PY00T-0Y-N_.V L {0} LK_PH_M 0.U/0V_X *0.U/0V_X 0.U/0V_X R _ *P/0V_ 0m(0mils) *0.U/0V_X *0.U/0V_X.V_K0_V R *0@0_ XTL_OUT XTL_IN PU_SEL GT_SM GLK_SM U V_ V_REF V_OT_. V_SR_. V_PU_. XTL_OUT XTL_IN 0 REF_0/PU_SEL S SL VSS_OT VSS_ VSS_ST VSS_SR VSS_PU VSS_REF SLGLVVTR V_SR_I/O V_PU_I/O OT_ OT_# M M_SS SR_/ST 0 SR_#/ST# SR_ SR_# *PU_STOP# PU_ 0 PU_# PU_0 PU_0# KPWRG/P# REFLK_R REFLK#_R LK_VG_M_R LK_VG_M#_R REFSSLK_R REFSSLK#_R PIE_GPLL_R PIE_GPLL#_R IS_PU_STOP# *0U/.V_X LK_UF_LK_P_R LK_UF_LK_N_R LK_UF_LK0_P_R LK_UF_LK0_N_R VR_PWRG_LKEN R TP TP0 0U/.V_X RP RP RP 0K_ RP 0.U/0V_X R R0 R V *EV@_ EV@_ *_ *short_pr *short_pr *short_pr 0 0.U/0V_X *short_pr LK_UF_REFLKP {0} LK_UF_REFLKN {0} TP PH_LK_M LK_UF_REFSSLKP {0} LK_UF_REFSSLKN {0} LK_UF_PIE_GPLLP {0} LK_UF_PIE_GPLLN {0} LK_UF_LKP {0} LK_UF_LKN {0} LK RYSTL LK PU_SEL LK I LK POWERGOO V V R R 0K_ VPU R 0K_ VR_PWRG_LKEN XTL_IN Y XTL_OUT *0K_ PU_SEL {0,} ST N00_00M Q GT_SM GT_SM {,,} {} VR_PWRG_K0# Q N00_00M R 00K/F_.MHZ_0 0 P/0V_N P/0V_N R 0K_ R V 0K_ PU_SEL PU =MHz (default) 0 PU=00MHz {0,} SLK N00_00M Q GLK_SM GLK_SM {,,} Size ocument Number Rev LOK GENERTOR Quanta omputer Inc. PROJET : TE ate: Monday, January, 0 Sheet of

4 {} MI_TXN0 {} MI_TXN {} MI_TXN {} MI_TXN {} MI_TXP0 {} MI_TXP {} MI_TXP {} MI_TXP {} MI_RXN0 {} MI_RXN {} MI_RXN {} MI_RXN {} MI_RXP0 {} MI_RXP {} MI_RXP {} MI_RXP.GT/s data rate {} FI_TXN[:0] FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN {} FI_TXP[:0] FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP {} FI_FSYN0 {} FI_FSYN {} FI_INT {} FI_LSYN0 {} FI_LSYN U MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] G MI_TX#[] F MI_TX#[] H MI_TX#[] MI_TX[0] F MI_TX[] E MI_TX[] G MI_TX[] E FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] G FI_TX#[] E FI_TX#[] F FI_TX#[] G FI_TX#[] FI_TX[0] FI_TX[] 0 FI_TX[] FI_TX[] G FI_TX[] E0 FI_TX[] F0 FI_TX[] G FI_TX[] F FI_FSYN[0] E FI_FSYN[] FI_INT F FI_LSYN[0] FI_LSYN[] -ZIF-0-K0 MI Intel(R) FI PI EXPRESS -- GRPHIS PEG_IOMPI PEG_IOMPO PEG_ROMPO PEG_RIS PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[0] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX#[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[0] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_RX[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] K J J G G F F E 0 J H H F G E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K G0 G F E PEG_OMP PEG_RIS R0 R./F_ 0/F_ del in UM {,,,} {,} PLTRST# {} {} H_PEI PM_SYN {} H_PWRGOO PM_RM_PWRG R R R R R R TP TP TP0 TP TP TP TP TP TP TP.K/F_ 0/F_ 0/F_ 0/F_./F_./F_ H_TERR# XP_TI_R XP_TO_M XP_TI_M XP_TO_R H_OMP H_OMP H_OMP H_OMP0 H_PROHOT#_ PU_PM_THRMTRIP# H_PURST#_R PM_RM_PWRG H_VTTPWRG PU_PLTRST# JTG MPPING XP_OS0 J XP_OS K XP_OS K XP_OS J XP_OS J XP_OS H XP_OS K XP_OS H Ra Rb Rc R0 *short_ Rd Re T T G T H K T N K P L N N K M M L R R0 R0 R00 U OMP OMP OMP OMP0 SKTO# TERR# PEI PROHOT# THERMTRIP# RESET_OS# PM_SYN VPWRGOO_ VPWRGOO_0 SM_RMPWROK TPPWRGOO VTTPWRGOO RSTIN# *short_ *0_ *0_ *short_ MIS THERML PWR MNGEMENT PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] -ZIF-0-K0 LOKS R MIS JTG & PM XP_TI XP_TO XP_TRST# R _ LK LK# LK_ITP LK_ITP# PEG_LK PEG_LK# PLL_REF_SSLK PLL_REF_SSLK# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PM_EXT_TS#[0] PM_EXT_TS#[] PRY# PREQ# TK TMS TRST# TI TO TI_M TO_M R# R0 T0 E F L M N LK_REFSSLKP_R LK_REFSSLKN_R R_RMRST#_ SM_ROMP_0 SM_ROMP_ SM_ROMP_ N PM_EXT_TS#0 P PM_EXT_TS# T P N P T T R R P N XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO_R XP_TI_M XP_TO_M Processor hot throttle {} R R R R R R R R R R0 H_PROHOT# EV@0_ EV@0_ 00/F_./F_ 0/F_ 0K_ *short_ *short_ 0K_ *IV@0X Ra R Rb *short_ VTT VTT VTT LK_PU_LKP {} LK_PU_LKN {} TP TP LK_PIE_GPLLP {0} LK_PIE_GPLLN {0} TP0 TP TP TP TP LK_REFSSLKP {0} LK_REFSSLKN {0} R_RMRST#_ {} PM_EXTTS#0 {} PM_EXTTS# {} SYS_RESET# {} R0 _ H_PROHOT#_ If Ra no stuff must change Rb to 0 ohm 0 For EP Scan hain (efault) PU Only STUFF -> Ra, Rc, Re NO STUFF -> Rb, Rd STUFF -> Ra, Rb NO STUFF -> Rc, Rd, Re Thermal Trip VTT GMH Only STUFF -> Rd, Re NO STUFF -> Ra, Rb, Rc VTT Power Good FI isable (iscrete only) {,} ELY_VR_PWRGOO Q N00_00M {} HWPG R *short_ R *short_ U V ost own Study HWPG_ R0 K/F_ H_VTTPWRG TSH0FU(F) R0 K/F_ H_TERR# R0 H_PURST#_R R0 XP_TMS R0 XP_TI_R R0 XP_PREQ# R0 XP_TLK R VTT./F_ *_ *_ *_ *_ *_ R R R0 R R EV@K_ FI_INT EV@K_ FI_FSYN0 EV@K_ FI_FSYN EV@K_ FI_LSYN0 EV@K_ FI_LSYN PU_PM_THRMTRIP# VTT R *./F_ R K_ Q0 MMT0--F_00M SYS_SHN# R 00K_ SYS_SHN# {} {,} MPWROK R *0_ R *0_ R *short_ PM_THRMTRIP# PM_THRMTRIP# {} Local Temperature PU FN TRL VL VPU R0 R 0_ *0_ #Shut down on degree# U VPU_HW_S R V SET THM@K/F_ 0.U/0V_X R 0_ THER_SH# HYST OT# G0TU VL R *0_ VPU VPU V V R R m(0mils) *0K_ *0_.U/.V_X Q *MMT0--F_00M R *short_ TEMP_LERT# PUFN#_ON_R_ {,} TEMP_LERT# Q *N00_00M {} VFN SYS_SHN# {} U VIN VO /FON VSET GPU FNPWR =.*VSET 0mils TH_FN_POWER 0 0U/.V_X {} FNSIG 0.0U/V_X V R0 0K_ FNSIG *0.0U/V_X N 0-000L Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER /(HOST&PEX) Monday, January, 0 ate: Sheet of

5 UURNLE/LRKSFIEL PROESSOR (R) 0 {} M Q[:0] U M Q0 0 M Q S_Q[0] 0 M Q S_Q[] M Q S_Q[] M Q S_Q[] 0 M Q S_Q[] 0 M Q S_Q[] E0 M Q S_Q[] M Q S_Q[] M Q S_Q[] F0 M Q0 S_Q[] E M Q S_Q[0] F M Q S_Q[] E M Q S_Q[] M Q S_Q[] E M Q S_Q[] M Q S_Q[] H0 M Q S_Q[] G M Q S_Q[] K M Q S_Q[] J M Q0 S_Q[] G M Q S_Q[0] G0 M Q S_Q[] J M Q S_Q[] J0 M Q S_Q[] L M Q S_Q[] M M Q S_Q[] M M Q S_Q[] L M Q S_Q[] L M Q S_Q[] K M Q0 S_Q[] N M Q S_Q[0] P M Q S_Q[] H M Q S_Q[] F M Q S_Q[] K M Q S_Q[] K M Q S_Q[] F M Q S_Q[] G M Q S_Q[] J M Q S_Q[] J M Q0 S_Q[] J0 M Q S_Q[0] J M Q S_Q[] L0 M Q S_Q[] K M Q S_Q[] K M Q S_Q[] L M Q S_Q[] K M Q S_Q[] L M Q S_Q[] N M Q S_Q[] M0 M Q0 S_Q[] R M Q S_Q[0] L M Q S_Q[] M M Q S_Q[] N M Q S_Q[] T M Q S_Q[] P M Q S_Q[] M M Q S_Q[] N M Q S_Q[] M M Q S_Q[] T M Q0 S_Q[] T M Q S_Q[0] L M Q S_Q[] R M Q S_Q[] P S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] P Y Y P E E F M M0 M M H M M M M M G M M M M M N0 M M N M M M QSN0 F M QSN J M QSN N M QSN H M QSN K M QSN P M QSN T M QSN M QSP0 F M QSP H M QSP M M QSP H M QSP K0 M QSP N M QSP R M QSP Y M 0 W M M M V M M V T M M Y M U M M 0 T M U M G M T M V M M LKP0 {} M LKN0 {} M KE0 {} M LKP {} M LKN {} M KE {} M S#0 {} M S# {} M OT0 {} M OT {} M M[:0] {} M QSN[:0] {} M QSP[:0] {} M [:0] {} {} M Q[:0] M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to on So-IMM side for larkfield design only M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U S_Q[0] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] F S_Q[0] F S_Q[] S_Q[] F S_Q[] F S_Q[] G S_Q[] H S_Q[] G S_Q[] J S_Q[] J S_Q[] G S_Q[0] G S_Q[] J S_Q[] J S_Q[] J S_Q[] K S_Q[] L S_Q[] M S_Q[] K S_Q[] K S_Q[] M S_Q[0] N S_Q[] F S_Q[] G S_Q[] J S_Q[] K S_Q[] G S_Q[] G S_Q[] J S_Q[] H S_Q[] K S_Q[0] K S_Q[] M S_Q[] N S_Q[] K S_Q[] K S_Q[] M S_Q[] M S_Q[] P S_Q[] N S_Q[] T S_Q[0] N S_Q[] N S_Q[] N S_Q[] T S_Q[] T S_Q[] N S_Q[] P S_Q[] P S_Q[] T S_Q[] T S_Q[0] P S_Q[] R0 S_Q[] T0 S_Q[] R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] W W M V V M M M0 E M M H M M K M M H M M L M M R M M T M M M QSN0 F M QSN J M QSN L M QSN H M QSN L M QSN R M QSN R M QSN M QSP0 E M QSP H M QSP M M QSP G M QSP L M QSP P M QSP R M QSP U V T V M 0 M M M R M T R M M R M R M R M M 0 P M R M F M P M N M M LKP0 {} M LKN0 {} M KE0 {} M LKP {} M LKN {} M KE {} M S#0 {} M S# {} M OT0 {} M OT {} M M[:0] {} M signals are not present on larkfield processor. ll M signal can be left as N on larkfield and connect directly to on So-IMM side for larkfield design only M QSN[:0] {} M QSP[:0] {} M [:0] {} {} {} {} {} {} {} M S#0 M S# M S# M S# M RS# M WE# S_S[0] S_S[] U S_S[] E S_S# S_RS# E S_WE# -ZIF-0-K0 {} {} {} {} {} {} M S#0 M S# M S# M S# M RS# M WE# S_S[0] W S_S[] R S_S[] S_S# Y S_RS# S_WE# -ZIF-0-K0 Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER /(R) ate: Monday, January, 0 Sheet of

6 VI PSI# VI VI0 VI VI IH_PRSTP# VI VI TP_VSS_SENSE_VTT VTT_SENSE ISENSE VI VI VI IH_PRSTP# VI PSI# VI VI VTT_ VTT_ VI0 GFXVR_EN VSENSE {} VSSSENSE {} PSI# {} IH_PRSTP# {} H_VI0 {} H_VI {} H_VI {} H_VI {} H_VI {} H_VI {} H_VI {} ISENSE {} GFXVR_VI_0 {0} GFXVR_VI_ {0} GFXVR_VI_ {0} GFXVR_VI_ {0} GFXVR_VI_ {0} GFXVR_VI_ {0} GFXVR_VI_ {0} V_XG_SENSE {0} VSS_XG_SENSE {0} GFXVR_IMON {0} GFXVR_PRSLPVR {0} GFXVR_EN {0} VTT VTT VTT.V VXG V_ORE VTT VTT VTT V_ORE.V_PUVQ V_ORE VXG Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : PROESSER /(POWER) Monday, January, 0 TE VTT Rail Values are uburndal VTT=.0V H_VTTVI=Low,.V H_VTTVI=High,.0V HFM_VI : Max.V LFM_VI : Min 0.V (mils) 0 del in VG del in VG 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0 0U/.V_X 0 0U/.V_X R *K_ R *K_ TP TP 0U/.V_X 0U/.V_X R *K_ R *K_ R0 *K_ R0 *K_ 0 0U/.V_X 0 0U/.V_X R *K_ R *K_ 0U/.V_X 0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X *0.0U/0V_X *0.0U/0V_X POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG -ZIF-0-K0 POWER GRPHIS VIs GRPHIS R -.V RILS FI PEG & MI SENSE LINES.V.V UG -ZIF-0-K0 GFX_VI[0] M GFX_VI[] P GFX_VI[] N GFX_VI[] P GFX_VI[] M GFX_VI[] P GFX_VI[] N GFX_VR_EN R GFX_PRSLPVR T GFX_IMON M VXG_SENSE R VSSXG_SENSE T VXG T VXG T VXG T VXG T VXG R VXG R VXG R VXG R VXG P VXG0 P VXG P VXG P VXG N VXG N VXG N VXG N VXG M VXG M VXG M VXG0 M VXG L VXG L VXG L VXG L VXG K VXG K VXG K VXG K VXG J VXG0 J VXG J VXG J VXG H VXG H VXG H VXG H VTT_ J VTT_ J VTT_ H VTT_ K VTT_ J VTT_0 J VTT_ J VTT_ H VTT_ G VTT_ G VTT_ G VTT_ F VTT_ E VTT_ E VQ J VQ F VQ E VQ E VQ VQ VQ VQ Y VQ W VQ0 W VQ U VQ T VQ T VQ P VQ N VQ N VQ L VQ H VTT0_ P0 VTT0_0 N0 VTT0_ L0 VTT0_ K0 VPLL L VPLL L VPLL M VTT_ J VTT_ J0 VTT_ J VTT_ H VTT_ H0 VTT_ H 0 0U/.V_X 0 0U/.V_X *0.0U/0V_X *0.0U/0V_X 0U/.V_X 0U/.V_X *0U/.V_X *0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X R K_ R K_ *IV@0U/V_P_Eb *IV@0U/V_P_Eb 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X TP TP R *K_ R *K_ 0U/.V_X 0U/.V_X R 00/F_ R 00/F_ 0 0U/.V_X 0 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X R K_ R K_ *0U/V_P_Eb *0U/V_P_Eb POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF -ZIF-0-K0 POWER PU ORE SUPPLY.V RIL POWER SENSE LINES PU VIS UF -ZIF-0-K0 ISENSE N VTT_SENSE PSI# N VI[0] K VI[] K VI[] K VI[] L VI[] L VI[] M VI[] M PRO_PRSLPVR M VTT_SELET G V_SENSE J VSS_SENSE_VTT V G V G V G V G V G V G0 V G V G V G V0 G V F V F V F V F V F V F0 V F V F V F V0 F V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V V V V V V 0 V V V V0 V Y V Y V Y V Y V Y V Y0 V Y V Y V Y V0 Y V V V V V V V V V V V V0 V V V V V V V0 V V U V U V U V U V U V U0 V U V U V U V0 U V R V R V R V R V R V R0 V R V R V R V0 R V P V P V P V P V P V P0 V P V P V P V00 P VTT0_ F0 VTT0_ E0 VTT0_ 0 VTT0_ 0 VTT0_ Y0 VTT0_ W0 VTT0_ U0 VTT0_0 T0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ H VTT0_ H0 VTT0_ J VTT0_ J VTT0_ H VTT0_ H VTT0_ G VTT0_0 G VTT0_ G VTT0_ G VTT0_ F VTT0_ F VTT0_ F VTT0_ F VTT0_ E VTT0_ E VTT0_ VTT0_0 VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_ VTT0_0 VTT0_ VTT0_ VSS_SENSE J VTT0_ J VTT0_ J 0U/.V_X 0U/.V_X 0 U/.V_X 0 U/.V_X TP TP R *short_ R *short_ 0U/.V_X 0U/.V_X R *K_ R *K_ R EV@0_ R EV@0_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X IV@0U/.V_X IV@0U/.V_X 0.U/.V_X 0.U/.V_X IV@0U/.V_X IV@0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X U/.V_X U/.V_X R *short_ R *short_ *0U/V_P_Eb *0U/V_P_Eb 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X TP TP 0 IV@0U/.V_X 0 IV@0U/.V_X IV@0U/.V_X IV@0U/.V_X 00 0U/.V_X 00 0U/.V_X 0 0U/.V_X 0 0U/.V_X *0U/V_P_Eb *0U/V_P_Eb 0.U/0V_X 0.U/0V_X IV@0U/.V_X IV@0U/.V_X IV@0U/.V_X IV@0U/.V_X U/.V_X U/.V_X.U/.V_X.U/.V_X IV@0U/.V_X IV@0U/.V_X *IV@0U/V_P_Eb *IV@0U/V_P_Eb R EV@K_ R EV@K_ R K_ R K_ R *K_ R *K_ 0 0U/.V_X 0 0U/.V_X R *K_ R *K_ 0U/.V_X 0U/.V_X R K_ R K_ U/.V_X U/.V_X 0 0U/.V_X 0 0U/.V_X 0U/.V_X 0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X IV@0U/.V_X IV@0U/.V_X 0 0U/.V_X 0 0U/.V_X R0 *K_ R0 *K_ *0U/V_P_Eb *0U/V_P_Eb 0U/.V_X 0U/.V_X R 00/F_ R 00/F_ 0U/.V_X 0U/.V_X *0.0U/0V_X *0.0U/0V_X 0U/.V_X 0U/.V_X U/.V_X U/.V_X R K_ R K_ 0.U/0V_X 0.U/0V_X 00 0U/.V_X 00 0U/.V_X R K_ R K_ 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X *0U/.V_X *0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X 0U/.V_X

7 UURNLE/LRKSFIEL PROESSOR () UH T0 VSS T VSS R VSS R VSS R VSS R VSS R VSS R0 VSS R VSS R VSS0 R VSS R VSS R VSS R VSS P0 VSS P VSS P VSS P0 VSS P VSS P VSS0 P VSS N VSS N VSS N VSS N0 VSS N VSS M VSS M VSS M VSS M0 VSS0 M VSS M VSS M VSS M VSS M VSS M VSS L VSS L VSS L VSS L0 VSS0 L VSS L VSS L VSS L VSS L VSS K VSS K VSS K VSS K0 VSS K VSS0 J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS J VSS J VSS H VSS0 H VSS H VSS H VSS H VSS H0 VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS H VSS H VSS G0 VSS F VSS F VSS F VSS E VSS0 VSS -ZIF-0-K0 VSS E VSS E VSS E VSS E VSS E0 VSS E VSS E VSS E VSS E VSS0 E VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS00 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 0 VSS0 Y VSS0 Y VSS0 Y VSS0 W VSS W VSS W VSS W VSS W VSS W0 VSS W VSS W VSS W VSS W VSS0 W VSS V0 VSS U VSS U VSS U VSS T VSS T VSS T VSS T VSS T VSS0 T0 VSS T VSS T VSS T VSS T VSS T VSS R0 VSS P VSS P VSS P VSS0 N VSS N VSS N VSS N VSS N VSS N0 VSS N VSS N VSS N VSS N VSS0 N VSS M0 VSS L VSS L VSS L VSS L VSS L VSS L VSS K VSS K VSS0 K0 The larkfield processor's PI Express interface may not meet PI Express.0 jitter specifications. Intel recommends placing a.0k /- % pull down resistor to VSS on FG[] pin for both rpg and G components. This pull down resistor should be removed when this issue is fixed. R R R *short_ *short_ *short_ UI K VSS K VSS K VSS K VSS J VSS J0 VSS J VSS J VSS H VSS H VSS0 H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS H VSS0 H VSS G VSS G VSS G0 VSS G VSS G VSS G VSS F0 VSS F VSS F VSS0 F VSS F VSS F VSS E VSS E VSS E VSS E VSS E VSS E VSS E VSS00 E VSS0 E VSS0 E VSS0 E VSS0 VSS0 0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS T VSS_NTF T VSS_NTF R VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS -ZIF-0-K0 NTF FG0 (PI-Epress onfiguration Select) FG (isplay Port Presence) FG (PI-Epress Static Lane Reversal) {} R_VREF_Q0 {} R_VREF_Q FG0 FG FG FG TP_RSV_R TP_RSV_R UURNLE/LRKSFIEL PROESSOR( RESERVE, FG) TP R R *0_ *0_ FG[ :0 ] - PI_Epress onfiguration Select * = x PEG * 0= x PEG 0 isabled; No Physical isplay Port attached to Embedded iplay Port Single PEG Normal Operation UE J S_IMM_VREF H S_IMM_VREF M0 FG[0] M FG[] P FG[] L FG[] L0 FG[] M FG[] N FG[] M FG[] K FG[] K FG[] K FG[0] J FG[] N0 FG[] N FG[] J FG[] J FG[] J0 FG[] K0 FG[] H RSV_TP_ P RSV L RSV L RSV L RSV J RSV G RSV M RSV L RSV G RSV G RSV E RSV E0 RSV RSV RSV 0 RSV 0 RSV U RSV T RSV0 RSV RSV RSV_NTF_ RSV_NTF_ J RSV J RSV RSV_NTF_ RSV_NTF_ RSV_NTF_0 RSV_NTF_ J RSV J RSV H RSV K RSV L RSV R RSV_NTF_ J RSV J RSV P RSV_NTF_0 -ZIF-0-K0 RESERVE Enabled; n external isplay port device is connected to the Embedded isplay port ifurcation enabled Lane Numbers Reversed -> 0, -> RSV_NTF_ T RSV_NTF_ T RSV_NTF_ R RSV L RSV L RSV P0 RSV P RSV L RSV0 T RSV T RSV P RSV R RSV_NTF_ T RSV_NTF_ T RSV_NTF_ P RSV_NTF_ R RSV R RSV_TP_ E RSV_TP_0 F KEY RSV RSV RSV_R R RSV J RSV_R R RSV H RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ RSV_TP_0 RSV_TP_ RSV_TP_ RSV_TP_ R RSV_TP_ G RSV_TP_ E RSV_TP_ V RSV_TP_ V RSV_TP_ N RSV_TP_ RSV_TP_0 RSV_TP_ W RSV_TP_ W RSV_TP_ N RSV_TP_ E RSV_TP_ VSS P *0_ *0_ TP For iscrete only FG0 R FG R FG R FG R *.0K/F_.0K/F_ *.0K/F_ *.0K/F_ 0 Quanta omputer Inc. PROJET : TE Size ocument Number Rev PROESSER / () ate: Monday, January, 0 Sheet of

8 S Power Enable RM Reset.VSUS 0 {} S_.V S_.V PR0 *0/F_ V_S {} R_RMRST#_PH R K_ PR 00K_ PU TSH0FU(F) MINON {,,,}.V_PUVQ_PG R *00K_ 0.U/0V_X Q SS--F_0.M R *0_ R_RMRST# {,} PR PR *0_ S_Reduce {} MINON_ON_G {,} {} R_RMRST#_ R_RMRST#_ PQ N00K_00M *Short_ R0 00K_ VQ Power Good VQ Power Switch VQ ischarge.v_puvq V_S V.VSUS.VSUS.V_PUVQ R.K/F_ R 0K/F_ Q FV0N_00M R 0K/F_ Q N00_00M.V_PUVQ_PG {,,} MIN R *00K_ MIN 0.0U/V_X Q O_. 0.U/0V_X 0.U/0V_X 0.U/0V_X.V_PUVQ 0.U/0V_X {,} MINON_ON_G R 0_ Q N00K_00M 0.U/0V_X.V_PUVQ /maximum Q0 可換 O0,cost down. RM Power Good V_S R V_S PM_RM_PWRG: Never drive hight before R voltage ramp to stable.vsus.v_puvq_pg 0K/F_ U R TSH0FU(F).K/F_ R0 R 0/F_ *short_ PM_RM_PWRG {,} R *.K/F_ PM_RM_PWRG R *K/F_ Quanta omputer Inc. PROJET : TE Size ocument Number Rev S Power Reduction ate: Monday, January, 0 Sheet of

9 INTVRMEN - Integrated SUS.V VRM Enable High - Enable Internal VRs 0 RT_ELL RT_ELL {0} Y.KHZ_0 {,0} {,} PEEP Z_SIN0_UIO {} P/0V_ P/0V_ R R TP TP0 TP PH_GPIO TP SPI_SI_R M_ 0K_ TP R 0M_ RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK Z_SYN Z_RST# Z_SOUT PH_JTG_TK PH_JTG_TMS PH_JTG_TI PH_JTG_TO PH_JTG_RST# SPI_LK_R SPI_S0#_R SPI_S# SPI_SI_R SPI_SO RT_X RT_X IEX PEK-M (H,JTG,ST) 0 P 0 G0 F0 E F H J0 M K K J J V Y Y V U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN Ibex-M OF 0 RT H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN IH H_SIN H_SIN H_SO H_OK_EN# / GPIO (V) H_OK_RST# / GPIO (V_S) JTG_TK JTG_TMS JTG_TI JTG_TO TRST# SPI_LK SPI_S0# SPI_S# SPI_MOSI SPI_MISO IbexPeak-M_Rev_0 JTG SPI LP (V) FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# LRQ0# LRQ# / GPIO SERIRQ ST ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STIOMPO STIOMPI STLE# (V) ST0GP / GPIO (V_S) STGP / GPIO F K K K K H H H H F F F F H H F F F F T Y V ST_OMP ST_LE# L0 {,} L {,} L {,} L {,} LFRME# {,} LRQ# {} V V V.0V SERIRQ {,} ST_RXN0 {} ST_RXP0 {} ST_TXN0 {} ST_TXP0 {} ST_RXN {} ST_RXP {} ST_TXN {} ST_TXP {} ST/ST HM not support R R R TP TP TP TP 0K_ 0K_./F_ R0 0K_ ST_LE# {} del in VG H O {} {} {} {} {} {} {} V del in VG {} {} {} INT_RT_LU INT_RT_GRE INT_RT_RE INT_RT_LK INT_RT_T INT_RT_HSYN INT_RT_VSYN INT_LVS_RIGHT INT_LVS_IGON INT_LVS_PWM {} INT_L_EILK {} INT_L_EIT {} {} {} {} {} {} {} {} R R del in VG TP0 TP INT_L_TXLLKOUT- INT_L_TXLLKOUT INT_L_TXLOUT0- INT_L_TXLOUT- INT_L_TXLOUT- TP0 INT_L_TXLOUT0 INT_L_TXLOUT INT_L_TXLOUT TP0 IV@0K_ IV@0K_ R R R IV@0_ IV@0_ L_TRL_LK L_TRL_T LVS_IG LVS_VG LVS_VREFH LVS_VREFL RT_LU RT_GRE RT_RE RT_HSYN_R RT_VSYN_R K/ IREF IEX PEK-M (LVS,I) T T Y Y V P P T T V V Y V 0 Y V P P Y T U T Y T U0 T V V Y Y U L_KLTEN L_V_EN L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_IG LV_VG LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS-- LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS-- LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T RT_LUE RT_GREEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN RT Ibex-M SVO_TVLKINN OF 0 SVO_TVLKINP SVO igital isplay Interface ISPLY PORT ISPLY PORT ISPLY PORT SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P J G J G F H T T G J U J G 0 0 W Y E V0 E0 0 F H U0 U T J0 G0 J G F H E TP TP del in VG INT_HMI_SL {} INT_HMI_S {} P_UXN R P_UXP R _TMS_T# _TMS_T _TMS_T# _TMS_T _TMS_T0# _TMS_T0 _TMS_LK# _TMS_LK IV@0K_ V IV@0K_ Port-_HP {} del in VG TP0 IbexPeak-M_Rev_0 [RT] RT TTERY VPU (0mils) (0mils) R_VRT R SM0K--F_00M SM0K--F_00M RT_ELL (0mils) 0 U/0V_X P Setting Port Strap LVS L T Port SVO_TRLT How to enable Port? PU to.v with.k/- % PU to.v with.k/- % How to disable Port? N N HMI R0 R R R R IV@0_ IV@.K/F_ IV@0/F_ IV@0/F_ IV@0/F_ LVS_VREFH LVS_VREFL LVS_IG RT_LU RT_GRE RT_RE RT_N0 K_ N -T-0-K0 Port Port ep P_TRLT P_TRLT FG[] PU to.v with.k/- % PU to.v with.k/- % P to directly N N N _TMS_T _TMS_T# _TMS_T _TMS_T# _TMS_T0 _TMS_T0# _TMS_LK _TMS_LK# 0 IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X IHM@0.U/0V_X TP0 TP0 TP00 TP TP TP TP TP TMS_T {} TMS_T# {} TMS_T {} TMS_T# {} TMS_T0 {} TMS_T0# {} TMS_LK {} TMS_LK# {} lzia {0} {0} {0} {0} Z_RST#_UIO Z_SOUT_UIO Z_SYN_UIO IT_LK_UIO.0V R R R R *_ *_ *_ *_ R0 _ PH_JTG_TMS PH_JTG_RST# PH_JTG_TI R _ R0 _ Z_SOUT *0P/0V_ R _ Z_SYN *0P/0V_ R _ Z_ITLK P/0V_N PH_JTG_TO PH_JTG_TK Z_RST# RESET JUMP RT_ELL R RT_ELL R n R delay circuit with a time delay in the range of ms to ms should be provided 0K_ RT_RST# G U/.V_X *SHORT_ P 0K_ SRT_RST# G U/.V_X *SHORT_ P M byte SPI ROM U SPI_SO R *short_ SPI_SO_R SO V SPI_SI_R R *short_ SPI_SI SPI_HOL# SI HOL R SPI_LK_R R *short_ SPI_LK SPI_WP# WP R SK SPI_S0#_R R0 *short_ SPI_S0# E VSS WQVSSIG.K/F_.K/F_ V 0.U/0V_X PH M M M PM HM HM/PM QM/QS Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (ST,H,LP) Monday, January, 0 ate: Sheet of

10 IEX PEK-M () UI Y VSS[] VSS[] H VSS[0] VSS[0] H VSS[] VSS[] J VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] L G VSS[0] VSS[0] L VSS[] VSS[] L VSS[] VSS[] L0 0 VSS[] VSS[] L VSS[] VSS[] M 0 VSS[] VSS[] M VSS[] VSS[] M0 VSS[] VSS[] N VSS[] VSS[] M VSS[] VSS[] M VSS[0] VSS[0] M 0 VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] N VSS[] VSS[] P VSS[] VSS[] 0 VSS[] VSS[] P VSS[] VSS[] P0 VSS[0] VSS[0] P H VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P VSS[] VSS[] P E VSS[] VSS[] R E VSS[] VSS[] R E0 VSS[] VSS[] T E VSS[] VSS[] T E0 VSS[] VSS[] T E VSS[00] VSS[00] T E VSS[0] VSS[0] T E VSS[0] VSS[0] T E VSS[0] VSS[0] U0 E VSS[0] VSS[0] U E0 VSS[0] VSS[0] U E VSS[0] VSS[0] U E VSS[0] VSS[0] P F VSS[0] VSS[0] V F VSS[0] VSS[0] P F VSS[0] VSS[0] V G VSS[] VSS[] V0 G VSS[] VSS[] V G VSS[] VSS[] V0 G0 VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[0] VSS[0] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V H VSS[] VSS[] V VSS[] VSS[] V 0 VSS[] VSS[] V VSS[] VSS[] W E VSS[] VSS[] W E VSS[] VSS[] Y E0 VSS[0] VSS[0] Y E VSS[] VSS[] Y E0 VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y0 E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y E VSS[] VSS[] Y F VSS[0] VSS[0] Y F VSS[] VSS[] P G0 VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] Y G VSS[] VSS[] P G VSS[] VSS[] T G VSS[] VSS[] G VSS[] VSS[] T G0 VSS[] VSS[] G VSS[0] VSS[0] Y G VSS[] VSS[] T F VSS[] VSS[] M H VSS[] VSS[] T H0 VSS[] VSS[] M H0 VSS[] VSS[] K H VSS[] VSS[] K H VSS[] VSS[] V H VSS[] {} PIE_RXN {} PIE_RXP G {} PIE_TXN {} PIE_TXP {} PIE_RXN {} PIE_RXP WLN {} PIE_TXN {} PIE_TXP {} PIE_RXN {} PIE_RXP LN {} PIE_TXN {} PIE_TXP {} LK_PIE_LN# {} LK_PIE_LN LN {} PIE_LK_REQ# {} LK_PIE_G# {} LK_PIE_G G {} PIE_LK_REQ# {} LK_PIE_MINI# {} LK_PIE_MINI WLN {} PIE_LK_RQ# SMUS MLK IbexPeak-M_Rev_0 MT G@0.U/0V_X G@0.U/0V_X 0.U/0V_X 0.U/0V_X PIE_LK_REQ0# TP0 TP PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_RQ# PIE_LK_REQ# TP TP TP0 TP TP TP TP TP TP TP TP TP 0.U/0V_X 0.U/0V_X TP TP TP0 TP TP TP TP0 TP0 Q V_S Q PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ PIE_RXN PIE_RXP PIE_TXN_ PIE_TXP_ N_MLK {} N_MT {} IEX PEK-M (PI-E,SMUS,LK) U G0 PERN J0 PERP F PETN H PETP W0 PERN 0 PERP 0 PETN 0 PETP PIE_RXN U0 PIE_RXP PERN T0 PIE_TXN_ PERP U PIE_TXP_ PETN V PETP N00_00M N00_00M PERN PERP PETN E PETP F PERN H PERP G PETN J PETP PERN W PERP PETN PETP T PERN U PERP U PETN V PETP G PERN J PERP G PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P IbexPeak-M_Rev_0 Ibex-M OF 0 PI-E* P PIELKRQ0# / GPIO M (V_S) LKOUT_PIEN M LKOUT_PIEP U PIELKRQ# / GPIO (V) M LKOUT_PIEN M LKOUT_PIEP N PIELKRQ# / GPIO0 (V) H LKOUT_PIEN H LKOUT_PIEP PIELKRQ# / GPIO (V_S) M LKOUT_PIEN M LKOUT_PIEP M PIELKRQ# / GPIO (V_S) SMus (V_S) SMLERT# / GPIO SMLK SMT (V_S) SML0LERT# / GPIO0 SML0LK SML0T (V_S) SMLLERT# / GPIO (V_S) SMLLK / GPIO (V_S) SMLT / GPIO ontroller Link PEG (V_S) PEG LKRQ# / GPIO LKOUT_PEG N LKOUT_PEG P LKOUT_MI_N LKOUT_MI_P From LK UFFER lock Flex RYSTL XTL_IN L_LK L_T L_RST# XTL_OUT SMLERT# H SLK ST J SML0LERT# SM_LK_ME0 G SM_T_ME0 M SMLLERT# E0 MLK G MT H LK_PEG_REQ# N N R LK_PI_F XTL_IN XTL_OUT XLK_ROMP J0 LKOUT_PIEN J LK_FLEX0 LKOUT_PIEP (V) LKOUTFLEX0 / GPIO T LK_FLEX (V_S) (V) LKOUTFLEX / GPIO P H LK_FLEX PIELKRQ# / GPIO (V) LKOUTFLEX / GPIO T LK_R_ (V) LKOUTFLEX / GPIO N0 K LKOUT_PEG N K LKOUT_PEG P P PEG LKRQ# / GPIO (V_S) T T T LKOUT_P_N / LKOUT_LK_N T LKOUT_P_P / LKOUT_LK_P T LKIN_MI_N W LKIN_MI_P LKIN_LK_N P LKIN_LK_P P LKIN_OT_N F LKIN_OT_P E LKIN_ST_N / KSS_N H LKIN_ST_P / KSS_P H REFLKIN LKIN_PILOOPK P J XTL_IN H XTL_OUT H XLK_ROMP F LK_PIE_GPLLN {} LK_PIE_GPLLP {} LK_REFSSLKN {} LK_REFSSLKP {} LK_UF_PIE_GPLLN {} LK_UF_PIE_GPLLP {} LK_UF_LKN {} LK_UF_LKP {} LK_UF_REFLKN {} LK_UF_REFLKP {} LK_UF_REFSSLKN {} LK_UF_REFSSLKP {} *short_ LK_PI_F {} Placement close R IV@M/F_ R Y T T T R R T T IV@MHZ_0 LK_PEG_REQ# EV@0_ SLK {,} ST {,} *P/0V_N 0./F_ P/0V_N IV@P/0V_N IV@P/0V_N 0K_ LK_PH_M {}.0V V del in UM LK_R_ {} PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ0# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_REQ# PIE_LK_RQ# SMLERT# SML0LERT# SM_LK_ME0 SM_T_ME0 SMLLERT# MLK MT SLK ST LK_PEG_REQ# ate: Monday, January, 0 Sheet 0 of R R R R0 R R R R0 R R R0 R R R R R0 R R V V_S Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (PIE, SMUS, K) 0 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_.K_.K_ 0K_.K_.K_.K_.K_ IV@0K_ *EV@0K_

11 {} {} {} GNT0# GNT# GNT# V TP R PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# REQ0# REQ# REQ# REQ# PIRQE# PIRQF# PIRQG# INTH#.K_ PI_SERR# PI_PERR# PI_IRY# PI_EVSEL# PI_FRME# PI_PLOK# PI_STOP# PI_TRY# IEX PEK-M (PI,US,NVRM) H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 G F M H J0 G H G G H F M F K F H K K E E0 H F UE /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# Ibex-M OF 0 PI REQ0# REQ# / GPIO0 (V) REQ# / GPIO (V) REQ# / GPIO (V) GNT0# GNT# / GPIO (V) GNT# / GPIO (V) GNT# / GPIO (V) PIRQE# / GPIO (V) PIRQF# / GPIO (V) PIRQG# / GPIO (V) PIRQH# / GPIO (V) PIRST# SERR# PERR# IRY# PR EVSEL# FRME# PLOK# STOP# TRY# NVRM US NV_LE NV_ROMP TP M PME# US_O0# R *0_ PLT_RST-R# (V_S) O0# / GPIO N US_O# R *0_ PLTRST# (V_S) O# / GPIO0 J US_O# {} PLK_EUG R _ LK_M_LP_R (V_S) O# / GPIO F N US_O# R *0_ TP0 LKOUT_PI0 (V_S) O# / GPIO L P USO# USO# {,} TP LKOUT_PI (V_S) O# / GPIO E P US_O# {0} LK_PI_F R _ LK_PI_F_R LKOUT_PI (V_S) O# / GPIO G P USO#_ USO#_ {,} R _ LK_PI_E LKOUT_PI (V_S) O# / GPIO0 F SI# {} PLK_ P LKOUT_PI (V_S) O# / GPIO T SI# {} NV_E#0 NV_E# NV_E# NV_E# NV_QS0 NV_QS NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q0 / NV_IO0 NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_Q / NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS Y P V G P P T T V E J J G Y U V Y Y V F H J N0 P0 J0 L0 F0 G0 0 0 M N H J E F G H L M US_IS R R USP0- {} USP0 {} TP TP TP TP USP- {} USP {} USP- {} USP {} USP- {} USP {} TP0 TP TP TP USP- {} USP {} USP- {} USP {} USP0- {} USP0 {} TP TP TP TP USP- {} USP {}./F_ NV_LE {} *./F_ ard Reader SIM WLN US/US HM not support US for daughter board US for left side G US for left side.0v {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} SYS_PWROK {,} US_US_SW0 {} S_ {,} S_ {,} {} {} {} MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP SYS_RESET# PM_RM_PWRG {} RSMRST# {} R R R R NSWON# PIE_WKE# PM_SYN./F_ MI_OMP SYS_RESET# *short_ *short_ *short_ RSV_IH_LN_RST# EMI RSMRST# NSWON# PM_RI# PIE_WKE# *E@P/0V_N IEX PEK-M (MI,FI,GPIO) J W0 J0 G 0 G0 E F 0 E H 0 H F T M K 0 P F J J0 U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP SYS_RESET# SYS_PWROK PWROK MEPWROK LN_RST# RMPWROK RSMRST# PWRTN# RI# WKE# PMSYNH IbexPeak-M_Rev_0 *E@P/0V_N MI PLK_EUG LK_PI_F PLK_ Ibex-M OF 0 FI System Power Management (V_S) SUS_PWR_N_K / GPIO0 (V_S) PRESENT / GPIO (V) LKRUN# / GPIO (V_S) SUS_STT# / GPIO (V_S) SUSLK / GPIO (V_S) SLP_S# / GPIO (V_S) TLOW# / GPIO *E@P/0V_N (V_S) SUS_PWR_K {} SUS_PWR_K FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SLP_S# SLP_S# SLP_M# TP SLP_LN# / GPIO H J E F G W J F H J G P H K N M P Y P F E F SLP_M# SUS_PWR_K_R _PRESENT LKRUN# RSV_SUS_ST# SLP_S# PM_TLOW# Q R TP TP V_S FI_TXN0 {} FI_TXN {} FI_TXN {} FI_TXN {} FI_TXN {} FI_TXN {} FI_TXN {} FI_TXN {} FI_TXP0 {} FI_TXP {} FI_TXP {} FI_TXP {} FI_TXP {} FI_TXP {} FI_TXP {} FI_TXP {} FI_INT {} FI_FSYN0 {} FI_FSYN {} FI_LSYN0 {} FI_LSYN {} SUS# {} SUS# {} TP TP TP TP *0_ LKRUN# {} N00_00M SUS_PWR_K_R IbexPeak-M_Rev_0 EMI PWROK V_S RESET Study ost own 0.U/0V_X V PI_IRY# PI_STOP# PI_PIRQ# PI_PIRQ# V_S USO#_ US_O# US_O# US_O# RP.KX RP.KX 0 0 PI_SERR# PI_PIRQ# PI_FRME# REQ# V SI# US_O0# US_O# USO# V_S PM_RI# R0 PM_TLOW# R PIE_WKE# R SUS_PWR_K_R R _PRESENT R NSWON# R V RP REQ# PI_EVSEL# INTH# PI_TRY#.KX 0 V_S 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ PI_PLOK# PI_PERR# REQ0# PI_PIRQ# V REQ# PIRQE# PIRQF# LKRUN# PIRQG# SYS_RESET# RSMRST# RSV_IH_LN_RST# R0 R R R R R R R0.K_.K_.K_.K_.K_ K_ 0K_ 0K_ V U *TSH0FU(F) PLT_RST-R# R0 00K_ R V_S *0.U/0V_X R0 *00K/F_ *SHORT_ R EV@0_ 0.U/0V_X PLTRST# {,,,} TP VG_PLTRST# R *0_ {,} ELY_VR_PWRGOO {,} MPWROK *LP0G00M0RR SYS_PWROK U TSH0FU(F) R0 R 00K_ 0K_ SYS_PWROK Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (PI,ONFI,US,MI) Monday, January, 0 ate: Sheet of

12 {} R_RMRST#_PH {,} TEMP_LERT# {,} US_US_SW OR_I OR_I GPIO OR_I GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO EST_N# GPIO GPIO GPIO OR_I TEMP_LERT# GPIO GPIO GPIO OR_I OR_I GPIO IEX PEK-M (GPIO,VSS_NTF,RSV) UF Ibex-M Y MUSY# / GPIO0 (V) OF 0 LKOUT_PIEN H LKOUT_PIEP H TH / GPIO (V) TH / GPIO (V) LKOUT_PIEN F J TH / GPIO (V) LKOUT_PIEP F F0 GPIO (V_S) GPIO MIS K LN_PHY_PWR_TRL / GPIO (V_S) 0GTE U T GPIO (V_S) STGP / GPIO (V) LKOUT_LK0_N/LKOUT_PIEN M F TH0 / GPIO (V) LKOUT_LK0_P/LKOUT_PIEP M Y SLOK / GPIO (V) PEI G0 GPIO (V_S) V GPIO (V_S) STGP / GPIO (V) STGP / GPIO (V) P STOUT0 / GPIO (V) F PIELKRQ# / GPIO (V_S) STOUT / GPIO (V) STGP / GPIO (V) H0 GPIO H (V_S) PIELKRQ# / GPIO F (V_S) GPIO M (V_S) STP_PI# / GPIO V (V) STLKREQ# / GPIO V (V) SLO / GPIO (V) VSS_NTF_ VSS_NTF_ VSS_NTF_ 0 VSS_NTF_ NTF VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E VSS_NTF_ F VSS_NTF_ F VSS_NTF_ H VSS_NTF_ IbexPeak-M_Rev_0 PU RSV RIN# T GTE0 PH_PEI_R RIN# PROPWRG E0 PH_THRMTRIP#_R THRMTRIP# 0 TP TP W TP TP Y TP Y TP V TP V TP F TP M TP0 N TP J TP K TP K TP M TP N TP M0 TP N0 TP H TP N_ N_ N_ N_ N_ T INIT_V# P TP 0 VSS_NTF_ H VSS_NTF_ H VSS_NTF_ H VSS_NTF_ J VSS_NTF_0 J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J VSS_NTF_ J0 VSS_NTF_ J VSS_NTF_ J VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 E VSS_NTF_ E R TP TP TP0 TP TP IEX PEK-M () UH VSS[0] VSS[0] K0 VSS[] VSS[] K 0 VSS[] VSS[] K VSS[] VSS[] K M VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K VSS[] VSS[] K 0 VSS[] VSS[] K VSS[] VSS[] K GTE0 {} VSS[0] VSS[0] K VSS[] VSS[] L VSS[] VSS[] L VSS[] VSS[] M LK_PU_LKN {} 0 VSS[] VSS[] VSS[] VSS[] LK_PU_LKP {} VSS[] VSS[] M0 VSS[] VSS[] M H_PEI {} VSS[] VSS[] M VSS[] VSS[] M RIN# {} VSS[0] VSS[00] M VSS[] VSS[0] H_PWRGOO {} VSS[] VSS[0] M0./F_ VSS[] VSS[0] M PM_THRMTRIP# {} VSS[] VSS[0] M VSS[] VSS[0] M R./F_ VSS[] VSS[0] M VTT VSS[] VSS[0] M 0 VSS[] VSS[0] M VSS[] VSS[0] M VSS[0] VSS[0] U0 VSS[] VSS[] M U VSS[] VSS[] V VSS[] VSS[] M VSS[] VSS[] M VSS[] VSS[] 0 VSS[] VSS[] 0 E VSS[] VSS[] N E VSS[] VSS[] N0 F VSS[] VSS[] N Y VSS[0] VSS[0] P H VSS[] VSS[] P U VSS[] VSS[] P F VSS[] VSS[] P P VSS[] VSS[] P N VSS[] VSS[] P F VSS[] VSS[] R F VSS[] VSS[] R F VSS[] VSS[] T F VSS[] VSS[] F VSS[0] VSS[0] H G VSS[] VSS[] T G VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] T H VSS[] VSS[] V H VSS[] VSS[] V V VSS[] VSS[] V0 H VSS[] VSS[] V H VSS[0] VSS[0] V0 H VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J0 VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] V J VSS[] VSS[] W J VSS[] VSS[] W J VSS[0] VSS[0] W T VSS[] VSS[] F J VSS[] VSS[] W K VSS[] VSS[] W M VSS[] VSS[] W0 N VSS[] VSS[] W K VSS[] VSS[] Y K VSS[] VSS[] Y K VSS[] VSS[] Y K VSS[] SPKR {,} {,0} GNT#/ GPIO PH_GPIO {} {} GNT0#, GNT# SPI_MOSI NV_LE SPI_SI_R PH Strap Pin onfiguration Table PEEP H_OK_EN #/GPIO 0 = efault Mode (Internal weak Pull-down) = No Reboot Mode with TO isabled GNT# 0 = efault Mode (Internal weak Pull-down) = No Reboot Mode with TO isabled 0 = Top lock Swap Mode = efault Mode (Internal pull-up) {} {} 0 R GNT0# GNT# oot IOS Strap PI_GNT0# GNT0# GNT# GNT# R K/F_ *K/F_ R0 *K_ R0 R JP V V oot IOS Location LP Reserved (NN) PI SPI R *0K/F_ *SHORT P *K/F_ *K/F_ IbexPeak-M_Rev_0 {} NV_LE R0 *0K_.V GPIO R 0K_ V_S GPIO R 0K_ V V GPIO = Enabled 0 = isabled (efault) GPIO R 0K_ V_S GPIO GPIO GPIO GPIO GPIO R R R R R *0K_ *0K_ 0K_ *0K_ 0K_ GPIO GPIO EST_N# GPIO GPIO R R R0 R R 0K_ 0K_ 0K_ 0K_ 0K_ RIN# GTE0 TEMP_LERT# GPIO R R R R 0K_ 0K_ 0K_ 0K_ GPIO This signal has a weak internal pull up. NOTE: This signal should not be pulled low GPIO R K_ V_S OR I SETTING oard I I UM SKU H VG SKU L W/ M W/O M W/ HMI W/O HMI W/O G W/ G " " W/O T W/ T or Old HW(00) New HW(0) I H L I H L I H L I H L I H L GPIO H L GPIO H L V_S R 0K_ GPIO V R 0K_ OR_I GPIO R 0K_ V R 0K_ T_etect# OR_I PUS# {} OR_I R 0K_ V V V R HM@0K_ OR_I OR_I OR_I R NHM@0K_ R 0K_ R *0K_ R IV@0K_ R0 EV@0K_ GPIO 0 = Intel ME rypto Transport Layer Security (TLS) cipher suite with no confidentiality = Intel ME rypto Transport Layer Security (TLS) cipher suite with confidentiality GPIO R *0K_ 0 = isables the VccVRM. Need to use on-board filter circuits for analog rails. = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. This signal has a weak internal pull-up. Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (GPIO & Strap) Monday, January, 0 ate: Sheet of

13 R V.0V *short_0 *0U/V_P_Eb *short_ VORE =.(0mils) R UG.0V_VORE_IH U/.V_X VORE[] V[] VORE[] Ibex-M.U/.V_X VORE[] OF 0 V[] VORE[] VORE[] RT VSS_[] F VORE[] F VORE[] VSS_[] F0 VORE[] F VORE[] H.0V VORE[0] VLVS H VORE[] VSS_LVS H0 VORE[] LVS H VORE[] VTX_LVS[] J0 VORE[] VTX_LVS[] *short_ J VORE[] VTX_LVS[] R VTX_LVS[] 0m(mils) V ORE.0V_PH_VPLL_EXP V.LN_VPLL_EXP V.S_V_EXP 0.U/.V_X U/.V_X U/.V_X U/.V_X U/.V_X 0.U/0V_X VIO =.0(0mils) R R0 TP *short_0 *short_ *0.U/0V_X 0.U/0V_X 0.U/0V_X V_VGG K J N0 N N N N N J J T T U U V V W W E E G G H N0 N N VIO[] VPLLEXP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] V_[] POWER PI E* HVMOS MI V_[] V_[] V_[] VVRM[] VMI[] VMI[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] VPNN[] NN / SPI VME_[] VME_[] VME_[] VME_[] E0 E F F H H P P T T T T U M K K0 K K K M M M M M P P V =m(mils) V R H0KF-T_. R *0_ 0U/.V_X *0U/.V_X 0.U/0V_X 0.0U/V_X VLVS= m(mils) R0 EV@0_ VLVS R IV@0_ R EV@0_ VTX_LVS R IV@0.uh 0M IV@.U/.V_X IV@0.U/0V_X IV@0.0U/V_X V_V_GIO R *short_ 0 0.U/0V_X V_ = 0.(0mils) VVRM= m(mils).s_vmi_vrm R0 *short_ VMI R0 *short_ U/.V_X VMI= m(mils) VPNN= m(mils) V_NVRM_VQ R0 *short_ 0.U/0V_X VME_= m(mils).v_vme_spi R *short_ 0.U/0V_X V V_LO V.V V.V VTT.V V UJ Ibex-M TP VLK P.0V_VUSORE VLK[] 0 OF 0VIO[] V R *short_ VIO[] V P PSUSYP VLK[] VIO[] Y U/.V_X Y0 0.U/0V_X PSUSYP VIO[] Y US V_S_VPUS VSUS_[] V R *short_ VLN = 0.(0mils) VSUS_[] U.0V.0V_VUX VSUS_[] U 0.U/0V_X R *short_ F VLN[] VSUS_[] U VSUS_[] P 0.U/0V_X F VLN[] VSUS_[] P VSUS_[] N *0.0U/0V_X VSUS_[] N VME =.(00mils) VME[] VSUS_[] M.0V.0V_VEPW VSUS_[0] M R *short_ VME[] VSUS_[] L VSUS_[] L VME[] VSUS_[] J VSUS_[] J F VME[] VSUS_[] H VSUS_[] H 0U/.V_X F VME[] VSUS_[] G VSUS_[] G 0U/.V_X F VME[] VSUS_[] F VSUS_[0] F 0 U/.V_X V VME[] VSUS_[] E VSUS_[] E 0 U/.V_X V VME[] VSUS_[] VSUS_[] U/.V_X V VME[] VSUS_[] VSUS_[] Y VME[0] VSUS_[].V.0V VRTEXT 0.U/0V_X V.LN_V PL V.LN_V PL VIO =.0(0mils) R 0 *short_.0v_ssv U/.V_X U/.V_X U/.V_X 0.U/0V_X VSST Y Y V U H J H F H F V VME[] VME[] PRT VVRM[] VPLL[] VPLL[] VPLL[] VPLL[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] PSST POWER lock and Miscellaneous VSUS_[] VIO[] VREF_SUS VREF PI/GPIO/LP V_[] V_[] V_[0] V_[] V_[] V_[] V_[] U V F K J L M N P U VREF_SUS VREF V_VPPI 0.0V_VUSORE VREF_SUS< m SM0K--F_00M U/.V_X VREF< m R R R SM0K--F_00M U/.V_X 0.U/0V_X 0.U/0V_X 00/F_ 00/F_ *short_ V_S V_S V V V.0V V_S.V.0V R R RT POWER {,,,} V MINON *short_vfi_vrm TP *short_ m(mils) V.LN_VPLL_FI.0V_VPLL_FI U SHN VO T J M VVRM[] VFIPLL VIO[] *0U/.V_X FI IbexPeak-M_Rev_0 V_LO R *.K/F_.0V L 0uh 00M V.LN_V PL 0 *0U/.V_P_Eb U/.V_X R *short_ V.LN_INT_VSUS Y 0.U/0V_X PSUS VSUS_ = 0.(0mils) PI/GPIO/LP VSTPLL[] K P V.LN_VPLL V_S V_S_VPSUS VSUS_[] VSTPLL[] K TP0 R *short_ U VSUS_[0] U0 0.U/0V_X VSUS_[] U VVRM[] T0 R *short_ VSUS_[].V V_ = 0.(0mils) V V_[] VIO[] H VIO =.0(0mils) V V V_VPORE VIO[0] H R *short_ V_[] Y V_ST.0V 0.U/0V_X VIO[] 0 R *short_ V_[] VIO[] F U/.V_X VIO[] V_PU >m(mils) T V_PU_IO[] VIO[] F0 U ST VTT VTT_VPPU VIO[] F R *short_ V_PU_IO[] PU VIO[] H0 0.U/.V_X VIO[] 0.U/0V_X 0.U/0V_X VIO[] 0 VRT VIO[] RT VIO[0] VRT= m(mils) VME =.(00mils) RT_ELL 0.U/0V_X L0.0V_VEPW VSUSH VME[] 0.U/0V_X VME[] Y H VME[] Y VSUSH= m(mils) VME[] *0.U/0V_X VIN *G SET R *0_ V.LN_V PL U/.V_X V_S R *short_ V._._H_IO U/.V_X IbexPeak-M_Rev_0 Quanta omputer Inc. PROJET : TE Size ocument Number Rev PH / (POWER) Monday, January, 0 ate: Sheet of

14 M 0 M M M M M M 0 M M M M M M M M M M M0 M M M M M M M M M M M M M M M QSP0 M QSN0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q IMM0_S0 IMM0_S SMR_VREF_Q0 SMR_VREF_IMM PM_EXTTS#0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP M QSP M QSP M QSP M QSP M QSP SMR_VREF_Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M [:0] {} M S#0 {} M S# {} M S# {} M S#0 {} M S# {} M LKP0 {} M LKN0 {} M LKP {} M LKN {} M KE0 {} M KE {} M S# {} M RS# {} M WE# {} M QSP[:0] {} M QSN[:0] {} M M[:0] {} M OT0 {} M OT {} M Q[:0] {} GLK_SM {,,} GT_SM {,,} R_VREF_Q0 {} MINON_ON_G {,} R_RMRST# {,} PM_EXTTS#0 {} SMR_VREF_IMM {}.VSUS V SMR_VTERM SMR_VTERM.VSUS SMR_VREF_Q0 V.VSUS SMR_VTERM SMR_VREF_IMM.VSUS.VSUS.VSUS SMR_VREF Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM-0 Monday, January, 0 TE SO-IMM SP ddress is 0X0 SO-IMM TS ddress is 0X0 Place these aps near So-imm0. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% H= R *0_ R *0_.U/.V_X.U/.V_X *0U/.V_P_Ea *0U/.V_P_Ea.U/.V_X.U/.V_X *0.0U/0V_X *0.0U/0V_X 0 0.U/0V_X 0 0.U/0V_X Q N00_00M Q N00_00M 0 0P/0V_X 0 0P/0V_X 0 U/.V_X 0 U/.V_X R 0K/F_ R 0K/F_.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT R *short_ R *short_ 0 U/.V_X 0 U/.V_X 0 U/.V_X 0 U/.V_X R *0K/F_ R *0K/F_ R *00K/F_ R *00K/F_ P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R0 *0K/F_ R0 *0K/F_ 0.U/0V_X 0.U/0V_X *0.0U/0V_X *0.0U/0V_X 0.U/0V_X 0.U/0V_X 0.U/.V_X 0.U/.V_X *0.0U/0V_X *0.0U/0V_X.U/.V_X.U/.V_X 0 *0.0U/0V_X 0 *0.0U/0V_X R K/F_ R K/F_ U/.V_X U/.V_X.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X R 0K/F_ R 0K/F_ 0.U/.V_X 0.U/.V_X 0.U/0V_X 0.U/0V_X *0.0U/0V_X *0.0U/0V_X R _ R _ 0.U/0V_X 0.U/0V_X R *K/F_ R *K/F_.U/.V_X.U/.V_X *0.U/0V_X *0.U/0V_X R K/F_ R K/F_.U/.V_X.U/.V_X.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X

15 M M M M IMM_S M M M M Q M M 0 M M M Q M Q M M Q M Q M Q M Q M Q0 M Q M Q M M M M M M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M M M M M 0 M M M M M QSP0 M M0 M M M QSN0 IMM_S0 M SMR_VREF_Q M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP M QSP M QSP M QSP M QSP M QSP SMR_VREF_Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M [:0] {} M S#0 {} M S# {} M S# {} M S#0 {} M S# {} M LKP0 {} M LKN0 {} M LKP {} M LKN {} M KE0 {} M KE {} M S# {} M RS# {} M WE# {} M QSP[:0] {} M QSN[:0] {} M M[:0] {} M OT0 {} M OT {} M Q[:0] {} GLK_SM {,,} GT_SM {,,} R_RMRST# {,} PM_EXTTS# {} SMR_VREF_IMM {} R_VREF_Q {} V.VSUS V SMR_VTERM.VSUS.VSUS.VSUS SMR_VTERM SMR_VREF_IMM SMR_VREF_Q V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January, 0 TE Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R IMM- Monday, January, 0 TE SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Place these aps near So-imm. Some Projects replace 0UF 00 by.uf 00 It can cost down 0% H= R *00K/F_ R *00K/F_ 0 0.U/0V_X 0 0.U/0V_X.U/.V_X.U/.V_X R0 0K/F_ R0 0K/F_ 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X *0.0U/0V_X *0.0U/0V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X R K/F_ R K/F_ 0 U/.V_X 0 U/.V_X 0 U/.V_X 0 U/.V_X 0 U/.V_X 0 U/.V_X 0 *0.0U/0V_X 0 *0.0U/0V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT U/.V_X 0 U/.V_X.U/.V_X.U/.V_X.U/.V_X.U/.V_X *0.0U/0V_X *0.0U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0.U/0V_X 0 *0.0U/0V_X 0 *0.0U/0V_X 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X 0.U/0V_X 0.U/0V_X P00 R SRM SO-IMM (0P) JIM RSK-00-TP P00 R SRM SO-IMM (0P) JIM RSK-00-TP 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q R *0_ R *0_.U/.V_X.U/.V_X 0 *0.U/0V_X 0 *0.U/0V_X.U/.V_X.U/.V_X 0 *0U/.V_P_Ea 0 *0U/.V_P_Ea *0.0U/0V_X *0.0U/0V_X 0.U/0V_X 0.U/0V_X.U/.V_X.U/.V_X R 0K/F_ R 0K/F_ R0 K/F_ R0 K/F_ 0.U/0V_X 0.U/0V_X

16 isplay Port Enable [HM] V I PU V LEVEL SHIFT ENLE V R IHM@0K_ HMI LEVEL SHIFT (UM) {} TMS_T TMS_T {} TMS_T# TMS_T# U00 IN_ IN_- OUT_ OUT_- HMITXP HMITXN HMITXP {} HMITXN {} TMS_LK TMS_LK# R IHM@.K/F_ R *IHM@.K/F_ INT_HMI_SL INT_HMI_S R0 IHM@.K_ R IHM@.K_ HMI_LF_HPOUT OE# Q0 IHM@N00_00M R *IHM@0K_ {} TMS_T TMS_T HMITXP TMS_T# IN_ OUT_ HMITXP {} {} TMS_T# HMITXN IN_- OUT_- 0 HMITXN {} {} TMS_T0 TMS_T0 HMITX0P HMITX0P {} TMS_T0# IN_ OUT_ {} TMS_T0# HMITX0N IN_- OUT_- HMITX0N {} {} TMS_LK TMS_LK HMILK HMILK {} {} TMS_LK# TMS_LK# IN_ OUT_ HMILK- IN_- OUT_- HMILK- {} INT_HMI_SL HMI_LK {} INT_HMI_SL HMI_LK {} INT_HMI_S SL SL_SINK HM_T {} INT_HMI_S S S_SINK HM_T {} HMI_LF_HPOUT HP HP_SINK 0 HMI_ON_HP HMI_ON_HP {} LEVEL SHIFT SETTING V V Hot Plug etector (UM) OE# _EN O_ 0 OE# _EN N(O_) V[] V[] V[] V[] V[] V[] V[] V[] 0 V 0.(0mils) R R R R0 *IHM@.K_ *short_ *IHM@.K_ *short_ SR0 SR R0 R R R IHM@.K_ *IHM@0_ IHM@0K_ *IHM@.K EN OE# *IHM@0_ R V SR0 SR O_ EQ_0 EQ_ SR0 SR N(O_) N(EQ_0) N(EQ_) IHM@PIVPLSRZE [] [] [] [] [] [] [] [] [] [0] Slew Rate ontrol Function SR SR0 Rise/Fall Time 0ps ps 0ps 0ps Reserve R R R R *IHM@0_ *IHM@0_ *IHM@0_ *IHM@0_ O_ O_ EQ_0 EQ_ {} Port-_HP Q0 R0 IHM@00K_ IHM@N00_00M HMI_LF_HPOUT R IHM@00K_ IHM@0.U/0V_X IHM@0.0U/V_X V IHM@0.U/0V_X IHM@0.0U/V_X V V R R IHM@.K_ IHM@.K_ HMI_LK HM_T LVS (UM) RT (UM) {,} INT_LVS_RIGHT LVS_RIGHT {,} {,} INT_LVS_IGON LVS_IGON {,} {,} INT_L_TXLLKOUT {,} INT_L_TXLLKOUT- {,} INT_L_TXLOUT0 {,} INT_L_TXLOUT0- L_TXLLKOUT {,} L_TXLLKOUT- {,} L_TXLOUT0 {,} L_TXLOUT0- {,} {,} INT_RT_RE {,} INT_RT_GRE {,} INT_RT_LU RT_RE {,} RT_GRE {,} RT_LU {,} {,} INT_LVS_PWM LVS_PWM {,} {,} INT_L_TXLOUT {,} INT_L_TXLOUT- L_TXLOUT {,} L_TXLOUT- {,} {,} INT_RT_LK {,} INT_RT_T RT_LK {,} RT_T {,} {,} INT_L_EILK {,} INT_L_EIT L_EILK {,} L_EIT {,} {,} INT_L_TXLOUT {,} INT_L_TXLOUT- L_TXLOUT {,} L_TXLOUT- {,} {,} INT_RT_HSYN {,} INT_RT_VSYN RT_HSYN {,} RT_VSYN {,} Quanta omputer Inc. PROJET : TE Size ocument Number Rev UM Monday, January, 0 ate: Sheet of

17 HMI onn [HM] V F HM@NNOSM0F- V HM@RSX0M-0_ 0 HMITXP_R HMITXN_R HMITXP_R HMITXN_R HMITX0P_R HMITX0N_R HMILK_R HMILK-_R HMI_LK HM_T V_ HMI_ON_HP 0 N SHELL 0 Shield - Shield Shield 0- K K Shield K- E Remote N LK T V HP ET SHELL HM@-0-L *E@0.U/V_Y HM@0.U/V_Y {} {} {} {} {} {} {} {} {} {} HMITX0P HMITX0N HMITXP HMITXN HMITXP HMITXN HMILK HMILK- HMI_LK HM_T HMITX0P HMITX0N HMITXP HMITXN HMITXP HMITXN HMITX0P_R HMITX0N_R HMITXP_R HMITXN_R HMITXP_R HMITXN_R HMILK HMILK- RN HMILK_R HMILK-_R HM@LPSN00HLL RN: footprint is choke model RN RN RN HM@0X HM@0X HM@0X HMI_LK HM_T HMITX0P_R HMITX0N_R HMITXP_R HMITXN_R HMITXP_R HMITXN_R HMILK_R HMILK-_R HMITX0P_R HMITXP_R HMITXP_R HMILK_R near to N R *E@00_ R *E@00_ R *E@00_ R *E@00_ HMITX0N_R HMITXN_R HMITXN_R HMILK-_R {} HMI_ON_HP HMI_ON_HP HMI_LK HM_T EMI 此組之後可以刪掉, 重覆到了 0 *E@P/0V_N 0 *E@P/0V_N Quanta omputer Inc. Size ocument Number Rev HMI ONN PROJET : TE ate: Monday, January, 0 Sheet of

18 L POWER SWITH <LS> HLL Sensor <HSR> VPU R 00K_ VPU V R0 0K_ LONG V Q ME0_.(mils) LV V R0 K_ ISPON ISPON {} SM0K--F_00M 0.U/0V_X LI# MR HNTR-G LI# {} R LV L *SHORT_ {} LVS_IGON R 00K_ 00K_ Q 0.0U/V_X R Q /F_ N00_00M LISHG LON# Q TTKT_00M @0U/.V_X IV@SM0K--F_00M E_FPK# {} Q Q TEUTL_0M EV@N00_00M V R EV@0K_ R 00K_ LVS_RIGHT {} Q EV@N00_00M L Panel Module [LS] VIN V L_EILK *E@P/0V_N R R R 0 L_EIT *E@P/0V_N.K_.K_ *LP0G00M0RR *SHORT_ V L_EILK L_EIT ISPON_O_R L_K_POWER *E@0.U/V_X LV {0} {0} *E@0.U/V_X 0. (0mils) MI_LK MI_IN R L L {} {} {} {} {} {} {} {} L_EILK L_EIT L_TXLOUT- L_TXLOUT L_TXLOUT- L_TXLOUT {} L_TXLLKOUT- {} L_TXLLKOUT L_TXLOUT- L_TXLOUT L_TXLOUT0- L_TXLOUT0./F_ {} LVS_PWM LV V LV L_EILK L_EIT L_TXLOUT- L_TXLOUT L_TXLLKOUT- L_TXLLKOUT L_TXLOUT0- L_TXLOUT0 LVS_PWM ISPON_O_R L_K_POWER _POWER USP0-_L USP0_L SY000T-Y-N_00M SY000T-Y-N_00M *E@0P/0V_N *E@0P/0V_N N RT <RT> US for RT OR (Right) <US> {} RT_RE {} RT_GRE {} RT_LU VPU {} US_EN#.P/0V_N.P/0V_N U/V_X L LM0SN_00M L LM0SN_00M GREEN_L L LM0SN_00M ULE_L 0.P/0V_N.P/0V_N U GPU IN OUT IN OUT OUT EN# - O# RE_L.P/0V_N USPWR *0U/.V_X V {} RT_LK {} RT_T V {} RT_VSYN {} RT_HSYN RE_L GREEN_L ULE_L USP_L USP-_L N G [] change footprint USP0_L USP0-_L L *E@LPSN00HLL EMI O-LY USP0 {} USP0- {} {,} USO# change footprint USP_L USP-_L EMI L E@LPSN00HLL USP {} USP- {} V R *SHORT_ 0.(0mils) Quanta omputer Inc. PROJET : TE Size ocument Number Rev L/LE Panel/ ate: Monday, January, 0 Sheet of

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