JM50_R21_0120_1_REGERBER_MDRR

Transcription

1 M0 Ultrabook lock iagram Rev.0 VRM Page, L Panel PU nvidia NPL Page 0~ PE ep LVS PU Sandy ridge Page ~ R MHz R SO-IMM & Memory own Page ~ HMI Page Page HMI MI x FI 0 Miniard (HLF) WLN + T Touchpad Keyboard Page ebug onn. E NPEL FN Page 0 Page Page 0 LP SPI ROM (M+M) Page PH Panther Point US.0 US.0 PIEx ST Page 0~ 0 roadcom M0 Realtek RTS0 Page Page 0 Miniard (FULL) SS (mst) Page igaln ardreader IN RJ Page Power +V_ORE +VFX_ORE System Page 0 Speaker Page udio Jack (combo) Page zalia odec L ischarge ircuit Page Reset ircuit Page Page zalia & TT. onn. Page 0 Skew Holes Page 0 MOS amera Page luetooth US Port() Page Page US Port() Page harger Page 0 US Port() H O Page Page Page VTT R +.VS +VS +V_ORE harger etect Page Page Page Page Page Page Page Page 0 Page Load Switch Page Power Protect Page -HW R iv.-n R ept. lock iagram Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

2 PH_PT PIO PH_PT PIO PIO 00 PIO 0 PIO [:] PIO 0 PIO 0 PIO 0 PIO 0 PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO 0 PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO Use s Signal Name Internal & External Pull-up/down Power E NPEL E PIO P0 P P P P P P P P0 P P P P P P P P0 P P P P P P P P0 P P P P P P P PE0 PE PE PE PE PE PE PE PF0 PF PF PF PF PF PF PF P0 P P P PH0 PH PH PH PH PH PH PI0 PI PI PI PI PI PI PI PJ0 PJ PJ PJ PJ PJ Use s Signal Name SM_US RESS : SM-us evice SM-us ddress SO-IMM x ( 0h ) SO-IMM 0000x ( h ) PIE PIE PIE PIE PIE PIE PIE PIE ST0 ST ST ST ST ST N/ US 0 US Port () Minicard WLN N/ US US US Port () US.0 Port () US.0 US US Port () N/ US N/ LN US N/ N/ US N/ N/ US N/ US MOS amera ST H US WLN N/ US 0 ard Reader ST O US N/ N/ US N/ N/ US N/ N/ System Setting Joyoung_hianhg -HW R iv.-n R ept. M0.0 Monday, February, 0 ate: Sheet of

3 +VP +VP,,,0,,, +VP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN[:0] FI_TXP[:0] FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN +VP.Ohm % R00 P_OMP 0KOhm /LVS R00 KOhm /ep R0 P_HP#_PH P_UXN_PH P_UXP_PH P_TXN0_PH P_TXN_PH P_TXP0_PH P_TXP_PH U00 M MI_RX#[0] P MI_RX#[] P MI_RX#[] P0 MI_RX#[] N MI_RX[0] P MI_RX[] P MI_RX[] P MI_RX[] K MI_TX#[0] M MI_TX#[] N MI_TX#[] R MI_TX#[] K MI_TX[0] M MI_TX[] P MI_TX[] T MI_TX[] FI_TXN0 U FI_TXN FI0_TX#[0] W FI_TXN FI0_TX#[] W FI_TXN FI0_TX#[] FI_TXN FI0_TX#[] W FI_TXN FI_TX#[0] V FI_TXN FI_TX#[] Y FI_TXN FI_TX#[] FI_TX#[] FI_TXP0 U FI_TXP FI0_TX[0] W0 FI_TXP FI0_TX[] W FI_TXP FI0_TX[] FI_TXP FI0_TX[] W FI_TXP FI_TX[0] T FI_TXP FI_TX[] FI_TXP FI_TX[] FI_TX[] FI0_FSYN FI_FSYN U FI_INT 0 FI0_LSYN FI_LSYN F ep_ompio ep_iompo ep_hp ep_ux# F ep_ux ep_tx#[0] ep_tx#[] E ep_tx#[] E ep_tx#[] ep_tx[0] ep_tx[] E0 ep_tx[] E ep_tx[] MI Intel(R) FI P PI EXPRESS -- RPHIS PE_IOMPI PE_IOMPO PE_ROMPO PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_OMP R00 %.Ohm PIEN_RXN[:0] 0 H PIEN_RXN J PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN 0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN H PIEN_RXN E PIEN_RXN K PIEN_RXN0 PIEN_RXP[:0] 0 K PIEN_RXP K PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP F PIEN_RXP PIEN_RXP PIEN_RXP H PIEN_RXP F PIEN_RXP K PIEN_RXP0 PIEN_TXN0 X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN H PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN0 K PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN F PIEN_TXN X00 0.UF/0V PIE_RXN PIEN_TXN X00 0.UF/0V PIE_RXN J PIEN_TXN0 X0 0.UF/0V PIE_RXN H PIEN_TXN X0 0.UF/0V PIE_RXN M0 PIEN_TXN X0 0.UF/0V PIE_RXN F0 PIEN_TXN X0 0.UF/0V PIE_RXN PIEN_TXN X0 0.UF/0V PIE_RXN J PIEN_TXN X0 0.UF/0V PIE_RXN0 F PIEN_TXP0 X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP E PIEN_TXP X00 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP0 K PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP E PIEN_TXP X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP0 X0 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K0 PIEN_TXP X0 0.UF/0V PIE_RXP 0 PIEN_TXP X00 0.UF/0V PIE_RXP PIEN_TXP X0 0.UF/0V PIE_RXP K PIEN_TXP X0 0.UF/0V PIE_RXP0 PIE_RXN[:0] 0 PIE_RXP[:0] 0 R. 0/0 ES 0V HW R iv.-n R ept. PU()_MI,P,PE,FI Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

4 U00 +.VS_VQ +.VS_VQ,,0,,,,,0 H_SN_IV# +VP H_PEI H_THRMTRIP# H_PM_SYN H_PUPWR PM_RM_PWR 0KOhm UF_PLT_RST# T00 T00 Ohm % R00 H_PROHOT# Ohm N_R00_MIL_SMLL R00 R00 R00 % N_R00_MIL_SMLL R0.KOhm R00 TP_SKTO#_R TP_TERR#_R H_PROHOT#_ R00 0V00000 H_PM_SYN_R H_PUPWR_R VPWROO_R R. UF_PU_RST# F E PRO_SELET# PRO_ETET# TERR# PEI PROHOT# THERMTRIP# PM_SYN UNOREPWROO SM_RMPWROK RESET# MIS THERML PWR MNEMENT LOKS R MIS JT & PM LK LK# PLL_REF_LK PLL_REF_LK# LK_ITP LK_ITP# SM_RMRST# SM_ROMP[0] SM_ROMP[] SM_ROMP[] PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] J H N N T0 F E N N L L J M0 L K E E H0 J J LK_EXP_P_R LK_EXP_N_R LK_P_P_R LK_P_N_R SM_ROMP_0 SM_ROMP_ SM_ROMP_ LK_XP_ITP_P LK_XP_ITP_N XP_ebug XP_PRY# XP_PREQ# XP_TK XP_TMS XP_TRST# XP_TI XP_TO R0 R0 R0 /LVS R0 R0 R00 XP_RESET# % % % XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM R00 T00 T0 /LVS.Ohm 0 T00 T00 T00 T00 T00 T00 T00 T0 T0 T0 T0 T0 T0 T0 T0 T0 KOhm RN00 RN00 KOhm +VP /ep /ep PURMRST# LK_EXP_P LK_EXP_N LK_P_P LK_P_N R RM RESET System Memory Impedance ompensation Huron River platform esign uide P. Table. Remove XP interface. 0VH VH VS +VS,0,,,,,,,,,0,,,,,,,,0,,,,,,0,, +VSUS +VSUS,,,0,0,, +VP +VP,,,0,,, +V +V,,,,, R.0 PU/P for JT signals +VP XP_TMS R0 Ohm XP_TI R0 Ohm XP_TO R0 Ohm XP_PREQ# R00 Ohm XP_TK R0 Ohm XP_TRST# R0 Ohm R0 ES 0V R.0 0 Sandy ridge:r0 = 0 ohm (0V00000) Ivy ridge:r0 = 0 ohm (0V00000) PM_SYS_PWR is the power good for +.V_VQ ifferent from EVEREST R00 +VSUS PM_RM_PWR R0 N_R00_MIL_SMLL R00 KOhm % +.VS_VQ R0 0 %. Volt 0V00000 R0.KOhm % +VSUS 00 0.UF/0V U00 V N Y Vcc=~. R0.KOhm RV-0 0.V/0m 00 0 UF/.V PM_PWROK,0, +.0VS_PWR, R. R. add S power reduction 0 VR_HOT# R0 If support S power reduction with power good.. Mount U00, 00, 0, 00, R00, R0, R0, Unmount R00. hange R0 to kohm from 00ohm, change R00 to 0ohm from 0ohm - esign uide.0 page 0 R.0 0 Intel omments H_PROHOT# 00 PF/0V Q00 N00 S THRO_PU THRO_PU 0 -HW R iv.-n R ept. PU()_LK,MIS,JT Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

5 S +.V +.V,,,,0, +.V +.V,,,,0, M Q[:0] M S0 M S M S M S# M RS# M WE# U00 M Q0 M Q S_Q[0] J M Q S_Q[] P M Q S_Q[] L M Q S_Q[] J0 M Q S_Q[] J M Q S_Q[] L M Q S_Q[] L M Q S_Q[] R M Q S_Q[] P M Q0 S_Q[] U M Q S_Q[0] V M Q S_Q[] R M Q S_Q[] P M Q S_Q[] T M Q S_Q[] U M Q S_Q[] M Q S_Q[] M Q S_Q[] M Q S_Q[] M Q0 S_Q[] M Q S_Q[0] M Q S_Q[] M Q S_Q[] Y M Q S_Q[] V M Q S_Q[] R M Q S_Q[] Y M Q S_Q[] R M Q S_Q[] M Q S_Q[] U M Q0 S_Q[] M Q S_Q[0] M Q S_Q[] M Q S_Q[] R M Q S_Q[] W M Q S_Q[] M Q S_Q[] M Q S_Q[] R M Q S_Q[] T M Q S_Q[] Y M Q0 S_Q[] M Q S_Q[0] V M Q S_Q[] M Q S_Q[] Y M Q S_Q[] M Q S_Q[] U M Q S_Q[] M Q S_Q[] M Q S_Q[] M Q S_Q[] V M Q0 S_Q[] P0 M Q S_Q[0] P M Q S_Q[] V M Q S_Q[] T M Q S_Q[] P M Q S_Q[] P M Q S_Q[] N M Q S_Q[] N M Q S_Q[] M Q S_Q[] M Q0 S_Q[] N M Q S_Q[0] N M Q S_Q[] M Q S_Q[] K S_Q[] S_S[0] F S_S[] S_S[] E S_S# S_RS# T S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] U V Y T0 U0 0 Y0 L M QS#0 R M QS# V M QS# T M QS# V M QS# Y M QS# T M QS# K M QS# J M QS0 R0 M QS Y M QS U M QS W M QS V M QS T M QS K M QS M 0 M E M M T M U M M T M Y M V M E M 0 0 M 0 M W M Y M U M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 T00 T00 T00 M IM0_S#0 M IM0_OT0 M QS#[:0] M QS[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M S0 M S M S M S# M RS# M WE# U00 L S_Q[0] L S_Q[] N S_Q[] R S_Q[] K S_Q[] K S_Q[] N S_Q[] R S_Q[] U S_Q[] T S_Q[] V S_Q[0] S_Q[] U S_Q[] R S_Q[] Y S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] F S_Q[] F S_Q[0] 0 S_Q[] S_Q[] E S_Q[] F S_Q[] E S_Q[] E S_Q[] E S_Q[] E S_Q[] S_Q[] S_Q[0] F S_Q[] 0 S_Q[] F S_Q[] S_Q[] F S_Q[] S_Q[] E S_Q[] S_Q[] E S_Q[] F S_Q[0] E S_Q[] S_Q[] Y0 S_Q[] E S_Q[] S_Q[] S_Q[] W S_Q[] W S_Q[] U S_Q[] N S_Q[0] N S_Q[] U S_Q[] U S_Q[] N S_Q[] R S_Q[] K S_Q[] L S_Q[] S_Q[] S_Q[] M0 S_Q[0] L S_Q[] F S_Q[] H0 S_Q[] S_S[0] S_S[] T S_S[] V S_S# F0 S_RS# S_WE# R SYSTEM MEMORY S_K[0] S_K#[0] S_KE[0] S_K[] S_K#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y R F E E T L V T0 K M V E E R K F E U0 0 V0 0 E0 E T V T U M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS0 M QS M QS M QS M QS M QS M QS M QS M 0 M M M M M M M M M M 0 M M M M M M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_LK_R M IM0_LK_R# M IM0_KE M IM0_S#0 M IM0_S# M IM0_OT0 M IM0_OT M QS#[:0] M QS[:0] M [:0] ES 0V ES 0V R.0 S circuit: RM_RST# to memory should be high during S R. add S power reduction +.V R00 KOhm always support S PWR Reduction Remove bypass R Q00 N00 R00, R_RMRST# KOhm PURMRST# R00 use k ohm esign uide 0. p0() lose to IMM,,0 RMRST_NTRL_PH R.0 / 00 0.UF/0V %.KOhm R00 -HW R iv.-n R ept. PU()_R Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

6 +VP +VORE +VP,,,0,,, +VORE,,0 U00F +VP +VORE E E E E E E F F F F F F F F H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 ORE SUPPLY POWER PE N R SENSE LINES SVI QUIET RILS VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO_SEL VPQE VPQE0 VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO F 0 J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 0 J J W W M N F N N +VIO_PU_F VP_SEL 0 UF/.V H_PU_SVILRT# H_PU_SVILK H_PU_SVIT V_SENSE_R VSS_SENSE_R 0 UF/.V 00 UF/.V 0 UF/.V R0 % % R0 R00 R0 0 UF/.V 00 UF/.V 0 UF/.V +VP lose to PU +VP 0 UF/.V 00 UF/.V 00 UF/.V +VP N_R00_MIL_SMLL R00 % Ohm vx_c00_small +V +VP +VP +VP +VP 0V00000 R00 Ohm % SP00 N_R00_0MIL_SMLL SP00 N_R00_0MIL_SMLL +VP_SENSE +VSSP_SENSE 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 00 UF/.V VR_SVI_LERT# 0 VSENSE VSSSENSE vx_c00_small 0 0UF/.V vx_c00_small 0 UF/.V vx_c00_small R0 0KOhm 00 0UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V vx_c00_small lose to VR VSENSE 0 VSSSENSE 0 vx_c00_small 00 0UF/.V vx_c00_small 00 0UF/.V vx_c00_small 0 UF/.V 0 UF/.V 00 0UF/.V SP00 0 UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V R00 00 UF/.V vx_c00_small 00 0UF/.V vx_c00_small.ohm % 00 0UF/.V VR_SVI_LK 0 0 UF/.V +VP R.0 / lose to PU R00 % SP00 lose to VR R00 % VR_SVI_T 0 ES 0V HW R iv.-n R ept. PU()_PWR Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

7 ecoupling guide from Intel P R0. +VFX_ORE uf * pcs 0uF * pcs uf * pcs +VFX_ORE uf * pcs 0uF * pcs uf * pcs(power request) +VP +.V +VS +VP,,,0,,, +.V,,,,,0, +VS +VFX_ORE raphics core voltage Voltage range: 0 -.V +.VS +VFX_ORE +.VS +.VS,,,0, +VFX_ORE,0 +.VS,,, +V_SM_VREF +V_SM_VREF 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 0 UF/.V U00 R Reference Voltage +V_SM_REF 0mil +.VS_VQ R. add S power reduction 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V vx_c00_small 00 0UF/.V 00 UF/.V +VS 0 0UF/.V vx_c00_small vx_c00_small VS 0 0UF/.V VT_SENSE VSST_SENSE PLL supply voltage ( + specification) vx_c00_small 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V vx_c00_small E00 0UF/V 0 0UF/.V vx_c00_small 0 UF/.V vx_c00_small 0 0UF/.V 0 UF/.V vx_c00_small 0 UF/.V 0 0UF/.V 0 vx_c00_small UF/.V SP00 N_R00_0MIL_SMLL SP00 N_R00_0MIL_SMLL 0 UF/.V 0 0UF/.V vx_c00_small 0 UF/.V MX:. T:. 0 UF/.V MX:0 vx_c00_small T: 0 0UF/.V 0 0UF/.V 0 UF/.V 0 0 E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y F L L N N0 N P P0 R R R U V V V V W0 VX VX0 VX VX SM_VREF VX VX VX VX VX VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ0 VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ0 VX VQ VX VQ VX0 VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ VX VQ0 VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX_SENSE VSSX_SENSE VPLL VPLL VPLL0 VS VS VS VS VS VS0 VS VS VS VS VS VS VS VS VS VS0 RPHIS POWER SENSE LINES.V RIL S RIL SENSE LINES QUIET RILS R -.V RILS VQ VQ0 VQ_SENSE VSS_SENSE_VQ VS_SENSE VS_VI[0] VS_VI[] Y J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 M N U0 +V_SM_VREF VS_SEL0 VS_SEL hief River +V_SM_VREF MX: hief River ecoupling guide from Intel (EE) +.VS_VQ uf * 0pcs 0uF * pcs 0uF * pcs Filtered( Only) T00 T00 00 UF/.V vx_c00_small R00 0 UF/.V 0 0UF/.V R00 00 UF/.V 0 0UF/.V vx_c00_small +.VS_VQ R00 KOhm R00 KOhm VS_SEL0 VS_SEL vx_c00_small VS_SENSE lose to PU 00 UF/.V 0 0UF/.V 0 0.UF/0V 00 UF/.V 0 0UF/.V vx_c00_small 00 UF/.V vx_c00_small +VS_SEL0 +VS_SEL L L H H 00 UF/.V 0 0UF/.V 0 0UF/.V vx_c00_small L H L H 0 UF/.V 00 UF/.V vx_c00_small 00 0UF/.V VS 0.V 0.V 0.V 0.V 0 UF/.V 0 0UF/.V vx_c00_small >00 ns +.VS_VQ 0 UF/.V JP00 MM_OPEN_MIL VS_SEL0 VS_SEL +VP +.VS > 0 SUS_E# R.0 00 Intel omments Processor I/O supply voltage for R ( + specification) R. add S power reduction E00 0UF/V R00 KOhm R00 KOhm IMX_VQ +.V_VQ +.V_VQ Power ood (U00 pin ) +0.VS R00 KOhm R00 KOhm ES 0V ecoupling guide for (EE) +VS uf * pcs 0uF * pcs -HW R iv.-n R ept. PU()_FX_PWR Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

8 ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. PU()_N.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. PU()_N.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. PU()_N.0 M0 Joyoung_hianhg VSS U00H 0V ES VSS U00H 0V ES VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS00 VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS 0 VSS VSS VSS E VSS E VSS F VSS F VSS F VSS0 F VSS F VSS F0 VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS 0 VSS VSS VSS VSS VSS VSS0 VSS H VSS H VSS0 J VSS J VSS J0 VSS J VSS J VSS J0 VSS J VSS J VSS J VSS J VSS0 J VSS J VSS K VSS K VSS L0 VSS L VSS L VSS L VSS L VSS L VSS L VSS0 L VSS0 L0 VSS0 L VSS0 L VSS0 L VSS0 M VSS0 M0 VSS0 M VSS0 M VSS00 M0 VSS M VSS M VSS0 M VSS M VSS M VSS M VSS M VSS N VSS N VSS N VSS0 N VSS N VSS N VSS N0 VSS N VSS N VSS N0 VSS N VSS P0 VSS0 P VSS P VSS P VSS R VSS R VSS R VSS R VSS R VSS R VSS R VSS0 T VSS T VSS T VSS T VSS T VSS T VSS T VSS U VSS U VSS U VSS0 U VSS U VSS U VSS V VSS V VSS V VSS V VSS V0 VSS V VSS V VSS0 W VSS W VSS W VSS W VSS Y VSS Y VSS Y0 VSS Y VSS Y VSS Y VSS0 Y VSS Y VSS Y VSS Y VSS Y VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS E VSS VSS NTF U00I 0V ES VSS NTF U00I 0V ES VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS0 VSS VSS VSS 0 VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS 0 VSS VSS VSS VSS E VSS E VSS0 E VSS E VSS E0 VSS F VSS F VSS F VSS F VSS F VSS0 F0 VSS F VSS VSS VSS VSS VSS H0 VSS H VSS H VSS0 H VSS H VSS H VSS H VSS J VSS J VSS J VSS K VSS K VSS K VSS K VSS0 L VSS L0 VSS L VSS L VSS L0 VSS L VSS L VSS L VSS L VSS0 P VSS0 P VSS0 P VSS0 P VSS0 P VSS0 P VSS0 P VSS0 R VSS0 R0 VSS0 R VSS00 R VSS T VSS T VSS T0 VSS T VSS T VSS T VSS T VSS T VSS0 U VSS U VSS V0 VSS V VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF VSS_NTF E VSS_NTF E VSS_NTF VSS_NTF0 VSS_NTF VSS_NTF0 VSS_NTF VSS_NTF E VSS_NTF E VSS0 M VSS M VSS M VSS N VSS N VSS N VSS N VSS N VSS0 N VSS N VSS N0 VSS N VSS N VSS N VSS N VSS N VSS N VSS N VSS L VSS M VSS W VSS W VSS W VSS W VSS W VSS W VSS Y VSS0 Y VSS Y VSS Y VSS M

9 F strapping information: F[]: PIE Static Numbering Lane Reversal- F[] is for the x - : (efault) Normal Operation, Lane # definition matches sockect pin map definition - 0: Lane Numbers Reversed F[]: Embedded isplayport etection - : (efault) isabled ; No Physical isplay Port attached to Embedded isplayport - 0: Enabled ; n external isplay Port device is connected to the Embedded isplay Port F[:]: PI Express Port ifurcation Straps - : (efault) x - 0 : x, x - 0 : Reserved - 00 : x, x, x F[]: PE EFER TRININ - : (efault) PE Train immediately following xxreset de assertion - 0: PE Wait for IOS training F F F F F R00 R00 R00 % KOhm % KOhm % KOhm Joyoung R.0 T0 T00 T0 T00 T0 T00 T0 T0 T00 T00 T00 T00 T00 T00 T00 T00 T0 T0 T0 T0 R. 0/0 F0 F F F F F F F F F F0 F F F F F F F V_VL_SENSE VSS_VL_SENSE VX_VL_SENSE VSSX_VL_SENSE V_IE_SENSE hief River R_WR_VREF0 R_WR_VREF0 PROESSOR RIVEN Vref PTH WS STUFFE Y EFULT: For ifim testing R0~ R0 close to pin < inch R. 0 R00 +VFX_ORE +VORE R_WR_VREF0 Q00 UMKN IMM0_VREF_Q VX_VL_SENSE V_VL_SENSE R0 0 % VSSX_VL_SENSE,,0 RMRST_NTRL_PH R00 R0.Ohm % R0.Ohm % R_WR_VREF0 IMM_VREF_Q R0 % KOhm R00 R00 % KOhm % /ep KOhm T0 T0 T0 0 H H K K F L F L H K H K F H K V T Y Y U U E E F E U00E F[0] F[] F[] F[] F[] F[] F[] F[] F[] F[] F[0] F[] F[] F[] F[] F[] F[] F[] V_VL_SENSE VSS_VL_SENSE VX_VL_SENSE VSSX_VL_SENSE V_IE_SENSE RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV0 RSV RSV RSV RSV RSV0 RSV RSV RSV RESERVE RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 _TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_E _TEST_E _TEST TEST TEST TEST TEST TEST_E _TEST TEST_E _TEST_ E N L L L M M U W P T K H M M N0 E E E E ES 0V R00 R0.Ohm % R0.Ohm % % KOhm R0 0 % VSS_VL_SENSE Q00 UMKN -HW R iv.-n R ept. PU()_RSV Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

10 PU XP connector heck onnector PH XP connector -HW R iv.-n R ept. PU_PH_XP Joyoung_hianhg ustom M0 ate: Monday, February, 0 Sheet 0 of.0

11 +VORE hief River ecoupling guide from Intel P R0. +VORE.uF * pcs uf * pcs vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V 0.UF/.V vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small vx_c00_small.uf/.v.uf/.v.uf/.v.uf/.v.uf/.v.uf/.v vx_c00_small vx_c00_small vx_c00_small hief River +VORE.uF * pcs uf * pcs (power request) UF/.V UF/.V UF/.V UF/.V 0 UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V 0 UF/.V UF/.V UF/.V -HW R iv.-n R ept. PU EOUPLIN Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

12 F_VREF_0_M F_VREF_Q0_M M IM0_LK_R#0 M IM0_LK_R0 M RS# M S# M WE# M S M S M S0 M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M QS M RS# M S# M WE# M S M S M S0 M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M QS M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M QS M RS# M S# M WE# M S M S M S0 M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M QS M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M QS M RS# M S# M WE# M S M S M S0 M RS# M S# M WE# M S M S M S0 M IM0_OT0 M 0 R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M M RS# M S# M WE# M S M S M S0 M RS# M S# M WE# M S M S M S0 M IM0_OT0 M 0 M QS# R_RMRST# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_S#0 F_VREF_0_M F_VREF_Q0_M M M M M M 0 M M M M M M M M M M QS M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M M M S0 M S M IM0_OT0 M IM0_S#0 M RS# M S# M WE# M IM0_KE0 M M M M M M M 0 M 0 M M M M M M M S F_VREF_0_M F_VREF_Q0_M M M QS# M QS M M 0 M IM0_KE0 M IM0_LK_R0 M Q M QS#0 M Q M M WE# M S M M M IM0_LK_R#0 M M M Q M Q0 M S M M IM0_S#0 M Q M M S# M 0 M M M S0 M M M RS# M Q M M IM0_OT0 M QS0 M R_RMRST# M Q M Q +0.VS,, +.V,,,,0, M [:0] M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M RS# M WE# M S# M IM0_S#0 M IM0_OT0 R_RMRST#, M QS#[:0] M QS[:0] M Q[:0] M S[:0] +V_VREF_Q_IMM0, +V_VREF IMM0, +0.VS +.V +.V +.V +.V N +0.VS +.V F_VREF_Q0_M F_VREF_0_M +0.VS +.V +.V +.V +.V +.V +.V ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. R()_SO-IMM0.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. R()_SO-IMM0.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 -HW R iv.-n R ept. R()_SO-IMM0.0 M0 Joyoung_hianhg Memory own H Layout Note: Place these caps near SO IMM 0 Layout Note: Place these caps near SOIMM 0 place close to balls 0 Near Memory ontroller Follow design guide 0 /.. Place each cap close to each VrefQ or Vref ram all R. /0 RN0 Ohm RN0 Ohm 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm R 0V0000 0OHM R 0V0000 0OHM R0 R0 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/V 0.UF/V RN0 Ohm RN0 Ohm U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# R0 R0 R0 R0 RN0 Ohm RN0 Ohm 0 0.UF/0V 0 0.UF/0V RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0 0.UF/0V 0 0.UF/0V 0 UF/.V 0 UF/.V U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm V PF/V V PF/V RN0 Ohm RN0 Ohm UF/.V UF/.V RN0 Ohm RN0 Ohm R 0V0000 0OHM R 0V0000 0OHM 0 0.UF/0V 0 0.UF/0V R0 R0 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm R0 R0 RN0 Ohm RN0 Ohm R0 R0 0UF/.V 0UF/.V RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V R0 R0 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V RN0 Ohm RN0 Ohm U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm R0 R0 RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0 0.UF/0V 0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V 0 0UF/.V 0 0UF/.V U0 0V00000 EJ0SE-J-F U0 0V00000 EJ0SE-J-F Q0 Q QS Q Q Q QS# VREFQ E Q E Q E Q E RS# F K F OT S# K# KE VREF J VSS VSS VSS VSS VSS F VSS F VSS J VSS J VSS L VSS0 L VSS N VSS N V V V V V V K V K V M V M N N F N F N H N H J N S# H WE# H RESET# N ZQ H 0 K L L K L L M M N M 0/P H M /# K N 0 J K J VSSQ VSSQ VSSQ VSSQ VSSQ VQ VQ VQ E VQ E M/TQS NU/TQS# RN0 Ohm RN0 Ohm RN0 Ohm RN0 Ohm 0.UF/0V 0.UF/0V 0UF/.V 0UF/.V RN0 Ohm RN0 Ohm

13 +.V +.V,,,,0, +.V +.V Layout Note: Place these caps near SO IMM +0.VS +0.VS +0.VS,, + E0 +VS +V_VREF IMM +VS 0,,,,,,,,,0,,,,,,,,0,,,,,,0,, +V_VREF IMM, 0UF/V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0UF/.V 0UF/.V UF/.V UF/.V UF/.V 0 UF/.V +V_VREF_Q_IMM +V_VREF_Q_IMM, M [:0] M Q[:0] +.V +.V M IM0_LK_R0 M IM0_LK_R#0 M IM0_LK_R M IM0_LK_R# 0 0PF/0V 0PF/0V PLE LOSE TO SOIMM J0 M 0 M 0 M M M M M 0 M M M M 0 0 M 0/P M M /# M 0 M M IM0_LK_R 0 K M IM0_LK_R# 0 K# M IM0_LK_R0 0 K0 M IM0_LK_R#0 0 K0# M IM0_S# R0 S# M IM0_S#0 S0# M IM0_OT 0 OT M IM0_OT0 OT0 M WE# WE# M RS# 0 RS# M S# R0 S# M S M S 0 M S0 0 0 M IM0_KE KE M IM0_KE0 KE0 +VS R0 0KOhm 0 SMus Slave ddress: H SP0 S S0 take care if can't boot or S issue M QS M QS[:0] M QS# QS M QS#[:0] M QS QS# M QS# QS M QS QS# M QS# QS M QS QS# M QS# QS M QS QS# M QS# QS M QS QS# M QS# QS M QS QS# M QS# QS M QS0 QS# M QS#0 QS0 0 QS#0 M 0 M M M should connect to N directly M esign uide.0 P. () M M M M0 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q 0~ ~ ~ ~ ~ 0~ ~ ~ Layout Note: Place these caps near SO IMM Reserve 0 0.UF/V T0 +V_VREF IMM +V_VREF_Q_IMM PM_EXTTS#0_IM_.UF/.V.UF/.V 0 0.UF/V 0.UF/V 0.UF/V J0 V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS EVENT# TEST N N VREF VREFQ V V V V V0 V V V V VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS0 VSS N N NP_N NP_N VTT VTT VSP 0 0.UF/V +0.VS 0.UF/V Frank 00 VREF and VREFQ need to separate It follow EVEREST and Intel spec. 0 0.UF/V +VS.UF/.V,, SM_LK_S,, SM_T_S SP0 SP0 R00 SM_LK_S_H R00 SM_T_S_H 0 00 SL S RESET# 0 R_RMRST#, R_IMM_0P V0RM000 R_IMM_0P V0RM000 H:.mm PETRON OMPUTER IN R()_SO-IMM Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

14 R Vref +.V +V_VREF IMM0 +V_VREF_Q_IMM0 +.V,,,,0, +V_VREF IMM0, +V_VREF_Q_IMM0, M: Fixed SO-IMM VREF_Q +.V +V_VREF_R +V_VREF IMM0 R KOhm +V_VREF IMM +V +VSUS +V,,,,, +VSUS,,, +V +V,0,, 0 0.UF/V R KOhm R For R_VREF command & address. +.V efault M +V_VREF_Q_IMM0 R KOhm +V_VREF_Q_IMM R.0 R KOhm 0 0.UF/V IMM0_VREF_Q R0 IMM_VREF_Q M R0 M: Processor enerated SO-IMM VREFQ New Requirement If support M :. Mount R0,R0,R0,R0,R0,R,0. Un mount R0,R0 -HW R iv.-n R ept. R()_/Q Voltage Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

15 R.-- PETRON OMPUTER IN VI ontroller Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

16 RT battery,0 T00 +RTT +RTT +V PR. R00 KOhm +V_RT 00 +RT_T V/0. 00 UF/0V +V_RT +V +VS +VSUS_OR +V_RT, R.0 elete +RTT +V,,,0,,,,0,,, +VS,,,,,,,,,0,,,,,,,,0,,,,,,0,, +VSUS_OR,,,,,, +.0VM_OR +.0VM_OR N +VTT_PH_VIO +VTT_PH_VIO, +V_RT RTRST# R delay should be ms~ms R00 % 0KOhm 00 UF/0V JRST00 SL_JUMP Request by S for MOS clear function MOS Settings lear MOS Keep MOS JRST00 Shunt Open (efault) N N 00 PF/0V RT_X_ X00.KHZ SP00 R00 0MOhm U00 R00 R00 MOhm % 0KOhm N N TPM Settings 00 UF/0V lear ME RT Registers Keep ME RT Registers Intel. esign uide, page 0 N N JRST00 Shunt JRST00 SL_JUMP Open (efault) INTVRMEN: Integrated SUS.0V VRM Enables Low: Enable External VRs High:Enable Internal VRs PH_INTVRMEN R00 % 00KOhm N T0 00 N T0 T0 +V_RT 00 Frank add 00 for EMI request, Z_LK_U Z_SYN_U S_SPKR Z_RST#_U Z_SIN0_U Z_SOUT_U N R. 0/ IO PF/0V T0 T0 0KOhm % R00 00 PF/0V T00 T00 T00 SP00 SP00 SP00 SP0 RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INTVRMEN Z_LK Z_SYN Z_RST# Remove TP Z_SIN_U Z_SIN_U Z_SOUT R00 near R00 H_OK_EN# RREER_RESET PH_JT_TK_UF K N L T0 K E N J RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# H_SIN0 H_SIN H_SIN H_SIN H_SO RT IH H_OK_EN#/PIO H_OK_RST#/PIO JT_TK ST LP ST FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP STRXN STRXP STTXN STTXP E SNN_PH_RQ#0 K SNN_LP_RQ# V Serial Interrupt Request M M P P M0 M P P0 H H 0 F F Y Y R.0 Y Y T0 T0 R.0 LP_0 0,, LP_ 0,, LP_ 0,, LP_ 0,, LP_FRME# 0,, INT_SERIRQ 0,, ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP ST_RXN ST_RXP ST_TXN ST_TXP H H O mst isolate schematic for Z _SYN and SOUT follow EIH T00 T00 T00 PH_JT_TMS PH_JT_TI PH_JT_TO H K H JT_TMS JT_TI JT_TO JT STIOMPO STIOMPI STROMPO Y Y0 ST_OMP R00 %.Ohm +VTT_PH_VIO STOMPI ST_OMP R0 %.Ohm +VTT_PH_VIO SPI_LK T SPI_LK STRIS H RIS_ST R0 % N SPI_S#0 SPI_S# SPI_SI SPI_S# Y T V SPI_S0# SPI_S# SPI_MOSI SPI STLE# ST0P/PIO P V ST0P R0 0KOhm ST_LE# T0 +VS SPI_SO U SPI_MISO STP/PIO P S_IT0 OUR_POINT_ES 0V R. /0 R.0 For JT to pull high and low. Remove JT schematic Strap information: Pull High +VS S_SPKR: No reboot strap Low: isable (efault) High:Enable S_SPKR R00 KOhm +VS INT_SERIRQ R0 0KOhm Z_SOUT:.Flash descriptor security: Sampled Low: in effect. Sampled High: override Z_SOUT R0 KOhm +VSUS_OR ST0P R0 0KOhm.Z_SOUTwhich sample high on the rising edge of PWROK Will also disable Intel ME. Z_SYN: On ie PLL VR voltage selector Low:.V (efault) High:.V note : R has no strap Hrron River Platform Schematic esign hecklist (0 page ) Z_SYN R0 KOhm VVRM use +.VS in mobile +VSUS_OR PETRON OMPUTER IN PH()_ST,IH,RT,LP Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of 0.0

17 Frank 0_dd US.0 and ard Reader PIE and LKRQ Frank 0_dd PIE and LKRQ in Port. +VS +VTT_PH_OR +VSUS_OR +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, +VTT_PH_OR,, +VSUS_OR 0,,,,,, Joyoung R.0 PIE_RXN_R PIE_RXP_R PIE_TXN_R PIE_TXP_R PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RXN_mST PIE_RXP_mST PIE_TXN_mST PIE_TXP_mST UF/V 0.UF/V 0.UF/V 0.UF/V PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_WLN_ PIE_TXP_WLN_ J V U E F Y J V U U00 PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp SMUS SMLERT#/PIO SMLK SMT SML0LERT#/PIO0 SML0LK SML0T E H EXT_SI# SL_ S_ RMRST_NTRL_PH_R R SML0_LK SML0_T R.0 / /NON_S EXT_SI# 0, SL_ S_ RMRST_NTRL_PH,,0 T T LK_UF_PYLK_N LK_UF_PYLK_P RN0 0KOhm RN0 0KOhm LK_UF_EXP_N LK_UF_EXP_P RN0 0KOhm LK_UF_OT_N RN0 LK_UF_OT_P 0KOhm RN0 0KOhm LK_UF_KSS_N RN0 0KOhm LK_UF_KSS_P RN 0KOhm RN 0KOhm LK_UF_REF R 0KOhm LOK TERMINTION for FIM efault power-on mode is I. N PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN R. remove /nimt remark LK_PIE_R# LK_PIE_R 0 T0 T0 T0 T0 T0 T0 T0 T0 SP SP 0.UF/V 0.UF/V LK_REQ0# PIE_TXN_LN_ PIE_TXP_LN_ PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_US0_ PIE_TXP_US0_ F E Y H Y J U V 0 J0 Y0 0 E W Y Y0 Y J PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp PERn PERp PETn PETp LKOUT_PIE0N LKOUT_PIE0P PI-E* 00MHz PIELKRQ0#/PIO LKOUT_PIEN 00MHz LKOUT_PIEP LOKS ontroller SMLLERT#/PHHOT#/PIO SMLLK/PIO SMLT/PIO L_LK Link L_T L_RST# PE LKRQ#/PIO 00MHz LKOUT_PE N LKOUT_PE P 00MHz LKOUT_MI_N LKOUT_MI_P E M M T P0 M0 V U SMLLERT# SML_LK SML_T LK_REQ_PE_# LK_PIE_PE#_PH_L LK_PIE_PE_PH_L R0 R0 N_R00_0MIL_SMLL N_R00_0MIL_SMLL R.0 SML_LK SML_T LKREQ_PE# 0 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 LK_EXP_N LK_EXP_P To E R.0 /0 R.0 / R. S RM reset TRL +VSUS_OR EXT_SI# R 0KOhm SL_ RN0.KOhm S_ RN0.KOhm RMRST_NTRL_PH_R R0 0KOhm SML0_LK RN0.KOhm SML0_T RN0.KOhm SML_LK RN0.KOhm SML_T RN0.KOhm SMLLERT# R 0KOhm **UNSTUFF** LK_PIE_mST#_PH LK_PIE_mST_PH LK_PIE_WLN#_PH LK_PIE_WLN_PH LK_REQ_mST# LK_REQ_R# LK_REQ_WLN# LK_PIE_LN# LK_PIE_LN LK_REQ_LN# SP0 SP0 SP0 SP0 SP SP R0 /NON_mST SP0 SP0 SP0 T T LK_REQ# LK_REQ# LK_REQ# LK_PH_SR_N LK_PH_SR_P LK_REQ# LK_PH_SR_N LK_PH_SR_P LK_REQ_PE_# T T T LK_PH_SR_N LK_PH_SR_P LK_PH_SR_N LK_PH_SR_P LK_REQ# LK_PH_SR_N LK_PH_SR_P LK_REQ# M V0 Y Y Y Y L V V L 0 E V0 V T PIELKRQ#/PIO 0MHz LKOUT_P_N LKOUT_P_P LKOUT_PIEN 00MHz LKOUT_PIEP 00MHz LKIN_MI_N PIELKRQ#/PIO0 LKIN_MI_P LKOUT_PIEN 00MHz LKIN_N_N LKOUT_PIEP LKIN_N_P PIELKRQ#/PIO OUR_POINT_ES MHz LKIN_OT_N LKIN_OT_P LKOUT_PIEN 00MHz LKOUT_PIEP 00MHz LKIN_ST_N PIELKRQ#/PIO LKIN_ST_P.MHz LKOUT_PIEN 00MHz REFLKIN LKOUT_PIEP MHz PIELKRQ#/PIO LKIN_PILOOPK LKOUT_PE N 00MHz XTL_IN LKOUT_PE P XTL_OUT PE LKRQ#/PIO XLK_ROMP LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO M M F E J0 0 E K K K H V V Y LK_P_N LK_P_P LK_UF_EXP_N LK_UF_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P LK_UF_OT_N LK_UF_OT_P LK_UF_KSS_N LK_UF_KSS_P LK_UF_REF XTL_IN XTL_OUT XLK_OMP R0 0.Ohm LK_P_N LK_P_P LK_PI_F +VIFFLKN MOhm R Joyoung R.0 modify LK_REQ -MHz is required in:. FIM. TM for PH isplay lock gereration in Integrated raphics platforms SP 0 0PF/0V X0 MHZ 0 XTL_OUT_ 0PF/0V N N N PH LKREQ Setting: Not connected to device. R.0 0 +VSUS_OR LK_REQ0# R0 0KOhm **UNSTUFF** LK_REQ# R 0KOhm **UNSTUFF** LK_REQ# RN0 0KOhm LK_REQ_PE_# RN0 0KOhm LK_REQ# R 0KOhm **UNSTUFF** onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. +VS Eric Fang to lan hien on //00 LK_REQ# Remove XP. V V K K K LKOUT_PIEN 00MHz LKOUT_PIEP PIELKRQ#/PIO LKOUT_ITPXP_N 00MHz LKOUT_ITPXP_P 0V FLEX LOKS LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO K F H K R.0 / SYSRM00 SYSRM0 SYSRM0 SYSRM0 R.0 Modify RM Strap PIN +VS +VS +VS +VS LK_REQ# LK_REQ# LK_REQ# LK_REQ# R R R R 0KOhm 0KOhm +VSUS_OR 0KOhm 0KOhm LK_REQ_PE_# R0 0KOhm Joyoung R.0 add PIO Table for on board RM Strap. On oard RM Setting PIO PIO PIO PIO XXXX On oard RM Setting No on board RM Micron MHz Elpida MHz Elpida MHz 00 Micron MHz T ommon efinition MHz ommon efinition 00MHz R 0KOhm R 0KOhm R R R 0KOhm 0KOhm 0KOhm / /ELPI /MIRON R R R 0KOhm 0KOhm 0KOhm / /MIRON /ELPI N N N N SYSRM00 SYSRM0 SYSRM0 SYSRM0 LK_REQ_PE_# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm LK_REQ# R 0KOhm N PH()_PIE,LK,SM,PE PETRON OMPUTER IN Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

18 +VSUS_OR +VSUS_OR 0,,,,,, +VS +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, U00 +VTT_PH_OR +V +VTT_PH_OR, +V,0,,,0,,,,0,,, MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP E0 0 E 0 J J0 W W0 V Y Y0 Y U MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI FI FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT J Y E H J 0 F E J0 H W FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT +V_RT +VSUS +VSUS +VSUS +V_RT 0, +VSUS,,,0,0,, +VSUS,,, +VSUS,,, J MI_ZOMP FI_FSYN0 V FI_FSYN0 +VTT_PH_OR R0 %.Ohm MI_OMP_R MI_IROMP FI_FSYN 0 FI_FSYN N R0 % RIS_PY H MIRIS FI_LSYN0 V FI_LSYN0 FI_LSYN 0 FI_LSYN Remove SUSK#. R.0 dd XP_RESET# dd ME_PWROK.,0, PM_RSMRST# has pull down 0k ohm in E PM_PWROK SYS_PWROK PM_SYSRST#_R R0 0 ME_PWROK R PM_PWROK_R L0 N PWROK SUSLK/PIO SUSLK 0 0 PM_RM_PWR 0 PM_RSMRST# ME_SUSPWRNK R.0 0 PM_PWRTN# dd PM_PWRTN#_R 0 0 SUSK# +VS ME PRESENT T0 T0 R SUS_PWR_K_R /NON_S R0.V/0. 0 R. S 0/ R R R /S R 0KOhm R. S 0/ R. S 0/ R. S 0/ _PRESENT_R TLOW# RI# SUSK#_R PM_RSMRST_R SUS_PWR_K_R K P L K E0 H0 E0 0 SUSK# SYS_RESET# SYS_PWROK PWROK RMPWROK RSMRST# System Power Management SUSWRN#/SUSPWRNK/PIO0 PWRTN# PRESENT/PIO TLOW#/PIO RI# SWVRMEN PWROK WKE# LKRUN#/PIO SUS_STT#/PIO SLP_S#/PIO SLP_S# SLP_S# SLP_# SLP_SUS# PMSYNH SLP_LN#/PIO E N 0 H F 0 P K SWOVREN PH_PROK PIE_WKE# PM_SUS_STT# SLP_S# SLP_SW#_R R 00KOhm % R 00KOhm % R. S 0/ R R R R N +V_RT SWOVREN - On ie SW VR Enable HIH - Enabled(EFULT) ; LOW-isabled /NON_S PM_RSMRST_R E_RST# 0, /S R. IO, 0/ LN_WKE# 0, T0 T0 PM_LKRUN# 0, PM_SUS# 0 PM_SUS# 0 R.0 ME_PM_SLP_M# 0 SLP_SUS# 0, H_PM_SYN R.0 ME_PM_SLP_LN# 0 R.0 0V OUR_POINT_ES SYS_PWROK for PH R. Remove some SP in P +VSUS PM_PWROK U0 V ELY_VR_N_LL_SYS N Y Vcc=~. SYS_PWROK +VSUS_OR RI# R 0KOhm R.0 TLOW# PIE_WKE# R 0KOhm R KOhm R.0 +VS PM_LKRUN# R0 0KOhm ME_PM_SLP_M# R 0KOhm PM_PWROK R 0KOhm ME_SUSPWRNK R 0KOhm N R. /0 ME PRESENT R 0KOhm ME_PM_SLP_LN# R 0KOhm PETRON OMPUTER IN PH()_FI,MI,SYS PWR Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

19 +VS +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, +VS L_KEN_PH L_VEN_PH SP0 SP0 J M U00 L_KLTEN L_V_EN SVO_TVLKINN SVO_TVLKINP P P L_TRL_LK.KOhm RN0 L_TRL_T.KOhm RN0 EI_LK_PH.KOhm RN0 EI_T_PH.KOhm RN0 Pull up.k ohm in bus for LVS. Remove LVS net name and add port. L_KLT_TRL EI_LK_PH EI_T_PH R.0 N R0 R0 LVS_LLKN_PH LVS_LLKP_PH LVS_L0N_PH LVS_LN_PH LVS_LN_PH LVS_L0P_PH LVS_LP_PH LVS_LP_PH SP0.KOhm L_TRL_LK L_TRL_T LV_I LV_V LV_VREF P T0 K T P F F E E K K0 N M K J N M K J F0 F H H F F H H F F L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_I LV_V LV_VREFH LV_VREFL LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS_LK# LVS_LK LVS_T#0 LVS_T# LVS_T# LVS_T# LVS_T0 LVS_T LVS_T LVS_T LVS igital isplay Interface SVO_STLLN SVO_STLLP SVO_INTN SVO_INTP SVO_TRLLK SVO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M0 P P0 P M T T T0 V V0 V V U U V V P P P P T Y Y Y Y isplay Port isplay Port SVO N N R0 0.% KOhm N P T T M0 M M T T RT_LUE RT_REEN RT_RE RT LK RT T RT_HSYN RT_VSYN _IREF RT_IRTN RT P_TRLLK P_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P M M T T H F E F E J HMI LK_PH HMI T_PH HMI_HP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN0_PH HMI_TXP0_PH HMI_LKN_PH HMI_LKP_PH isplay Port OUR_POINT_ES 0V RT isable: (For discrete graphic). N: RT_RE,RT_REEN,RT_LUE RT_HSYN,RT_VSYN. -kω ±0.% pull-down to N: _IREF. onnected to N: RT_ITRN. onnect to +V.: V isplay Port isable: (For discrete graphic). N: LL LVS isable: (For discrete graphic). N: LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK#, LVS_T [:0], LVS_T# [:0], LVS_LK, LVS_LK# L_V_EN, L_KLTEN, L_KLTTL, LV_VREFH LV_VREFL, LV_I, LV_V. onnected to N: VccLVS,VccTX_LVS PETRON OMPUTER IN PH()_P,LVS,RT Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

20 +VS +VSUS +VS +VSUS,,,0,0,, +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, V_PWRON R +VSUS Frank SP0 is removed in EIH. ST_O_# has short pin in EIH. **UNSTUFF** R. add Zero Power O **UNSTUFF** **UNSTUFF** R +VS R R R R U0 V Y N SNLV0KR N PU_HOL_RST# PU_PWR_EN PU_PWR_EN is active high 0KOhm 0KOhm 0KOhm 0KOhm R0 0KOhm R SUS_E# 0,,, MP_PWR_TRL# ST_O_# EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH PU_PWR_EN PU_PWR_EN US_RX_N US_RX_N US_RX_N US_RX_P US_RX_P US_RX_P US_TX_N US_TX_N US_TX_N US_TX_P US_TX_P US_TX_P ST_O_# SP0 SP0 +VS R00 T0 R00 PU_PWR_EN_R N T0 R.0 00 T0 R0 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 KOhm INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PU_HOL_RST#_R PU_SELET# S_IT PU_PWM_SELET# STP_OVR MP_PWR_TRL# ST_O_# EXTTS_SNI_RV0_PH EXTTS_SNI_RV_PH PI_PME# J H J H H K K N0 H H M M Y K L M0 Y 0 E 0 E J 0 E0 F 0 V U Y0 0 U Y V W0 K0 K H E0 E F 0 K0 U00E TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP RSV US0 port RXN TP US0 port RXN TP US0 port RXN TP US0 port RXN TP US0 port RXP TP US0 port RXP TP0 US0 port RXP TP US0 port RXP TP US0 port TXN TP US0 port TXN TP US0 port TXN TP US0 port TXN TP US0 port TXP TP US0 port TXP TP US0 port TXP TP US0 port TXP TP0 PIRQ# PIRQ# PIRQ# PIRQ# REQ#/PIO0 REQ#/PIO REQ#/PIO NT#/PIO NT#/PIO NT#/PIO PI OUR_POINT_ES PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PME# US RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS Y V U T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 0 E0 0 0 L K E NV_ROMP US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_IS +V +VSUS_OR +VS +.VS PLT_RST# R T T +V,,,, +VSUS_OR 0,,,,,, +VS,,, +.VS,,,,0, PLT_RST# N N US_PN0 US_PP0 US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN US_PP US_PN0 US_PP0 US_PN US_PP : R=. ohm for E. R T T T0 T % %.Ohm.Ohm US PORT US P00 US P0 US P0 US P0 US P0 US P0 US P0 US P0 US P0 US P US P US P +VSUS_OR Mini PIE (mst) External.0/.0 External Main External Main T ebug Port amera WiFi 0 LK_TPM LK_PI_F LK_KPI_PH LK_EU PLT_RST# :R0=00ohm for E. Ohm Ohm Ohm Ohm T0 R R0 R0 R LK_TPM_R LK_PI_F_R LK_KPI_PH_R LK_EU_R LK R H H J K H0 PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI MHz O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO K0 L O0#/PIO O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO O#/PIO0 O#/PIO 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 Remove O# to XP. 0 0PF/0V N N 0 0PF/0V Reserved for Wireless team 0V R R /HRUS0 Place within 00 mils of PH R /RUS0 US_O# R. add O# pin for add US port US_O# R US_O0# S_IT0,S_IT : oot IOS Strap oot IOS Strap S_IT S_IT0 0 0 oot IOS Location LP STP_OVR: swap override Strap/ Top-lock swap override jumper Low=Enabled swap override/ Top-lock swap override **UNSTUFF** **UNSTUFF** PU_PWM_SELET# PU_SELET# PU_HOL_RST#_R PU_PWR_EN_R R0 0KOhm R 0KOhm R 0KOhm R KOhm +VS U0 V +V This Signal has a weak internal pull-up. 0 S_IT0 S_IT0 0 0 Reserved (NN) Reserved SPI (PH) Sampled on rising edge of PWROK. R KOhm High=efault STP_OVR R KOhm PLT_RST# N Y Vcc=~. 0V N R R 0KOhm UF_PLT_RST#,0,,,,,0 S_IT R.0 dd S_IT signal. R KOhm N N N PETRON OMPUTER IN PH()_PI,NVRM,US Joyoung_hianhg M0 Monday, February, 0 ate: Sheet of.0

21 +VS +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, +VSUS +VSUS,,,,0,0,, +VSUS_OR +VSUS_OR 0,,,,,, +VS +VS R.0 Remove RIT_PH_PIO0_R to XP T0 PIO0 PIO PU_HP_INTR# PIO T H E U00F MUSY#/PIO0 TH/PIO TH/PIO TH/PIO TH/PIO TH/PIO TH/PIO0 TH/PIO 0 0 ST_O_PWRT T0 T0 T0 R. add Zero Power O ST_O_PWRT **UNSTUFF** **UNSTUFF** **UNSTUFF** R.0 / R 0KOhm R 0KOhm /S dd PM_LNPHY_EN dd HOST_LERT#_R. LN_LPWR 0, EXT_SMI# SP0 SP0 R00 US0_EXT_SMI# PM_LNPHY_EN HOST_LERT#_R PU_PRSNT# 0 U PIO LN_PHY_PWR_TRL/PIO PIO STP/PIO 0TE PEI RIN# P U P R. /0 Frank 000 H_THRMTRIP# is not connected pull up resister but EIH does not. H_PEI_R R Ohm R 0TE 0 H_PEI H_PEI_E 0 RIN# 0 N R 0KOhm N R 0KOhm /NON_S P_I0 P_I PU_PWROK has 00 ms software delay, no hardware delay requirement Reserve PH_PIO dd ST_O_PRSNT#_R and FI_OVRVLT., PU_PWROK T PU_PWROK O_ON R.0 00 R. hange WLN_ON to WLN_ON_PH 0, RF_ON R Frank 0 EE define PIO for ROOM LN chip. T0 ST_O_PRSNT#_R R. add Zero Power O ST_PWR_EN#_R R.0 / O_ON WLN_LE PIO WLN_ON_R STP_PI# ST_O_PRSNT#_R FI_OVRVLT P_I0 P_I 0 T E E P K K V M N M TH0/PIO SLOK/PIO PIO/MEM_LE PIO PIO STP_PI#/PIO PIO STP/PIO STP/PIO SLO/PIO STOUT0/PIO PIO PU/MIS PROPWR THRMTRIP# INIT_V# F_TVS TS_VSS TS_VSS TS_VSS TS_VSS N_ Y Y0 T Y H K H0 K0 P PM_THRMTRIP# INIT_V# NV_LE N % R T0 R0 KOhm TS Signal isable uideline TS_VSS[:] should pull down to N esign uide 0. () R0.KOhm +.VS H_PUPWR H_THRMTRIP#, R.0 H_SN_IV# 0,, T_ON T_ON R V STOUT/PIO Vss_NTF **UNSTUFF** **UNSTUFF** **UNSTUFF** EXT_SMI# US0_EXT_SMI# PM_LNPHY_EN O_ON Joyoung R.0 mount if suppot O RIN# has pull high at E side PU_HP_INTR# PU_PWROK R R R R R R KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm +VSUS_OR +VS dd RIT_TEMP_REP#_R. R.0 Intel omments Joyoung R.0 Joyoung R. remove /nimt remark R.0 R. S 0/ T PH_LERT# T T_LE Frank R NO T module, but the PIO control pin will conntact to page. It supports combo card. Frank 00 No WLN LE,so PIO pin change test point Frank 00 RIT_TEMP_REP#_R change net name RIT_TEMP_REP# and contact to E(follow I0) Frank 0 Remove ST_ET#_R to XP Frank 0 Remove PLL_OVR_EN and ST_PWR_EN#_R to XP Frank 0 Remove FI_OVRVLT to XP Frank 0 Remove RIT_TEMP_REP#_R to XP V E E F F STP/PIO PIO Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF Vss_NTF0 Vss_NTF Vss_NTF H H J J J J J J E E F F Unused PIO OUR_POINT_ES 0V PIO0 R 0KOhm **UNSTUFF** PIO R 0KOhm **UNSTUFF** **UNSTUFF** STP_PI# WLN_LE PIO #0 hecklist PU_PWROK R R R R0 0KOhm 0KOhm 0KOhm 0KOhm N N +VS +VS R % KOhm FI_OVRVLT R FI TERMINTION VOLTE OVERRIE - PIO (FI_OVRVLT) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT R0 00KOhm ST_O_PRSNT#_R MI TERMINTION VOLTE OVERRIE - PIO (ST_O_PRSNT#) LOW - TX, RX terminated to same voltage ( ouplong Mode) EFULT 00KOhm R0 0KOhm N N Joyoung R.0 +VS R. add Zero Power O PU_PRSNT# PU_PRSNT# R /UM 0KOhm R 0KOhm WLN_ON_R R KOhm PLL ON IE VR ENLE NHIH - ISLE (EFULT) LOW - ENLE N Joyoung R.0 for IOS detect Panel +VS PIO PIO R R /LVS /ep 0KOhm 0KOhm PETRON OMPUTER IN PH()_PU,PIO,MIS Joyoung_hianhg N M0 Monday, February, 0 ate: Sheet of.0

22 +.0VS,,, +VTT_PH_VIO 0, +VTT_PH_OR, +.VS,,,0, +.VS,,, +VS,0,,,,,,,,0,,,,,,,,0,,,,,,0,, +VP,,,,0,,, +VFI_VRM +VS_V_ +VM_SPI +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO N +VTT_PH_VIO N +VS_V N +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR N +VFI_VRM +.VS +VS_V_IO N +VM_VPSPI N N N +VIO_PU_V_MI N N N N +.0VS +VTT_PH_OR +VFI_VRM +V +V_NVRM_VPNN +.VS +.0VS +VTT_PH_VIO +VTT_PH_OR +.VS +.VS +VS N N +VFI_VRM N +VTT_PH_OR +VIO_PU_V_MI +VTT_PH_OR +VP +VS_V_ +VS_V_ +VS_V_ +VM_SPI +VFI_VRM +VTT_PH_OR_VLKMI N N N +.VS +V N N +VS N +.VS_VTX_LV +VS_V_LV +VTT_PH_V +VTT_PH_VIO N N N +VS +VSUS_OR ate: Sheet of Monday, February, 0 PETRON OMPUTER IN PH()_POWER,N.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 PETRON OMPUTER IN PH()_POWER,N.0 M0 Joyoung_hianhg ate: Sheet of Monday, February, 0 PETRON OMPUTER IN PH()_POWER,N.0 M0 Joyoung_hianhg m +VTT_PH_VPLL_EXP.=0m+.+. +VTT_PH_V_EXP 0m VVRM use +.VS in mobile H_SYN should pull high to +VSUS m R. R.0 elete +VTT_PH_V +VTT_PH_VPLL_EXP +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_FI +VS_V +VS_V_IO +V +VS_V_LVS +VM_VPSPI +V_NVRM_VPNN +.VS_VTX_LV +VIO_PU_V_MI +VTT_PH_OR_VLKMI R.0 R.0.. R.0 Intel omments R.0 Intel omments Frank 000 EVERST remove.vs and +VTT_PH_OR Frank 00 Follow Everest. 0m m/=.m./=m./*=. m/=.m m m/*pin=m./=m m/=.m 0m m/=.m 0m m/=.m R. /0 R. /0 R. /0 R.0 / SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL POWER V ORE MI VIO RT LVS FI FT / SPI HVMOS U00 OUR_POINT_ES 0V POWER V ORE MI VIO RT LVS FI FT / SPI HVMOS U00 OUR_POINT_ES 0V Vccore Vccore Vccore Vccore Vccore F Vccore F Vccore Vccore Vccore Vccore0 Vccore Vccore Vccore J Vccore J Vccore J VccFTERM J VccFTERM J VccIO N VccIO N VccIO N VccIO P VccIO0 P VccIO T VccIO N VccIO N VccIO P VccIO P Vcc U VccTX_LVS M VccTX_LVS M VccLVS K VccVRM T VccVRM P VccPLLEXP J VccFIPLL VccIO N VccTX_LVS P VccTX_LVS P Vss U VssLVS K VccIO P Vcc V Vcc V Vcc H VccFTERM VccFTERM VccMI T0 VccIO N VccIO N Vccore J Vccore J VccSPI V VcclkMI VccMI U0 0 0UF/0V 0 0UF/0V L0 kohm/00mhz L0 kohm/00mhz 0 UF/.V 0 UF/.V 0.0UF/V 0.0UF/V UF/.V UF/.V 0PF/0V 0PF/0V 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small 0.UF/V 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL R0 R0 0 UF/.V 0 UF/.V U00H OUR_POINT_ES 0V U00H OUR_POINT_ES 0V VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS F0 VSS F VSS VSS F VSS F VSS F VSS0 F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS F VSS0 F VSS VSS VSS VSS VSS H VSS H VSS H VSS H VSS H0 VSS0 H VSS H VSS H VSS J VSS J VSS J VSS K VSS K VSS0 K VSS K VSS K VSS K VSS K VSS L VSS L VSS L VSS L VSS L VSS0 L VSS L VSS L VSS L VSS L VSS M VSS M VSS M VSS00 M VSS0 M VSS0 M VSS0 M VSS0 N VSS0 N VSS0 N VSS0 N VSS0 P VSS0 P VSS P VSS P0 VSS P VSS P VSS P VSS P VSS P VSS R VSS0 R VSS T VSS T VSS T VSS T VSS T VSS T VSS T0 VSS T VSS T VSS T VSS T VSS U VSS U0 VSS V VSS V0 VSS V VSS V0 VSS0 V VSS V VSS V VSS V VSS W VSS W VSS W VSS W VSS W VSS W VSS0 W VSS W VSS W VSS W0 VSS W VSS V VSS Y VSS Y VSS Y VSS0 VSS E VSS VSS P VSS0 H VSS F VSS VSS VSS J VSS J VSS E VSS T VSS0 T VSS0 M VSS L VSS L L0 kohm/00mhz L0 kohm/00mhz R R 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0PF/0V 0PF/0V UF/.V UF/.V 0 UF/.V 0 UF/.V SR0 N_R00_0MIL_SMLL SR0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL 0 UF/.V 0 UF/.V 0 UF/.V 0 UF/.V SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL R R UF/.V UF/.V 0.0UF/V 0.0UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL R R SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V 0.UF/V 0.UF/V SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL 0.0UF/V 0.0UF/V SP0 N_R00_0MIL_SMLL SP0 N_R00_0MIL_SMLL 0 0UF/.V vx_c00_small 0 0UF/.V vx_c00_small L0 kohm/00mhz L0 kohm/00mhz