TWSL_N14P-GV2_S2G_0624_for ERD

Transcription

1 +V/+V S +.0V is-harge +VGORE +.0V_GFX/V_GFX PG. PG. PG. PU ore RL harge PG.~ PG. PG. PG. PG.0 +.V_GFX PG. K LNE TP K SOIMM Max. G PG. SOIMM Max. G H O PG. PI-E x ard Reader -GRT ROM PG. PG. PI-E x LNE LNE PG. FN TWS Shark ay IGRM R L hannel ST0 ST LN WLN US.0 RTLGS-G T OMO PORT0 GbE PG.0 ccelerometer PG. SMUS PG. ITE PG. mst PG. PG. PG. PG. PG. 00MT/s 00MT/s R L hannel ST0 G/s ST G/s ST G/s ST LP TPM SLTT. INTEL Haswell Processor : aul / Quad ore Power : / (Watt) Package : rpg Size :. x. (mm) FI Lynx Point PG.~ MI INTEL PH Power :. Watt Package : FG Size : 0 x 0 (mm) PG.~ UIO OE L-G PI-E x ep (.Gb/s) I (.Gb/s) RT US.0 PG. PORT US.0 P Port US.0 Ports X PG. US.0 Ports XPG. Speaker HP/MI nalog MI PG.~ R 00MHz VRM Mxx,bit ep PORT0 nvii NP-GS G FG0 mm X mm US harge SLG RE rof PORT, PG. PG. PG. PG.~0 RT S P to LVS onverter PGE RE rof PG. PORT Webcam RE rof PG. LVS Interface LVS HMI RT PG. PG. PG. 0 Stackup TOP GN IN IN V OT RE rof PROJET : TWS Quanta omputer Inc. RE rof Size ocument Number Rev ustom N LOK IGRM ate: Friday, ugust, 0 Sheet of

2 FI_SYN IN_# IN_# IN_0# IN_LK# IN_ IN_ IN_0 IN_LK FI_SYN & FI_INT Trace length < 0000 Mils Impendance = 0 ohm EP_ISP_UTIL EP_TXP0 EP_TXP EP_TXN0 EP_TXN Haswell Processor (MI,PEG,FI) EP_TXP0 EP_TXP U RE rof MI_TXN0 MI_RX#[0] MI_TXN MI_RX#[] MI_TXN MI_RX#[] MI_TXN MI_RX#[] 0 MI_TXP0 0 MI_RX[0] MI_TXP 0 MI_RX[] MI_TXP 0 MI_RX[] MI_TXP MI_RX[] MI_RXN0 MI_TX#[0] MI_RXN MI_TX#[] MI_RXN MI_TX#[] MI_RXN MI_TX#[] MI_RXP0 MI_TX[0] MI_RXP MI_TX[] MI_RXP MI_TX[] MI_RXP MI_TX[] P FI_TXN0 N FI_TX#[0] FI_TXN R FI_TX#[] FI_TXP0 P FI_TX[0] FI_TXP FI_TX[] J FI_INT FI_INT R0 *0_/S FI_SYN_R H FI_SYN P_LNE0_N T P_LNE_N T0 I_TX#[0] P_LNE_N U I_TX#[] P_LNE_N U I_TX#[] P_LNE0_P U I_TX#[] P_LNE_P U0 I_TX[0] P_LNE_P V I_TX[] P_LNE_P V I_TX[] I_TX[] T U I_TX#[0] U I_TX#[] U I_TX#[] U I_TX#[] V I_TX[0] T I_TX[] V I_TX[] I_TX[] P N I_TX#[0] P I_TX#[] N0 I_TX#[] R I_TX#[] P I_TX[0] R I_TX[] P0 I_TX[] ep_romp I_TX[] E R *0_ R ep_romp INT_eP_HP_Q P EP_ISP_UTIL ep_hp EP_UXP EP_UXP N EP_UXN EP_UXN M ep_ux ep_ux# R P ep_tx[0] ep_tx[] EP_TXN0 P EP_TXN N ep_tx#[0] ep_tx#[] MI Intel(R) I FI ep HSW_RPG_ES_PG PI EXPRESS* - GRPHIS PEG_ROMPO E PEG_OMP M PEG_RX#0 PEG_RX#[0] K PEG_RX# PEG_RX#[] M PEG_RX# PEG_RX#[] L0 PEG_RX# PEG_RX#[] M PEG_RX# PEG_RX#[] L PEG_RX# PEG_RX#[] M PEG_RX# PEG_RX#[] L PEG_RX# PEG_RX#[] E PEG_RX#[] PEG_RX#[] E PEG_RX#[0] 0 PEG_RX#[] E PEG_RX#[] PEG_RX#[] E PEG_RX#[] E PEG_RX#[] L PEG_RX0 PEG_RX[0] L PEG_RX PEG_RX[] L PEG_RX PEG_RX[] K0 PEG_RX PEG_RX[] L PEG_RX PEG_RX[] K PEG_RX PEG_RX[] L PEG_RX PEG_RX[] K PEG_RX PEG_RX[] F PEG_RX[] E PEG_RX[] F PEG_RX[0] E0 PEG_RX[] F PEG_RX[] E PEG_RX[] F PEG_RX[] PEG_RX[] H _PEG_TX#0 PEG_TX#[0] H _PEG_TX# PEG_TX#[] J _PEG_TX# PEG_TX#[] H _PEG_TX# PEG_TX#[] J _PEG_TX# PEG_TX#[] G0 _PEG_TX# PEG_TX#[] _PEG_TX# PEG_TX#[] _PEG_TX# PEG_TX#[] PEG_TX#[] 0 PEG_TX#[] PEG_TX#[0] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] PEG_TX#[] J _PEG_TX0 PEG_TX[0] G _PEG_TX PEG_TX[] H _PEG_TX PEG_TX[] G _PEG_TX PEG_TX[] H _PEG_TX PEG_TX[] H0 _PEG_TX PEG_TX[] _PEG_TX PEG_TX[] _PEG_TX PEG_TX[] PEG_TX[] 0 PEG_TX[] PEG_TX[0] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_TX[] PEG_RX#[0..] H_PEI (0ohm) Route on microstrip only Spacing > mils Trace Length: inch HPEI Ra,a need placement close to E. Ra H_PEI, E_PEI R _ a PEG_RX[0..] 0 *P/0V_ PM_SYN (0ohm) PM_SYN Trace Length: ~. inches H_PWRGOO H_PWRGOO (0ohm) Trace Length: ~. inches PU RESET# PU_PLTRST# (0ohm) Trace Length: 0~ inches SM_RMPWROK Processor Input. R_VR_PWRG SYS_PWROK PM_RM_PWRG (0ohm) Trace Length: ~ inches PROHOT# (0ohm) Trace Length < inches, H_PROHOT# Rb need placment near PH /0 R.0 dd /0 R.0 dd +VST b need placment near VR b P/0V_ THERMTRIP# (0ohm) Trace Length:.~ inches, PM_THRMTRIP#R PM_THRMTRIP#_R +VS R,,,,,0, R 00K_ *0_ R 不不不 0/0/0 R 00K_ PLTRST# +.0V TP0 TP R R0 R0 TP_TERR#./F_ H_PROHOT#_R R *K/F_ Rb Haswell Processor (LK,MIS,JTG) PM_SYN_R *0_/S H_PWRGOO_R 0K_, PM_RM_PWRG_R R_RMRST#_R (0ohm) To change the resistor values in the RMPWROK logic to reduce the Trace Length < inches leakage on VPWRGOO +.VSUS PM_RM_PWRG_ (0ohm) Trace Length: < inches +.VSUS, R_RMRST# U PM_RM_PWRG_ HG0GW R R *0_/S *0.U/0V_ 0.U/0V_ SKTO# PU_PLTRST#R *0/F_ PU_PLTRST#R R.K_ G ->.K R.K/F_ R G ->.K *0.U/0V_ *.K/F_ P N R K M0 M T L 0 T U R 0_ R *0_ SKTO# TERR# PEI F_K PROHOT# THERMTRIP# PM_SYN UNOREPWRGOO SM_RMPWROK RESET# HSW_RPG_ES_PG PM_RM_PWRG_R PM_RM_PWRG MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM PM_RM_PWRG E LK LK# E SS_PLL_REF_LK F SS_PLL_REF_LK# H PLL_REF_LK G PLL_REF_LK# SM_RMRST# P SM_ROMP[0] R SM_ROMP[] P SM_ROMP[] R RM RESET 0 Host LK: Trace length < 000 MILS Trace spacing =,0 MILS, Impendence 0 ohm N R PRY# T PREQ# M TK N TMS M TRST# M TI TO L R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] LK_PU_LKP LK_PU_LKN LK_PLL_SSLKP LK_PLL_SSLKN LK_PLL_NSLKP LK_PLL_NSLKN PU_RMRST# SM_ROMP_0 SM_ROMP_ SM_ROMP_ SM_ROMP[0] W:mils/S:mils/L: 00mils, SM_ROMP[] W:mils/S:mils/L: 00mils, SM_ROMP[] W:mils/S:mils/L: 00mils, P XP_PRY# XP_PREQ# XP_TLK XP_TMS XP_TRST# XP_TI_R XP_TO R XP_RST# R0 XP_PM0 N N P P0 XP_PM XP_PM XP_PM XP_PM N XP_PM P XP_PM P XP_PM R0 *K_ *0_/S *0.U/0V_ R R R R LK_PU_LKP LK_PU_LKN LK_PLL_SSLKP LK_PLL_SSLKN LK_PLL_NSLKP LK_PLL_NSLKN 00/F_ /F_ 00/F_ TP TP PU XP TP TP0 TP TP TP *K_ +V XP_RST# TP TP TP TP TP TP TP TP PU_RMRST# R_VR_PWRG R_VR_PWRG (0ohm) Trace Length: ~ inches *MEK00V-0 *0.U/0V_ PM_RM_PWRG_R (0ohm) Trace Length: 0.~ inches +VIO_OUT, +VIO_OUT +.0V,,0,,, +.VSUS,,, +VS,,,0,,,,,,,,, +V,,,,0,,,,,,,,,,,,,0,,,,,0 INT_eP_HP_Q /0 R V.0 -> 0K +VIO_OUT Q N00 R 0K_ R 00K_ EP_HP, PEG x disable (UM only remove) _PEG_TX0 _PEG_TX _PEG_TX _PEG_TX _PEG_TX _PEG_TX _PEG_TX _PEG_TX PEG_TX[0..] PEG_TX#[0..] 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PEG_TX0 PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX PEG_TX 0.uF coupling aps for PIE GEN// _PEG_TX#0 _PEG_TX# _PEG_TX# _PEG_TX# _PEG_TX# _PEG_TX# _PEG_TX# _PEG_TX# 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PEG_TX#0 PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# PEG_TX# 0.uF coupling aps for PIE GEN// P & PEG ompensation +VIO_OUT +VIO_OUT R ep_romp Trace length < 00 Mils Trace Width 0 Mils Trace Spacing Mils R PEG_ROMP Trace length < 00 MILS Trace width = MILS Trace spacing = MILS./F_ ep_romp./f_ PEG_OMP RE rof Processor pull-up (PU) XP_TO XP_TMS XP_TI_R XP_PREQ# XP_TLK XP_TRST# RE rof H_PROHOT# R _ LK_PLL_SSLKP R0 *0K_ LK_PLL_SSLKN R *0K_ N R _ R0 *_ R0 *_ R *_ R0 _ R _ +VIO_OUT +.0V check RE rof PROJET : TWS Quanta omputer Inc. Size ocument Number Rev ustom HS / (PIE&MI&FI) ate: Friday, ugust, 0 Sheet of

3 Haswell Processor (R) 0 U U M Q[:0] M S#0 M S# M S# M S# M RS# M WE# TP RSV_V0 must be grounded M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q R T S_Q[0] M S_Q[] N S_Q[] T S_Q[] R S_Q[] N S_Q[] M S_Q[] M S_Q[] N S_Q[] M S_Q[] N S_Q[0] R S_Q[] T S_Q[] R S_Q[] T S_Q[] J S_Q[] K S_Q[] J S_Q[] K S_Q[] J0 S_Q[] K0 S_Q[0] J S_Q[] K S_Q[] F S_Q[] F S_Q[] F S_Q[] F S_Q[] G S_Q[] G S_Q[] G S_Q[] G S_Q[0] J S_Q[] J S_Q[] J S_Q[] H S_Q[] H S_Q[] H S_Q[] J S_Q[] H S_Q[] F S_Q[] F S_Q[0] S_Q[] S_Q[] S_Q[] F S_Q[] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[0] S_Q[] E S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[] S_Q[] S_Q[] E S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] V U S_S[0] S_S[] S_S[] U U S_S# U S_RS# S_WE# V0 RS_ RS_V0 HSW_RPG_ES_PG R SYSTEM MEMORY V S_LK[0] U S_LK#[0] S_KE[0] V S_LK[] U S_LK#[] S_KE[] V S_LK[] U S_LK#[] S_KE[] V S_LK[] U S_LK#[] S_KE[] M S_S#[0] L S_S#[] M S_S#[] M0 S_S#[] M S_OT[0] L S_OT[] L S_OT[] L0 S_OT[] P S_QS#[0] P S_QS#[] J S_QS#[] F S_QS#[] J S_QS#[] E S_QS#[] S_QS#[] S_QS#[] P S_QS[0] P S_QS[] K S_QS[] G S_QS[] H S_QS[] E S_QS[] S_QS[] S_QS[] M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP V M 0 S_M[0] M S_M[] V M S_M[] U M S_M[] M S_M[] M S_M[] M S_M[] M S_M[] M S_M[] M S_M[] V M 0 S_M[0] M S_M[] M S_M[] V M S_M[] M S_M[] M S_M[] M +VREF PU SM_VREF SMR_VREF_Q0_M S_IMM_VREFQ F SMR_VREF_Q_M S_IMM_VREFQ F *K_ R *K_ R0 M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] +VREF PU SMR_VREF_Q0_M SMR_VREF_Q_M M Q[:0] M Q0 R M Q T S_Q[0] M Q M S_Q[] M Q M S_Q[] M Q R S_Q[] M Q T S_Q[] M Q N S_Q[] M Q N S_Q[] M Q T S_Q[] M Q R S_Q[] M Q0 N S_Q[] M Q M S_Q[0] M Q T S_Q[] M Q R S_Q[] M Q M S_Q[] M Q N S_Q[] M Q R S_Q[] M Q R S_Q[] M Q M S_Q[] M Q M S_Q[] M Q0 T S_Q[] M Q T S_Q[0] M Q N S_Q[] M Q N S_Q[] M Q J S_Q[] M Q K S_Q[] M Q J S_Q[] M Q J S_Q[] M Q M S_Q[] M Q N S_Q[] M Q0 K S_Q[] M Q K S_Q[0] M Q L S_Q[] M Q M S_Q[] M Q L S_Q[] M Q M S_Q[] M Q L S_Q[] M Q M S_Q[] M Q L S_Q[] M Q M S_Q[] M Q0 G S_Q[] M Q J S_Q[0] M Q G S_Q[] M Q G S_Q[] M Q J S_Q[] M Q J S_Q[] M Q G0 S_Q[] M Q J0 S_Q[] M Q S_Q[] M Q S_Q[] M Q0 S_Q[] M Q S_Q[0] M Q S_Q[] M Q E S_Q[] M Q S_Q[] M Q E S_Q[] M Q E S_Q[] M Q S_Q[] M Q S_Q[] M Q S_Q[] M Q0 E S_Q[] M Q S_Q[0] M Q S_Q[] M Q S_Q[] S_Q[] R M S#0 P S_S[0] M S# S_S[] M S# S_S[] P M S# R S_S# M RS# P S_RS# M WE# S_WE# TP G R0 RSV_G RSV_R0 RSV_R0 must be grounded HSW_RPG_ES_PG R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_S#[] S_S#[] S_OT[0] S_OT[] S_OT[] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y F0 Y G0 Y G Y F P R P P R R R P P P P J L H P P P K M H R Y Y0 Y Y Y 0 R Y F P G M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 M LKN0 M KE0 M LKP M LKN M KE M S#0 M S# M OT0 M OT M QSN[:0] M QSP[:0] M [:0] PU SM_VREF +VREF PU PROJET : TWS Quanta omputer Inc. Size ocument Number Rev N ustom HS / (R I/F) ate: Friday, ugust, 0 Sheet of

4 V Output ecoupling Recommendations 0uFx ufx ufx 0uFx U/.VS_ U/.VS_ 0 U/.VS_ U/.VS_ 0 U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ 0 0U/.V_ TOP socket side on TOP, on OT near socket edge TOP, inside socket cavity OT, inside socket cavity U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ U/.VS_ *U/.VS_ U/.VS_ 0U/.V_ +VIN 0 U/.VS_ U/.VS_ U/.VS_ 0 U/.VS_ 0 U/.VS_ 0 U/.VS_ 0 U/.VS_ 0 U/.VS_ 0U/.V_ 0U/.V_ +V_ORE UF V V 0 V V V V V V V 0 V0 V V V V V V V V 0 V V0 V V V V V V V 0 V V V0 V E V E V E V E0 V G V G V E V F V F V0 F V F V F V F0 V F V F V F V F V F V G V0 H V H V G0 V G V H V H V H V H V H V H0 V0 H V H V H V J V J V J V J V J V J0 V J V0 J V J V J V J V G V H V J V K V L V M V0 N V P V R V T V U V U V V V V V W V W V0 V Y Y V Y V Y V Y V Y0 V Y V Y V Y V Y V00 Y V0 K V0 F V0 V0 HSW_RPG_ES_PG POWER ORE SUPPLY SENSE LINES SVI PEG N R Haswell Processor (POWER) VQ VQ VQ VQ E VQ E VQ E VQ E VQ H VQ K VQ0 N VQ N VQ T VQ T VQ T VQ T VQ W VQ W VQ W VQ W VQ0 RSV K RSV L RSV T RSV V RSV N RSV L RSV K RSV E RSV W RSV L RSV L RSV J VIO_OUT VIOPH VOMP_OUT VSS_P M VILERT# M VISLK L VISOUT PWR_EUG H P VSS T VSS L VSS T VSS M VSS M VSS M VSS M0 VSS M VSS L VSS M VSS T VSS T RSV_TP R RSV_TP R RSV_TP L RSV_TP V_SENSE VSS_SENSE N F P L K +VIO_OUT_R +VIO_PH_R +VIO_OUT_R H_PU_SVILRT# H_PU_SVILK H_PU_SVIT PWR_EUG_R +.VSUS. U/.VS_ U/.VS_ U/.VS_ U/.VS_ 0U/.V_ 0U/.V_ 0U/.V_ R 00_ R 00_ Sense resistor should be placed within inches (0. mm) of the processor socket Trace Impendence 0 ohm *0_0/S *0.00/F_0 *0_0/S TP 0_ +V_ORE V_SENSE VSS_SENSE U/.VS_ U/.VS_ U/.VS_ U/.VS_ 0U/.V_ 0U/.V_ 0U/.V_ R0 +.VSUS R R R 0 U/.VS_ U/.VS_ 0 U/.VS_ 0U/.V_ 0U/.V_ 0 0U/.V_ 0U/.V_ +VIO_OUT +VIO_PH Layout note: It is recommended to shield VISOUT signal by routing it in between the VISLK and VILERT# signals. Place PU resistor close to PU H_PU_SVIT VQ Output ecoupling Recommendations 0uFx ufx 0uFx0 +VIO_OUT H_PU_SVILK + *0U/V_ m 00m OT socket side ontop, on OT inside socket cavity ontop, on OT inside socket cavity /0: G 0 Place PU resistor close to PU The VILERT# signal must have a damping resistor to prevent overshoot *0.U/0V_ +VIO_OUT H_PU_SVILRT# +VIO_OUT R 0/F_ R Haswell PWR_EUG requires a 0-Ohm pull-up resistor to PH.0-V V ore when routed to XP /F_ R _ SVI LK VR_SVI_LK SVI T G V0. -> 0 Ohm SH V0. -> 0 Ohm VR_SVI_T SVI LERT G V0. -> Ohm SH V0. -> Ohm VR_SVI_LERT# Power Test Propose +.0V +VPU R 00K_ NT PWR_EUG_R R *0K_ R R 0/F_ 0K/F_ PU VQ /0: R.0 add +.0V R +VIO_OUT +VIO_OUT, +VIO_PH 0 +.V,,,0,,,, +.0V,,0,,, +V_ORE, +VST +.VSUS,,, HW Thrm Protect For degree,.v limit, (SW) R.0 stuff 0 For degree,.v limit, (HW) THRM_MOINTOR *0.U/0V_ *0_ +.0V +.0V +VST R0 0 *0U/.V_ *0_ R 0_ +VIO_OUT +VIO_PH PROJET : TWS Quanta omputer Inc. *0U/.V_ *.U/.V_ 00 *.U/.V_ Size ocument Number Rev N ustom HS / (POWER) ate: Friday, ugust, 0 Sheet of P

5 Haswell Processor (RESERVE, FG) UG 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS E VSS E0 VSS E VSS E VSS E VSS0 E VSS E VSS E VSS E VSS E VSS E VSS F VSS F VSS F VSS G VSS0 G VSS E VSS G VSS E VSS G VSS H VSS H0 VSS H VSS G VSS G VSS0 H VSS G VSS G VSS H VSS H VSS H VSS H VSS H VSS H VSS J VSS0 J VSS K VSS K VSS K VSS K VSS K VSS K0 VSS K VSS E VSS VSS0 HSW_RPG_ES_PG VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 K K L L0 L L L L L L L L0 L L E L W L L L L L L M0 M M M E M M M N0 N N N N N N N N0 N N N P P0 P P P P P W Y R R R R R R R R R R R T0 T T T T T T T T0 T T 0 UH VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS0 VSS VSS 0 VSS VSS VSS VSS VSS 0 VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 E VSS E0 VSS E VSS E VSS E VSS E VSS F0 VSS F VSS F VSS F VSS00 F VSS0 F VSS0 F VSS0 F0 VSS0 F VSS0 F VSS0 F VSS0 F VSS0 F VSS0 F0 VSS0 F VSS F VSS F VSS F VSS F VSS F VSS F VSS G VSS G VSS G VSS0 G VSS G VSS G VSS G VSS G VSS G VSS G VSS G VSS H0 VSS H VSS0 H VSS H VSS J VSS J VSS J0 VSS J VSS J VSS J VSS0 K VSS VSS HSW_RPG_ES_PG VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS0 VSS VSS VSS VSS VSS VSS RSV K0 K K K K K K K K K K K L L L M M M M0 M M M N N0 N N N N N N N N N N N P P P R R R R0 R R R T T0 T T T T T T T T T U U V V V0 V V W W0 W W W W W R0 J H L F T K R./F_./F_ R00 TP0 TP TP For PU debug. TP TP FG0 FG FG FG FG FG FG FG R0 FG_ROMP TP TP0 TP TP./F_ RSV0 RSV RSV TESTLO Haswell Processor (GN) 0 UE T0 R0 FG[0] P0 FG[] P FG[] T FG[] N FG[] T FG[] N FG[] R FG[] T FG[] N0 FG[] P FG[0] P FG[] N FG[] N FG[] P FG[] R FG[] P FG[] R FG[] P FG[] FG[] T FG_ROMP T T RSV_TP 0 RSV_TP RSV_TP RSV_TP RSV_TP FG W W RSV_TP G RSV_TP W TESTLO_G L0 RSV L RSV RSV RSV_TP RSV_TP L RSV_TP W0 W RSV_TP RSV_TP W TESTLO HSW_RPG_ES_PG FG[] (PHYSIL_EUG_ENLE (FX PRIVY)) 0 Enable; SET FX ENLE IT IN EUG, isable; FG RESERVE R RSV_TP RSV_TP RSV_TP RSV_TP *K_ F_G G RSV R RSV M RSV M RSV F RSV M RSV K RSV E RSV U0 RSV P0 N RSV R RSV_TP E RSV_TP E0 RSV_TP RSV P RSV R RSV L RSV L TP TP TP TP R *K_ R *K_ E_PWROK, Processor Strapping FG (PEG Static Lane Reversal) Normal Operation The FG signals have a default value of '' if not terminated on the board. 0 Lane Reversed FG R *K_ FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG (P Presence Strap) FG (PEG efer Training) isable; No physical P attached to ep Enable; n ext P device is connected to ep PEG train immediately following xxreset de assertion PEG wait for IOS training FG FG FG FG R R R0 R K_ *K_ K_ *K_ PROJET : TWS Quanta omputer Inc. Size ocument Number Rev N ustom HS / (GN) ate: Friday, ugust, 0 Sheet of

6 / for S SUSK#E SUSWRN# PH Pull-high/low(LG) Lynx Point (MI,FI,PM) / for S SUSWRN#E R0 *0_/S SUSWRN# J SUSWRN#/SUSPWRNK/GPIO0 (SUS) SLP_S# H R *0_/S SUS# (+VS) NSWON# R *0_/S NSWON#_R K PWRTN# SLP_# F TP / for S / for S _PRESENT R *0_/S _PRESENT_R E PRESENT / GPIO(SW) SLP_SUS# F R *0_/S SLP_SUS#E (SW) PM_TLOW# K TLOW# / GPIO (SUS) PMSYNH Y (+VS) PM_SYN PM_RI# N (+VS) G SLP_LN# SYS_PWROK_R RI# SLP_LN# 0 TP0 TP SLP_WLN#/ GPIO ( SW) *0.U/0V_ LPT_PH_M_ES/G Reserve for power on sequence *0_/S MI_IREF.K/F_ MI_OMP RSMRST# for S for S P Res place close to PH XP_RST# XP_RST# M SYS_RESET# WKE# K PIE_WKE# PIE_WKE#,0 LK R 不不不不 short pad 0/0/0 (+V) T R 0_ SYS_PWROK_R N LKRUN# SYS_PWROK SYS_PWROK LKRUN# LKRUN#, G V0. -> ohm HSYN_OM R *0_, IMVP_PWRG (+VS) SH V0. -> 0 ohm VSYN_OM E_PWROK_R SUS_STT#, E_PWROK R 0_ F0 U PWROK SUS_STT# / GPIO (SUS) (+VS) E_PWROK_R R *0_/S PWROK_R PWROK SUSLK / GPIO (SUS) Y PH_SUSLK_L PH_SUSLK_L (+VS) PM_RM_PWRG PM_RM_PWRG H RMPWROK SLP_S# / GPIO ( SUS) Y TP +.V RSMRST# SUS_STT# R0 PM_RI# R0 SLP_LN# R0 SUSK# R SUSWRN# R PM_RM_PWRG R MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP R0 R *0_ *0_/S *0K_ 0K_ *0K_ *0K_ *0K_ *00_ R R +V_EEP_SUS SUSK# U W R0 MI0RXN P MIRXN V0 MIRXN MIRXN Y P0 MI0RXP R MIRXP W0 MIRXP MIRXP E0 MI0TXN MITXN E MITXN MITXN 0 MI0TXP MITXP MITXP MITXP E Y MI_IREF MI_IROMP W V TP TP R J SUSK# RSMRST# System Power Management MI FI J FI_RXN0 L FI_RXN J FI_RXP0 L FI_RXP FI_SYN FI_INT FI_IREF FI_ROMP V TP Y TP V TP W TP0 U TP U TP SWVRMEN PWROK SLP_S# L L0 T R L R R SWVREN PWROK R *0_/S.K/F_ R 0_ R *0_/S FI_TXN0 FI_TXN FI_TXP0 FI_TXP FI_SYN FI_INT +.V *0_ SUS# RSMRST# PWROK_E,, LVS_LON PH to Res routeing. ohm Impedance. Res to connector filter routeing 0ohm Impedance. RT_ RT_G RT_R _IREF (0ohm) Trace length < 00 MILS Trace spacing = 0 MILS Reserve from EMI request RT_ *.P/V_ ISP_ON PST_PWM RT_G R *.P/V_ R R R R _ R0 _ RT_R PH Nut: QI P/N: MUL0000 (Location:H,H) Lynx Point ( I) 0/F_ PH_HSYN_R PH_VSYN_R K G N /F IREF U0 U *.P/V_ 0/F_ 0/F_ U EP_KLTEN EP_V_EN EP_KLTTL T U RT_LUE V RT_GREEN RT_RE M M RT LK RT T N N RT_HSYN RT_VSYN _IREF RT_IRTN LVS RT LPT_PH_M_ES/G igital isplay Interface R0 P_TRLLK R P_TRLT R P_TRLLK R P_TRLT N0 P_TRLLK N P_TRLT System PWR_OK(LG) SYS_PWROK P_UXN H H P_UXP P_HP K0 P_UXN K K P_UXP P_HP K P_UXN J J P_UXP P_HP H *0_/S IMVP_PWRG SVO_LK SVO_T HMI_HP_ON 0 +V_EEP_SUS,,,0, +V_RT,0, +.0V,,,0,,, +VPU,,,,,, +VS,,,0,,,,,,,,, +V,,,,0,,,,,,,,,,,,,0,,,,,0 +V,,,,,,0 R INT. HMI IMVP_PWRG, PM_TLOW# PIE_WKE# NSWON#_R _PRESENT_R R R0 R R R.K_ K_ *0K_ 0K_ *00K_ +VS ES V0. -> TLOW# is in SUS well SH V0. -> TLOW# pull up to S power G V0. say that PWRTN# is internal pulled-up in PH to. V SW through a weak pull-up resistor ( kω nominal) R 0K_ E_PWROK +V LKRUN# XP_RST# R R R 0K_ K_ *K_ INT HMI etect Function +V_RT R0 0K_ SWVREN On ie SW VR Enable PROJET : TWS Quanta omputer Inc. RSMRST# R 00K_ High = Enable (efault) Low = isable Size ocument Number Rev N ustom PH / (MI/FI/VIEO) ate: Friday, ugust, 0 Sheet of

7 Reserve for EMI *0P/0V_ check PH Strap Table SPKR GPIO No reboot mode setting oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] RSV Lynx Point (H,JTG,ST) Pin Name Strap description Sampled onfiguration GNT# / GPIO GNT# / GPIO GPIO Top-lock Swap Override PWROK PWROK INTVRMEN Integrated.0V VRM enable LWYS H_OK_EN#/GPIO H_SO GPIO LKGEN_RT_X for S +V_RT +V_EEP_SUS SIO_EXT_SI# R Z_SPKR Z_SIN0 R TP TP TP TP SIO_EXT_SI# PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO PH_SPI_IO PH_SPI_IO 0K_ TP TP TP TP M_ RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_SOUT PH_JTG_TI_R PH_SPI_LK PH_SPI_S0# PH_SPI_SI PH_SPI_SO GPIO PH_JTG_TK_R PH_JTG_TMS PH_JTG_TO_R R *0_/S PH_SPI_S# PH_SPI_IO PH_SPI_IO Flash escriptor Security Only for Interposer Flash escriptor Security On-die PLL Voltage Regulator PWROK PWROK PWROK PWROK RSMRST# RSMRST# GNT# 0 0 efault (weak pull-down 0K) = Setting to No-Reboot mode 0 "top-block swap" mode = efault (Int PU) 0 = isable = Enable 0 Override = efault (weak pull-up 0K) Internel PU GNT0# 0 H_SYN On-ie PLL VR Voltage Select RSMRST 0 = Support by.v (weak pull-down) = Support by.v oot Location SPI LP 0 Security Effect (Int P) = an be Overridden 0 isable = Enable (Int PU) SPI_MOSI itpm function isable PWROK 0 efault (weak pull-down 0K) = Enable SUSLK / GPIO On-die PLL Voltage Regulator PWROK TP G0 U RTX RTX INTRUER# INTVRMEN Z_LK H_LK Z_SYN H_SYN Z_SPKR Z_RST# L0 SPKR H_RST# TP L K G F RTRST# SRTRST# H_SIN0 H_SIN H_SIN H_SIN LPT_PH_M_ES/G RT IH H_SO (+V) H_OK_EN# / GPIO (+VS) H_OK_RST# / GPIO JTG_TK JTG_TMS E JTG_TI F JTG_TO TP TP TP0 J SPI_LK J SPI_S0# L J0 SPI_S# SPI_S# H SPI_MOSI H SPI_MISO J J SPI_IO SPI_IO SPI JTG ST G LP 0 L0 0 L L L LFRME# LRQ0# G0 LRQ# / GPIO (+V) SERIRQ L P STLE# (+V) T ST0GP / GPIO (+V) U STGP / GPIO TP TP 0 = isable = Enable (Int PU) PH_RQ#0 PH_RQ# SERIRQ ST0RXN E ST0RXP ST0TXN W Y ST0TXP STRXN 0 E0 STRXP STTXN V0 W0 STTXP STRXN STRXP STTXN Y W STTXP STRXN E STRXP STTXN R T STTXP STRXN / PERN STRXP / PERP V STTXN / PETN W STTXP / PETP STRXN / PERN E STRXP / PERP P STTXN / PETN R STTXP / PETP Y ST_ROMP R ST_ROMP ST_ROMP Impedance = 0 ohm Trace length < 00 mils Trace spacing = mils ST_IREF Port isable Port isable G V0. -> 0 ohm SH V0. -> 0 ohm ST_IREF GT_STOP# S_IT0 GT_STOP# Z_SPKR PH_INVRMEN ircuit [Need external pull-down for LP IOS] efault weak pull-up on GNT0/# R R R R R +V_H_IO PH_SPI_SI L0,, L,, L,, L,, TP TP R LFRME#,, GPIO_E.K_ G recommended that coupling capacitors should be close to the connector (<00 mils) for optimal signal quality. *0_/S R 0_.K/F_ 0K_ *0K_ 0K_ R *K_ R R R R R R +V +V R PH_SUSLK_L Z_SOUT +V SERIRQ, ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP ST_RXN ST_RXP ST_TXN ST_TXP +.V +.V +V *K_ ST_LE# EMI GPU_HOL_RST#, / Install for Intel G +V PI_GNT# 0K_ *K_ *K_ *K_ *K_ *K_ +V_RT O (ST.Gb/s) H0 (ST.0Gb/s) mst (ST.0Gb/s) S_IT0 *K_ Z_SYN R +V S_IT R R0 *K_ IT_LK_UIO T_OFF#, PH SPI ROM(LG) RT ircuitry(rt) RT Power trace width 0mils. IT_LK_UIO +V power leakage in S mode: Please always remove pull high. (Intel release document: 已已不已 strap pin) 0// PLL_OVR_EN *K_ *K_ +.0V,,,0,,, +V_RT,0, +VPU,,,,,, +V,,,,0,,,,,,,,,,,,,0,,,,,0 +V_EEP_SUS,,,0, +V,,,,,,0 +V_H_IO +V *P/0V_ 0 0.U/0V_ Z_RST#_UIO Z_SOUT_UIO Z_SYN_UIO +V_RT_0 PH_SPI_S# R *0_ PH_SPI_S0# R 0_ RT ONN T H us(lg) PH_SPI_S0#R PH_SPI_LK PH_SPI_SI PH_SPI_SO 0 *P/0V_ PH_SPI_IO PH_SPI_IO R _ R _ R _ MI RT lock.khz Vender WIN Socket USE GREEN LK 0mils If E support embedded flash, SPI power must be used S_0N power rail for E load code. lose to PH Z_LK Z_RST# Z_SOUT R 0_ Z_SYN TP TP TP0 TP 0 *P/0V_ R0 0_ R 0_ +V_RT TP Size M M R R U/.V_ RT_RST# 0 PH JTG ebug(lg) P/N +VS R0 *0/F_ R *00/F_ R R 0K/F_ 0K/F_ R0 U/.V_ U/.V_ R *0/F_ R *00/F_ K_ K_ +V U R 0_SPI_LK_R E# V R 0_ SPI_SI_R SK R 0_ SPI_SO_R SI SO HOL# WP# VSS QEM-F/Q (QE) KEZN00 ( QEM-F/Q (QE)) KEFP0N0 (WQVSSIQ) FHS0FS0 *0_ SRT_RST# RT_RST# SRT_RST# PH_JTG_TMS PH_JTG_TI_R PH_JTG_TO_R PH_JTG_TK_R R *00/F_ +V R *0/F_ J *SOLERJUMPER- J *SOLERJUMPER- R *_ TP PROJET : TWS Quanta omputer Inc. 0 0.U/0V_ Size ocument Number Rev N ustom PH / (ST/H/SPI) ate: Friday, ugust, 0 Sheet of

8 PI/USO# Pull-up(LG) PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# EL_INTH# L_K MP_PWR_TRL# US.0 for S US_O# US_O# US_O# US_O# check +V,,,,,0, R R0 R0 R +V_EEP_SUS MP Switch ontrol Low = MP ON MP_PWR_TRL# High = MP OFF (efault) MP_PWR_TRL# RP 0 S_IT TP PI_GNT# SMus/Pull-up(LG) US0_RX+ US0_RX+ US0_RX- US0_RX- US0_TX- US0_TX- US0_TX+ US0_TX+ TP OR_I EL_INTH# PLTRST#.K_.K_.K_.K_ 0K_0PR_ RP 0 0K_0PR_ R TP _LE# EI_SELET# T_OMO_EN# GPU_SELET# +V.K_ /0: R.0 =>rename PH_TP US_O# US_O0# RF_PWR_OFF# US_O# Port, isable Port, isable Port, isable Port, isable PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# T_OMO_EN# GPU_SELET# EI_SELET# S_IT _LE# PI_GNT# MP_PWR_TRL# L_K EL_INTH# *K_ PI_PME# PLTRST#,,,,,,,, R Lynx Point (PI,US,NVRM) MLK PH_TP MT +V R W W R P V V P E E E R 00K_ E E Y H0 L0 K M0 0 0 L G F L M 0 Y SM_PH_T SM_PH_LK UE TP TP TP TP T_IREF USRXN USRXN USRXN USRXN USRXP USRXP USRXP USRXP USTXN USTXN USTXN USTXN USTXP USTXP USTXP USTXP PIRQ# PIRQ# PIRQ# PIRQ# GPIO0 (+V) GPIO (+V) GPIO (+V) GPIO (+V) GPIO (+V) GPIO (+V) PIRQE# / GPIO (+V) PIRQF# / GPIO (+V) PIRQG# / GPIO (+V) PIRQH# / GPIO (+V) PME# PLTRST# Thermal PI LPT_PH_M_ES/G Q *N00W +V SM_ME_LK +V_EEP_SUS Q N00W US SM_ME_T R - Link ardreader L_LK_R L_T_R SM_RUN_T,,,.K_ USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS (+VS) O0# / GPIO (+VS) O# / GPIO0 (+VS) O# / GPIO (+VS) O# / GPIO (+VS) O# / GPIO (+VS) O# / GPIO (+VS) O# / GPIO0 (+VS) O# / GPIO R R R.K_.K_ L_LK L_T L_RST#.K_ TP TP F F0 F F G K L G H 0 0 G F F G K K M L P V U P M T N M +V SM_RUN_LK,,, L_RST#_R US_IS US_O0# US_O# US_O# US_O# US_O# US_O# US_O# RF_PWR_OFF# LN TP TP TP USP0- USP0+ USP- USP+ USP- USP WLN US.0 US.0/US.0 OMO st Right_US_up amera /: GPIO change netname to RF_PWR_OFF# for LK_REQ/Strap Pin(LG) LK_PIE_REQ# PIE_LKREQ_R# LK_PIE_REQ0# LK_PIE_REQ# LK_PIE_REQ# LK_PEG_REQ# LK_PEG_REQ# LK_PEG_REQ# LK_UF_LK_N LK_UF_LK_P LK_UF_PIE_GPLL# LK_UF_PIE_GPLL LK_UF_REFLK# LK_UF_REFLK LK_UF_REFSSLK# LK_UF_REFSSLK LK_PH_M PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN PIE_RXN_R PIE_RXP_R PIE_TXN_R PIE_TXP_R USP- USP+ Right_US_down USP0- USP0+ WLN USP- USP+ FP USP- USP+ TV ard LK_PIE_RN LK_PIE_RP R0./F_ R Ra R Rb R PIE_RXN PIE_RXP PIE_TXN PIE_TXP R R R0 R0 R0 +.V SG : Rb ; UM/ OPT : Ra R R R0 R R R R R R LOK TERMINTION for FIM PIE_LKREQ_R# 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ R R +V +V_EEP_SUS 0.U/0V_ 0.U/0V_ Lynx Point (PI-E,SMUS,LK) for S PIE_TXN_LN_ PIE_TXP_LN_ 0.U/0V_PIE_TXN_R_ 0.U/0V_PIE_TXP_R_ 0.U/0V_ 0.U/0V_ *0_/S.K/F_ PIE_TXN_ PIE_TXP_ PIE_IREF PIE_ROMP LK_PIE_REQ0# LK_PH_SRN LK_PH_SRP LK_PIE_REQ# LK_PH_RN LK_PH_RP PIE_LKREQ_R# OR_I0 OR_I OR_I LK_PH_SRN LK_PH_SRP LK_PIE_REQ# LK_PIE_REQ# LK_PH_PEGN LK_PH_PEGP LK_PEG_REQ#_R PIE lock WLN LN GPU TP TP 0 PIE_LKREQ_WLN# 0 0 W Y E T R W Y E T R E W V Y W E T0 T E0 0 N N E0 0 Y Y F F T F F V E E 0 E J J Y F LK_PIE_WLNN LK_PIE_WLNP LK_PIE_LNP LK_PIE_LNN PIE_LKREQ_LN# LK_PIE_VG# LK_PIE_VG LK_PEG_REQ# Remove for UM only. U PERN / USRN PERP / USRP PETN / USTN PETP / USTP PERN/ USRN PERP/ USRP PETN/ USTN PETP/ USTP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PERN PERP PETN PETP PIE_IREF PIE_ROMP TP TP LKOUT_PIE0N LKOUT_PIE0P PI-E* PIELKRQ0# / GPIO (+VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (+V) LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP (+V) PIELKRQ# / GPIO0/ SMI# PIELKRQ# / GPIO (+VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (+VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (+VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (+VS) LKOUT_PIEN LKOUT_PIEP PIELKRQ# / GPIO (+VS) LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO TP TP LPT_PH_M_ES/G (+VS) RP 0_PR_ R R R SMUS LOKS (+VS) (+VS) (+VS) SMLLERT# / PHHOT# / GPIO (+VS) FLEX LOKS *0_/S *0_/S *0_/S SMLERT# / GPIO SMLLK / GPIO (+VS) (+VS) LKOUT_ITPXP_N LKOUT_ITPXP_P (+V) LKOUTFLEX /(+V) GPIO LKOUTFLEX / GPIO (+V) LK_PH_SRN LK_PH_SRP LK_PH_SRP LK_PH_SRN LK_PH_PEGN LK_PH_PEGP SMLK SMT SML0LERT# / GPIO0 SML0LK SML0T SMLT / GPIO LKOUT_PEG N LKOUT_PEG P PEG LKRQ# / GPIO LKOUT_PNS_N LKOUT_PNS_P LKOUT_P_N LKOUT_P_P LKOUT_MI_N LKOUT_MI_P LKIN_MI_N LKIN_MI_P LKIN_GN_N LKIN_GN_P LKIN_OT_N LKIN_OT_P LKIN_ST_N LKIN_ST_P REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT ILK_IREF IFFLK_ISREF LKOUT_MHZ0 LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LKOUTFLEX0 / GPIO LKOUTFLEX / GPIO (+V) LK_PIE_REQ# LK_PIE_REQ# LK_PEG_REQ#_R N R0 U N U R H K N Y Y U H H F F J0 J F F0 Y W R T H G E F M L M N E F 0 0 F F F SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T Reserve SMT_INT# for JW. RMRST_NTRL_PH SMLLERT#_R SM_ME_LK SM_ME_T LK_PEG_REQ# LK_PH_ITPN LK_PH_ITPP LK_UF_PIE_GPLL# LK_UF_PIE_GPLL LK_UF_LK_N LK_UF_LK_P LK_UF_REFLK# LK_UF_REFLK LK_UF_REFSSLK# LK_UF_REFSSLK LK_PH_M LK_PI_F XTL_IN ILK_IREF ILK_IS LK_PI_TPM_R LK_PI_R_R LK_PH_PI LK_PH_PI LK_PH_PI LK_FLEX0 LK_FLEX LK_FLEX LK_FLEX R for S *0_ TP TP TP SM_PH_LK SM_PH_T LK_PLL_NSLKN LK_PLL_NSLKP LK_PLL_SSLKN LK_PLL_SSLKP LK_PU_LKN LK_PU_LKP TP TP TP TP TP TP0 R0 TP TP *0_/S *_ EMI LK_PH_M LK_M_EUG close U LK_M_K /: MHz for TPM LK_PI_F_R LK_PI_LP_R LK_PI_E_R SM_INT# RF Friday, ugust, 0 ate: Sheet of 0 0/ EMI Jerry hange from P(H00J0) to P(H00J0) LK_PI_TPM PH_XTL_IN LK_PI_TPM LK_PI_F SMus/Pull-up(LG) RMRST_NTRL_PH SMLERT# SM_PH_LK SM_PH_T SM_ME0_LK SM_ME0_T SMLLERT#_R LK_M_EUG LK_M_K +.0V,,,0,,, +.V,,0,,,, +VS,,,,0,,,,,,,,, +V,,,,0,,,,,,,,,,,,,0,,,,,0 +V_EEP_SUS,,,0, +V_EEP_SUS R R R R R R0 R R R R R _ *0_/S *.K/F_.K/F_ K_ 0K_.K_.K_.K_.K_ 0K_ R R R 0 *P/0V_ *P/0V_ +.V 0 +VXK_VRM PROJET : TWS Quanta omputer Inc. *P/0V_ *P/0V_ Size ocument Number Rev ustom N PH / (PIE/US/LK)

9 Lynx Point (GPIO,VSS_NTF,RSV) UF S_GPIO R0 00_ S_GPIO_R T MUSY# / GPIO0 SIO_EXT_SMI# SIO_EXT_SMI# F (+V) TH / GPIO OR_I (+V) TH / GPIO OR_I G (+V) TH / GPIO T_OFF# Y (+V), T_OFF# GPIO LN_ISLE#_R K (+VS) LN_PHY_PWR_TRL / GPIO RF_OFF# (+VS) RF_OFF# GPIO (+VS) Reserve O_PRSNT#_R N STGP / GPIO (+V),, GPU_PWROK GPU_PWROK TH0 / GPIO IOS_RE (+V) SLOK / GPIO, GPU_HOL_RST# GPU_HOL_RST# R *0_ GPU_HOL_RST#_R Y0 (+V) GPIO GPIO R (+VS) GPIO PLL_OVR_EN R *0_/S PLL_OVR_EN_R (SW) GPIO +V R0 0K_ GPIO N (+VS) GPIO GPIO P (+V) GPIO / NMI# R *0_/S GPU_PWR_EN_R T (+V) 0, GPU_PWR_EN STGP / GPIO R FI_OVRVLTG K (+V) STGP / GPIO *0/F_ GPU_PRSNT# M STOUT0 / GPIO MFG_MOE T (+V) SLO / GPIO (+V) / Reserve TEST_SET_UP N (+V) STOUT / GPIO GPIO K (+V) STGP / GPIO SV_ET U GPIO (+V) (+V) E VSS_NTF_ E VSS_NTF_ VSS_NTF_ VSS_NTF_ GPIO NTF PU/MIS TH / GPIO (+V) TH / GPIO (+V) G TH / GPIO0 (+V) H TH / GPIO (+V) N0 TP Y PEI T RIN# PROPWRG V V THRMTRIP# U PLTRST_PRO# VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ E VSS_NTF_ E VSS_NTF_0 VSS_NTF_ E VSS_NTF_ E VSS_NTF_ VSS_NTF_ N0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ GPIO GPIO GPU_OPT_IS# GPIO R E_RIN# PH_THRMTRIP# R *0_ R 0_ *0_/S E_0GTE E_PEI, E_RIN# H_PWRGOO PM_THRMTRIP#R, PU_PLTRST#R, Hi Lo GPIO LVS interface ep interface MFG-TEST MFG_MOE Swap GPIO S_GPIO RF_OFF# Intel ME rypto Transport Layer Security (TLS) cipher suite Low = isable (efault) High = Enable LN_ISLE#_R R R *0K_ GPIO R 0K_ R 0 = SGPIO = efault GPIO R *0K_ GPIO R 0K_ R R0 *0K_ R R K_ R0 GPIO K_ *0_ +V +V for S *0K_ *0K_ GPIO R *0K_ R R 0K_ *0_ R R +V_EEP_SUS 0K_ 0K_ 0K_ +V_EEP_SUS,,,0, +VS,,,0,,,,,,,,, +V,,,,0,,,,,,,,,,,,,0,,,,,0 +VS,,,,,,,,,0, +VS +V GPIO Pull-up/Pull-down(LG) +V R0 SIO_EXT_SMI# GPIO O_PRSNT#_R IOS REOVERY for S GPU_HOL_RST#_R R R T_OFF# PH MIS PU /P E_0GTE E_RIN# GPU_PWROK UM=0 *0_ PH_THRMTRIP# R R00 R R0 IOS_RE R R R 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ GPU_PWROK R R +V 0K_ 0K_ for S +V_EEP_SUS *0K_ 0K_ *K_ High = isable (efault) Low = Enable +V 0 +V +.0V OR_I[:0] Model Name QLGS 0000 TWS 0000 TWJ IOS_RESP R *0_ TEST_SET_UP R 0K_ +V SV etect R 0 = SV etect = efault *00K_ SV_ET R0 0K_ +V_EEP_SUS SV_SET_UP for S High = Strong (efault) HSW OR I SETTING OR_I0 OR_I OR_I OR_I OR_I OR_I GPIO GPIO GPIO GPIO GPIO GPU_PRSNT GPU_OPT_IS# GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO0 MOEL IT0 MOEL IT MOEL IT MOEL IT MOEL IT No olby=0, olby= Reserve Reserve Reserve Reserve Reserve Optimus=, UM=0 Optimus=0, is only= LPT_PH_M_ES/G R R R00 R0 R R OR_I0 OR_I OR_I OR_I R0 *0K_ R 0K_ R 0K_ R 0K_ R 0K_ R 0K_ OR_I0 OR_I OR_I OR_I RU0 OR_I0 R 0K_ RU OR_I R *0K_ RU OR_I R *0K_ RU OR_I R *0K_ RU OR_I R *0K_ RU OR_I R0 *0K_ for S +V_EEP_SUS +V GPU_OPT_IS# GPIO0 Optimus=0, is only= GFX Present Rb R 0K_ R GPU_OPT_IS# R *0K_ GPIO Optimus=, UM=0 +V Ra *00K_ GPU_PRSNT# R 0K_ SG UM Stuff Ra Rb N Rb Ra +V STGP/GPIO 0 = TLS no confidentiality (Int P) = TLS with confidentiality GPIO GPU_PWR_EN_R TLS onfidentiality FI_OVRVLTG Internal P R0 *K_ R Size ocument Number Rev N ustom PH / (GPIO/MIS) ate: Friday, ugust, 0 Sheet of +V *K_ +V PROJET : TWS Quanta omputer Inc.

10 SI change for EEP S +.0V +.0V R +V +V +V +V R +.0V +.0V +VXK_VRM_R +.V +V.0S_V_SSFF +.0V +.0V +VIO_PH */F_ +V_XK_ *0_/S +.V +V for S +V_EEP_SUS +V_RT R U/.V_ R U/.V_ R U/.V_ R U/.V_ R U/.V_ R U/.V_.0 (0mils) 0m (0mils) +V.0S_VLKF00 +V.0S_VSSF00 *0_/S L R00 L 0_ R0 U/.V_ R0 U/.V_ R R 0.U/0V_ R *0_/S 0. (0mils) +VXK_VRM +V.0S_V_XK_ *0_/S *0_/S *0_/S 0 +V.S_V_FLEX0 +V.S_V_FLEX +V.S_V_FLEX +V.S_V_SEPI +V.0S_V_SSFF 0. (0mils) *0_/S 0 +VLKF *0_/S *0_/S 0 U/.V_ 0.U/0V_ U/.V_ *0_/S *0_/S *0_/S 0.U/0V_ *0uH/00M_ +V.0S_VLKF00 +V.0S_VSSF00 *0_/S *0_/S 0. (0mils) 0. (0mils) m (0mils) +V.0S_VPPU R 0.U/0V_ 0.U/0V_ U/.V_ 0. (0mils) 0 0 *0U/.V_ 0 0U/.V_ +V.S_VTS +V.S_VPTS U/.V_ +VPRTSUS_P Lynx Point (POWER) 0 +V,,,,,,,,,,,,,,,,,0,,,,,0 +VIO_PH +V_EEP_SUS,,,, +.0V,,,,, +VS,,,,,,,,,0, +.V,,,,,, +V,,,,,,0 +VS,,,,,,,,,,,, UJ POWER 0. (0mils) F P M L L M U V Y 0 G0 G E0 E W0 K0 K J J K P P VVRM[] V[] VLK_[] VLK_[] VLK_[] VLK_[] VLK_[] VLK_[] VLK[] VLK[] VLK[] VLK[] VLK[] VLK[] VLK[] VLK[] VLK[] VLK[0] VVRM[] V_[] V_[] V_PRO_IO[] V_PRO_IO[] VSUS_[] VRT PRT[] PRT[] lock and Miscellaneous THERML PU RT ST FUSE GPIO/LP US H VSUS_[] VSUS_[] VSUS_[] VSUS_[] VUSPLL V_[] VIO[] VIO[] VIO[] VIO[] VSS PSUS VSUS_[] VSUS_[] VSW_ V_[] V_[] V_[] VIO[] PSST V[] V[] VSW[] VSW[] VVRM[] VIO[] VSUSH R R R U U L U0 V V0 Y0 M Y R0 R +V._VPUS +V.0M_VUSSUS m (0mils) m (0mils) E F G U P P0 L R N K +V.0S_VUS 0.U/0V_ +V.S_VUG 0.U/0V_ +V.0S_VUSORE U/.V_. (0mils) 0. (0mils) +VPSW +V.S_VPORE +V.0S_VUX +VSST +V.S_VPFUSE R0 R U/.V_ PH_V 0 PH_V 0m (0mils) +V_H_IO 0.0U/V_ 0.U/0V_ for S PH VRM Power +V.0S_VPLL_ST +V.0S_V_EXP. (0mils) *0_/S R *U/.V_ +V_EEP_SUS R R R *0_/S *0_ *0uH/00M_ *0_/S *0U/.V_ 0.U/0V_ 0.U/0V_ R R R R R0 0.U/0V_ R *0_/S *0_/S *0_/S 0 *0_/S *0_/S *0_/S *0_/S *0_/S +V +.0V +.0V +.0V for S +.0V +.0V L0 R *0_/S +V +V_EEP_SUS +V_EEP_SUS for S +V +.0V +VS +.0V +.V +.0V +.0V PH VRM Power +.0V +.V PH VRM Power +.0V +.V U/.V_ L L R +V_EEP_SUS 0. (0mils). (0mils) 0. (0mils). (0mils) +V.0S_V_EXP *0U/.V_ +V_EEP_SUS +V.0S_V_EXP for S 0.U/0V_ *U/.V_ *0U/.V_ *0uH/00m_ R0 *U/.V_ *uh/m_ *0_/S U/.V_ U/.V_ U/.V_ 0U/.VS_ +V.0S_V_EXP +V.0M_VSW./F_ +V.0S_PH_V +PH_VSW 0. (0mils) +V_EEP_SUS (0mils) +V_USSUS +VPLL_US 0. (0mils) +V.0M_VSUS m (mils) +V.0S_VPLL_FI *0U/.V_ 0. (0mils) PH band gap Power +VS MIN U/.V_ U/.V_ U/.VS_ Q *N00 0 E E0 E E E G G0 G G Y U U0 U U V V0 V Y Y0 Y V U M M0 M P R T J0 J J J K K K0 Y N N +V_G Lynx Point (POWER) UG POWER VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[0] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[] VSW[0] VSW[] VSW[] PSUSYP VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VSUS_[] VSUS_[] PSUS_[] PSUS_[] VVRM[] VVRM[] VIO[] PSUS VVRM[] VIO[] VIO[] V ORE VMPHY US FI LPT_PH_M_ES/G RT SPI MI / PIE HVMOS V_ VSS VG_ V_[] V_[] VVRM[] VIO[0] VSPI +V 0m ( mils) L m (0mils) +V.S_G m (0mils) +V.S_V_GIO PH VRM Power +V.0S_VPLL_EXP L +V.M_VPSPI m (0mils). (0mils) If E support embedded flash, SPI power must be used S_0N power rail for E load code. If have power noise issue then stuff it. +V +.V_LO *U/.V_ U VIN VOUT EN GN P P M R0 R E K N * G00-0TU H0KF-T/._ 0 0 R R R R 0.U/0V_ *0U/.V_ +V.0S_V_EXP R U/.V_ 0U/.V_ 0.U/0V_ 0.0U/V_ *0_ *0_ *0_ *0_/S R *uh/m_ *0_/S +.V +.V_LO +V +V_G *0_/S +.0V +.V +V +V 0.U/0V_ +VRTEXT LPT_PH_M_ES/G PH VIO Power PH S PWR +VS R *0_ +V_EEP_SUS +.0V. (0mils) +V.0S_V_EXP 0 0U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ Near Pin N,N U/.V_ 0/0: Stage for S function +VS U/.V_ R +VS Q O0 +V_EEP_SUS 0, SLP_SUS_ON 0 U *U/.V_ IN IN SLP_SUS_ON ON/OFF *GTU R *00K/F_ OUT GN 0, SLP_SUS_ON Q N00KW R0 0_ 00K/F_ R 0_ R 00K/F_ *U/.V_ R _.U/0V_ Q N00KW PROJET : TWS Quanta omputer Inc. *U/.V_ N Size ocument Number Rev ustom PH / (POWER) Friday, ugust, 0 ate: Sheet of 0

11 UH Lynx Point (GN) UI L L L M M M M M0 M M N N0 N N P P P P R K T0 T T T0 T T T T V V V V V V0 V W F Y0 Y Y0 Y Y Y VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] K L L M M N N N N P P P P P0 P R R R R R R R R T U0 U U U U U U V V V V W W Y Y Y Y Y Y Y0 Y E E F F G G G G G J J J0 J J J J J J K K K K L L VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] Y VSS[] T VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] V VSS[] F VSS[] F0 VSS[] F VSS[] F VSS[] VSS[0] VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H0 VSS[] H VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] K0 VSS[] K VSS[] K0 VSS[] K VSS[] K VSS[0] VSS[] LPT_PH_M_ES/G LPT_PH_M_ES/G PROJET : TWS Quanta omputer Inc. Size ocument Number Rev N ustom PH / (GN) ate: Friday, ugust, 0 Sheet of

12 R R0 M [:0] M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# 0K_ M WE# 0K_,,, SM_RUN_LK,,, SM_RUN_T M OT0 M OT M QSP[:0] M QSN[:0] M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S SM_RUN_LK SM_RUN_T M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P /# S0# 0 S# 0 K0 0 K0# 0 K K# KE0 KE 0 S# RS# WE# 0 S0 0 S 00 SL S 0 OT0 OT M0 M M M M 0 M M M QS0 QS QS QS QS QS QS 0 QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q[:0] Reseve for RF +.VSUS +V PM_EXTTS#0, R_RMRST# SMR_VREF_Q0_M *.U/.V_ *.U/.V_. +V R +.VSUS 0K_ PM_EXTTS#0 +SMR_VREF_Q0 +SMR_VREF_IMM JIM V V V V V V V V 00 V 0 V0 0 V V V V V V V V VSP N N NTEST 0 EVENT# RESET# VREF_Q VREF_ VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) R-IMM0_H=._ST VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS 0 VTT 0 VTT GN 0 GN 0 +0.V_R_VTT R-IMM0_H=._ST +SMR_VREF_IMM +VREF PU, +0.V_R_VTT,, +.VSUS,,, +V,,,,,0,,,,,,,,,,,,0,,,,,0 +VREF PU, +.VSUS Place these aps near So-imm0. +0.V_R_VTT Place these aps near So-imm0. VREF Q0 M Solution 0/ : INTEL suggestion +.VSUS +SMR_VREF_IMM 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0/ : INTEL suggestion +.VSUS R K/F_ 0 U/.V_ 0U/.VS_ 0U/.VS_ 0 U/.V_ 0U/.V_ *0U/.V_ SMR_VREF_Q0_M SMR_VREF_Q0_M R *0_/S R K/F_ SMR_VREF_Q0_M, +VREF PU R R K/F_ *0_/S 0.0U/V_ R./F_ +SMR_VREF_IMM 0U/.VS_ 0U/.VS_ 0U/.VS_ 0U/.VS_ *0U/.V_ 0U/.V_ 0U/.V_ +SMR_VREF_IMM +SMR_VREF_Q0 +V 0.U/0V_.U/.V_ 0.U/0V_ 0.U/0V_.U/.V_ 0.U/0V_ 0.0U/V_ R./F_ R K/F_ PROJET : TWS Quanta omputer Inc. /: layout modify 0.U/.V_ Size ocument Number Rev N ustom R IMM0-RVS (.H) ate: Friday, ugust, 0 Sheet of

13 +V R R M [:0] M S#0 M S# M S# M S#0 M S# M LKP0 M LKN0 M LKP M LKN M KE0 M KE M S# M RS# 0K_ M WE# 0K_,,, SM_RUN_LK,,, SM_RUN_T M OT0 M OT M QSP[:0] M QSN[:0] M 0 M M M M M M M M M M 0 M M M M M IMM_S0 IMM_S M M M M M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN JIM /P /# S0# 0 S# 0 K0 0 K0# 0 K K# KE0 KE 0 S# RS# WE# 0 S0 0 S 00 SL S 0 OT0 OT M0 M M M M 0 M M M QS0 QS QS QS QS QS QS 0 QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) R-IMM_H=._RVS Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q[:0] +0.V_R_VTT,, +.VSUS,,, +V,,,,,0,,,,,,,,,,,,0,,,,,0 +SMR_VREF_IMM SMR_VREF_Q_M,,,,, R_RMRST#,,,, MLK MT PM_EXTTS#0 +V. +V +.VSUS PM_EXTTS#0 MLK MT PM_EXTTS#0 PM_EXTTS#0_E JIM V V V V V V V V 00 V 0 V0 0 V V V V V V V V VSP N N NTEST 0 EVENT# RESET# +SMR_VREF_Q VREF_Q +SMR_VREF_IMM VREF_ R *0K_ VSS VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS0 VSS VSS VSS VSS VSS P00 R SRM SO-IMM (0P) R-IMM_H=._RVS R Thermal Sensor U SLK S LERT# OVERT# *G0PU V XP VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS0 VSS VSS 0 VTT 0 VTT GN 0 GN 0 XN GN *0.0U/V_ R_THERM *00P/0V_ R_THERM +0.V_R_VTT +V Q *METR0-G +.VSUS Place these aps near So-imm. +0.V_R_VTT U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ +SMR_VREF_IMM 00 0.U/0V_.U/.V_ VREF Q M Solution Place these aps near So-imm. 0/: INTEL suggestion SMR_VREF_Q_M SMR_VREF_Q_M R 0.0U/V_ *0_/S +.VSUS R K/F_ SMR_VREF_Q_M R K/F_ U/.V_ 0U/.VS_ 0 U/.V_ 0U/.V_ +SMR_VREF_Q R0./F_ 0U/.VS_ 0U/.VS_ 0U/.VS_ 0U/.VS_ +V *0U/.V_ 0.U/0V_ 0.U/0V_ 0.U/0V_.U/.V_ 0U/.VS_ *0U/.V_ 0U/.V_.U/.V_ PROJET : TWS Quanta omputer Inc. 0U/.V_ Size ocument Number Rev N ustom R IMM-RVS (.H) ate: Friday, ugust, 0 Sheet of

14 LK_PEG_REQ# U,,, GPU_PWROK Q PEX_IOV/Q : 00m NM-GS TEU +.0V_GFX G N PEG_TX0 G PEX_IOV_ PEX_RX0 To be placed no further from the GPU [PEG Interface] PEX_RX0_N M PEG_TX#0 G PEX_IOV_ N PEG_TX PEX_LKREQ# Q than bewteen the PS and GPU G PEX_IOV_ PEX_RX PEX_RX_N M PEG_TX# *TEU H PEX_IOV_ P PEG_TX 0 U/.VS_ H PEX_IOV_ PEX_RX PEX_RX_N P PEG_TX# 0 U/.VS_ PEX_IOV_ N PEG_TX 0 U/.VS_ G PEX_RX PEG_TX# 0 U/.VS_ PEX_RX_N M G PEX_IOVQ_ N PEG_TX +V 0U/.VS_ G PEX_IOVQ_ PEX_RX PEG_TX# 0 0U/.VS_ PEX_RX_N M G PEX_IOVQ_ P PEG_TX 0 0U/.VS_ G PEX_IOVQ_ PEX_RX PEG_TX# U 0U/.VS_ PEX_RX_N P H PEX_IOVQ_ N PEG_TX MVHG0FTG 0.U/0V_ H PEX_IOVQ_ PEX_RX PEX_RX_N M PEG_TX# H PEX_IOVQ_ N0 PEG_TX,,,,,0, PLTRST# PLE NER LLS H PEX_IOVQ_ PEX_RX PEG_TX# PEX_RX_N M0 PEGX_RST# J PEX_IOVQ_ P0, GPU_HOL_RST# U/.V_ K PEX_IOVQ_0 PEX_RX PEX_RX_N P U/.V_ L PEX_IOVQ_ N U/.V_ M PEX_IOVQ_ PEX_RX R0 U/.V_ PEX_RX_N M N PEX_IOVQ_ N 00K_ PEX_IOVQ_ PEX_RX0 PEX_RX0_N M P PLE UNER G PEX_RX PEX_RX_N P N.U/.V_ PEX_RX PEX_RX_N M.U/.V_ N PEX_RX PEX_RX_N M P PEX_RX PEX_RX_N P N PEX_RX +V_GFX PEX_RX_N M +V_GFX R.K_ J J J L 0 H T V N_ N_ N_ N_ N_ N_ N_ N_ N_ N_0 N_ N_ N_ PEX_TX0 PEX_TX0_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX0 PEX_TX0_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N PEX_TX PEX_TX_N K J H G K J L K K J H G K J L K K0 J0 H0 G0 K J L K K J H G K J L K _PEG_RX0 _PEG_RX#0 _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# _PEG_RX _PEG_RX# 0 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ PEG_RX0 PEG_RX#0 PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# PEG_RX PEG_RX# +.0V_GFX R00.K_ GPU_POK 00 *000P/0V_ GPU_PGOK- Q00.K_ MMT0--F +V R00 Q00 TEU P/0V_ R00 *.K_ R00 00K/F_ For GPU_PWROK sequence to early issue( Stage) GPU_PWROK,,, PEX_REFLK PEX_REFLK_N L K LK_PIE_VG LK_PIE_VG# +V_GFX V : m J K L M V_ V_ V_ V_ PEX_TSTLK_OUT PEX_TSTLK_OUT_N PEX_WKE PEX_RST_N J K J J PEX_TSTLK PEX_TSTLK# VG_RST# R R *00_ *0_/S PEGX_RST# PLE LOSE TO G.U/.V_.U/.V_ PLE LOSE TO GPU LLS U/.V_ 0.U/0V_ 0 0.U/0V_ 0.U/0V_ PEX_LKREQ_N PEX_TERMP TESTMOE PEX_PLLV PEX_PLL_HV PEX_SV_V.V_UX_N K P K G H G P PEX_LKREQ# R 0K_ PEX_TERMP R.K/F_ TESTMOE R 0K_ +V_GFX R L PEX_PLLV PEX_PLLV : 0m PEX_SV_V : 0m +V_GFX 0 0.U/0V_.U/.V_.U/.V_ 0 PLE NER G *0_ H0KF-00T0.U/.V_ U/.V_ 0.U/0V_ +.0V_GFX PLE NER G LOSE TO PS PLE UNER G PLE NER LLS V_SENSE GN_SENSE L L VGPU_ORE_SENSE 0 VSS_GPU_SENSE 0,, +V_GFX,,,0, +.V_GFX,, +.0V_GFX,,,,,0,,,,,,,,,,,,0,,,,,0 +V PROJET : TWS Quanta omputer Inc. Size ocument Number Rev N NM-GS - / (PIE) ate: Friday, ugust, 0 Sheet of

15 U NM-GS F_M0 U0 F_M[0:0] F_M T F_M0 (F_M) F_00 [MEMORY I/F ] F_M U F_M (F_M) F_0 F_M R F_M F_0 F_M R F_M (F_M0) F_0 F_M U F_M (F_M0) F_0 F_M U F_M (F_M) F_0 F_M U F_M (F_M) F_0 F_M V F_M F_0 F_M V F_M (F_M) F_0 F_M0 V0 F_M (F_M) F_0 F_M U F_M0 (F_M0) F_0 F_M U F_M (F_M) F_ F_M V F_M (F_M) F_ F_M V F_M (F_M) F_ F_M Y F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M0 F_M (F_M) F_ F_M F_M0 (F_M) F_0 F_M F_M (F_M) F_ F_M Y F_M (F_M) F_ F_M Y F_M (F_M) F_ F_M W F_M (F_M) F_ F_M Y0 F_M (F_M) F_ F_M F_M (F_M) F_ F_M Y F_M (F_M) F_ F_M Y F_M (F_M) F_ F_M0 Y F_M (F_M) F_ V F_M0 F_0 F_M (N) F_ F_ VM_M0 P0 F_ VM_M[:0] VM_M F F_QM0 F_ VM_M F F_QM F_ VM_M M F_QM F_ VM_M F_QM F_ VM_M L F_QM F_ VM_M M F_QM F_ VM_M F F_QM F_0 F_QM F_ F_ VM_WQS0 M F_ VM_WQS[:0] VM_WQS G F_QS_WP0 F_ VM_WQS E F_QS_WP F_ VM_WQS M F_QS_WP F_ VM_WQS E F_QS_WP F_ VM_WQS K0 F_QS_WP F_ VM_WQS N F_QS_WP F_ VM_WQS F F_QS_WP F_0 F_QS_WP F_ F_ VM_RQS0 M0 F_ VM_RQS[:0] VM_RQS H0 F_QS_RN0 F_ VM_RQS E F_QS_RN F_ VM_RQS M F_QS_RN F_ VM_RQS F0 F_QS_RN F_ VM_RQS K F_QS_RN F_ VM_RQS M F_QS_RN F_ VM_RQS F F_QS_RN F_0 F_QS_RN F_ F_ PVQ : 000m F_ +.V_GFX 0 FVQ_ FVQ_ FVQ_ F_LK0 FVQ_ F_LK0_N PLE LOSE TO GPU LLS FVQ_ F_LK E FVQ_ F_LK_N.U/.V_ F FVQ_.U/.V_ G FVQ_.U/.V_ FVQ_ (F_EUG) F_EUG0.U/.V_ FVQ_0 (N) F_EUG U/0V_ FVQ_ F_VREF_N U/0V_ E FVQ_ 0 U/0V_ E FVQ_ F_M_RFU0 U/0V_ E FVQ_ F_M_RFU 0.U/0V_ H0 FVQ_ 0.U/0V_ H FVQ_ F_WK0 0 0.U/0V_ H FVQ_ F_WK0_N 0.U/0V_ H FVQ_ F_WK H FVQ_ F_WK_N H FVQ_0 F_WK PLE LOSE TO G H FVQ_ F_WK_N H FVQ_ F_WK 00 0U/.V_ H FVQ_ F_WK_N 0 0U/.V_ H0 FVQ_ U/.VS_ H FVQ_ F_WK0 U/.VS_ H FVQ_ F_WK0_N H FVQ_ F_WK H FVQ_ F_WK_N H FVQ_ F_WK H FVQ_0 F_WK_N L FVQ_ F_WK M FVQ_ F_WK_N N FVQ_ P FVQ_ RSV R FVQ_ T FVQ_ F_LL_V T0 FVQ_ T FVQ_ F_PLL_V V FVQ_ W FVQ_0 FVQ_PROE W0 FVQ_ W FVQ_ GN_PROE Y FVQ_ FVQ_ F_L_P_VQ F_L_PU_GN F_LTERM_GN L VM_Q0 M VM_Q L VM_Q M VM_Q N VM_Q P VM_Q R VM_Q P VM_Q J VM_Q H VM_Q J VM_Q0 H VM_Q G VM_Q E VM_Q E VM_Q F0 VM_Q VM_Q VM_Q VM_Q VM_Q F VM_Q0 F VM_Q H VM_Q H VM_Q P VM_Q P VM_Q P VM_Q P VM_Q L VM_Q L VM_Q L VM_Q0 L VM_Q G VM_Q F VM_Q G VM_Q F VM_Q 0 VM_Q VM_Q VM_Q VM_Q J VM_Q0 K VM_Q J0 VM_Q K VM_Q M VM_Q M VM_Q N VM_Q M0 VM_Q N VM_Q N VM_Q P0 VM_Q0 P VM_Q M VM_Q L VM_Q K VM_Q K VM_Q VM_Q VM_Q 0 VM_Q VM_Q F VM_Q0 G VM_Q G VM_Q G VM_Q R0 R R F_EUG F_EUG H R K L0 H J G0 G J K J0 J J J H J J J E PS_F_LMP K +F_PLLV U +F_PLLV F FVQ_SENSE F F_GN_SENSE J F_L_P_VQ U NM-GS F_M0 0 F_M[0:0] F_M E F_M0 (F_M) F_00 F_M F F_M (F_M) F_0 F_M F_M MEMORY I/F F_0 F_M F_M (F_M0) F_0 F_M F_M (F_M0) F_0 F_M F_M (F_M) F_0 F_M G F_M (F_M) F_0 F_M F F_M F_0 F_M E F_M (F_M) F_0 F_M0 F_M (F_M) F_0 F_M F_M0 (F_M0) F_0 F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M E F_M (F_M) F_ F_M F F_M (F_M) F_ F_M 0 F_M (F_M) F_ F_M0 0 F_M (F_M) F_ F_M F_M0 (F_M) F_0 F_M F_M (F_M) F_ F_M G F_M (F_M) F_ F_M G F_M (F_M) F_ F_M F F_M(F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M F_M (F_M) F_ F_M0 F_M (F_M) F_ E F_M0 F_0 F_M (N) F_ F_ VM_M0 E F_ 0 VM_M[:0] VM_M E F_QM0 F_ VM_M F_QM F_ VM_M F_QM F_ VM_M F F_QM F_ VM_M F F_QM F_ VM_M 0 F_QM F_ VM_M F_QM F_0 F_QM F_ F_ VM_WQS0 0 F_ 0 VM_WQS[:0] VM_WQS F_QS_WP0 F_ VM_WQS F_QS_WP F_ VM_WQS F_QS_WP F_ VM_WQS E F_QS_WP F_ VM_WQS E F_QS_WP F_ VM_WQS 0 F_QS_WP F_ VM_WQS F_QS_WP F_0 F_QS_WP F_ F_ VM_RQS0 F_ 0 VM_RQS[:0] VM_RQS E F_QS_RN0 F_ VM_RQS F_QS_RN F_ VM_RQS F_QS_RN F_ VM_RQS F_QS_RN F_ VM_RQS F_QS_RN F_ VM_RQS 0 F_QS_RN F_ VM_RQS F_QS_RN F_0 F_QS_RN F_ F_ F_ F_LK0 F_LK0_N VM_LK0 F_LK VM_LK0# F_LK_N VM_LK VM_LK# (F_EUG) F_EUG0 *0./F_ R (N) F_EUG +.V_GFX *0./F_ R F_M_RFU0 F_M_RFU F_WK0 F_WK0_N F_WK F_WK_N F_WK F_WK_N F_WK F_WK_N F_WK0 F_WK0_N F_WK F_WK_N F_WK F_WK_N F_WK R 0_ F_WK_N F_LMP, R 0K_ F_PLL_V 0.U/0V_ PLE NER G LOSE TO PS +F_PLLV : m H0KF-00T0 L +.0V_GFX R0 *0_ +.V_GFX U/.VS_ PLE LOSE TO G R *0_ 0.U/0V_ R 0./F_ +.V_GFX 0.U/0V_ H F_L_PU_GN R./F_ PLE LOSE TO LL H F_L_TERM_GN R _ G VM_Q0 E VM_Q G VM_Q F VM_Q F VM_Q G VM_Q F VM_Q G VM_Q G VM_Q F VM_Q E VM_Q0 F VM_Q F VM_Q G VM_Q E VM_Q F VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q F VM_Q G VM_Q E VM_Q G VM_Q VM_Q E VM_Q G VM_Q F VM_Q G VM_Q0 VM_Q G VM_Q E VM_Q E VM_Q F VM_Q E0 VM_Q 0 VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q VM_Q0 VM_Q VM_Q VM_Q E E0 F0 G F_EUG G0 F_EUG 0 F E F E H +F_PLLV F_M R 0K_ F_M R 0K_ F_M R 0K_ F_M R 0K_ F_M R 0K_ F_M R *0K_ F_M R *0K_ F_M R *0K_ F_M R *0K_ F_M R *0K_ VM_Q[:0] VM_Q[:0] VM_Q[:0] VM_Q[:0] 0 VM_LK0 0 VM_LK0# 0 VM_LK 0 VM_LK# 0 *0./F_ R +.V_GFX *0./F_ R 0.U/0V_ PLE LOSE TO LL PROJET : TWS Quanta omputer Inc. PLE LOSE TO GPU LLS,,0,,, +.V_GFX +.0V_GFX Size ocument Number Rev N ustom NM-GS - / (Memory) Friday, ugust, 0 Sheet ate: of

16 H G G J U NM-GS IFP_PLLV IFP_IOV IFP_IOV IFP_RSET [IFP/_LVS] IFP_TX IFP_TX_N IFP_TX0 IFP_TX0_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N IFP_TX IFP_TX_N M N P N N M L K J H J H P P M L N M K L F G F G F N IFP_PLLV IFP_UX_IW_SL [IFP/_TMS] IFP_UX_IW_S_N IFP_PLLV IFP_L0 IFP_L0_N IFP_L IFP_L_N IFP_L IFP_L_N IFP_L IFP_IOV IFP_L_N IFP_IOV IFP_RSET IFP_RSET IFP_UX_IX_SL IFP_UX_IX_S_N IFP_L0 IFP_L0_N IFP_L IFP_L_N IFP_L IFP_L_N IFP_L IFP_L_N G G K J J J H H G G K K M M M M L L K K IFPEF_PLLV IFPE_IOV IFPF_IOV IFPEF_RSET [IFPE/F_P] IFPE_UX_IY_SL IFPE_UX_IY_S_N IFPE_L0 IFPE_L0_N IFPE_L IFPE_L_N IFPE_L IFPE_L_N IFPE_L IFPE_L_N IFPF_UX_IZ_SL IFPF_UX_IZ_S_N IFPF_L0 IFPF_L0_N IFPF_L IFPF_L_N IFPF_L IFPF_L_N IFPF_L IFPF_L_N F F E E F F G F G0 P P _V _VREF _RSET [/_RT] _RE _GREEN _LUE _HSYN _VSYN K L0 L M N +.0V_GFX L0 H0KF-00T0 PLLV : 00m NV_PLLV PLLV I_SL I_S R R I_SL I_S R R 0.K_.K_ LK_M_VG_ R *0_ U/.VS_ 0.U/0V_ SP_PLLV E SP_PLLV 0P/0V_ 0 0P/0V_ Y MHZ +-0PPM XTLOUT +.0V_GFX L H0KF-00T0 U/.VS_.U/.V_ 0.U/0V_ VI_PLLV 0.U/0V_ VI_PLLV [XTL IN] XTL_IN XTL_OUT XTL_OUTUFF XTL_SSIN H H J H LK_M_VG_ XTLOUT R R 0K_ 0K_ PROJET : TWS Quanta omputer Inc. PLE LOSE TO GPU PLE LOSE TO LLS,,,,, +V_GFX +.0V_GFX Size ocument Number Rev N NM-GS - / (isplay) ate: Friday, ugust, 0 Sheet of

17 NP-GV I: Netname NP-GS ROM_SO 0K PU ROM_SLK K PU STRP0 K PU STRP K P UE NM-GS [MIO] ROM_SI ROM_SO ROM_SLK R *.K/F_ R 0K/F_ R K/F_ R *0K/F_ +V_GFX R K/F_ R *K/F_ STRP0 STRP STRP STRP STRP R0.K/F_ R0 *.K/F_ R *.K/F_ R.K/F_ R0 *K/F_ R0 K/F_ R0 *.K/F_ R0.K/F_ +V_GFX R0 *0K/F_ R0.K/F_ Logical Strap it Mapping.K/F_: SF RES HIP.K /W +%(00) 0K/F_: S00F RES HIP 0K /W +% (00) K/F_: S0F RES HIP K /W +% (00) 0K/F_: S00F RES HIP 0K /W +-%(00) 0.K/F_: S0F RES HIP 0.K /W +-%(00).K/F_: SF RES HIP.K /W +-% (00).K/F_: SF RES HIP.K /W +-% (00) STRP K P STRP STRP F_LMP_TGL_REQ# JTG_TI VG_OVT# LERT K P K P +V R 0K_ +V_GFX R *0K_ R 0K_ R 0K_ [MIO] VRM (R / 000MHz) onfiguration Table ROM_SI G Samsung Mx G Hynix Mx G Samsung Mx G Micron Mx efault: SM G VRM VRM (RL / 00MHz) onfiguration Table ROM_SI.K P G Samsung Mx.K P.K P G Micron Mx 0.K P 0K P 0K P G Samsung Mx G Micron Mx 0K P 0K P NP-GV I: 0x Netname ROM_SO ROM_SLK STRP0 STRP STRP STRP STRP NP-GV K PU K P K PU K P K P K P K P GPU_PROHOT# R 0K_ +V_GFX PEGX_RST# JTG_TRST# R 0K_ GPIO0 Q0 N00 F_LMP VG_OVT# +V_GFX Q *N00 GPU_OVT# GPIO SSIGNMENTS.K_.K_ R R R R.K_.K_ JTG_TI JTG_TRST# NE_SL NE_S GPU_EILK GPU_EIT GFx_SL GFx_S M0 P M P N R R R R T T K K JTG_TK GPIO0 JTG_TMS [MIS_GPIO/I/JTG/THER] GPIO JTG_TI GPIO JTG_TO GPIO JTG_TRST_N GPIO GPIO GPIO I_SL GPIO I_S GPIO GPIO GPIO0 I_SL GPIO I_S GPIO GPIO GPIO IS_SL GPIO IS_S GPIO GPIO GPIO THERMP GPIO THERMN GPIO0 GPIO P M L P P L M N M M L M N M N P R M R P P P GPIO0 GPIO R VG_OVT# LERT R 0_ *0_ R0 *0_ R 0K_ F_LMP,, GPU_STNY 0 GPU_PWM_VI 0 GPU_PROHOT#,0 GPU_PSI 0 +V_GFX GPIO R 0K_ Q N00 +V +V_GFX 0.U/0V_ F_LMP_TGL_REQ# R0 STRP0 STRP STRP STRP STRP 0.K/F_ J J STRP0 J STRP J STRP J STRP STRP J MULTISTRP_REF_GN, [MIS_ROM] GPU_F_EN ROM_SLK H ROM_S_N H H ROM_SI ROM_SO H UFRST_N E L L 0 ROM_SLK ROM_SI ROM_SO MEK00V-0 MEK00V-0 R0, GPU_F_EN *0K_ F_LMP,, +V +V_GFX +V_GFX GPU_V_EN,0, Q *NSZPX GFx SMus Isolation R R0 GFx_SL GFx_S.K_.K_ R Q N00W F_LMP,, GPU_V_EN,0, R *0_ *0_ +V_GFX R Type Samsung KWGE- Quanta P/N: KMGGT0 Micron MTJMJT-0G:K Quanta P/N: KMGSTL0 MLK,,,, MT,,,, (G bits) (G bits) onfiguration * x pcs * x pcs PROJET : TWS Quanta omputer Inc. Size G G Size ocument Number Rev N ustom NM-GS - / (MIS) ate: Friday, ugust, 0 Sheet of