Quanta Y11C - Schematics.

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1 IS (" / " / ") Lay-Vine Intel resent ay ULT Platform lock iagram RL SOIMM Maxima Gs PGE RL SOIMM Maxima Gs PGE System IOS SPI ROM PGE ST0 - st H Package :. (mm) Power : PGE ST O Package :. (mm) Power : PGE 0 mst / NGFF SS Package : (mm) Power : PGE RL RL ST0 G/s ST G/s ST G/s roadwell U Processor Processor : aul ore Power : (Watt) Package : G Size : 0 X (mm) Pre-L US.0 Interface PGE ~0 SPI Interface Fingerprint amera TPM Port Port Touch Screen Port SLTT. PGE PGE PGE Elan EKTH for "," Elan EKTH for " LP Interface PIE Gen x Lane PGE zalia PI-E X Lane ep X P Port US.0 Interface NVII NP-GT Package *mm W MHz PGE PGE ~ US.0 Port,,(US.0 Port 0,,) VRM R x M X X 00Mhz RT Package : QFN- PGE PGE LVS (H) PGE / ep PGE / HMI onn PGE US.0 Port x PGE P L STK UP LYER : TOP LYER : SGN LYER : IN(High) LYER : IN(Low) LYER : SV LYER : OT 0 G-Sensor HPTR PGE Keyboard PGE SM US ite Embedded ontroller Power : Package : LQPF udio odec L Power : Package : MQFN ard Reader RTS-GR Power : Package : LQPF LN ontroller RTLGSH(Giga) RTLGSH(0/00) Power : Package : OFN Halt Mini ard Intel Rambo Peak WLN / T ombo Port Touch Pad PGE Size : x (mm) PGE Size : x (mm) PGE Size : x (mm) PGE Int PGE PGE FN PGE Speaker PGE Head Phone MP HP0RTJR PGE ombo Jack PGE Subwoofer PGE Subwoofer MP HP00RTJR PGE igital MI PGE PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom lock iagram N ate: Sheet of Tuesday, September 0, 0

2 ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms / del / del [] IN_# [] IN_# [] IN_0# [] IN_LK# [] IN_ [] IN_ [] IN_0 [] IN_LK TP0 [] INT_eP_UXP [] INT_eP_UXN [] INT_eP_TXP0 [] INT_eP_TXP [] INT_eP_TXN0 [] INT_eP_TXN ep_romp EP_ISP_UTIL INT_eP_UXP INT_eP_UXN INT_eP_TXP0 INT_eP_TXP INT_eP_TXN0 INT_eP_TXN +VIO_OUT R U P_LNE0_N P_LNE_N I_TXN0 P_LNE_N I_TXN P_LNE_N I_TXN P_LNE0_P I_TXN P_LNE_P I_TXP0 P_LNE_P I_TXP P_LNE_P I_TXP I_TXP I_TXN0 I_TXN I_TXN 0 I_TXN I_TXP0 0 I_TXP I_TXP I_TXP 0 EP_ROMP EP_ISP_UTIL EP_UXP EP_UXN ep_txp0 ep_txp ep_txp ep_txp ep_txn0 ep_txn ep_txn ep_txn *HSW_ULT_RL ep./f_ ep_romp PI EXPRESS* - GRPHIS [,] H_PROHOT# TP TERR# [] E_PEI E_PEI R./F_ PROHOT# R 0K/F_ PROPWRG U PRO_ETET# K TERR# N PEI K PROHOT# PROPWRG PWR MNGEMENT THERML MIS JTG & PM R SM_RMRST# SM_ROMP0 SM_ROMP SM_ROMP SM_PG_NTL PRY# PREQ# PRO_TK PRO_TMS PRO_TRST# PRO_TI PRO_TO PM#0 PM# PM# PM# PM# PM# PM# PM# V SM_RMRST# U0 SM_ROMP_0 V0 SM_ROMP_ U SM_ROMP_ V J K E0 E E F F J0 H0 H H K H K0 J XP_TK0 XP_TMS_PU XP_TRST#_PU XP_TI_PU XP_TO_PU R R0 R 00/F_ /F_ 00/F_ R_PG_NTL [] XP_PRY#_PU [] XP_PREQ#_PU [] XP_TK0 [,] XP_TMS_PU [] XP_TRST#_PU [,] XP_TI_PU [] XP_TO_PU [] XP_PM0 [] XP_PM [] +.VSUS R 0_ R_RMRST# [,] 0 ep_ompio and IOMPO signals should be shorted near balls and routed with typical impedance < mohms *HSW_ULT_RL Processor pull-up (PU) H_PROHOT# XP_TO_PU R _ +V.0S_VST R0 _ +V.0S_VST XP_TMS_PU R *_ XP_TI_PU 公公公公公公公公公公公 R0 *_ XP_TRST#_PU R0 _ XP_TK0 R _ PROJET : Y Quanta omputer Inc. N Size ocument Number Rev ustom ULT /(ep/i) ate: Sheet of Tuesday, September 0, 0

3 [] M Q[:0] [] M Q[:0] [] M QSN[:0] [] M QSP[:0] [] M QSN[:0] [] M QSP[:0] Haswell ULT Processor (RL) 0 U [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q U H H S_Q0 K S_Q K S_Q H S_Q H0 S_Q K S_Q K0 S_Q M S_Q M S_Q P S_Q P S_Q0 M S_Q M0 S_Q P S_Q P0 S_Q P S_Q R S_Q M S_Q K S_Q L S_Q K S_Q0 R S_Q N S_Q P S_Q R S_Q M S_Q K S_Q L S_Q K S_Q R S_Q N S_Q0 Y S_Q W S_Q Y S_Q W S_Q V S_Q U S_Q V S_Q U S_Q Y S_Q W S_Q0 Y S_Q W S_Q V S_Q U S_Q V S_Q U S_Q K0 S_Q K S_Q M S_Q M S_Q0 K S_Q K S_Q M0 S_Q M S_Q M S_Q K S_Q M S_Q K S_Q M S_Q K S_Q0 M S_Q K S_Q S_Q U V S_0 Y S_ S_ U Y S_S# W S_RS# S_WE# R SYSTEM MEMORY S_LK0 S_LK#0 S_KE0 S_LK S_LK# S_KE S_KE S_KE S_S#0 S_S# S_OT0 S_QSN0 S_QSN S_QSN S_QSN S_QSN S_QSN S_QSN S_QSN S_QSP0 S_QSP S_QSP S_QSP S_QSP S_QSP S_QSP S_QSP S_M0 S_M S_M S_M S_M S_M S_M S_M S_M S_M S_M0 S_M S_M S_M S_M S_M V U U Y W W Y Y P R P J N M M V V L L J N N N W W L L U Y R P U R V0 W Y U0 P W U R V U M QSN0 M QSN M QSN0 M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP0 M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M [:0] [] [] M S#0 [] M S# [] M S# [] M S# [] M RS# [] M WE# M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q Y W Y W V U V U Y W Y W V U V U M K L K R N R P N R R P K M K L Y W Y W V U V U Y W Y W V U V U R R L M N P K K N0 R0 K L K0 M0 R P L M U M M K S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q S_Q0 S_Q S_Q S_Q S_0 S_ S_ S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK0 S_LK#0 S_KE0 S_LK S_LK# S_KE S_KE S_KE S_S#0 S_S# S_OT0 S_QSN0 S_QSN S_QSN S_QSN S_QSN S_QSN S_QSN S_QSN S_QSP0 S_QSP S_QSP S_QSP S_QSP S_QSP S_QSP S_QSP S_M0 S_M S_M S_M S_M S_M S_M S_M S_M S_M S_M0 S_M S_M S_M S_M S_M N M Y L K U0 W V0 M K L W0 V N N W V N N V0 W M M V W M M P0 R0 P R R P W Y Y U K V U K R P M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LKP0 [] M LKN0 [] M KE0 [] M LKP [] M LKN [] M KE [] M S#0 [] M S# [] M [:0] [] *HSW_ULT_RL SM_VREF_ SM_VREF_Q0 SM_VREF_Q P SM_VREF R SMR_VREF_Q0_M P SMR_VREF_Q_M 0mils width SM_VREF [] SMR_VREF_Q0_M [] SMR_VREF_Q_M [] INT *HSW_ULT_RL PROJET : Y Quanta omputer Inc.

4 U/.V_ U/.V_ U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ 0 U/.V_ +V_ORE 0 0 U/.V_ U/.V_ U/.V_ E E E E E E E U/.V_ U/.V_ U/.V_ E E E E E E E E U/.V_ U/.V_ U/.V_ E E E F F F F F0 U/.V_ U/.V_ U/.V_ F F F F G G G 0 G U/.V_ U/.V_ U/.V_ G G G G G G G G U/.V_ U/.V_ G G G G G G H J U/.V_ U/.V_ K K L M M P U W U/.V_ U/.V_ U/.V_ G PV install for RF F UF V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V POWER HSW ULT POWER VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ RSV RSV RSV RSV RSV RSV RSV RSV RSV VIO_OUT VIO_OUT VILERT# VISLK VISOUT PWR_EUG# VR_EN VR_REY VST VST VST H J J J N P R Y Y0 Y Y0 P T 0 E0 G U V E0 L N L H F0 E E lose to PU irect tie to PU V/-all H_PU_SVILRT# VR_SVI_LK H_PU_SVIT PWR_EUG R 0U/.V_.U/.V_ 0K_ +V.0S_VST 0U/.V_. FG0- need Reserve TP +.VSUS.U/.V_ 0U/.V_.U/.V_.U/.V_ +VIO_OUT +VIO_OUT IMVP_PWRG_R 0U/.V_ +VIO_OUT 0.U/.V_ 0U/.V_ PWR_EUG [] 0U/.V_ H_VR_ENLE_MP [] IMVP_PWRG_R [,] IMVP_PWRG [,] Layout note: need routing together and LERT need between LK and T. H_PU_SVILRT# VR_SVI_LK H_PU_SVIT R _ [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] [] +V.0S_VST R /F_ FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG SVI LERT SVI LK +V.0S_VST Place PU resistor close to VR R 0/F_ *0.U/0V_ SVI T FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG VR_SVI_LERT# [] VR_SVI_LK [] VR_SVI_T [] R./F_ R.K/F_ FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG_ROMP T_IREF 0 0 Y Y Y0 V V V0 U0 T T T T0 U U V E J0 H V U UE FG0 FG FG FG FG FG FG FG FG FG FG0 FG FG FG FG FG FG FG FG FG FG_ROMP RSV RSV RSV RSV RSV T_IREF RSV_TP RSV_TP RSV_TP RSV_TP RSV *HSW_ULT_RL +VPU RESERVE R.K/F_ R0 RSV_TP RSV_TP RSV_TP RSV RSV RSV PRO_OPI_ROMP RSV RSV RSV RSV L0 N0 W Y Y V P N P0 R0 IO Thrm Protect For degree,.v limit, (SW) 0 0.U/0V_.K/F_ For degree,.v limit, (HW) PRO_OPI_ROMP R./F_ 0 VST_PWRG H_VST_PWRG_R H_VST_PWRG THRM_MOINTOR [] L J N E T U V F H J N R T U0 L M P U0 U RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV_TP RSV_TP RSV_TP RSV_TP V_SENSE _SENSE P0 P N N E E 00- ±% pull-up to V near processor. R0 R0 00/F_ +V_ORE V_SENSE [] _SENSE [] 00/F_ +V.0S_VST R 0K_ [,,,,] HWPG R0V-0 H_VST_PWRG [] *0P/0V_ +.0V THER_PU R 00K_ NT 0.U/0V_ +V.0S_VST *U/.V_ 0 *U/.V_ RSV RSV W Y +V.0S_VST *HSW_ULT_RL R 0/F_ PWR_EUG +VIO_OUT [] +VIO_OUT [] Processor Strapping FG (Physcial ebug Enable) FX Privacy FG (P Presence Strap) isable: The FG signals have a default value of '' if not terminated on the board. 0 isable; No physical P attached to ep Enable: Set FX Enable in FX interface MSR Enable; n ext P device is connected to ep FG FG ircuit R *K_ R K_ R *0K_ PROJET : Y Quanta omputer Inc. +.VSUS [,,,,] +.0V [,,,0,,,,,,0] +V_ORE []

5 0 INT _TEST_Y_W _TEST_Y_W _TEST_Y_W _TEST_Y_W _TEST TEST TEST TEST TEST TEST TEST_0 TEST TEST TEST_Y_W _TEST_Y_W _TEST_Y_W TEST_W _TEST_Y_W TEST_V TEST_W TEST_Y0 TEST_ Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Y N ULT / (RSV,GN) ustom Tuesday, September 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Y N ULT / (RSV,GN) ustom Tuesday, September 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Y N ULT / (RSV,GN) ustom Tuesday, September 0, 0 UI *HSW_ULT_RL 0 E E F0 F F0 F F F F F0 F F F G G G G G G H H H J0 J J J K K L L L L L0 L L L M N0 N P P R0 R R T T U0 U U U V0 V V W0 W Y0 Y Y V H V H ISY_HIN_NTF_Y Y ISY_HIN_NTF_Y Y ISY_HIN_NTF_Y0 Y0 ISY_HIN_NTF_Y Y ISY_HIN_NTF_Y Y ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_0 0 ISY_HIN_NTF_ ISY_HIN_NTF_ ISY_HIN_NTF_V V ISY_HIN_NTF_W W ISY_HIN_NTF_W W ISY_HIN_NTF_W W ISY_HIN_NTF_W W ISY_HIN_NTF_W W ISY_HIN_NTF_W W TP TP TP UG *HSW_ULT_RL E0 E E F F F F F F G G G G G0 G G G H H H0 H H H H0 H H H H H0 H H H H H H H J J J J J J J J J J J J J0 J J J J J0 J K K K L L L0 L L L L L L L L L0 L L L L L L L0 L M M M M M N N N N N N N N0 N N N N N N N N0 N N P0 P L0 N P0 TP TP UH *HSW_ULT_RL P P P P P P P P P P P P R R R R R R R R R R R T T T T0 T T T T T T T U U U U0 U U U U U0 U U U U U U V V V0 V V V V V V V V V V V V V V W W W W W W W0 W W W W0 W W W0 Y Y Y Y Y Y Y0 Y Y Y Y Y Y Y TP TP TP

6 Lynx Point-LP Platform ontroller Hub (LVS,I) UM 0 [] PH_LVS_LON [] PH_ISP_ON [] PH_PST_PWM PH_LVS_LON PH_ISP_ON PH_PST_PWM EP_KLEN EP_VEN EP_KLTL EP SIEN P_TRLLK P_TRLT P_UXN P_UXP P_HP SVO_LK SVO_T HMI_HP_ON SVO_LK [] SVO_T [] HMI_HP_ON [] INT. HMI UL for S PV..dd SUSWRN# to SUSK#...00 SUSWRN# R *0_ [] SUSK#_E [,] SYS_PWROK [,] E_PWROK [] RSMRST# [] SUSWRN#_E PV..dd SUSWRN# to SUSK#...00 [,] NSWON# [] _PRESENT_E [] SYS_RESET# R 0_ *0.U/0V_ SYS_RESET# E_PWROK E *0P/0V_E_PWROK E *0P/0V_ R 0_ PLTRST# RSMRST# SUSWRN# NSWON#_R _PRESENT_R SI..hange RF_OFF_PH to GPIO.../ R *0_/S PM_TLOW# [,] RF_OFF_PH [,] PH_SLP_S0_N TP PH_SLP_S0_N PIO SWVRMEN [] For S -->Ra SWVRMEN SWVRMEN W Non-S -->Rb Ra R *0_/S PWROK_E PWROK_E [] SUSK# K V PWROK R *0_ RSMRST# SUSK# PWROK Rb G Y G System Power Management J W SLP_S# RSMRST# V SUSWRN#/SUSPWRNK/GPIO0(SUS) SLP_S# T L J N F M SYS_RESET# SYS_PWROK PH_PWROK PWROK PLTRST# PWRTN# PRESENT / GPIO(SW) TLOW# / GPIO(SW) SLP_S0# SLP_WLN#/ GPIO(SW) *HSW_ULT_RL WKE# LKRUN#/ GPIO SUS_STT# / GPIO (SUS) SUSLK / GPIO (SUS) SLP_S# / GPIO ( SW) SLP_# SLP_SUS# SLP_LN# J V G E P L P J PIE_WKE# LKRUN# SLP_SUS# PIE_WKE# [,,,] LKRUN# [] SLP_S# [] SUS# [,] SUS# [,] SLP_# [] SLP_SUS#_E for S SLP_SUS#_E [] *HSW_ULT_RL ISPLY P_TRLLK P_TRLT P_UXN P_UXP P_HP EP_HP INT_eP_HP_Q PH Pull-high/low(LG) PM_TLOW# PIE_WKE# R R hange to k for LN wake from OFF state issue SUSK# R SUSWRN# R heck SUSWRN# need PU? 0K_ K_ +VS +V_EEP_SUS 0K_ for S 0K_ PLTRST#(LG) PLTRST# R 00K_ heck Q00 Rise/Fall time less than 00ns PLTRST# [,,,,,] Reserve EP_HP opposites circuit! +VIO_OUT System PWR_OK(LG) SYS_PWROK E_PWROK R0 0K_ [,,,0,,,,,,,,,,,0,,,,,0] [,,0,,,,,,,,,,0] +V +VS PWRTN# internally PU in PH to.v_sw R G V0. -> 0K *0K/F_ SH V0. -> K +V INT_eP_HP_Q INT_eP_HP LKRUN# SYS_RESET# RSMRST# R R R.K/F_ 0K_ 0K_ ULT_EP_HP [] R 00K_ RTR Vender request P 00kohm PROJET : Y Quanta omputer Inc. PWROK_E R 00K_ N Size ocument Number Rev ustom ULT /(Power Manger) ate: Sheet of Tuesday, September 0, 0

7 +V_RT Lynx Point-LP Platform ontroller Hub (H,JTG,ST) PH Strap Table SPKR GSPI0_MOSI /GPIO GPIO Pin Name Strap description Sampled onfiguration SIO_0 /GPIO SWVRMEN [] RT_RST# R [] Z_SIN0 [,] XP_TRST#_PU [] JTG_TK_PH [] JTG_TI_PH [] JTG_TO_PH [] JTG_TMS_PH [,] JTGX_PH TP No reboot mode setting Top-lock Swap TLS onfidentiality eep Sx Well On-ie Voltage Regulator Enable PWROK PWROK PWROK PWROK 0 efault (weak pull-down 0K) = Setting to No-Reboot mode 0 "top-block swap" mode = efault (weak pull-up 0K) INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up H_SO /IS0_TX Z_LK Z_SYN Z_RST# Z_SOUT XP_TRST#_PU JTG_TK_PH JTG_TI_PH JTG_TO_PH JTG_TMS_PH JTGX_PH UJ RT_X W RTX RT_X Y RTX RT_RST# U RTRST# SRT_RST# V SRTRST# M_ SM_INTRUER# U INTRUER# PH_INVRMEN V INTVRMEN Flash escriptor Security Only for Interposer oot IOS Selection *HSW_ULT_RL RT UIO SPI JTG PWROK LWYS ST LP J W ST_RN0/ PERN_L H H_LK / IS0_SLK ST_RP0/ PERP_L V ST_TN0/ PETN_L H_SYN/ IS0_SFRM ST_TP0/ PETP_L J ST_RN/ PERN_L H U ST_RP/ PERP_L H_RST#/ IS_MLK ST_TN/ PETN_L ST_TP/ PETP_L Y0 J H_SIN0/ IS0_RX ST_RN/ PERN_L H U ST_RP/ PERP_L H_SIN/ IS_RX ST_TN/ PETN_L U ST_TP/ PETP_L H_SO/ IS0_TX F W0 ST_RN/ PERN_L0 E H_OK_EN# / IS_TX ST_RP/ PERP_L0 V0 ST_TN/ PETN_L0 H_OK_RST/ IS_SFRM ST_TP/ PETP_L0 Y IS_SLK U PH_TRST# E PH_TK PH_TI E PH_TO L PH_TMS RSV RSV E V JTGX RSV PH_SPI_LK SPI_LK PH_SPI_S0# Y SPI_S0# Y SPI_S# SPI_S# PH_SPI_SI SPI_MOSI PH_SPI_SO SPI_MISO PH_SPI_IO Y PH_SPI_IO F SPI_IO SPI_IO 0 efault (weak pull-down 0K) = an be Overridden U L0 W L Y L W L V LFRME# STLE# U GNT0# 0 ST_RXN0 ST_RXP0 ST_TXN0 ST_TXP0 ST_RXN ST_RXP ST_TXN ST_TXP ST_RXN ST_RXP ST_TXN ST_TXP ST0GP/ GPIO V _LE# STGP/ GPIO STGP/ GPIO U V SIO_EXT_SMI# PI_SERR# STGP/ GPIO STGP ST_ROMP ST_ROMP ST_IREF ST_IREF RSV L RSV K0 oot Location LP SPI(efault) 0 = ME rypto Transport Layer Security cipher suite with no confidentiality(efault) = Intel ME rypto TLS cipher suite with confidentiality Should be always pull-up L0 [,,] L [,,] L [,,] L [,,] LFRME# [,,] ST_RXN0 [0] ST_RXP0 [0] ST_TXN0 [0] ST_TXP0 [0] ST_RXN [0] ST_RXP [0] ST_TXN [0] ST_TXP [0] ST_RXN [] ST_RXP [] ST_TXN [] ST_TXP [] _LE# [] R R SIO_EXT_SMI# [] PI_SERR# [] 0K_.0K/F_ ircuit H (ST.0Gb/s) O (ST.0Gb/s) mst / NGFF (ST Gb/s) +V.0S_STPLL G recommended that ST coupling capacitors should be close to the connector (<00 mils) for optimal signal quality. +V_RT +.0V +V R0 ST_LE# [] +V_RT [] GPIO_E R R +.0VS *0_ 0K_ 0K_ R [] PH_SPI_S0#_R [] PH_SPI_LK_R [] PH_SPI_SI_R [] PH_SPI_SO_R R R *_ R _ R _ R0 _ *_ lose to hipset PH_INVRMEN K_ Z_SOUT SWVRMEN [] JTGX_PH PH_SPI_S0#_R PH_SPI_LK_R PH_SPI_SI_R PH_SPI_SO_R JTG_TMS_PH JTG_TI_PH JTG_TO_PH JTG_TK_PH RT lock.khz no stuff If use green lock Vender EON 0 Winbond Gigaevice Socket RT ircuitry(rt) +V_RT_0 +V_RT_0 *P/0V_ *P/0V_ +V_EEP_SUS Y *.KHz N T_ONN FHS0FS0 T-_-_ [] Z_SYN_UIO [] Z_RST#_UIO [] Z_SOUT_UIO [] IT_LK_UIO Size M M M RT Power trace width 0mils. PV modify +VPU R0 *K_ +V_RT_ *T Uninstall for Green-LK R *0P/0V_ P/N R R *0M_ RT_X PH SPI ROM(LG) H us(lg) KEEFP0N0 (WQFIQ) KEEGN0Q0 (GSIGR) 0mils KEEZN0Q0 (ENQH-0HIP) FHS0FS0 RT_X *K_ Z_SYN R _ R0 _ R _ R _ U0&U footprint 要要要 U/0V_ +VSPI R.K/F_ PH_SPI_IO R0 Z_SYN Z_RST# Z_SOUT Z_LK /F_ IOS_WP# +V [,,,0,,,,,,,,,,,0,,,,,0] +V [,,,,0,,,,0] +.0V [,,,0,,,,,,0] +VS [,,0,,,,,,,,,,0] +VPU [,,,,,,,] +V_RT [0,] +V.0S_STPLL [0] N *0_/S *U/.V_ LKGEN_RT_X [] +V_RT RT_RST# R RT_RST# 0K/F_ R 0K/F_ PV modify GPIO Pull UP _LE# SIO_EXT_SMI# PI_SERR# STGP R 0K_ *0_ SRT_RST# 0 RT_RST# SRT_RST# M SPI ROM Socket U PH_SPI_S0#_R PH_SPI_LK_R E# PH_SPI_SI_R SK PH_SPI_SO_R SI SO IOS_WP# WP# GSIGR KEEFP0N0 U/.V_ R R R R0 PH_SPI_IO E_RT_RST [] V +V 0K_ 0K_ 0K_ 0K_ 0.U/0V_ PROJET : Y Quanta omputer Inc. +VSPI HOL# HOL# *LQM-F/Q FHS0FS0 PH_SPI_S0#_R 0-00L-P-SOKET TP PH_SPI_LK_R TP0 PH_SPI_SI_R +VS R0 *0_ TP- need place to TOP TP PH_SPI_SO_R TP IOS_WP# +V_EEP_SUS R0 *0_/S TP HOL# TP U PH_SPI_S0# R /F_ PH_SPI_S0#_R +VSPI PH_SPI_LK R0 /F_ PH_SPI_LK_R E# V PH_SPI_SI R0 /F_ PH_SPI_SI_R SK R00.K/F_ PH_SPI_SO R /F_ PH_SPI_SO_R SI HOL# SO HOL# R0 /F_ R/R/R0/R/R/R close to U pin WP# P/0V_ Q N00 R J *SOLERJUMPER- U/.V_ Size ocument Number Rev ustom ULT /(ST/H) ate: Sheet of Tuesday, September 0, 0

8 PI/USO# Pull-up(LG) GPU_PWR_EN TS_INT#_ PIRQ# PIRQ# GPIO_ULT GPIO_ULT GPU_EVENT# G_F_EN GPU_HOL_RST# GPU_HOL_RST# SMLERT# US_O# US_O# US_O# US_O# US.0 [] [] [] [] [] [] [] [] R0 R R R R R R0 R R R SI modify R R R R R US0_RX- US0_RX+ US0_TX- US0_TX+ US0_RX- US0_RX+ US0_TX- US0_TX+ 0K_ 0K_ 0K_ 0K_ 0K_ 0K_ *0K_ *0K_ *0K_ 00K_ 0K_ 0K_ 0K_ 0K_ 0K_ 00 Modify US.0 for HM0 Lynx Point-LP Platform ontroller Hub (H,JTG,ST) 0 +V UN UK G [] US0_RX- F PERN / USRN [] US0_RX+ 0 PERP / USRP N SMLERT# [] US0_TX- PETN / USTN SMLERT# / GPIO(SUS) [] US0_TX+ PETP / USTP / Modify for P SM_PH_LK F SMLK [] US0_RX- G PERN/ USRN H SM_PH_T [] US0_RX+ amera PERP/ USRP SMT [] US0_TX- PETN/ USTN [] US0_TX+ PETP/ USTP L SML0LERT# [] PIE_RXN_WLN G SML0LERT# / GPIO0(SUS) WLN [] PIE_RXP_WLN F PERN N SM_ME0_LK [] PIE_TXN_WLN 0.U/0V_ PIE_TXN_WLN_ PERP SML0LK [] PIE_TXP_WLN 0.U/0V_ PIE_TXP_WLN_ 0 PETN K SM_ME0_T +V_EEP_SUS PETP SML0T for S F [] PIE_RXN_LN PIE_RXN_LN F L_LK LN [] PIE_RXP_LN PIE_RXP_LN G PERN U SMLLERT# TP0 [] PIE_TXN_LN 0.U/0V_ PIE_TXN_LN_ PERP SMLLERT# / PHHOT# / GPIO(SUS) L_T [] PIE_TXP_LN 0 0.U/0V_ PIE_TXP_LN_ PETN U SM_ME_LK F PETP SMLLK / GPIO(SUS) L_RST# [] PIE_RXN_R F0 H SM_ME_T PERN_L0 US.0(M/-) (USP0) [] PIE_RXP_R E0 SMLT / GPIO(SUS) US.0(M/-) (USP) [] PIE_TXN_R 0 0.U/0V_ PIE_TXN_R_ PERP_L0 [] PIE_TXP_R 0.U/0V_ PIE_TXP_R_ PETN_L0 PETP_L0 / Modify for GPIO_ULT TS_INT#_ PIRQ# PIRQ# GPIO_ULT GPU_PWR_EN GPU_HOL_RST# GPU_EVENT# G_F_EN G0 H0 E F U P N N L L R L U USRN USRP USTN USTP USRN USRP USTN USTP PIRQ#/ GPIO PIRQ#/ GPIO PIRQ#/ GPIO PIRQ#/ GPIO0 GPIO GPIO GPIO GPIO GPIO PME# PI US - Link USN0 USP0 USN USP USN USP USN USP USN USP USN USP USN USP USN USP USRIS# USRIS RSV RSV O0# / GPIO0(SUS) O# / GPIO(SUS) O# / GPIO(SUS) O# / GPIO(SUS) US.0 Small board(usp) FP Small board (USP) ardreader WLN TS N M R T R P R0 T0 M L M N P N R P (USP) (USP) / Modify for USP- [] USP+ [] USP- [] USP+ [] USP- [] USP+ [] [0] USP- [] USP+ [] USP- [] USP+ [] US_O# US_O# US_O# US_O# USP0- [] USP0+ [] USP- [] USP+ [] +V.0S_USPLL WLN [] [] / Modify for [] [] / Modify for LK_PIE_WLNN LK_PIE_WLNP PIE_LKREQ_WLN# [] LK_PIE_LNN LN [] LK_PIE_LNP TIE TRES TOGETHER LOSE TO PINS WITH LENGTH TO RESISTOR [] PIE_LKREQ_LN# ardreader [] LK_PIE_RN J0 US_IS R [] LK_PIE_RP J./F_ N0 M0 L T H V PIE_LKREQ_R# R0 / Modify for R PIE_IREF.0K/F_PIE_ROMP PIE_LKREQ0# PIE_LKREQ# LK_PIE_WLNN LK_PIE_WLNP PIE_LKREQ_WLN# LK_PIE_LNN LK_PIE_LNP PIE_LKREQ_LN# LK_PIE_RN LK_PIE_RP PIE_LKREQ_R# PIE_LKREQ# F E H0 G0 E F E E U Y N U T PERN_L PERP_L PETN_L PETP_L PERN_L PERP_L PETN_L PETP_L PERN_L PERP_L PETN_L PETP_L PIE_IREF PIE_ROMP RSV RSV LKOUT_PIE0N LKOUT_PIE0P PIELKRQ0# / GPIO LKOUT_PIE_N LKOUT_PIE_P PIELKRQ# / GPIO LKOUT_PIE_N LKOUT_PIE_P PIELKRQ# / GPIO0 LKOUT_PIE_N LKOUT_PI_P PIELKRQ# / GPIO LKOUT_PIE_N LKOUT_PIE_P PIELKRQ# / GPIO LKOUT_PIE_N LKOUT_PIE_P PIELKRQ# / GPIO *HSW_ULT_RL PI-E* LOK SIGNLS SMUS XTL_IN XTL_OUT LKOUT_ITPXP# LKOUT_ITPXP_P LKOUT_LP_0 LKOUT_LP_ IFFLK_ISREF RSV RSV TESTLOW_ TESTLOW_ TESTLOW_K TESTLOW_L N P K M K L XTL_IN XTL_OUT K_XP_N_R K_XP_P_R RP install for XP LK_PI_E_R LK_PI_LP_R R *0_ / non-stuff R XLK_ISREF R R R R 0K/F_ 0K/F_ 0K/F_ 0K/F_ R _ R _ R *0_PR_ RP.0K/F_ E E E P/0V_ EMI(near PH) P/0V_ EMI(near PH) *P/0V_ K_XP_N [] K_XP_P [] LK_M_K [] LK_M_EUG [] LK_PI_TPM [] +V.0S_XK_LPLL [0] *HSW_ULT_RL [,] MLK [,] MT SMus/Pull-up(LG) +V Q SM_ME_LK SM_ME_T LK_REQ/Strap Pin(LG) PIE_LKREQ0# R 0K_ PIE_LKREQ_R# R 0K_ PIE_LKREQ_WLN# R0 0K_ PIE_LKREQ_LN# R 0K_ PIE_LKREQ# R 0K_ PIE_LKREQ# R 0K_ / Modify for +V XTL_IN XTL_OUT PH_XTL_IN [] R *0_/S TP *P/0V_ R *M_ *MHZ +-0PPM Y *P/0V_ for S +V_EEP_SUS SMus/Pull-up(LG) R0.K_ SM_PH_LK R.K_ SM_PH_T R.K_ SM_ME0_LK R.K_ SM_ME0_T *N00W +V TP R R0.K_.K_ SM_ME_LK SM_ME_T +V R.K_ Q R R 0K_ K_ SMLLERT# SML0LERT# [,,,] SM_RUN_T +V [,,,] SM_RUN_LK R.K_ SM_PH_T SM_PH_LK PROJET : Y Quanta omputer Inc. N00W [,,,0,,,,,,,,,,,0,,,,,0] +V [,,,0,] +V_EEP_SUS N

9 [] SIO_EXT_SI# SIO_EXT_SI# T_OFF [] T_OFF [,] RF_OFF_PH R *0_ RF_OFF_PH_R LN_ISLE# GPIO_ULT / add GPIO for GPIO_ULT [,0] _M_EN R *0_ GPIO_ULT [0] ZERO_O_P# R *0_ O_PRSNT#_R / Modify for GPIO OR_I GPIO_ULT OR_I GPIO OR_I EVSLP0 [] EVSLP EVSLP EVSLP GPIO_ULT OR_I TP for G GPIO_ULT SI..hange EL_INT# to GPIO.../ OR_I T_OMO_EN# [] T_OMO_EN# [] EL_INT# GPIO_ULT [] _FW_GPIO R 0_ GPIO0_ULT / add GPIO for OR_I0 OR_I OR_I OR_I GPIO0_ULT MPHY_PWREN [0] MPHY_PWREN GPIO_ULT SPKR [] Z_SPKR [] SPKR Lynx Point-LP Platform ontroller Hub RP RP 0 (H,JTG,ST) Haswell (GPIO) I0_SL 0 SIO_ GSPI_MOSI URT_RX SIO_ GSPI0_MISO I0_S UO I_S SIO_M GSPI_MISO SIO_ GSPI0_LK SIO_LK URT0_TX 0 U PH_THRMTRIP# GSPI_LK GPIO(SUS) THRMTRIP# PM_THRMTRIP# [] 0K_0PR_ 0 M GPIO(SUS) 0K_0PR_ +V M GPIO0(SUS) RIN#/ GPIO V E_RIN# E_RIN# [] +V RP M SERIRQ R 0K_ 0 URT_RST LN_PHY_PWR_TRL / GPIO(SW) SERIRQ T +V URT0_RX SERIRQ [,] URT0_RTS T URT_TS URT0_TS GPIO(SUS) R GSPI0_S URT_TX H GPIO(SUS) PH_OPI_ROMP W PH_OPI_ROMP./F_ GSPI_S GPIO(SUS) RSV F0 0K_0PR_ Y +V GPIO RSV T GPIO GPIO (SUS) GPIO Pull-up/Pull-down(LG) +V_EEP_SUS M R GSPI0_S GPIO(SW) GSPI0_S/ GPIO SIO_EXT_SI# R 0K_ N L GSPI0_LK T_OFF R0 0K_ GPIO(SUS) GSPI0_LK/ GPIO RF_OFF_PH_R hange R Netname R 0K_ N N GSPI0_MISO GPIO_ULT R 0K_ GPIO(SW) GSPI0_MISO/ GPIO GPIO_ULT R 0K_ GPIO(SUS) GSPI0_MOSI/ GPIO L / add PU GPIO_ULT R0 0K_ P EVSLP0/ GPIO R GSPI_S L GSPI_S/ GPIO GPIO_ULT R 0K_ EVSLP/ GPIO L GSPI_LK GPIO_ULT R 0K_ N GSPI_LK/ GPIO EVSLP/ GPIO N GSPI_MISO K GSPI_MISO/ GPIO GPIO(SUS) K GSPI_MOSI +V G GSPI_MOSI/ GPIO0 GPIO(SUS) G J URT0_RX GPIO_ULT R 0K_ GPIO(SUS) URT0_RX/ GPIO GPIO0_ULT R 0K_ K URT0_TX O_PRSNT#_R R 0K_ GPIO(SUS) URT0_TX/ GPIO / Modify for GPIO R 0K_ U J URT0_RTS EVSLP0 R 0K_ GPIO URT0_RTS/ GPIO Y G URT0_TS EVSLP R 0K_ GPIO URT0_TS/ GPIO T_OMO_EN# R *0K_ P GPIO0_ULT R 0K_ GPIO0 K URT_RX E_RIN# R 0K_ G URT_RX/ GPIO0 GPIO LN_ISLE# GPIO(SUS) G URT_TX SUS -->heck list P URT_TX/ GPIO +V -->atasheet GPIO_ULT R 0K_ GPIO(SUS) J URT_RST MPHY_PWREN R 00K_ L URT_RST/ GPIO MPHY_PWREN R *0K_ GPIO(SUS) J URT_TS T URT_TS/ GPIO GPIO(SUS) F I0_S SIO_POWER_EN/ GPIO0 I0_S/ GPIO +VS Y F I0_SL HSIOP/ GPIO I0_SL/ GPIO GPIO_ULT R 0K_ G I_S P I_S/ GPIO LN_ISLE# R 0K_ MUSY# / GPIO F I_SL I_SL/ GPIO GPIO R 0K_ V SPKR/ GPIO SIO_LK/ GPIO E SIO_LK SIO_M/ GPIO F SIO_M lose to E +V.0S_VST SIO_0/ GPIO SIO_/ GPIO E SIO_ PM_THRMTRIP# R K_ SIO_/ GPIO SIO_ SIO_/ GPIO E SIO_ *HSW_ULT_RL GPIO PU/MIS SERIL IO Model OR_I[:] 0 amera OR_I Reserve OR_I 0 Pavillian Envy OR_I[:] 00 " 0 0 " " OR_I0 0:UM :IS R 0K_ OR_I0 R *0K_ R0 *0K_ OR_I R 0K_ +V_EEP_SUS R 0K_ OR_I R *0K_ R *0K_ OR_I R 0K_ R 0K_ OR_I R0 *0K_ R 0K_ OR_I R *0K_ R R0 R0 *0K_ 0K_ 0K_ OR_I OR_I OR_I R R R 0K_ *0K_ *0K_ Stuff N IS Ra Rb UM Rb Ra [,,,0,,,,,,,,,,,0,,,,,0] +V [,,0,,,,,,,,,,0] +VS N PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom ULT / (GPIO/MIS) ate: Sheet of Tuesday, September 0, 0

10 +.0V V_0=. +V.0S_ORE_PH UP POWER Lynx Point-LP Platform ontroller Hub (H,JTG,ST)(POWER) 0 TP +.0V +.0V +.0V Place close to Pin G and G0 SI modify VSW=m PV install for RF TP 0 U/.V_ +V.X_.X_O TP +V_EEP_SUS +VS U/.V_ U/.V_ 0U/.VS_ cpsus=0m U/.V_ *U/.V_ +V.0S_ILE *U/.V_ 0 U/.V_ U/.VS_ U/.V_ U/.VS_ U/.V_ U/.VS_ U/.VS_ VSUS_=m +V.0X_MOPHY_PH VHSIO=. VSTPLL=m +V.0S_STPLL SI hange to uf for Intel recommend cpsus=0m +V.0_VUSSUS cpsus=m 0 +V.0M_SW +V.0M_FHV0 +V.0M_FHV +V.0_SUS_PH +V.0S_USPLL +V.X_.X_PZSUS_PH U/.V_ U/.V_ U/.V_ U/.V_ G +PH_VSW G0 +V.0_USSUS U/.VS_ +V._PSUS J H H E F E F G G G 0 K L0 M N P J VH=m H H V_0 V_0 V_0 ORE V_0 V_0 PSUSYP PSUSYP VSW VSW VSW VSW VSW PSUS PSUS VHSIO VHSIO VHSIO V_0 VMPHY V_0 VUSPLL VSTPLL US PSUS H VH VRM PSUS GPIO/ L VSUS_ VSUS_ RT SPI I VSUS_ VRT PRT VSPI VLK VLK VLKPLL VLK VLK VLK RSV RSV RSV VSUS_ VSUS_ THERML SENSOR VTS_ V_ V_ OPI RSV VPLL VPLL SERIL IO VSIO VSIO SUS OSILLTOR H +V._SW_PRTSUS +V_EEP_SUS U/.V_ G0 VRT < m +V_RT U/.V_ E +VRTEXT 0.U/0V_ 0.U/0V_ +.0V_MOPHY 0.U/0V_ YVSPI=m *0.U/0V_ +V.M_PSPI +V_EEP_SUS R *0_.uH/00m_ +V J +V.0S_XK_ L U/.V_ +.0V K 00 U/.VS_ 0 U/.VS_ +V.0S_XK_LPLL L.uH/00m_ 0 U/.V_ +.0V VLKPLL=m J R T U/.VS_ U/.VS_ +V.0S_SSF00 +.0V VLK=00m U/.V_ +V.0S_SSFF +.0V K U/.V_ M0 V E0 +V._PSUS E +V._PSUS VTS_=m J +V.S_TS +.V +V.S_PTS +V K K V_=m 0.U/0V_.uH PN V-0JZ00 VPLL=m +.0V [] SLP_SUS_ON W 0 U/.V_ +V.0S_PLLOPI 0 *U/.VS_ 0 *U/.VS_ U VSIO=m T +V.S_.S_SIO_PH +V U/.V_ R 00K_ L L 0 U/.V_ *0P/0V_.uH/00m_.uH/00m_ +VS U IN IN 0mil 0mil +V.0S_STPLL +V.0S_USPLL for S ON/OFF I(P) GTU-Lay +V.0X_MOPHY_PH OUT GN +V_EEP_SUS 0.U/0V_ +VS VSW_=m+.V SW_P *U/.V_ 0.U/.V_ H0 VSW_ US PSUS cpsus=m +V.0_OSSUS U/.V_ +V U/.VS_ +V.S_PORE V W V_ V_ INT *HSW_ULT_RL RSV V_0 V_0 0 G +V.0S_US G 0 U/.V_ +.0V +V.X_.X_O R *0_ +.V R *0_/S +V [,,,,,,,,,,,,,,0,,,,,0] +V [] +V.0S_USPLL [,,,,0,,,,0] +V [] +V.0S_STPLL [] +V.0S_XK_LPLL [,,,,,,,,,0] +.0V [,] +V_RT [,,,,,,,,,,,,0] +VS [,,,,,] +.VSUS [,,,,,,,,0] +VS N PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom ULT /(POWER-) ate: Sheet of Tuesday, September 0, 0 0

11 [] H_VST_PWRG +.0V [] XP_PREQ#_PU [] XP_PRY#_PU [] FG0 [] FG [] FG [] FG [] XP_PM0 [] XP_PM [] FG [] FG [] FG [] FG H_VST_PWRG R K_ [] PWR_EUG 0 0.U/0V_ [,,,] SM_RUN_T [,,,] SM_RUN_LK [,] XP_TK0 R FG FG FG OSFN_0 OSFN_ FG FG FG FG VST_PWRG_XP NSWON# H_SYS_PWROK_XP XP_TK XP_TK0 K_ N *SE_SH-00-0-L---TR OSFN_0 OSFN_ FG FG FG0 FG OSFN_0 OSFN_ FG FG FG FG XP_RST XP_RESET_N XP_TO XP_TRST# XP_TI XP_TMS R0 FG [] FG [] FG [] FG [] FG0 [] FG [] FG [] FG [] FG [] FG [] FG [] FG [] K_XP_P [] K_XP_N [] K_ FG +.0V 0.U/0V_ XP_RESET_N R K_ +V H_SYS_PWROK_XP R0 *K_ +V_EEP_SUS 0.U/0V_ 0.U/0V_ +V 0.U/0V_ PS +V_EEP_SUS N 0 0 *ES_-0N +VS R *0_ SUS# [,,] SLP_S# [] SUS# [,] SLP_# [] RT_RST# [] NSWON# [,] SYS_RESET# [] PH_SLP_S0_N [,] SUS# [,,] +V_EEP_SUS [,,,,] HWPG XP_TI +V.0S_VST XP_TO XP_TI_R XP_TMS XP_TRST# R *_ R *0_ U V OE OE 0 OE OE P GN *SNTLVRGYR XP_TI_R XP_TO [,] SYS_PWROK XP_TO_PU [] XP_TI_PU [] XP_TMS_PU [] XP_TRST#_PU [,] H_SYS_PWROK_XP [,] JTGX_PH [] JTG_TMS_PH XP_TK0 XP_TMS [,,,,,] PLTRST# R K_ XP_RST [] JTG_TI_PH XP_TI [] JTG_TO_PH XP_TI_R R [] JTG_TK_PH *0_ R *0_ XP_TO XP_TK0 XP_TK PROJET : Y Quanta omputer ULT Inc. Size ocument Number Rev N HSW XP & PS ate: Tuesday, September 0, 0 Sheet of

12 R R0 [] M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# [] M WE# 0K/F_ 0K/F_ [,,,] SM_RUN_LK [,,,] SM_RUN_T [] M OT0 [] M OT [] M QSP[:0] [] M QSN[:0] PU racket M 0 M M M M M M M M M M 0 M M M M M IMM0_S0 IMM0_S SM_RUN_LK SM_RUN_T M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN IMM & Footprint 同 Joshua 提提 JIM M Q 0 Q0 M Q Q M Q Q M Q Q M Q Q M Q0 0 Q M Q Q M Q Q M Q Q M Q 0 Q M Q 0/P Q0 M Q Q M Q /# Q M Q 0 Q M Q Q M Q0 Q M Q 0 Q M Q0 0 0 Q M Q Q M Q Q 0 M Q S0# Q0 M Q 0 S# Q 0 M Q 0 K0 Q M Q 0 K0# Q M Q 0 K Q M Q K# Q M Q KE0 Q M Q KE Q M Q 0 S# Q M Q RS# Q M Q0 WE# Q0 0 M Q 0 S0 Q M Q 0 S Q M Q 00 SL Q M Q S Q M Q Q 0 M Q 0 OT0 Q M Q OT Q 0 M Q Q M Q M0 Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q0 0 M Q M Q M Q M Q M Q 0 M Q Q M Q QS0 Q M Q QS Q M Q0 QS Q0 M Q QS Q M Q QS Q M Q QS Q M Q QS Q M Q 0 QS Q M Q QS#0 Q M Q QS# Q M Q QS# Q M Q QS# Q 0 M Q QS# Q0 M Q0 QS# Q M Q QS# Q M Q QS# Q EZIW R-IMM0_H=.0_ST ddr-ddrsk-00-tpb-0p-ldv GMK000 I SOKET R SOIMM(0P,H.0,ST) P00 R SRM SO-IMM (0P) M Q[:0] [] +V [] PM_EXTTS#0 [,] R_RMRST# SMR_VREF_Q0_M. +V R PM_EXTTS#0 +.VSUS 0K/F_ JIM V V V V V V V V 00 V 0 V0 0 V V V V V V V V VSP N N NTEST 0 EVENT# RESET# *0.U/0V_ +SMR_VREF_Q0 +SMR_VREF_IMM VREF_Q VREF_ 0 0 P00 R SRM SO-IMM (0P) VTT 0 VTT GN 0 GN 0 R-IMM0_H=.0_ST ddr-ddrsk-00-tpb-0p-ldv GMK000 I SOKET R SOIMM(0P,H.0,ST) [,,,,0,,,,,,,,,,0,,,,,0] [,,,,] +.VSUS [,] +0.V_R_VTT [] +SMR_VREF_IMM +V +0.V_R_VTT For EMI RESERVE +.VSUS E *0P/0V_ E *0P/0V_ E *0P/0V_ E 0P/0V_ E *0P/0V_ E *0P/0V_ E *0P/0V_ +0.V_R_VTT E *0P/0V_ E *0P/0V_ +.VSUS E E E E0 E E E *0P/0V_ *0P/0V_ *0P/0V_ *0.U/0V_ *0.U/0V_ *0.U/0V_ *0.U/0V_ Place these aps near So-imm0. uf/0uf pcs on each side of connector +.VSUS 0 U/.V_ +0.V_R_VTT U/.V_ 0 U/.V_ U/.V_ 0 U/.V_ U/.V_ U/.V_ U/.V_ U/.V_ 0 0U/.V_ U/.V_ 0 U/.V_ U/.V_ +SMR_VREF_IMM *0.U/0V_ 0 0U/.V_ 00 *.U/.V_ 0 0U/.V_ +SMR_VREF_Q0 0 0U/.V_ 0 *0.U/0V_ 0U/.V_ *.U/.V_ 0U/.V_ 0U/.V_ +V 0 0U/.V_ 0.U/0V_ [] SMR_VREF_Q0_M SMR_VREF_Q0_M R0 R./F_ [] SM_VREF 0.0U/V_ /F_ +.VSUS R0 R.K/F_ 0 0.0U/V_ R VREF Q0 M Solution SMR_VREF_Q0_M R.K/F_./F_ /F_ +.VSUS R.K/F_ +SMR_VREF_IMM R0.K/F_ PROJET : Y Quanta omputer Inc. 0U/.V_.U/.V_ N Size ocument Number Rev ustom R IMM0-ST(.0H) ate: Sheet of Tuesday, September 0, 0

13 +V R R 0K/F_ 0K/F_ [] M [:0] [] M S#0 [] M S# [] M S# [] M S#0 [] M S# [] M LKP0 [] M LKN0 [] M LKP [] M LKN [] M KE0 [] M KE [] M S# [] M RS# M 0 M M M M M M M M M M 0 M M M M M M OT0 M OT M QSP M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSN M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN IMM & Footprint 同 Joshua 提提 M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q [] M WE# [] +SMR_VREF_IMM IMM_S0 WE# Q0 0 IMM_S 0 S0 Q [,,,] SM_RUN_LK [,,,] SM_RUN_T [] M QSP[:0] [] M QSN[:0] JIM /P /# S0# 0 S# 0 K0 0 K0# 0 K K# KE0 KE 0 S# RS# 0 S 00 SL S 0 OT0 OT M0 M M M M 0 M M M QS0 QS QS QS QS QS QS 0 QS QS#0 QS# QS# QS# QS# QS# QS# QS# P00 R SRM SO-IMM (0P) Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q 0 Q0 Q 0 Q Q Q Q Q Q Q Q R-IMM_H=.0_RVS ddr-ddrrk-00-tpb-0p-ruv GMK000 Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q 0 Q0 Q Q Q M Q[:0] [] SMR_VREF_Q_M Local Thermal Sensor MV 可可可 [] PM_EXTTS#0 [,] R_RMRST# [,] MLK [,] MT +V R MLK MT PM_EXTTS#0. +V +.VSUS PM_EXTTS#0 U SLK S LERT# OVERT# JIM V V V V V V V V 00 V 0 V0 0 V V V V V V V V VSP N N NTEST 0 EVENT# RESET# *0.U/0V_ +SMR_VREF_Q VREF_Q VREF_ *0K/F_ 0 0 V XP *EM--ZL-TR Need heck PN(EO) XN GN P00 R SRM SO-IMM (0P) R-IMM_H=.0_RVS ddr-ddrrk-00-tpb-0p-ruv GMK VTT 0 VTT 0 HOLE 0 HOLE 0 P 0 P *0.0U/V_ R_THERM *00P/0V_ R_THERM Main:L0000 nd:l0000 +V +0.V_R_VTT R Thermal Sensor Q *METR0-G EM--ZL-TR(h) TMPGKR(h) +VPU R 00K_ +VS R 0K_ +.VSUS RL SOIMM OT GENERTION N00 Q R./F_ [,,,,] +.VSUS [,] +0.V_R_VTT [,,,,0,,,,,,,,,,0,,,,,0] M OT0 [] +V Place these aps near So-imm. uf/0uf pcs on each side of connector +.VSUS 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ 0U/.V_ +0.V_R_VTT R./F_ 0 U/.V_ M OT [] Q 0 U/.V_ RE0L R./F_ M OT0 U/.V_ R_VTT_PG_TRL U/.V_ R./F_ M OT 0 U/.V_ U/.V_ U/.V_ 0.U/0V_ U/.V_ U/.V_ 0U/.V_ R *0_ S [] U/.V_ +V Q U/.V_ N00K 0 0.U/0V_ U/.V_ 0.U/.V_ R_PG_NTL 0U/.V_ R_PG_NTL [] R 0U/.V_ *M/F_ +SMR_VREF_IMM +SMR_VREF_Q *0.U/0V_ *.U/.V_ *0.U/0V_ *.U/.V_ [] SMR_VREF_Q_M VREF Q M Solution SMR_VREF_Q_M R./F_ N R 0 0.0U/V_ /F_ +.VSUS R.K/F_ SMR_VREF_Q_M R0.K/F_ PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom R IMM-RVS(.0H) ate: Sheet of Tuesday, September 0, 0

14 PROJET :Y0 Quanta omputer Inc. Size ocument Number Rev ustom NS-GT (PIE I/F) /NV ate: Sheet of Tuesday, September 0, 0

15 PROJET :Y0 Quanta omputer Inc. Size ocument Number Rev ustom NS-GT (MEMORY/GN) ate: Sheet of Tuesday, September 0, 0

16 PROJET :Y0 Quanta omputer Inc. Size ocument Number Rev ustom NS-GT (ISPLY) ate: Sheet of Tuesday, September 0, 0

17 PROJET :Y0 Quanta omputer Inc. Size ocument Number Rev ustom NS-GT (GPIO/STRPS) ate: Sheet of Tuesday, September 0, 0

18 PROJET :U Quanta omputer Inc. Size ocument Number Rev ustom NM-GS (PIE I/F) /NV ate: Sheet of Tuesday, September 0, 0

19 PROJET :U Quanta omputer Inc. Size ocument Number Rev ustom NM-GS (MEMORY/GN) ate: Sheet of Tuesday, September 0, 0

20 0 PROJET :U Quanta omputer Inc. Size ocument Number Rev ustom NM-GS (ISPLY) ate: Sheet of Tuesday, September 0, 0 0

21 PROJET :U Quanta omputer Inc. Size ocument Number Rev ustom NM-GS (GPIO/STRPS) ate: Sheet of Tuesday, September 0, 0

22 PROJET :U Quanta omputer Inc. Size ocument Number Rev ustom GPU Memory (R) ate: Sheet of Tuesday, September 0, 0

23 US.0 re-driver for amera EQ.db / E.db EQ db / E db / REXT.K _EQ _EQ0 _EQ _EQ d d.d.d _E _E0 _E _E d no de-emphasis.d TST : Low = Normal LFPS swing / Hight =Turn down LFPS swing d non-us.0 re-driver : stuff Rb _EQ0 _EQ _E0 _E _EQ0 _EQ _E0 _E TST R R R0 R R R R R R From HOST For Re-driver : stuff a *.K_ *.K_.K_ *.K_ *.K_.K_.K_ *.K_ *.K_ +V +V 0.U/0V_ 0.U/0V EQ0 _EQ _E0 _E _EQ0 _EQ _E0 _E US.0 Re-driver U0 0 _IN- _IN+ _OUT- _OUT+ US0_TX+ US0_TX- US0_RX+ US0_RX- Rb a R *0_ US0_TX+_L US0_TX- 0.U/0V_ US0_TX-_ R *0_ US0_TX-_L US0_TX+ 0.U/0V_ US0_TX+_ R *0_ US0_RX+_L R *0_ US0_RX-_L US0_RX- 0.U/0V_ US0_RX-_ US0_RX+ 0.U/0V_ US0_RX+_ [] US0_TX+ [] US0_TX- [] US0_RX+ [] US0_RX- _OUT- _OUT+ _IN- _IN+ V V TST _EQ0 _EQ REXT _E0 _E _EQ0 P# _EQ I_EN _E0 GN 0 _E GN GN GN GN GN GN GN 0 GN GN GN GN For Re-driver : stuff a a US_SSTX-_ 0.U/0V_ US_SSTX+_ 0.U/0V_ US_SSRX-_ 0_ US_SSRX+_ 0_ Need confiem TST R.K_ US_SSTX- [] US_SSTX+ [] US_SSRX- [] US_SSRX+ [] non-us.0 re-driver : stuff Rb US0_TX-_L US0_TX+_L US0_RX-_L US0_RX+_L Rb R R R0 R *0.U/0V_ US_SSTX- *0.U/0V_ US_SSTX+ *0_ US_SSRX- *0_ US_SSRX+ PSTQFNGTR- N PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom RT ate: Sheet of Tuesday, September 0, 0

24 LI Switch [] EMU_LI LVS_LON RIGHT R 0 *.U/V_ 0 / Modify for For ep LVS_LON R K/F_ P/0V_ [] PH_ISP_ON R R 0.U/V_ *0_/S PN_LON K/F_ 00K/F_ VJ U/.V_ +V 0 *.U/V_ LON_ON MEK00V-0 SI...hange LVS_LON to PN_LON.../ U IN IN ON/OFF R 0 0.U/V_ OUT GN P/0V_ 00K/F_ 00m 0.U/V_ L 0 LIGHT 0.U/V_ 0.0U/V LIGHT 0.U/V_ 0.U/V_ 0.0U/V_ 0.U/0V_ +VL_ON 0U/.V_ [,] TS_ON / Modify for /:modify for cost saving RIGHT R0 / : Waiting for MI ONN +V [] IGITL_ [] IGITL_LK K/F_ P/0V_ [] US_SSTX+ [] US_SSTX- [] USP- [] USP+ +V_TS R 0_ VJ L MM000GE +VL_ON 0.0U/V_ / PV Stuff for EMI *0P/0V_ *0P/0V_ E *00P/0V_ 0 *0.0U/V_ USP-_ USP+_ TS_INT# 0.U/0V_ / Modify for camera 0.U/0V_ L 0_ IGITL_LK_L MV..dd U at +V_TS for RF.../ +V_TS / : amera modify [] ULT_EP_HP N INT SPEKER ONN 0 *U/.V_ EP_HP_R / el R0 / Modify for camera [] US_SSRX+ US_SSRX- [] US_SSRX+ [] US_SSRX- _LIGHT +V_TS LVS onn. 0-00t-00-0p-l INT_eP_TXN_R INT_eP_TXP_R INT_eP_TXN0_R INT_eP_TXP0_R INT_eP_UXP_R INT_eP_UXN_R LON_ON VJ TS_INT# USP+_ USP-_ +V_M FW_GPIO _FW_GPIO US_SSTX+ US_SSTX- N R close to U for ep,stuff R 00K/F_ PKTR-G for ep,stuff U & L for LVS,stuff & R _TX_HMI+ _TX_HMI+ _TX0_HMI+ _TX_HMI+ EMI Solution R 0/F_ R 0/F_ R 0/F_ R 0/F TX_HMI- _TX_HMI- _TX0_HMI- _TX_HMI- HMI SMus Isolation +V R Q.K_ [] SVO_LK HMI_SL_R HMI_SLK +V [] INT_eP_UXN [] INT_eP_UXP [] INT_eP_TXP0 [] INT_eP_TXN0 [] INT_eP_TXP [] INT_eP_TXN / dd for amera INT_eP_UXN INT_eP_UXP INT_eP_TXP0 INT_eP_TXN0 INT_eP_TXP INT_eP_TXN 0 0.U/0V_INT_eP_UXN_R 0.U/0V_ INT_eP_UXP_R 0.U/0V_ INT_eP_TXP0_R 0.U/0V_ INT_eP_TXN0_R 0.U/0V_ INT_eP_TXP_R 0.U/0V_ INT_eP_TXN_R For EP Only: stuff Rd,Re,Rf Rd [] PH_PST_PWM R 0_ Re [] PH_LVS_LON R 0_ RIGHT LVS_LON _IN_LK _IN_LK# R R *0_/S *0_/S _TX_HMI+ _TX_HMI- [] SVO_T +V HMI_S_R R.K_ N00W HMI_ST lose to HMI connector +V 0.U/0V_ lose to Q [] HMI_HP_ON Q0 N00K R 00K/F_ +V GPU_L_HMIP R0 M_ Q0 N00 R R R R0 R R R R HMI_HP R 0/F_ 0/F_ 0/F TX_HMI+ 0/F TX_HMI- 0/F TX0_HMI+ 0/F TX0_HMI- 0/F IN_LK 0/F IN_LK# 0K/F_ [] IN_ [] IN_# [] IN_ [] IN_# [] IN_0 [] IN_0# [] IN_LK [] IN_LK# +V_HMI for EMI request IN_ IN_# IN_ IN_# IN_0 IN_0# IN_LK +V_HMI *0.0U/V_ HMI_HP 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ IN_LK# 0.U/0V_ R00V-0 V_HSMK R V_HSMT R0 R00V-0 _IN_LK _IN_LK#.K_.K_ *0P/0V_ *0P/0V_ HMI_ET_ V *TVM0GRM0R _TX_HMI+ _TX_HMI+ _TX_HMI- _TX0_HMI- _TX_HMI+ _TX_HMI- _TX_HMI+ _TX_HMI- _TX0_HMI+ _TX_HMI- +V_HMI HMI_SLK HMI_ST 0P/0V_ 0 N SHELL + Shield - + Shield - 0+ SHELL 0 Shield 0- K+ K Shield K- SHELL E Remote N LK T GN +V HP ET SHELL HMI ONN 0 / dd amera power 0mil +V L0 *0_ +V_M L 0_ / PV Stuff for EMI 0 mils F FUSEV_POLY +V +V_HMI V SSM spec is 0V *TVM0GRM0R 0.0U/V_ 0.U/0V_ +V_M_ *.U/.V_ +V +V For EP Only: stuff INT_eP_UXN_R INT_eP_UXP_R RIGHT LVS_LON [] +V_TS [,,,,,,,,0] +VS [,,,,0,,,,,,,,,,0,,,,,0] +V [,,,,,,,,] +VPU [,,,0,,,,0] +V [,,0,,,,,,0] N R0 R R R *00K_ *00K_ *K_ *K_ PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom L ONN/LI/M/-MI ate: Tuesday, September 0, 0 Sheet of

25 udio odec +V L +V_V H00KF-T U/.V_ lose to PIN 0U/.VS_ 0.U/0V_ +.V +V L *H00KF-T L H00KF-T >0mils trace +V_V-IO 0 0U/.VS_ 0.U/0V_ +V_V 0U/.VS_ GN L H00KF-T 0.U/0V_ lose to PIN +V *Z0-0H E [] [] [] Z_SOUT_UIO [] [] Z_SYN_UIO Z_RST#_UIO TO igital MI [] [] IT_LK_UIO Z_SIN0 IGITL_ IGITL_LK Z_RST#_UIO *0.U/0V_ [] [] P# HP_EP L_SPK+ Z_SOUT_UIO H_SIN0 +V_V-IO GN SHIEL TO Headphone jack +V +V_V L0 H00KF-T +V_V +V +V_V +V_V U U0 0.U/0V_ 0U/.VS_ Vout Vin 0P/0V_ GN GN YP V V lose to PIN *.U/.V_ 0.U/0V_ MI0 V GN EN 0.0U/0V_ U/.V_ R0 00_00m GPIO/ MI-T *U/.V_ *TPSVR R 00_00m MI_LK_R GPIO0/ MI-LK GN HP00VR GN 0P/0V_ R 0K_ lose to PIN +V R *0_/S LO-P 0U/.VS_ GN Vset=.V R0 _ +V_V 0.U/0V_ 0U/.VS_ 0.U/0V_ L_SPK+ L_SPK- R_SPK- R_SPK+ L_SPK- P- N IS_IN lose to Pin IS_LRK R P IS-OUT P+.U/.V_ 0K_ IS-SLK Z_SPKR [] 0.0U/V_ IS-MLK N00 R_SPK- R_SPK+ OMO-ET P# HP_EP MP_EEP lose to Pin lose to Pin 0 0 ST-OUT IT-LK ST-IN V-IO SYN RESET# PEEP SPK-L+ P SPK-L- SPK-R- SPK-R+ MI/GPIO EP/P Globe Input Mute PV igital PV REG-OUT GN nalog 0U/.VS_ Sense MI-VREFO 0 MONO-OUT Sense SENSE VREF HPOUT-L HPOUT-R LINE-L LINE-R MI-R 0 MI-L JREF LINE-VREFO PVEE HPOUT_L HPOUT_R VREFOUT_ MI_L MI_R L x QFN SU_OUT lose to Pin R R 0K/F_ R GN.K/F_ lose to codec *0_/S 0.U/0V_.U/.V_.U/.V_ *.U/.V_ R.U/.V_ SENSE_ lose to PIN GN HPOUT_L [] HPOUT_R [] MUTE_LE_NTL [] R0 R0 0_ GN *0_ K/F_ GN SHIEL GN SHIEL EXT_MI_L TO udio Jack MI SU_OUT [] SU_OUT [] MP_EEP heck layout mount location 0.U/0V_ MP_EEP_L GN R lose to Speaker Speaker ohm: 0mils L L L L hange FOOTPRINT to 00 check value 00K/F_ TI00U00 TI00U00 TI00U00 TI00U00 MP_EEP_R +V_V GN L_SPK+_R L_SPK-_R R_SPK-_R R_SPK+_R 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_ 0.U/0V_ Q R 0K_ 0 N INT SPEKER ONN 0U/.VS_ 0 E 000P/0V_ +.V R0 *.K_ Q Z_RST#_UIO P# *MMT0 [,] VOLMUTE# MEK00V-0 Z_SIN0 E0 *P/0V_ Z_SOUT_UIO E *0P/0V_ Z_SYN_UIO E *0P/0V_ IT_LK_UIO E *P/0V_ +V_V VREFOUT_ R *U/.V_ 0K_ GN OMO-ET R0 R0 *0K_ R0 *0_/S.K_ EXT_MI_L R.K_ OMO-ET_R R 0K_ 0U/.VS_ GN +VS USPW_ON# E _LE# E ST_LE# E EEP_PWRLE# E +VPU E +VS E0 [] US0_TX+_ [] US0_TX-_ [] US0_RX+_ [] US0_RX-_ MM000GE [] USP+ [] USP- L [] _LE# [] ST_LE# [] EEP_PWRLE# +V +VPU SI..dd pin +VS for US port 0.U/0V_ +VS *0P/0V_ [,] USPW_ON# *0P/0V_ SENSE_ *0P/0V_ EXT_MI_L *0P/0V_ [] LINEOUT_L_ LINEOUT_L_ 0.U/0V_ [] LINEOUT_R_ LINEOUT_R_ 0.U/0V_ USP+_ USP-_ GN GN GN update Pin-define On 0/0 SM FP 0P N lose to OE place to near U or under U GN GN [0,,] [,,,,0,,,,,,,,,,0,,,,,0] [,,,0,,,,0] N R E E E0 E 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_ *0_/S +.V +V +V PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom udio odec Tuesday, September 0, 0 ate: Sheet of E

26 Head Phone out +V_MP +V_MP +V L H00KF-T(0,.)_ The de-pop circuit +UIO_V_V [] [] HPOUT_L HPOUT_R GN 0_ 0_ GN R R R R *0_ *0_/S *0_/S *0_ dd uf caps for the coupling. (IT recommend) HPOUT_L GN HPOUT_R 00 U/0V_ R 0_ R 0_ U/0V_ Placement close the OE (U0000) HPOUT_L_ U/0V_ U/0V_ HPOUT_R_ 0 U/0V_ GN LINEOUT_R R *0_/S 0 U/0V_ LINEOUT_L R *0_/S U V 0 HPLEFT LEFTINML- GN LEFTINP+ V GN TP HPRIGHT RIGHTINP+ GN 0 RIGHTINM- GN GN GN GN S# TEST TEST GN GN GN PP PM P GN GN GN GN GN 0 P HP0RTJR 0 U/0V_ GN 0 *000P/0V_ LINEOUT_L +V_MP LINEOUT_R 0 U/V_ GN LINEOUT_R_ LINEOUT_L_ 0 *000P/0V_ GN LINEOUT_R_ [] LINEOUT_L_ [] P#_R R 00K_ R K/F_ +UIO_V_V R K/F_ R 0K/F_ R 0_ Q +UIO_V_V SU_OUT_L+ SU_OUT_LR Q0 N00W [,,] VOLMUTE# +V VOLMUTE# R 00K/F_ GN GN TP HP0RTJR R +V_MP R R HPOUT_L R HPOUT_R *0_ *0_ LINEOUT_L_ LINEOUT_R_ N00W R 0K/F_ R 0_ Q SU_OUT_R+ MP_P#_R K/F_ K/F_ HP_EP [] HP_EP T--F For Envy " & " Subwoofer MP_LK MP_T SU_OUT_RR N00W For Pavilion " Subwoofer(Reserve) For Envy"" Subwoofer +UIO_V_V +UIO_V_V PV L H00KF-T(0,.)_ 0 *0.U/0V_ L +V L +V *H00KF-T(0,.)_ *H00KF-T(0,.)_ *0U/.VS_ *0.U/0V_ *U/0V_ *U/0V_ GN GN +UIO_V_V R *00K_ R *00K_ [] SU_OUT [] P# P# +V R *00K/F_ U S R *00K/F_ FULT PV N_ R *00K/F_ N_ R *0_/S R *0_/S GIN0 R0 change to 00 PV R 0_ GIN *0U/V_ +V V PV... hange footprint to 00 U/V_ U/V_ GN U/V_ R 00K/F_ GV R.K/F_ 0 PLIMIT R *.K/F_ 0.U/V_ R.K/F_ INN SU_OUT 0 U/V_ R 0K/F_ R 0_ 0.U/V_ INP hange footprint to 00 R N_ 0K/F_ *0.U/V_ +V R0 00K/F_ PTL PV..dd R0 00K at U pin TP TPPWPR GN PVL PVL SN_ OUTN_ PGN OUTN_ SN_ SP_ 0 OUTP_0 PGN OUTP_ SP_ PV PV *0U/V_ *0U/V_ 0 0U/V_ 0U/V_ 000P/0V_ 0.U/V_ PV hange footprint to U/0V_ 0 0.U/0V_ PV 000P/0V_ 0.U/V_ hange footprint to 00 +UIO_V_V / new add U Vout Vin +V R R *0.U/0V_ *0_ *0_ 0 YP *.U/.V_ GN EN R *0K_ +V 0 +UIO_V_V *U/0V_ *TLV0VR +UIO_V_V Vset=.V HP0VR SR G SL G0 GN V PV PV PGN PGN *U/0V_ *0.U/0V_ PV..dd For Pop-Noise..0 / add R/R / add R/R / EL R/R U *0_ SWP R and Location [] SU_OUT R0 *0_ GN R *0_ *0.U/0V_ SU_OUT_L+ 0 INL+ R0 SU_OUT_ *0.U/0V_ SU_OUT_L R *0_ SU_OUT_LR SU_OUT+_L *K/F_ INL- SU_OUT_ *0.U/0V_ SU_OUT_R R *0_ SU_OUT_RR SU_OUT-_L INR- R *0_ 0 *0.U/0V_ SU_OUT_R+ INR+ GN GN SWP R and 0 Location 0 N N / add /R SI..dd R0/R0 For fine tune subwoofer.../ +V R *00K_ [,,] VOLMUTE# SU_OUT+_L_ E *0P/0V_ SU_OUT-_L_ E *0P/0V_ P# SU_OUT-_R_ E *0P/0V_ T--F SU_OUT+_R_ E *0P/0V_ R0 *0_ P#_R SU_OUT+_L_P_ OUTL+ SU_OUT-_L_P_ OUTL- SU_OUT-_R_P_ OUTR- SU_OUT+_R_P_ OUTR+ P P P P P P P P P P 0 hange Net Name for option *TP0 HP00RTJR SU_OUT+ SU_OUT- SU_OUT+_L SU_OUT+ SU_OUT- SU_OUT-_L E E0 E E 0P/0V_ 0P/0V_ 0P/0V_ 0P/0V_ R/R lose lose U SU_OUT+_L R 0_ SU_OUT+_R_P_ SU_OUT-_L R 0_ SU_OUT-_R_P_ SU_OUT+_R_P_ L PY00T-Y-N SU_OUT-_R_P_ L PY00T-Y-N For Envy " & " Subwoofer N -00L GIN GIN0 d 0 GN SU_OUT+_L_P SU_OUT-_L_P SU_OUT-_R_P_ SU_OUT+_R_P_ SU_OUT+_L_P_ SU_OUT-_L_P_ SU_OUT-_R_P_ SU_OUT+_R_P_ / : LOSE TO U For Envy"" Subwoofer L0 L L L E E E E0 E E 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_ 000P/0V_ *PY00T-Y-N *PY00T-Y-N *PY00T-Y-N *PY00T-Y-N SU_OUT+_L_P SU_OUT-_L_P SU_OUT-_R_P_ SU_OUT+_R_P_ SU_OUT+_L_ SU_OUT-_L_ SU_OUT-_R_ SU_OUT+_R_ N R/R lose to U(R0,R0) R/R0 lose U R0/R0/R/R0 lose U SI..dd L/L/L/L/R0/R0/R/R0 /SU////.../0 PV..dd R/R/R/R [,,,0,,,,0] +V R/R lose U (lose R/R0 [,,0,,,,,,0] *P Subwoofer ONN GN mplifier Gain Setting (typ) GIN GIN0 V/V d PROJET : Y Quanta omputer Inc.

27 *0P/0V_ For EMI 0 ~ ohm LN_XTL >0mil +.0V_LN_REGOUT Y Trace<0 mil Width > 0 mil *MHZ +-0PPM R *0/F_ Power trace Layout 寬寬 > 0mil a b For GbE * Place c,d,e,f, For 0/00 close to each V0 pin--,,, 0 N e,f c d e f g f Please add GN VIs connection with thermal P Ra * Place e, f,0 MI0+ R *0_ MI0- MIP0 REGOUT(N) +.0V_LN close to each V0 pin--, 0 only, +.0V_LN V0 MIN0 VREG(V) MI+ V0(N) V0(N) >0mil L.UH,+-0%,0M_0 MI- MIP LNWKE RTL GSH 0 MI+ MIN ISOLTE La MI- MIP(N) PERST V0 HSON MIN(N) +.0V_LN V0 HSOP e *0.U/0V_ XTL XTL R *0P/0V_ 0.U/0V_ *0_/S LN_XTL_IN.U/.VS_ 0.U/0V_ LN_XTL_IN [] 0.U/0V_ 0.U/0V_ 0.U/0V_ *U/.V_ U/.V_ 0.U/0V_ 0 *0.U/0V_ R.K/F_ U LNRSET +V_LN GN RTLGSH +.0V_LN RSET V0 XTL XTL LE0 LE V RSET 0 V0 KXTL KXTL LE0 LE/GPO LE(LE) MIP(N) MIN(N) V(N) LKREQ HSIP HSIN REFLK_P REFLK_N 0 TP R 0_ R *0_ LN_MLE# LN_WLE# LN_WLE# Green lk FOR : Stuff R,EL R FOR : Stuff R, EL R +.0V_LN_REGOUT VL V0 PIE_WKE#_R ISOLTE R PIE_RXN_LN_L PIE_RXP_LN_L +V FOR GIG: GSH: L0000 FOR 0/00 : EH: R K_ ISOLTE R K/F_ L0000I TRL(P) RTLGSH-G(QFN) L00000I TRL(P) RTLEH-G(QFN) if ISOLTE pin pull-low,the LN chip will not drive it's PI-E outputs ( excluding PIE_WKE# pin ) +.0V_LN_REGOUT +V_LN +.0V_LN R *0_/S PIE_WKE# [,,,] *0_ SW_WKE# TP PLTRST# [,,,,,] 0.U/0V_ PIE_RXN_LN [] 0.U/0V_ PIE_RXP_LN [] For GbE Stuff La, a,b For GbE * Place f close to each V0 pin-- (reserve) For 0/00 N: La, a,b For 0/00 STUFF : Ra, e * Place g close to each V0 pin-- 0 (reserve) For 0/00 * Stuff b and e only, close to each V pin--, For GIG R0 * Stuff a and b only, close to each V pin--, +V_LN R +VLNV 0 U +V_LN TX+ MT T RX+ NS U MI+ MI- PIE_LKREQ_LN# R 0 MI+ TR_V_ MI0- MI- TR_V_ MI0+ *0_/S LN_LKRQ +VLNV +VLNV LK_PIE_LNN LK_PIE_LNP PIE_TXN_LN PIE_TXP_LN R 0_ R 0_ LN_WLE 000P/0V_ 000P/0V_ LN_MLE RRRR *0_ *0_ *0_ *0_ LK_PIE_LNN [] LK_PIE_LNP [] PIE_TXN_LN [] PIE_TXP_LN [] (White) LN_WLE LN_WLE# MI-_ MI+_ MI-_ MI-_ MI+_ MI+_ MI0-_ MI0+_ LN_MLE LN_MLE# (mber) RJ N 0 LE_White_P LE_White_N [] PIE_LKREQ_LN# MI+_ MI-_ T+ T- /F_ LN_MTG T MI0+_ MI0-_ R+ R- /F_ LN_MTG0 T TX- RX- RX- RX+ RX0- TX- TX+ RX0+ TX0- TX0+ LE_M_P LE_M_N RJ_ONN GN GN R *0_/S R *0_/S 0.U/0V_ a c 0.U/0V_ b * Place c and d close to each V pin--.u/.vs_ 0.U/0V_ d Remove For Not Using SWR mode *0.U/0V_ e For GIG Stuff c,d For 0/00 *.U/.V_ N: c, d *.U/.V_ 0 0P/KV_0 R R0 MI+_ MI-_ /F_ LN_MTG MI+_ MI-_ /F_ LN_MTG T+ T- T TX+ MT TX- MI+ TR_V_ MI- R+ RX- MI- R- T 0 TR_V_ T RX+ MI+ NS For Giga :U + U For 0/00:U 0.0U/V_ E *P/0V_ FE :NS0,0EFLN0 [,,,,0,,,,,,,,,,0,,,,,0] +V [,0] +VLNV N PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom LN RTLGSH /RJ conn ate: Sheet of Tuesday, September 0, 0

28 [] PIE_LKREQ_R# PIE_LKREQ_R# PIE_LKREQ_R#_R R0 0K_ +V Reserve for EMI S_0 S_ S_ S_ E E E0 E.P/V_.P/V_.P/V_.P/V_ SP S_ SP S_0 MS_ SP S_LK MS_0 SP S_M MS_ SP S_ MS_ SP S_ MS_LK [,,,] PIE_WKE# R0 *0_/S S_# S_WP RTS_GPIO RTS_Vaux 0 +V 0.U/0V_.U/.VS_ PV.pF for ISN SP S_WP Share Pin S / MM MS_S Zdiff = 00 ohm [] LK_PIE_RP [] LK_PIE_RN [] PIE_RXP_R [] PIE_RXN_R [,,,,,] PLTRST# [] PIE_TXP_R [] PIE_TXN_R 0.U/0V_ 0.U/0V_ E *0P/0V_ PLTRST# PIE_LKREQ_R#_R PIE_TXP_R PIE_TXN_R LK_PIE_RP LK_PIE_RN PIE_RXP_R_ PIE_RXN_R_ Please add GN VIs connection with thermal P U PERST# LKREQ# HSIP HSIN REFLKP REFLKN HSOP HSON GN 0 WKE# MS_INS# S_# SP GPIO Vaux N N RTS RREF V V_IN R_V N VS SP SP 0 N N N SP 0 SP SP V_ SP RTS lose to chip pin S R R0 _ S_ S R R _ S_ S_M_R R _ S_M V_ U/0V_ S_LK_R R0 _ S_LK SI modify R/R0/R/R to ohm for EMI.P/V_ R REER N RTS_V RTS_VS R00 need colse to hip +V R.K/F_ 0.U/0V_ RTS_RREF *00P/0V_ RTS_V RTS_VS S_0_R S R 0.U/0V_ R _ R _ S_0 S_ lose to chip pin.u/.vs_ 0.U/0V_ +VR *0.U/0V_ LOSE ONN 0U/.V_ +VR S_ S_M S_LK S_0 S_ S_ S_WP S_# 0 T M V LK T0 T T W/P / GN GN GN GN RREER ONN H *H-N H *O-U- 0 0U/.VS_ 0.U/0V_ H *o-y- +VR H *o-ya- H *O-U- H *O-U- H *H-TIP Rx Type Thermal Nut H H *H-TP *H-TP Reserve for ES R change to.k H *H-0P H H-P H *O-Y- R.K/F_ H *H-P NGFF NUT H0 *H-TP H *INTEL-KT-SHRK-ULT lamp-iode H H *H-TP *H-TP H0 H-T0P H *H-P H *O-Y- H *O-Y- H *H-T00P PROJET : Y Quanta omputer Inc. N Size ocument Number Rev ustom R RTS & HOLE ate: Sheet of Tuesday, September 0, 0

29 E Power otton onnector Touch Pad onnector +VSUS 0.U/0V_ Q N00KW +VSUS R.K_ TPLK R.K_ TPT -00-p-l-smt TP_SM_LK FF0MR00 [,,,] SM_RUN_LK ual 0P/0V_ R0.K_ +VPU [] TPT L LM0SN TPT- TPLK- +V +VSUS [] TPLK L LM0SN 0P/0V_ R R0.K_ TP_SM_LK 0.U/0V_ hange FOOTPRINT to 00 TP_SM_T 0K/F_ N TP_SM_T [,,,] SM_RUN_T +VPU N EEP_PWRLE# *0P/0V_ [] EEP_PWRLE# EEP_PWRLE# Q N00KW [] LI_E# mils *0P/0V_ PWR_LE# PWR_LE# [] [] NSWON# 0 *0P/0V_ *0P/0V_ 0 *0P/0V_ POWER TN ONN FF0MR00-00-p-l-smt Pin : +VPU(LISWITH PWR) Pin : POWER LE Pin : LISWITH Pin : GN Pin : GN Pin : POWERON# Q TEU--F 0 0.U/0V_ KEYOR on. K ONN MY 0P/0V_ +V MY 0P/0V_ MX MY 0P/0V_ 0 0U/.VS_ MY[0..] MX MY 0P/0V_ [] MY[0..] MX U/0V_ MX[0..] MY 0 MY 0P/0V_ [] MX[0..] MX MY 0P/0V_ FN MX KEYOR PULL-UP MY0 0P/0V_ FN_PWM 0 *0P/0V_ MY0 MY 0P/0V_ MUTE_LE_NTL_R MX FNSIG 0 *0P/0V_ MX [] FN_PWM MY MY [] FNSIG MY RP 0P/0V_ MX0 0 MY MY [] MUTE_LE_NTL +VPU 0P/0V_ R.K_ FN onnect +V Q MY 0 MY MY MY 0P/0V_ N00K MY 0 MY MY0 MY0 0P/0V_ MY MY MY 靠靠 E R MY MY MX 0P/0V_ 0K/F_ MY MX 0P/0V_ MY MX +VPU *0PR-.K 0P/0V_ MY MX 0P/0V_ MY RP MY 0 MY MY MY MY MX 0P/0V_ MY0 0 MY MY MX0 0P/0V_ MY 0 MY0 MY MX 0P/0V_ MY MY MX 0P/0V_ MY +VPU *0PR-.K MY 0P/0V_ [] PSLE# R 00/F_ PSLE#_R MY 0 0P/0V_ MUTE_LE_NTL_R R00 MUTE_LE_NTL_R R *.K_MY MY 0P/0V_ 00/F_ WIRELESS_ON_R R *.K_MY MY 0P/0V_ WIRELESS_OFF_R MY 0P/0V_ LE_PW MY +V 0P/0V_ N p-l +V FFFR0 +V R0 M_ [] WIRELESS_ON R0 *00/F_ +VS E *0.U/V_ 0 *0.U/V_ WIRELESS_ON_R 0 *0.U/V_ +V E *0.U/V_ Q R *0.U/V_ *RE0L +V_LE_KLIGHT [] K_LE_EN M_ *0.U/V_ *0.U/V_ *0.U/V_ Q 0.U/0V_ 0.U/0V_ *0.U/V_ N00 0 *0.U/V_ N0 +V *0.U/V_ K_LIGHT_ONN_" *0.U/V_ *0.U/V_ +.VSUS *0.U/V_ *0.U/V_ *0.U/V_ R 0 *0.U/V_ *K/F_ 0.U/V_ 0.U/V_ 0 0.U/V_ +VS *0.U/V_ R *00/F_ 0.U/V_ *0.U/V_ 0 0.U/V_ WIRELESS_OFF_R 0 0.U/V_ [,,,,0,,,,,,,,,,0,,,,,0] +V Q0 0.U/V_ [,,,0,,,,0] +V *RE0L 0.U/V_ [,,,,,,,] +VPU 0.U/V_ [] WIRELESS_OFF 0.U/V_ 0.U/V_ 0.U/V_ 0.U/V_ PROJET : Y 0.U/V_ WIRELESS_ON E WIRELESS_OFF E *0P/0V_ *0P/0V_ R *K/F_ Q0 O0 FN +V E N *0.U/V_ Quanta omputer Inc. Size ocument Number Rev ustom P/TP/K/FN/EMI ap ate: Sheet of Tuesday, September 0, 0 E

30 H ST H onnector(able type)." Ra For " : stuff Ra,Rb ST_TXP0_ 0.0U/V_ ST_TXP0 [] ST_TXN0_ 0.0U/V_ ST_TXN0 [] ST_RXN0_ ST_RXP0_ Rb 0.0U/V_ 0.0U/V_ ST_RXN0 [] ST_RXP0 [] ST O ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ 0 0 H Mirror Pin-define / +V For " : stuff Rb +V Rb *0U/.VS_ 0U/.VS_ 0.U/0V_ " ST O O ST O ONNETOR '' ST O ypass P close conn O S TXP TXN RXN RXP P S +V 0 P +V M GN GN GN GN P GN * ST O sata-00--p-r / SI...hange footprint../ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ZERO_O_P# +V_O ZERO_O_# *0.0U/V_ *0.0U/V_ *0.0U/V_ *0.0U/V_ R K_ ST_TXP [] ST_TXN [] ST_RXN [] ST_RXP [] ZERO_O_P# [] +V R 0K_ O_EJET# [] ST O ZERO_O_# ZERO_O_P# ST_RXP_ ST_RXN_ ST_TXN_ ST_TXP_ 0 +V_O 0.0U/V_ 0.0U/V_ 0.0U/V_ 0.0U/V_ ST_RXP ST_RXN ST_TXN ST_TXP Q IN [,] M_ ZERO_PWR_O [0,] R M_ R Q O0 0.0U/V_ [0,] ZERO_PWR_O +V_O +V 0.U/0V_ R _ Q N00K +V_O 0 mils N00W SI..elete Q,Q.../ SI.dd Q.../ 0U/.VS_ 0.U/0V_ 0.U/0V_ 0.U/0V_ 0.U/0V_ IN ZERO_PWR_O E High : O power down Low : O power on E *0P/0V_ *0P/0V_ PROJET : Y Quanta omputer Inc. Size ocument Number Rev ustom HMI N ate: Sheet of Tuesday, September 0, 0 0

31 TPM (.) ddress HIGH EH/F (default) +V FOR EMI ccelerometer Sensor 沿沿 U R0 *0_/S +V_WLN_P *0.U/0V_ +V +G_SEN_PW U HPTR [,,] L0 [,,] L [,,] L [,,] L [,,] LFRME# [,,,,,] PLTRST# TPM_PP +V R *.K/F_ R *0_ L0 L L L [] LK_PI_TPM LFRME# PLTRST# [,] SERIRQ R *_ LK_PI_TPM for EMI *0P/0V_ R R R R R *0_ L0_T *0_ L_T *0_ L_T *0_ L_T LK_PI_TPM *0_ LFRME#_T SERIRQ TPM_TEST TPM_TEST R LFRME# E0 PLTRST# E *0_ *0P/0V_ *0P/0V_ U V 0 L0 V 0 L V L L VS LLK GN GN LFRME# GN LRESET# GN LPP# SERIRQ GPIO TEST/ GPIO LKRUN# PP TESTI N N XTLI/K IN N XTLO *SLTT. PLTRST# R TPM_PP *0.U/0V_ *.K/F_ *0.U/0V_ +V *0.U/0V_ [] EL_INT# EL_INT# *P/0V_ EL_INT# +G_SEN_PW [] MT [] MLK 0.U/0V_ EL_INT#_R 0 R00V-0 TP R0 +G_SEN_PW 0 0.U/0V_ +G_SEN_PW MT MLK *0_/S MT MLK R0 R Vdd_IO V RESERVE 0 INT RESERVE INT RESERVE RESERVE SO S SL GN GN S.K_.K_ L0000 *P/0V_ *P/0V_ N N MT MLK Touch screen [,] TS_ON Q00 TS_ON +VS +VS +V R *0K/F_ R *N00K *0K_ *0.0U/V_ Q0 *ME0T R 0_ +V_TS *0.U/0V_ Green LK ircuitry U R0 _ LN_XTL_IN_R [] LN_XTL_IN R0 *0_/S PH_XTL_IN_R M +V. [] PH_XTL_IN V M 0 [] LKGEN_RT_X / Modify for Khz VT Mhz/N 0.U/0V_ V_RT_OUT +VLNV VIO_M +.0V VIO_M GN 0.U/0V_ VIO_/N GN +V_ON GEN_XTL_OUT GN *0.U/0V_ GEN_XTL_IN XTL_OUT GN XTL_IN SI..hange pin power to +V_ON.../ SLGN IS:L00000 UM:L0000 0mils width(min) +VPU +V_RT_0,+V_RT_R,+V_RT.. +VLNV +V_RT_0 0 +V_RT_R R 0.U/0V_.U/.V_ 0/F_ U/.VS_ +V_RT P/0V_ GEN_XTL_IN 0 *0P/0V_ PH_XTL_IN 0.U/0V_ +VLNV Fingerprint onn Y MHZ +-0PPM GEN_XTL_OUT / el for *0P/0V_ LN_XTL_IN P/0V_ USP+ USP- R R *0_/S *0_/S USP+_ USP-_ *0.U/0V_ -00-p-l-smt FF0MR00 POWER TN ONN [] USP+ [] USP- +V USP+_ USP-_ +V USP+_ *lamp-iode N need heck USP-_ *lamp-iode +V SI..dd 0 for FR +v bypass cap.../ PROJET : Y Quanta omputer Inc. 0.U/0V_ N Size ocument Number Rev ustom TPM/G-Sensor/G-LK/TS/FP ate: Sheet of Tuesday, September 0, 0