Z09 Rev: 2C

Transcription

1 VER : OM P/N escription SYSTEM LOK IGRM Memory own Max. G M* P RIII-SOIMM P mst - H P0 ual hannel R III /00 MHZ IM Ivy ridge G 0 W P,,,, FI MI PI-E X ep MI(x) PIE.GT/s NVII GPU NP-GV G (Mb x IO x pcs) P,,,0,, X'TL.0MHz ep onn. P ST - H P0 ST FI MI US.0 * US.0 * ST - O P US Port P US.0(US.0) ST isplay HMI HMI onn. P onn. P US.0 US Port P US Port (harger) P US.0(US.0) US.0 P TTERY zalia US.0 PI-E x US.0 RT IH Panther Point PH G P,,, 0,, LP PI-E x PI-E x SPI X'TL.KHz X'TL MHz SPI ROM P MM PIE- PIE- PIE- M0 GIG LN P X'TL MHz RTS0-GR ardreader controller P augther board US-0 MINI R WLNT P RJ onn. P ardreader onn.(in) MI L-V UIO OE augther board P LP WPE E P atery harger V/V P P.0V.V/V P P VGFX_XG PU core P P OM Option Table Reference escription EV@ Optimize SKU SN@ For Sandy bridge. MI/HP JK K/ on. P Touch Pad on. P VGPU_ORE P VGPU_IO P ischarger P Thermal Protection P IV@ For Ivy bridge. IV@ For UM. * do not stuff Speaker WXVSSG SPI FLSH P EM--T HLL SENSOR P Fan river P Quanta omputer Inc. PROJET : Size ocument Number Rev lock iagram Monday, pril 0, 0 ate: Sheet of 0

2 <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_FSYN0 FI_FSYN FI_INT FI_LSYN0 FI_LSYN ep_iompo mil ep_ompio mil <> <> <> <> EP_UX# EP_UX EP_TX0# EP_TX0 EP_OMP INT_EP_HP# EP_UX# EP_UX EP_TX0# EP_TX0 Ivy ridge Processor (MI,PEG,FI) U G PEG_OMP PEG_IOMPI M PEG_IOMPO G P MI_RX#[0] PEG_ROMPO G P MI_RX#[] GRN[0..] <> P0 MI_RX#[] H GRN MI_RX#[] PEG_RX#[0] J GRN N PEG_RX#[] GRN P MI_RX[0] PEG_RX#[] GRN P MI_RX[] PEG_RX#[] GRN P MI_RX[] PEG_RX#[] GRN0 MI_RX[] PEG_RX#[] GRN K PEG_RX#[] GRN M MI_TX#[0] PEG_RX#[] GRN N MI_TX#[] PEG_RX#[] 0 GRN R MI_TX#[] PEG_RX#[] G GRN MI_TX#[] PEG_RX#[0] GRN K PEG_RX#[] GRN M MI_TX[0] PEG_RX#[] H GRN P MI_TX[] PEG_RX#[] E GRN T MI_TX[] PEG_RX#[] K GRN0 MI_TX[] PEG_RX#[] GRP[0..] <> K GRP PEG_RX[0] K GRP PEG_RX[] GRP U PEG_RX[] GRP W FI0_TX#[0] PEG_RX[] GRP W FI0_TX#[] PEG_RX[] GRP0 FI0_TX#[] PEG_RX[] GRP W FI0_TX#[] PEG_RX[] GRP V FI_TX#[0] PEG_RX[] GRP Y FI_TX#[] PEG_RX[] GRP FI_TX#[] PEG_RX[] F GRP FI_TX#[] PEG_RX[0] GRP PEG_RX[] GRP U PEG_RX[] H GRP W0 FI0_TX[0] PEG_RX[] F GRP W FI0_TX[] PEG_RX[] K GRP0 FI0_TX[] PEG_RX[] W FI0_TX[] G GTN EV@0.u/0V_ GTN T FI_TX[0] PEG_TX#[0] GTN EV@0.u/0V_ GTN FI_TX[] PEG_TX#[] GTN EV@0.u/0V_ GTN FI_TX[] PEG_TX#[] F GTN EV@0.u/0V_ GTN FI_TX[] PEG_TX#[] H GTN EV@0.u/0V_ GTN PEG_TX#[] GTN0 EV@0.u/0V_ GTN0 FI0_FSYN PEG_TX#[] K GTN EV@0.u/0V_ GTN FI_FSYN PEG_TX#[] F GTN 0 EV@0.u/0V_ GTN U PEG_TX#[] F GTN EV@0.u/0V_ GTN FI_INT PEG_TX#[] GTN EV@0.u/0V_ GTN 0 PEG_TX#[] J GTN EV@0.u/0V_ GTN G FI0_LSYN PEG_TX#[0] H GTN EV@0.u/0V_ GTN FI_LSYN PEG_TX#[] M0 GTN EV@0.u/0V_ GTN PEG_TX#[] F0 GTN EV@0.u/0V_ GTN PEG_TX#[] GTN 0 EV@0.u/0V_ GTN PEG_TX#[] J GTN0 EV@0.u/0V_ GTN0 F PEG_TX#[] ep_ompio F GTP EV@0.u/0V_ GTP G ep_iompo PEG_TX[0] GTP EV@0.u/0V_ GTP ep_hp PEG_TX[] GTP 0 EV@0.u/0V_ GTP PEG_TX[] E GTP EV@0.u/0V_ GTP G PEG_TX[] G GTP EV@0.u/0V_ GTP F ep_ux# PEG_TX[] GTP0 EV@0.u/0V_ GTP0 ep_ux PEG_TX[] K GTP EV@0.u/0V_ GTP PEG_TX[] G GTP EV@0.u/0V_ GTP PEG_TX[] E GTP EV@0.u/0V_ GTP ep_tx#[0] PEG_TX[] GTP EV@0.u/0V_ GTP E ep_tx#[] PEG_TX[] K GTP EV@0.u/0V_ GTP E ep_tx#[] PEG_TX[0] G GTP EV@0.u/0V_ GTP ep_tx#[] PEG_TX[] K0 GTP EV@0.u/0V_ GTP PEG_TX[] G0 GTP EV@0.u/0V_ GTP ep_tx[0] PEG_TX[] GTP EV@0.u/0V_ GTP E0 ep_tx[] PEG_TX[] K GTP0 EV@0.u/0V_ GTP0 E ep_tx[] PEG_TX[] ep_tx[] MI Intel(R) FI P PI EXPRESS -- GRPHIS PEG_IOMPO mil PEG_IOMPI, PEG_ROMPO mil, PEG_IOMPI and ROMPO signals should be shorted and routed with - max length = 00 mils - typical impedance = mohms PEG_IOMPO signals should be routed with - max length = 00 mils - typical impedance =. mohms GTN[0..] <> GTP[0..] <> SN_G_P0 0.uF coupling aps for PIE GEN// P_OMPIO and IOMPO signals should be shorted near balls and routed with - typical impedance < mohms G.0 : The recommended cap value is changed to 0nF for compatibility with PIe Gen on future platforms. For Gen only designs, it is acceptable to continue to use the 00nF capacitor. P & PEG ompensation.0v_vtt ep Hot-plug (isable).0v_vtt 00 change from 0k to k. R K_ EP_OMP R./F_ INT_EP_HP# PEG_OMP R.0V_VTT./F_ Note: Place PU resistor within inches of PU HP PU/P resistor values based on R and different to G Q N00E EP_HP R 00K_ EP_HP <> Quanta omputer Inc. PROJET : Size ocument Number Rev Ivy ridge / Monday, pril 0, 0 ate: Sheet of 0

3 oot S S RSM Ivy ridge Processor (LK,MIS,JTG).V_PU RM_PWRG SYS_PWROK 00 ns after.v_pu reaches 0% <,> H_PROHOT# <0> PM_THRMTRIP# <> H_SN_IV# Over 0 degree will drive low <> PM_SYN <0> H_PWRGOO Isolate Space:0mils.0V_VTT <0,> E_PEI R /F_ PU_PLTRST# U SM_RMPWROK LK J LK_PU_LKP <> H LK# LK_PU_LKN <> F 0 Remove R0/R/R/R. PRO_SELET# PLL_REF_LK G TP LK_PLL_SSLKP <> G LK_PLL_SSLKN <> TP PLL_REF_LK# PRO_ETET# TP LK_PIE_XPP_R LK_ITP N R0 *0_ LK_PIE_XPP <> N LK_PIE_XPN_R R *0_ LK_ITP# LK_PIE_XPN <> TP TP_TERR# TERR# Isolate Space:0mils T0 PEI SM_RMRST# PU_RMRST# <,> F SM_ROMP_0 R0 0/F_ NOTE: ll R_OMP signals R0 _ H_PROHOT#_R SM_ROMP[0] E SM_ROMP_ R0./F_ should be routed such that :- PROHOT# SM_ROMP[] G SM_ROMP_ R0 00/F_ - max length = 00 mils SM_ROMP[] - trace width = mils and *P/0V_N - M trace impedance < mohms (worst case resistance) THERMTRIP# Impedance ohm R *SHORT_ PM_SYN_R 0.U/0V_ R *SHORT_ H_PWRGOO_R R 0K_ PM_RM_PWRG_R E TP R0 _ PU_PLTRST#_R R PM_SYN UNOREPWRGOO SM_RMPWROK RESET# MIS THERML PWR MNGEMENT LOKS R MIS JTG & PM PRY# PREQ# TK TMS TRST# TI TO R# PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] N N L L J M0 L K G E E G G H0 J J XP_RST#_R TP TP TP TP0 TP TP00 TP TP0 TP XP_PREQ# TP XP_TLK_VT <,> XP_TMS_VT <,> XP_TRST# TP0 XP_TI_VT <> PH_XP_TO_VT <> 00 dd 0k to V,R k 00 del R0 R 0_ XP_RST# <> If motherboard only supports external graphics or if it supports Processor Graphics but without ep: onnect PLL_REF_SSLK on Processor to through K /- % resistor. onnect PLL_REF_SSLK# on Processor to VP through K / - % resistor Place near to XP connector.0v_vtt _ R PH_XP_TO_VT Option for Prochot# function ohm for unused, ohm for used H_PROHOT# R _ XP_TMS_VT XP_TI_VT XP_PREQ# R0 _ R _ R *_.0V_VTT *0/F_ XP_TLK_VT XP_TRST# R _ R _ SN_G_P0 When MP, JTG PU/P resistor can be removed? (Yes Intel, TI, TO, TMS, TRST#, TK,PREQ#, PRY#) V Thermal Trip <PU>.0V_VTT s leakage circuit V_S 0 add Q becaue Vh=./Vl=0.. R0 R0 *K_ *0K_ If PM_RM_PWEG connector,the R0 must stuff. V_S.V_PU 0.u/0V_ 0 change net to PI_PLTRST# <,> PI_PLTRST# 0 U 0.U/0V_X N V IN PU_PLTRST# OUT LVG0GW_N <,> IMVP_PWRG PM_THRMTRIP# Q N00_00M R K_ Q MMT0--F_00M SYS_SHN# <,>.V_PU <> SYS_PWROK *N00W Q R0 0_ <> PM_RM_PWRG 000 add resistor. U PM_RM_PWRG_Q HG0 R0 *0_ R0 00/F_ R 0/F_ PM_RM_PWRG_R R0 *_ Q <,> MINON_G *N00K R *.K/F_ PU_PLTRST#_R IN OUT L L H High-Z Quanta omputer Inc. PROJET : Size ocument Number Rev Ivy ridge / Monday, pril 0, 0 ate: Sheet of 0

4 Sandy ridge Processor (R) U U <> M Q[:0] <> M S#0 <> M S# <> M S# <> M S# <> M RS# <> M WE# M Q0 G M Q J M Q P M Q L M Q J0 M Q J M Q L M Q L M Q R M Q P M Q0 U M Q V M Q R M Q P M Q T M Q U M Q M Q M Q M Q M Q0 M Q M Q M Q Y M Q V M Q R M Q Y M Q R M Q M Q U M Q0 M Q M Q M Q R M Q W M Q M Q M Q R M Q T M Q Y M Q0 M Q V M Q M Q Y M Q M Q U M Q M Q M Q M Q V M Q0 P0 M Q P M Q V M Q T M Q P M Q P M Q N M Q N M Q G M Q G M Q0 N M Q N M Q G M Q K F E T S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] U V Y T0 M LK U0 M LK# M KE 0 M S# Y0 M OT L M QSN0 R M QSN V M QSN T M QSN V M QSN Y M QSN T M QSN K M QSN J M QSP0 R0 M QSP Y M QSP U M QSP W M QSP V M QSP T M QSP K M QSP G M 0 M E M M T M U M M T M Y M V M E M 0 0 M 0 M W M Y M U M M LK0 <> M LK0# <> M KE0 <> M LK <> M LK# <> M KE <> M S#0 <> M S# <> M OT0 <> M OT <> M QSN[:0] <> M QSP[:0] <> M [:0] <> <> M Q[:0] <> M S#0 <> M S# <> M S# <> M S# <> M RS# <> M WE# M Q0 L M Q L M Q N M Q R M Q K M Q K M Q N M Q R M Q U M Q T M Q0 V M Q M Q U M Q R M Q Y M Q M Q E M Q M Q M Q F M Q0 F M Q 0 M Q M Q E M Q F M Q E M Q E M Q E M Q E M Q G M Q0 G M Q F M Q 0 M Q F M Q M Q F M Q M Q E M Q M Q E M Q0 F M Q E M Q M Q Y0 M Q E M Q G M Q M Q W M Q W M Q U M Q0 N M Q N M Q U M Q U M Q N M Q R M Q K M Q L M Q G M Q G M Q0 M0 M Q L M Q F M Q H0 G T V F0 S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[] S_Q[0] S_Q[] S_Q[] S_Q[] S_S[0] S_S[] S_S[] S_S# S_RS# S_WE# R SYSTEM MEMORY S_LK[0] S_LK#[0] S_KE[0] S_LK[] S_LK#[] S_KE[] S_S#[0] S_S#[] S_OT[0] S_OT[] S_QS#[0] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS#[] S_QS[0] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_QS[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[] S_M[0] S_M[] S_M[] S_M[] S_M[] S_M[] Y R F E E T G L V G G T0 K M V E E R K F E U0 0 V0 G0 E0 E T V T U M LK M LK# M KE M S# M OT M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN M QSN M QSP0 M QSP M QSP M QSP M QSP M QSP M QSP M QSP M 0 M M M M M M M M M M 0 M M M M M M LK0 <> M LK0# <> M KE0 <> TP M S#0 <> TP M OT0 <> TP M QSN[:0] <> M QSP[:0] <> M [:0] <> SN_G_P0 SN_G_P0 M LK R /F_ 0.V_R_VTT M LK# u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ 0u/.V_ 00 for memory down PU P. s leakage circuit S circuit:- RM_RST# to memory should be high during S 000 hange to E for new IOS 0. V_S 00 move R to near Q and del net RMRST_NTRL_PH, and E_RMRST_NTRL and R. Q N00K <,> R_RMRST# R K/F_ PU_RMRST# <,> <> <> RMRST_NTRL_PH E_RMRST_NTRL <,> EEPS_E R *0_ R 0_.VSUS R0 K/F_ R K_ R *0_ 0 0.0u/0V_ R.K/F_ M 0 R0 _ M R _ M R _ M R _ M R _ M R _ M R0 _ M R _ M R _ M R _ M 0 R _ M R _ M R _ M R _ M R _ M R _ 0.V_R_VTT M WE# M S# M RS# M S#0 M S# M KE0 M OT0 M S#0 M S# R _ R _ R _ R _ R _ R0 _ R _ R _ R _ 0.V_R_VTT Quanta omputer Inc. PROJET : Size ocument Number Rev Ivy ridge / Monday, pril 0, 0 ate: Sheet of 0

5 .u/0v_.u/0v_.u/0v_.u/0v_.u/0v_ PU ore Power IVY W:T 0 IVY SPE.mΩ/Loadlineesign total :.uf x total : uf x tatal : 0u x(power side*) ose down IVY SPE.mΩ/Loadlineesign total :.uf x total : 0uF x tatal : 0u x(power side*) Layout note: need routing together and LERT need between LK and T SVI LK H_PU_SVILK.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ R0 V_ORE 000 remove for debug I. 0 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 000 remove for debug I..u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ 0u/.V_ 0u/.V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ *SHORT_ 0.u/0V_ 0u/.V_.u/0V_.u/0V_.u/0V_.u/0V_ 0u/.V_.u/0V_.u/0V_ 0.u/0V_.u/0V_ 0.u/0V_ VR_SVI_LK <>.u/0v_ 0u/V_ 0u/.V_ 0 0u/.V_.u/0V_.u/0V_.u/0V_.u/0V_ Sandy ridge Processor (POWER) 0u/V_ E E E E E E F F F F F F F F G H H H H H H H H H H0 J J J J J J J J J J0 J K K K K K K K K K L L L L L0 N N0 N N UF V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] SN_G_P0 Place PU resistor close to PU.0V_VTT SVI T H_PU_SVIT R0 ORE SUPPLY R0 0/F_ POWER *SHORT_ PEG N R SENSE LINES SVI QUIET RILS VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[0] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO0 VIO VIO_SEL VPQE[] VPQE[] VILERT# VISLK VISOUT V_SENSE VSS_SENSE VIO_SENSE VSS_SENSE_VIO F G G0 G J J J J J K0 K L L L L0 L L L L M M M M M N0 N N N 0 E E F F F0 G G G G0 G J J W W M N F G N N VR_SVI_T <>.0V_VTT VIO_SEL R 0u/.V_ 0u/.V_ 0 H_PU_SVILRT# H_PU_SVILK H_PU_SVIT R 0_ R 0_ 0u/.V_ 0 0u/.V_ PU VIO IVY W:. ose down SN : Spec 0uF/mohm x 0uF/mohm x 0uF x 0 0uF x 0 uf x uf x u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ IVY SPE uf_ x Socket TOP cavity uf_ x Socket OT cavity uf_ x Socket TOP cavity (no stuff) uf_ x Socket OT cavity (no stuff) 0uF_ x *SHORT_.0V_VTT Voltage selection for VIO: this pin must be pulled high on the motherboard On R H_SN_IV#_PWRTRL = low,.0v H_SN_IV#_PWRTRL = high/n,.0v.0v_vtt V_ORE V_SENSE <> VSS_SENSE <>.0V_VTT 0u/V_ 0 0u/.V_ VP_SENSE <> VSSP_SENSE <> Place PU resistor close to PU.0V_VTT H_PU_SVILRT# 0u/.V_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ R R 00_ R 00_ 0 *0u/V_ 0 TP *SHORT_ U/.V_X 0u/.V_ 0u/.V_ 0 0u/.V_ 0u/.V_ 0 R0 _ R /F_ VR_SVI_LERT#_R R PU VXG IVY W:T Spec.mΩ/Loadlineesign total : uf x total : 0uF x total : uf x tatal : 0u x (power side*) ose down.mω/loadlineesign total : uf x total : 0uF x tatal : 0u x (power side*) 0u/.V_ 0u/.V_ u/.v_ 0u/.V_ 0u/.V_ u/.v_ 0 u/.v_ 0u/.V_ 0u/.V_ 0 u/.v_ u/.v_ 0u/.V_ 0u/.V_ u/.v_ u/.v_ 0u/.V_ 0u/.V_ 0 u/.v_ 00 u/.v_ VXG_SENSE/VSSXG_SENSE R=00, Trace impedance.~., <mils. 0 Sandy ridge Processor (GRPHI POWER) 0 0u/V_ 0u/.V_ 0u/.V_ u/.v_ u/.v_ V_GFX Note: VR_REF_PU should have 0 mil trace width Y VR_REF_PU.V_PU PU VQ IVY W: Spec 0uF/mohm x TP V_GFX R 00_ M.V_PU F VQ[] N PU VPL <> V_XG_SENSE G VXG_SENSE VQ[] <> VSS_XG_SENSE 0 U/.V_X IVY W:. R 00_ VSSXG_SENSE TP0 Spec Real 0uF/mohm x 0uF x.v R *SHORT_ uf x uf x R0 *SHORT_ PU_VPLL VPLL[] 00 VPLL[] u/.v_ u/.v_ VPLL[] IVY SPE *0u/V_ 0uF x, 0uF_ x, uf_ x Socket OT edge. VS VQ_SENSE R0 *_.V_PU VSS_SENSE_VQ R *_ L L VS[] N VS[] N0 VS[] N VS[] IVY SPE 0 P VS[] R *00/F_ VS 0uF x, 0uF_ x Socket OT edge, 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/V_ P0 VS[] VS_SENSE U0 VS_SENSE <> R VS[] 0uF_ x Socket OT cavity. SN_IV# N. at SN ES # 0.v R VS[] R VS[] R *0K_ PU VS U VS[0] 00 for Intel fw issue, if solve need un-stuff. IVY W: V VS[] *n/0v_ V VS[] R0 IV@0_ Spec VS_VI0 <> V VS[] VS_VI[0] VS_VI <> 0uF/mohm x V VS[] VS_VI[] Real 0uF x 0 W0 VS[] R *0K_ VS[] uf x 0uF x -K pull-down resistor should be placed on the u/.v_ u/.v_ u/.v_ u/.v_ u/.v_ VS VI lines. This will ensure the VI is 00 prior to VIO stability.. R for SN ridge SN_G_P0 For SN ridge S STUFF NO_STUFF 00 stuff Q00 and un-staff R/R.. VI[] VS.VSUS R0 *0_0.V_PU 0 0.V enable - R/R 0.V disable - R *0_0 R/R Q O For IV ridge SMR_VREF VR_REF_PU.V_PU VI[0] VI[] VS 00 from.vsus change to.v_pu V R *0_ R 0 0.V *K/F_ 0 0.V MIN R 0.V 0_ Q 0P/0V_ N00K <,,> MIN MIN R 00K_ R SVI LERT *K/F_ <,> MINON_G MINON_G Quanta omputer Inc. S circuit:.v input to IV is gated & IV Read Vref 0.V is gated Q *SHORT_ change to K/F_ PROJET : VR_SVI_LERT# <> MN0K- Size ocument Number Rev Ivy ridge / ate: Monday, pril 0, 0 Sheet of E N P P P0 P P P P P P T T T T U V V V0 V V V V V V V W0 W W W W W W Y Y UG VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[0] VXG[] VXG[] VXG[] VXG[] VXG[] VXG[] GRPHIS POWER SENSE LINES S RIL.V RIL SENSE LINES QUIET RILS R -.V RILS SM_VREF VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[0] VQ[] VQ[] VQ[] VQ[] VQ[] VQ[] J J J J0 L0 L L L M M M0 N0 N N R R R0 R R R R0 V W 0 G 0u/.V_ u/.v_ *0u/.V_ u/.v_ 0 u/.v_ 0 *0u/.V_ u/.v_ 0u/V_ u/.v_ 0uF x uf x 0 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ 0u/.V_ u/.v_ u/.v_ u/.v_ u/.v_ u/.v_

6 UH VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] E VSS[] E VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F0 VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] G0 VSS[] G VSS[0] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J0 VSS[0] J VSS[] J VSS[] J0 VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] J VSS[] K VSS[0] K VSS[] L0 VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L0 VSS[0] L VSS[] L VSS[] L VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] VSS[0] SN_G_P0 Sandy ridge Processor () VSS VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] M M M M M M N N N N N N N0 N N N0 N P0 P P P R R R R R R R T T T T T T T U U U U U U V V V V V0 V V W W W W Y Y Y0 Y Y Y Y Y Y Y Y 0 E G R *SN@0_ FG (PI-E Static x Lane Reversal) FG (PI-E Static x Lane Reversal) G G G G G G G G G G E E E E E0 F F F F F F0 F G G G G H0 H H H H H H J J J K K K K L L0 L L L0 L L L L L M M UI VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] SN_G_P0 Processor Strapping FG (P Presence Strap) FG (PEG efer Training) VSS NTF VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[00] VSS[0] VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ M M M N N N N N N N N0 N N N N N N N P P P P P P P R R0 R R T T T0 T T T T T U U V0 V W W W W W W Y Y Y Y E E G G E E Normal Operation Normal Operation The FG signals have a default value of '' if not terminated on the board. 0 isable; No physical P attached to ep Enable; n ext P device is connected to ep PEG train immediately following xxreset de assertion TP TP FG FG FG FG FG FG FG TP TP TP TP TP TP TP Lane Reversed Lane Reversed PEG wait for IOS training Sandy ridge Processor (RESERVE, FG) 0 H H K K F G L F L H K H K F H K V T Y Y U U G E G E F E UE FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[] FG[0] FG[] FG[] FG[] FG[] FG[] FG[] FG[] V_VL_SENSE VSS_VL_SENSE VXG_VL_SENSE VSSXG_VL_SENSE V_IE_SENSE RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV SN_G_P0 FG[:] (PIE Port ifurcation Straps) : (efault) x - evice functions and disabled 0: x, x - evice function enabled ; function disabled 0: Reserved - (evice function disabled ; function enabled) 00: x,x,x - evice functions and enabled FG FG RESERVE R R _TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST_E _TEST_E _TEST_G _TEST_G _TEST_G _TEST_G _TEST_G _TEST_E _TEST_G _TEST_E _TEST_ *K/F_ *K/F_ RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV FG E S_IMM_VREFQ G S_IMM_VREFQ 00 stuff for revers FG FG FG E G N L L L M M U W P T K H G M M N0 E E G G G G G E G E R R R R SMR_VREF_Q0_M <> SMR_VREF_Q_M <> processor signal balls F and G for Ivy ridge -core and balls E and G for Ivy ridge -core K/F_ K/F_ *K/F_ for M solution need R/R, W/O M then N Quanta omputer Inc. PROJET : Size ocument Number Rev Ivy ridge / R R *K/F_ *K_ *K_ Monday, pril 0, 0 ate: Sheet of 0

7 PT/PPT (LVS,I) 0 <> MI_RXN0 <> MI_RXN <> MI_RXN <> MI_RXN <> MI_RXP0 <> MI_RXP <> MI_RXP <> MI_RXP <> MI_TXN0 <> MI_TXN <> MI_TXN <> MI_TXN <> MI_TXP0 <> MI_TXP <> MI_TXP <> MI_TXP 00 MI reverse 0 MI change to normal.0v_vtt R0 R0./F_ MI_OMP 0/F_ 00 add SUSWEN to SUSK connector. SUSWRN#_R R 0_ <> SUSK# R *0_ SUSK#_R <> XP_RST# XP_RST# *U/0V_ SYS_PWROK R0 *SHORT_ SYS_PWROK_R R *0_ E_PWROK_R R0 *SHORT_ PWROK_E R *SHORT_ PWROK_R R0 *SHORT_ <> PM_RM_PWRG PM_RM_PWRG <> PH_RSMRST# PH_RSMRST# <0,> IO_PIERST# R *0_ SUSWRN#_R <> NSWON# R *SHORT_ PM_PWRTN# TP0 <> PRESENT PRESENT PT/PPT (MI,FI,PM) U E0 G G0 E 0 J J0 W W0 V Y Y0 Y U J G H K P L L0 K E0 H0 MI0RXN MIRXN MIRXN MIRXN MI0RXP MIRXP MIRXP MIRXP MI0TXN MITXN MITXN MITXN MI0TXP MITXP MITXP MITXP MI_ZOMP MI_IROMP MIRIS SUSK# SYS_RESET# SYS_PWROK PWROK PWROK RMPWROK RSMRST# MI System Power Management V V_S V_S V_S SW FI SUSWRN#/SUSPWRNK/GPIO0 PWRTN# PRESENT / GPIO FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT FI_FSYN0 FI_FSYN FI_LSYN0 FI_LSYN SWVRMEN PWROK WKE# LKRUN# / GPIO SUS_STT# / GPIO SUSLK / GPIO SLP_S# / GPIO SLP_S# V_S SLP_S# SLP_# SLP_SUS# <> INT_LVS_LON <> INT_LVS_IGON Need notice IOS if MI or FI reverse. <> INT_LVS_RIGHT J Y FI_TXN0 <> E FI_TXN <> H FI_TXN <> FI_TXN <> J FI_TXN <> G0 FI_TXN <> G FI_TXN <> FI_TXN <> G FI_TXP0 <> F FI_TXP <> G FI_TXP <> E FI_TXP <> G FI_TXP <> J0 FI_TXP <> H FI_TXP <> FI_TXP <> 00 FI reverse W FI_INT <> 0 FI change to normal V FI_FSYN0 <> 0 FI_FSYN <> V FI_LSYN0 <> 0 FI_LSYN <> PWROK need to be shorted to RSMRST# when eep S/S state is not support SWVREN <> E PWROK_R R 0_ 000 change PWROK from PH_Rsmrst# to E control. PWROK <> PIE_WKE#_LN R 0_ PIE_LN_WKE# <> 00 add R un-stuff for normal s PIE LN wake up. N LKRUN# LKRUN# <,> G N 0 H F G0 G PH_SUSLK SLP_# SLP_SUS# TP TP TP LPP# <> 0 add for TPM LPP# pin. SUS# <> SUS# <> SLP_SUS# <,> _IREF R0 K/F_ % or % U J M L_KLTEN L_V_EN P L_KLTTL T0 K L LK L T T P L_TRL_LK L_TRL_T F F LV_IG LV_VG E E LV_VREFH LV_VREFL K K0 LVS_LK# LVS_LK N M LVS_T#0 K LVS_T# J LVS_T# LVS_T# N M LVS_T0 K LVS_T J LVS_T LVS_T F0 F LVS_LK# LVS_LK H H LVS_T#0 F LVS_T# F LVS_T# LVS_T# H H LVS_T0 F LVS_T F LVS_T LVS_T N P RT_LUE T RT_GREEN RT_RE T M0 RT LK RT T M M RT_HSYN RT_VSYN T T _IREF RT_IRTN Panther Point_RP0 LVS igital isplay Interface RT SVO_TVLKINN P P SVO_TVLKINP SVO_STLLN M M0 SVO_STLLP SVO_INTN P P0 SVO_INTP P SVO_TRLLK M SVO_TRLT P_UXN T T P_UXP P_HP T0 P_0N V V0 P_0P P_N V V P_P P_N U U P_P P_N V V P_P P P_TRLLK P P_TRLT P_UXN P P P_UXP P_HP T P_0N Y Y P_0P P_N Y Y P_P P_N P_P P_N P_P M P_TRLLK M P_TRLT P_UXN T T P_UXP P_HP H P_0N P_0P P_N F E P_P P_N F E P_P P_N J G P_P INT_HMITXN_ INT_HMITXP_ INT_HMITXN_ INT_HMITXP_ INT_HMITX0N_ INT_HMITX0P_ INT_HMILK-_ INT_HMILK_ isplayport isplayport HMI_LK_SW <> HMI_T_SW <> HMI_HP <> INT_HMITXN_ <> INT_HMITXP_ <> INT_HMITXN_ <> INT_HMITXP_ <> INT_HMITX0N_ <> INT_HMITX0P_ <> INT_HMILK-_ <> INT_HMILK_ <> INT. HMI PM_TLOW# E0 TLOW# / GPIO V_S PMSYNH P PM_SYN <> PM_RI# 0 RI# V_S SLP_LN# / GPIO K SLP_LN# Panther Point_RP0 PH Pull-high/low(LG) R.0 change R to K R.0 uses k V V_S System PWR_OK(LG) V_S IMVP_PWRG PU V PWROK_E P so N gate output dont need P again V_S LKRUN# R XP_RST# R.K_.K/F_ PM_RI# PM_TLOW# R R 0K_.K_ 0.u/0V_ *0.U/0V_ R PH_RSMRST# R SYS_PWROK R *K_ 0K_ *0K_ PIE_WKE#_LN R 0K_ SLP_LN# R *0K_ SUSWRN#_R R 0K_ PRESENT R *0K_ 00 stuff R. PM_RM_PWRG R 00/F_ wo S leakage, un-stuff R0 00 R0 un-stuff. to PH Pin, XP and EE debug <> SYS_PWROK SYS_PWROK U TSH0FU R0 PWROK_E R 00K_ *0_ PWROK_E <> U IMVP_PWRG_R IMVP_PWRG <,> GFX_PWRG <,> *TSH0 R0 0_ 0 add 0ohm to passed IMVP_PERG include GFX_PWRG to SYS_PWROK for PH check Quanta omputer Inc. PROJET : Size ocument Number Panther Point / Rev ate: Monday, pril 0, 0 Sheet 0 of

8 RT ircuitry(rt) 0mils 0MIL 0MIL H us(lg) PH JTG ebug (LG) PH ual SPI (LG) *SHORT_ VRT_ 0MIL T 0/ add R0 _ R _ R _ 0 *p/0v_ 0MIL VRT_ VRT_ R.K_ VRT_ Q MMT0 000 change footprint. 0 change back RT connect 0 change RT connect to P. 0 change back RT connector to socket. 0 For EMI solution. 0 p/0v_ <> PH_Z_OE_ITLK R0 _ <> PH_Z_OE_SYN R _ <> <> PH_SPI_S0# PH_SPI_LK PH_SPI_SI PH_SPI_SO PH_Z_OE_RST# PH_Z_OE_SOUT R 0/F_ XP_TMS_VT PH_XP_TO_VT PH_XP_TO XP_TLK_VT (efault for WIN) WQVSSIG / KEP0N >M WQVSSIG / KEFP0N0----->M V_PH_ME R0.K_ 0/ add U PH_SPI_S# PH_SPI_LK E# V R _ PH_SPI_SI R _ SK PH_SPI_SO R _ SI R SO HOL# 0 *p/0v_ WP# VSS 0 contact to E thougth series resistor. ROM-M_E <> PH_SPI_LK_E <> PH_SPI_SI_E <> PH_SPI_SO_E V_PH_ME R <> VPU R R0 K_ V_S SPI_S0#_UR_ME T RT SOKET R _ V_S R R 0/F_ 0/F_ R 00/F_ R 00/F_.K_ V_RT R R 00/F_ R 0mils R 0K_ u/.v_ *SHORT_ U E# SK SI SO WP# ROM-M_ME 0K_ V R HOL# VSS R u/.v_ u/.v_ R _ R _ *0_ R 0_ R V_PH_ME RT_RST# J *SHORT_ P SRT_RST# J *SHORT_ P.K_ R.K/F_ Z_ITLK_R Z_SYN_OE Z_RST#_R Z_SOUT_R.K_.K_ R 0K/F_ V_PH_ME V_PH_ME V_S 0.u/0V_ 0 0.u/0V_ PH_SPI_S0# PH_SPI_S# PH(LG) dd MOSFET to separate OE SYN signal V R *SHORT_ ZRH use N00 Z_SYN_OE Q <> SPKR R.0 N00K R M_ PH Strap Table Pin Name Strap description Sampled onfiguration 0 = efault (weak pull-down 0K) SPKR No reboot mode setting PWROK = Setting to No-Reboot mode GNT# / GPIO GNT# / GPIO GPIO F_TVS Top-lock Swap Override oot IOS Selection [bit-] oot IOS Selection 0 [bit-0] MI/FI Termination voltage PWROK INTVRMEN Integrated.0V VRM enable LWYS Should be always pull-up GPIO On-die PLL Voltage Regulator PWROK PWROK H_SO Flash escriptor Security RSMRST PWROK RSMRST# 0 = "top-block swap" mode GNT# 0 PT/PPT (H,JTG,ST) = efault (weak pull-up 0K) = overridden GNT0# 0 LRQ0# V LRQ# / GPIO SERIRQ ST0RXN ST0RXP ST0TXN ST0TXP STRXN STRXP STTXN STTXP H_SIN0 STRXN STRXP H_SIN STTXN STTXP H_SIN STRXN H_SIN STRXP STTXN STTXP H_SO STRXN STRXP H_OK_EN# / GPIO V STTXN STTXP H_OK_RST# / GPIO V_S STRXN STRXP STTXN JTG_TK STTXP JTG_TMS STIOMPO JTG_TI STIOMPI JTG_TO STROMPO STOMPI SPI_LK STRIS SPI_S0# SPI_S# STLE# SPI_MOSI V ST0GP / GPIO SPI_MISO V STGP / GPIO Panther Point_RP0 oot Location SPI LP 0 = effect (default)(weak pull-down 0K) 0 = Set to Vss (weak pull-down 0K) = Set to Vcc 0 = isable = Enable (weak pull-up 0K) * efault weak pull-up on GNT0/# [Need external pull-down for LP IOS] 0 for future PU, Sandy ridge N F_TVS needs to be pulled up to VccFTERM power rail through. kohm ±% - R change to 0 or not?? 0 = Support by.v (weak pull-down) H_SYN On-ie PLL VR Voltage Select RSMRST V_S R0 K_ Z_SYN_R Needs to be pulled High for Huron River platform. = Support by.v chklist. GPIO SWVREN 000-modify p/0v_ p/0v_ Z_SOUT_R PH_GPIO TP PH_GPIO TP 0 Remove net TP_INT#, becaue change to pin E. <,> XP_TLK_VT XP_TLK_VT <,> XP_TMS_VT XP_TMS_VT <> PH_XP_TO_VT PH_XP_TO_VT PH_XP_TO TP 00 change power plant to V_PH_ME Intel ME rypto Transport Layer Security (TLS) cipher suite internal P EEP S/S well On ie SW VR Enable <> V_PH_ME V_RT Y.KHZ R PH_Z_OE_SIN0 R RSMRST SW R0 0M_ M_ *K_ RT_X RT_X RT_RST# SRT_RST# SM_INTRUER# PH_INVRMEN Z_ITLK_R Z_SYN_R SPKR Z_RST#_R PH_SPI_LK PH_SPI_S0# PH_SPI_S# PH_SPI_SI PH_SPI_SO 0 = isable (efault) = Enable TP High = Enable (efault) Low = isable G K N L T0 K E G N J H K H T Y T V U U RTX RTX RTRST# SRTRST# INTRUER# INTVRMEN H_LK H_SYN SPKR H_RST# IH RT ST LP ST G JTG SPI <> V V_RT ME_WR# R R V_S V_RT FWH0 / L0 FWH / L FWH / L FWH / L FWH / LFRME# R0 R0 R R R R R.K_ K_ R LP_L0 <,0,> LP_L <,0,> LP_L <,0,> LP_L <,0,> LP_LFRME# <,0,> R.0 uses 0kohm E PH_RQ#0 TP K PH_RQ# TP V SERIRQ <,> R.K_ V M M ST_RXN0 <> P ST_RXP0 <> ST H P ST_TXN0 <> ST_TXP0 <> 000 acer request H,MST need ST. M0 M ST_RXN <0> P ST_RXP <0> mst P0 ST_TXN <0> ST_TXP <0> H G recommended that coupling capacitors should be H TP close to the connector (<00 mils) for optimal signal quality. 0 UM ST port, disable. F F TP Y Y Y Y ST_RXN_ <> ST O ST_RXP_ <> ST_TXN <> ST_TXP <> Y Y0 ST_OMP R./F_.0V_VTT ST_OMP R./F_ H ST_RIS R 0/F_ 00 PU 0k to V, becaue no sata LE. P ST_T# R 0K_ V ST0GP/GPIO STGP/GPIO V PH_O_EN PH_O_EN <> STGP/GPIO If these pins are unused use.k P S_IT0 R 0K_ V to 0k pull-up to Vcc_ or.k 0 add R PU 0K to V for PH_O_EN not use. to 0k pull-down to ground *K_ *K_ 0K_ *K_ *K_ *K_ 0K_ R.V K_ R SPKR PI_GNT# <> PH_INVRMEN *SHORT_ S_IT <> S_IT0 Z_SOUT_R F_TVS <0> H_SN_IV# <> PLL_OVR_EN <0> PH_GPIO <0> *0K_ SWVREN <> Used as GPIO only. at chklist. ME_WR default E setting folating V_PH_ME 00 add pull up 0k to PSI S#. SPI_S0#_UR_ME R0 K_ NV_LE Intel nti-theft H protection Only for Interposer PWROK 0 = isable (Internal pull-down 0kohm).V R *K_ NV_LE <> Quanta omputer Inc. PROJET : Size ocument Number Rev Panther Point / ate: Monday, pril 0, 0 Sheet of 0

9 TX cap place at connector side, cap to connector < 00mils <> <0> <> 00 dd PLK_TPM for TPM. <> PLK_TPM <0> LK_LP_EUG <> LK_PI_E <> <> <> <> <> <> <> <> US0_RX US0_RX US0_RX- US0_RX- US0_TX- US0_TX- US0_TX US0_TX S_IT OR_I PI_GNT# <> GPU_PWR_EN <> GPU_HOL_RST# <,> PI_PLTRST# R0 _ LK_PI_F R _ R _ R _ TP TP0 TP0 TP TP TP TP TP PI_PIRQ# PI_PIRQ# PI_PIRQ# PI_PIRQ# GPU_EISEL# GPU_SELET# REQ# OR_I MP_PWR_TRL# GPU_PWR_EN GPU_HOL_RST# EXTTS_SNI_RV_PH TP PI_PME# PI_PLTRST# PLK_TPM_R LK_PI_F_ LK_LP_EUG_ LK_PI PT/PPT (PI,US,NVRM) G J H J G H H K K N0 H H M M Y K L M0 Y G E 0 E J E0 F G V U Y0 U Y V W0 K0 K H G E0 E F G G0 K0 H H J K H0 UE TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP TP0 RSV TP TP TP TP US.0 TP US0_RXN TP US0_RXN TP US0_RXN TP US0_RXN TP US0_RXP TP0 US0_RXP TP US0_RXP TP US0_RXP TP US0_TXN TP US0_TXN TP US0_TXN TP US0_TXN TP US0_TXP TP US0_TXP TP US0_TXP TP0 US0_TXP PIRQ# PIRQ# PIRQ# PIRQ# REQ# / GPIO0 REQ# / GPIO REQ# / GPIO GNT# / GPIO GNT# / GPIO GNT# / GPIO PIRQE# / GPIO PIRQF# / GPIO PIRQG# / GPIO PIRQH# / GPIO PME# PLTRST# LKOUT_PI0 LKOUT_PI LKOUT_PI LKOUT_PI LKOUT_PI Panther Point_RP0 PI V V V V V V V V V V US V_S V_S V_S V_S V_S V_S V_S V_S RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV0 RSV RSV RSV RSV RSV RSV RSV RSV RSV USP0N USP0P USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USPN USPP USP0N USP0P USPN USPP USPN USPP USPN USPP USRIS# USRIS O0# / GPIO O# / GPIO0 O# / GPIO O# / GPIO O# / GPIO O# / GPIO O# / GPIO0 O# / GPIO Y V U G T0 U T T T Y T V V E F V V0 T Y T F K H E N M L0 K0 G0 E0 0 0 L K G E K0 L US_IS US_O0# US_O# US_O# RM_I0 US_O# RM_I RM_I RM_I NV_LE <> port can be used on debug mode USP0- <> USP0 <> M US left side USP- <> USP <> M usb left side TP TP TP TP US port/ may not be available on all PH sku (HM support port only) R USP- <> USP <> USP- <> USP <> USP0- <0> USP0 <0> amera M US right side TWL UM US port,,, disable../f_ US_O0# <> EHI EHI ardreader LN Wireless XHI for USP0- <> PIE_RX- <> PIE_RX <> PIE_TX- <> PIE_TX <> PIE_RX- <> PIE_RX <> PIE_TX- <> PIE_TX <0> PIE_RX- <0> PIE_RX <0> PIE_TX- <0> PIE_TX ardreader U PIE port for commeral model S can't weak up. G J PERN V PERP U PETN PETP E F PERN 0 0.U/0V_ PIE_TX-_ PERP 0 0.U/0V_ PIE_TX_ Y PETN PETP G J PERN 0 0.u/0V_ PIE_TXN_ V PERP 00 0.u/0V_ PIE_TXP_ U PETN PETP F E PERN Y PERP PETN PETP G H PERN Y PERP PETN PETP UM ~ PIE port disable J G PERN U PERP V PETN PETP G0 J0 PERN Y0 PERP 0 PETN PETP 0 0.u/0V_ 0 0.u/0V_ <> LK_PIE_MM# <> LK_PIE_MM <> PIE_LKREQ0# PT/PPT (PI-E,SMUS,LK) V_S SMLLERT# / PHHOT# / GPIO V_S SMLLK / GPIO V_S SMLT / GPIO L_LK L_T L_RST# PEG LKRQ# / GPIO V_S LKOUT_PEG N LKOUT_PEG P LKOUT_PIEN LKOUT_MI_N TP LKOUT_PIEP LKOUT_MI_P V PIE_LKREQ# M PIELKRQ# / GPIO LKOUT_P_N LKOUT_P_P LKOUT_PIEN LKOUT_PIEP V PIE_LKREQ# V0 LKIN_MI_N PIELKRQ# / GPIO0 LKIN_MI_P Y Y LKOUT_PIEN LKIN N LKOUT_PIEP LKIN P V_S PIE_LKREQ# PIELKRQ# / GPIO LKIN_OT_N Y LKIN_OT_P Y LKOUT_PIEN LKOUT_PIEP V_S PIE_LKREQ# L LKIN_ST_N PIELKRQ# / GPIO LKIN_ST_P 000 WLN support S wake up function. V <0> LK_PIE_WLN# V LKOUT_PIEN REFLKIN Wireless <0> LK_PIE_WLN LKOUT_PIEP V_S <0> PIE_LKREQ# PIE_LKREQ# L PIELKRQ# / GPIO LKIN_PILOOPK PI-E* E PERN PIE_TXN_ W PERP PIE_TXP_ Y PETN PETP Y0 Y LKOUT_PIE0N LKOUT_PIE0P V_S PIE_LKREQ0# J PIELKRQ0# / GPIO LOKS SMUS V_S SMLERT# / GPIO SMLK SMT V_S SML0LERT# / GPIO0 SML0LK SML0T ontroller Link FLEX LOKS E H G E M M T P0 M0 V U M M F E J0 G0 G E K K K H PIE_LKREQ_PEG#_R LK_UF_PIE_GPLLN LK_UF_PIE_GPLLP LK_UF_LKN LK_UF_LKP LK_UF_REFLKN LK_UF_REFLKP LK_UF_REFSSLKN LK_UF_REFSSLKP LK_PH_M LK_PI_F R0 EV@0_ PEG_LKREQ# <> LK_PIE_VGN <> LK_PIE_VGP <> LK_PU_LKN <> LK_PU_LKP <> LK_PLL_SSLKN <> LK_PLL_SSLKP <> XTL_IN XTL_OUT 0 0 add for Touch pad interrupt pin from GPIO to GPIO. SMLERT# SMLERT# <> SM_PH_LK SM_PH_LK <0> SM_PH_T SM_PH_T <0> RMRST_NTRL_PH RMRST_NTRL_PH <> SM_ME0_LK SM_ME0_T For LN 000 del net SMLLERT# SMLLERT#_R TP SM_ME_LK SM_ME_T For E L_LK L_LK <0> L_T L_T <0> L_RST# L_RST# <0> Y MHz_XTL 0p/0V_ R XTL_IN <> LK_PIE_LOM# XTL_IN LN V 0 LKOUT_PEG N V XTL_OUT <> LK_PIE_LOM LKOUT_PEG P XTL_OUT V_S LK_PIE_LN_REQ# E <> LK_PIE_LN_REQ# M_ PEG LKRQ# / GPIO 0p/0V_ XLK_ROMP XLK_ROMP Y R 0./F_.0V_VTT V0 TP V LKOUT_PIEN LKOUT_PIEP V_S 000 hange P from P to 0P. LK_PIE_REQ# T PIELKRQ# / GPIO V V K LK_FLEX0 R *SHORT_ SKU_I TP V LKOUT_PIEN LKOUTFLEX0 / GPIO LKOUT_PIEP V_S V F LK_FLEX LK_PIE_REQ# LKOUTFLEX / GPIO TP K PIELKRQ# / GPIO V H LKOUTFLEX / GPIO OR_I <0,> K <> LK_PIE_XPN LKOUT_ITPXP_N <> LK_PIE_XPP K V K R *SHORT_ LKOUT_ITPXP_P LKOUTFLEX / GPIO O_PRSNT# <> Panther Point_RP0 PLTRST#(LG) V 0 change power plant to V. 0.u/0V_ PI_PLTRST# PLTRST# U TSH0FU R 00K_ R *0_ PLTRST# <,,0,,> PI/USO# Pull-up(LG) V_S US_O0# R 0K_ US_O# R 0K_ US_O# R 0K_ US_O# R 0K_ MP Switch ontrol MP_PWR_TRL# MP_PWR_TRL# R Low = MP ON High = MP OFF (efault) *K_ PI_PIRQ# R PI_PIRQ# R PI_PIRQ# R PI_PIRQ# R0 V R 0 MP_PWR_TRL# EXTTS_SNI_RV_PH REQ# 0KX V.K_.K_.K_.K_ GPU_HOL_RST# GPU_EISEL# dgpu_selet# LK_REQ/Strap Pin(LG) V_S R 0K_ PIE_LKREQ# R 0K_ PIE_LKREQ# R0 0K_ PIE_LKREQ0# R 0K_ PIE_LKREQ# R0 0K_ LK_PIE_LN_REQ# R 0K_ LK_PIE_REQ# R 0K_ LK_PIE_REQ# V R 0K_ PIE_LKREQ# R 0K_ PIE_LKREQ# V_S SMus(E) V_S <> N_MLK <> N_MT R.K_ Q N00W R.K_ SMus(PH) S V R.K_ Q0 SM_ME_LK SM_PH_T SM_ME_T SM_PH_LK N00W R.K_ S0 LK_ST <,,> LK_SLK <,,> R0 0K_ PIE_LKREQ_PEG#_R RIII Memory down strap V_S R *RMI@K/F_ RM_I0 R RMI@0K_ R RMI@K/F_ RM_I R *RMI@0K_ R0 RMI@K/F_ RM_I R *RMI@0K_ R RMI@K/F_ RM_I R0 *RMI@0K_ V R *00K_ GPU_PWR_EN R0 0K_ RM Hynix Elpida RM_In 0x000 0x00 Optimize SKU V R EV@0K_ R00 IV@0K_ V R0 EV@0K_ R IV@0K_ dgpu_pw_trl# SKU_I SKU_I0 VG H/W Setup (GPIO) (GPIO) (GPIO) Signal Menu TL : dgpu_vron UM Only 0 0 UM Hidden UM boot SKU_I dgpu Only 0 or 0 GPU Hidden GPU boot Switchable (Mux) 0 0 UMGPU dgpu/sg UM boot Optimize (Muxless) 0 UM UM/SG UM boot SKU_I0 <0> dgpu_pw_trl# 0 = GPU power is control by PH GPIO (iscrete, SG or Optimize) = GPU power is control by H/W (pure iscrete SKU) 00 remove pull/down resistor LK_UF_LKN R0 0K_ LK_UF_LKP R0 0K_ LK_UF_PIE_GPLLN R 0K_ LK_UF_PIE_GPLLP R 0K_ LK_UF_REFLKN R 0K_ LK_UF_REFLKP R0 0K_ LK_UF_REFSSLKN R0 0K_ LK_UF_REFSSLKP R 0K_ LK_PH_M R 0K_ LOK TERMINTION for FIM 0 change footprint to dual type. V_S if net RMRST_NTRL_PH change to PH control need stuff R. R 0K_ SMLERT# R.K_ SM_PH_LK R0.K_ SM_PH_T R.K_ SM_ME0_LK R0.K_ SM_ME0_T R 0K_ SMLLERT#_R Quanta omputer Inc. PROJET : Size ocument Number Rev Panther Point / Monday, pril 0, 0 ate: Sheet of 0

10 <> <> <> <> <> <> <,> 000 del R and net SMLLERT# TP PT/PPT (GPIO,VSS_NTF,RSV) STGP / GPIOV TH0 / GPIO V SLOK / GPIO V GPIO / MEM_LEV_S GPIO SW GPIO V_S STP_PI# / GPIO V GPIO V STGP / GPIOV STGP / GPIOV SLO / GPIO V STOUT0 / GPIO V STOUT / GPIO V STGP / GPIO V GPIO V_S F VSS_NTF_ STGP : strap for reserved at chklist. Panther Point_RP0 STGP : strap for reserved at chklist. NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled. 0/0/0 add select resistor SIO_EXT_SMI# SIO_EXT_SI# PH_GPIO <> SKU_I0 GPU_PWROK WK_GPIO PLL_OVR_EN GPU_VRON TP S_GPIO SIO_EXT_SMI# OR_I SIO_EXT_SI# I_EN# SMI GPU_PWROK G_SENSOR_I PH_GPIO WK_GPIO PLL_OVR_EN STP_PI# MI_OVRVLTG FI_OVRVLTG MFG_MOE OR_I0 TEST_SET_UP RIT_TEMP_REP# SV_ET V R 00_ GPU_VRON UF T MUSY# / GPIO0 V V TH / GPIO TH / GPIO V V TH / GPIO H TH / GPIO V V TH / GPIO0 E TH / GPIO V V TH / GPIO 0 GPIO V_S LN_PHY_PWR_TRL / GPIO V_S G GPIO V_S 0GTE U 0 T E E P K K V M N M V V E E F VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ GPIO NTF PU/MIS PEI RIN# PROPWRG U P Y GPU_PW_TRL# L_SELET OR_I SIO_0GTE E_PEI_R SIO_RIN# V SGPIO SIO_0GTE <> E_PEI <,> SIO_RIN# <> H_PWRGOO <> SMI US.0 I TL LOW = US.0 I SV_SET_UP High = Strong (efault) TEST_SET_UP S_GPIO 0 GPIO Pull-up/Pull-down(LG) GPIO : If not used then use.-kω to 0-kΩ pull-down to. MI TERMINTION VOLTGE OVERRIE PH_GPIO PLL_OVR_EN SIO_EXT_SMI# SIO_EXT_SI# STP_PI# SIO_0GTE SIO_RIN# RIT_TEMP_REP# Y0 PH_THRMTRIP# R 0_ THRMTRIP# PM_THRMTRIP# <> 000 reserve GPIO PU VPU T R 0K_ INIT_V# WK_GPIO R0 *0K_ F_TVS Y F_TVS <> 00 un-stuff R for SW GPU_PWROK R *0K_ H TS_VSS TS_VSS TS_VSS TS_VSS N_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_ VSS_NTF_0 VSS_NTF_ VSS_NTF_ 0 0 P K H0 K0 P G G H H J J J J J J E E F F R0.K/F_ R V V *0_ TP R0 R R R R 0K_ K_ *K_ 0K_ *K_ V V_S V V R V_S R R0 R R R R <> <,> high low Low = Tx, Rx terminated to same voltage ( oupling Mode) (EFULT) MI_OVRVLTG high VR=.V_SUS for RL Low VR =.V_SUS(default) *0K_ SV_ET assign to VI for VR control 0K_ 0K_ 0K_ *0K_ *0K_ OR_I OR_I OR_I0 OR_I OR_I OR_I OR_I oard_i Hight=Symatic, LOW=ELN. R IV@K_ *0K_ GPU_PW_TRL# R R0 R R0 R0 R0 R R R R00 R0 R R R R GPU power is control by H/W (pure iscrete SKU) *0K_ 0K_ 0K_ 0K_ *0K_ *0K_ *0K_ 0K_ 0K_ V_S V *00K/F_ GPU power is control by PH GPIO (iscrete, SG or Optimize) R *0K_ 0K_ 0K_ 0K_ 00K_ V VPU V EV@00K_ L_SELET LVS = Pull HIGH ep = Pull LOW R R *LVS@.K/F_ EP@K_ R 00K_ FI TERMINTION VOLTGE OVERRIE FI_OVRVLTG R *K_ LOW - Tx, Rx terminated to same voltage G_SENSOR_I R 0K_ R *K_ High = isable (efault) G_SENSOR_I Low = Enable MFG-TEST MFG_MOE R R 0K_ *K_ V Quanta omputer Inc. PROJET : Size ocument Number Rev Panther Point / Monday, pril 0, 0 ate: Sheet of 0 0

11 PH(LG) PT/PPT (POWER) V V 00 remove vcc core power sense net Vcc =m(mils) L 0ohm/ PT/PPT (POWER) UG POWER.0V_VTT.0V_VTT R *0_ VccORE =. (0mils).0V_VTT 0.u/0V_ UJ POWER 0 remove 0ohm resistor. VORE[] V U 0.0u/V_ 0u/.V_ 0u/.V_ 000 change power plant from V_S to VPU. VORE[] VLK N 0 remove 0ohm resistor. VORE[] VLK VIO[] VPU u/.v_ u/.v_.u/.v_ F VORE[] VSS U R *SHORT_ u/.v_ VSW_= m P u/.v_ VSUS_ = m(mils) F VORE[] VPSW T VIO[0] G VORE[] VSW_ P V_S R near PH ball for VP sense G VORE[] VIO[] G VORE[] PH_VSW V T R *SHORT_ 00 change for SW G VORE[] VLVS K 0.u/0V_ PSUSYP VIO[].0V_VTT G VORE[0] T G VORE[] VSSLVS K When is sku and ep, LVS power can short to V_SUS_LKF T VIO[] J VORE[].0V_VTT VPLL_PY_PH *0.u/0V_ V_[] 0.u/0V_ 0 remove 0ohm resistor. J VORE[] M T V_VPUS.0V_VTT.0V_VPLL_EXP J VORE[] VTX_LVS[] 00 remove vccalcd and vcctx_lds power, when LVS disable. L *0uH/00m_ H VSUS_[] J VORE[] M VPLLMI T L *uh/m_ J VORE[] VTX_LVS[].0V_VTT R *SHORT_ VPLL_PY L VSUS_[] R *SHORT_ VORE[] P VIO[] V VTX_LVS[] *0u/.V_ VSUS_[] P VSUS L V 0 *0u/.V_ N VTX_LVS[] PSUS[] VSUS_[0] 0.u/0V_ VIO[] P V_VUG VME(.0V) =??(??mils) VSUS_[] J V_V_GIO V *u/.v_.0v_vtt VPLLEXP VSW[] T VUPLL R *SHORT_.0V_VTT VccIO =. (0mils) V.0V_VTT VIO[] VREFSUS=m N V_[] R *SHORT_ VSW[] VIO[] VccSW =.0 (0mils).0V_VTT V_PH_VREFSUS V_S 0 remove 0ohm resistor. VSW[] VREF_SUS M R0 0/F_ N VMI = m(0mils) VIO[] V 0.u/0V_.V_V_MI R00V-0 V_S u/.v_ u/.v_ u/.v_ V_[] 0 VSW[] N V_USSUS N u/.v_ u/.v_ u/.v_ PSUS[] 0.u/0V_ 00 change for SW VIO[] R *SHORT_ VSW[] N V_VPSUS N VSUS_[] VIO[] 0 VSW[] *u/.v_ N T VFI_VRM VFI_VRM u/.v_ 00 remove R for power plant chnge to.0v_vtt. VREF= m VIO[] VVRM[] VSW[].V V_MI witdth >= 0mils. 0 P V_PH_VREF VSW[] VREF P R 0/F_ V u/.v_ 0u/.V_ VIO[0] 0 P T0 VLKMI = 0m(mils) 0u/.V_ 0u/.V_ 0 R00V-0 VIO[] VMI[] VSW[] V N0 P.V_V_MI_I V_MI_I.0V_VTT VSUS_[] u/.v_ VIO[] VSW[0] N 00 change for SW P L *0uH/00m_ VSUS_[] VIO[] VLKMI R */F_ VSW[] P0 V_VPSUS R *SHORT_ V_S T VSUS_[] V V_V_EXP VIO[] R *SHORT_ VSW[] P VSUS_ = m(mils) u/.v_ *0u/.V_ VSUS_[] R *SHORT_ N VSW[] u/0v_ VIO[] W N G VSW[] V_[] VIO[] VFTERM[] VP_NN.V VPNN = 0 m(mils) W W V_VPORE R0 *SHORT_ VSW[] V_[] V 0.u/0V_ H G W T V VPORE = m(0mils) V_[] VFTERM[] R *SHORT_ VSW[] V_[] W 0.u/0V_ J VSW[] VFTERM[] 0.u/0V_ W 0.u/0V_ VFI_VRM VFI_VRM P VSW[] VVRM[] J.0V_VTT W J VFTERM[] VSW[] V_[] V.0V_VTT R0 *0_.0V_VPLL_FI G R *SHORT_ W VccFIPLL VSW[0] F V_VME_SPI VIO[] VSPI = 0m(mils) 0.u/0V_.0V_VPLL_FI P 0.u/0V_ VRTEXT N R *SHORT_ VIO[] V u/.v_ PRT H VSPI VIO[].0V_VTT U0.V_V_MI VFI_VRM VFI_VRM Y H 0 remove 0ohm resistor. VMI[] R *SHORT_ VVRM[] VIO[].V V_MI witdth >= 0mils. u/.v_ u/0v_ Panther Point_RP0 F m(0mils).0v_v PL VIO[]??m(??mils) u/.v_ VPLL V.LN_VPLL.0V_VTT m(mils).0v_v PL F VPLLST K L *0uH/00m_ VVRM= m(mils) VPLL R *SHORT_ F VFI_VRM *0u/.V_ VIFFLK F VVRM[] VccMI needs to be powered by the same.0 V voltage source as VIFFLKN F VIO[] the PU VIO, and the trace needs to be at least 0 mils width with full VSS/ 0 F VIFFLKN[] V reference plane..0v_vtt 000 change power plant to V for power saving. u/.v_ VIFFLKN[] VIO[] VIFFLKN= m(0mils) G.0V_VTT VIFFLKN[] 0 remove 0ohm resistor. V VIO[] VSS= m(0mils) V_VME_SPI R *0_ V.0V_SSV G u/.v_ VFI_VRM R *0_ V_S VSS VIO[] FI VIO V ORE FT / SPI MI HVMOS LVS RT lock and Miscellaneous ST PI/GPIO/LP US.V.0V_VTT R0 R *SHORT_ *0_ VVRM:.V (estop) 0/0 del for Pre-ES.V (Mobile) R 0_ Reserve V_S to VSPI for E co-layout.0v_vtt R 00 remove R for power plant chnge to.0v_vtt. VRT<m(mils) V_RT 0.u/0V_ VSST *u/.v_ V.0M_VSUS *SHORT_m(mils) VTT_VPPU 0.u/.V_ 0.u/0V_ 0.u/0V_ V PSST T V PSUS[] PSUS[] J V_PRO_IO PU MIS T VSW[] V VSW[] T VSW[].0V_VTT VME =.0(0mils) 00 remove R PU.VSUS. 0 u/.v_ 0.u/0V_ 0.u/0V_ VRT Panther Point_RP0 RT H VSUSH P V._._H_IO R *u/.v_ 0.u/0V_ *SHORT_ V_S VSUSH= 0m(mils) V_S V_S V_S V_S V R *0_.0V_VTT L 0uH/00m_.0V_V PL *0.u/0V_ R O 00K_ Q *0.u/0V_ R O 00K_ Q R /F_ L 0uH/00m_ V_SUS_LKF.u/.V_ u/0v_ L 0uH/00m_ 0u/.V_ u/.v_.0v_v PL <,> SLP_SUS# R *SHORT_ R *SHORT_ 0u/.V_ u/.v_ Q N00W 0 change mose footprint to dual type. 00 SW ricuit 000 modify cuirucit. Quanta omputer Inc. PROJET : Size ocument Number Rev Panther Point / Monday, pril 0, 0 ate: Sheet of 0

12 IEX PEK-M () PH(LG) Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Monday, pril 0, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Monday, pril 0, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : Panther Point / Monday, pril 0, 0 0 UH Panther Point_RP0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] 0 VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] F0 VSS[] F VSS[] VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[] F VSS[0] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[0] H VSS[] H VSS[] H VSS[] J VSS[] J VSS[] J VSS[] K VSS[] K VSS[0] K VSS[] K VSS[] K VSS[] K VSS[] K VSS[] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] L VSS[] L VSS[] L VSS[] M VSS[] M VSS[] M VSS[00] M VSS[0] M VSS[0] M VSS[0] M VSS[0] N VSS[0] N VSS[0] N VSS[0] N VSS[0] P VSS[0] P VSS[] P VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] P VSS[] P VSS[] R VSS[0] R VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T VSS[] T0 VSS[] T VSS[] T VSS[] T VSS[] T VSS[] U VSS[] U0 VSS[] V VSS[] V0 VSS[] V VSS[] V0 VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[] W VSS[0] W VSS[] W VSS[] W VSS[] W0 VSS[] W VSS[] V VSS[] Y VSS[] Y VSS[] Y VSS[0] VSS[] E VSS[] VSS[] P VSS[0] H VSS[] F VSS[] VSS[] VSS[] J VSS[] J VSS[] E VSS[] T VSS[0] T VSS[0] M VSS[] L VSS[] L UI Panther Point_RP0 VSS[] Y VSS[0] Y VSS[] Y VSS[] Y VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] VSS[] VSS[] 0 VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[0] VSS[] 0 VSS[] VSS[] VSS[] VSS[] VSS[] E VSS[] E VSS[] E0 VSS[] F0 VSS[00] F VSS[0] F VSS[0] F0 VSS[0] F VSS[0] F VSS[0] F VSS[0] F VSS[0] VSS[0] F0 VSS[0] F VSS[0] F0 VSS[] F VSS[] G VSS[] G VSS[] G VSS[] G VSS[] G VSS[] H VSS[] H VSS[] H VSS[0] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] H VSS[] VSS[0] VSS[] VSS[] VSS[] VSS[] VSS[] VSS[] 0 VSS[] VSS[] K VSS[] L VSS[] L VSS[] L0 VSS[] L VSS[] L VSS[0] L VSS[] L VSS[] M VSS[] P VSS[] M VSS[] M VSS[] M VSS[] M0 VSS[] M VSS[] M VSS[0] M VSS[] M VSS[] M VSS[] M VSS[] M VSS[] N VSS[] P0 VSS[] P VSS[] P VSS[0] T VSS[] P0 VSS[] P VSS[] P VSS[] P VSS[] R VSS[] R VSS[] T VSS[] T VSS[] T VSS[00] T VSS[0] W VSS[0] T VSS[0] T VSS[0] T VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[0] V VSS[] V VSS[] V VSS[] V VSS[] V VSS[] W VSS[] W VSS[] VSS[] VSS[0] VSS[] VSS[] E VSS[] E VSS[] G VSS[] G0 VSS[] G VSS[] G VSS[] G VSS[] G VSS[0] H VSS[] H VSS[] W VSS[] W VSS[] W VSS[0] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] Y VSS[] G VSS[] N VSS[0] J VSS[] N VSS[] H VSS[] H VSS[] H VSS[] H0 VSS[] H VSS[] H VSS[] F VSS[] K VSS[] K VSS[] H VSS[0] K VSS[] K VSS[] VSS[] VSS[] E0 VSS[] G VSS[] G VSS[] H VSS[0] T VSS[] G VSS[] G VSS[] VSS[] P VSS[] F VSS[] H0 VSS[] M VSS[] P VSS[] P VSS[] E VSS[0] VSS[] G VSS[] J

13 . R IMM- H H0 H H0 S0 S RV add 00 change to K/F_ 00 change to K/F_ M solution Place these aps near So-imm0. M 0 M M M M M M 0 M M M M M M M M M LK_SLK LK_ST IMM_S0 IMM_S M QSP M QSP M QSP M QSP0 M QSP M QSP M QSP M QSP M QSN M QSN0 M QSN M QSN M QSN M QSN M QSN M QSN SMR_VREF_Q0 SMR_VREF_IMM_ SMR_VREF_Q0 M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q SMR_VREF_Q0_M M [:0] <> M S#0 <> M S# <> M S# <> M S# <> M RS# <> M WE# <> LK_SLK <,,> LK_ST <,,> R_RMRST# <,> M S#0 <> M S# <> M LK0 <> M LK0# <> M LK <> M LK# <> M KE0 <> M KE <> M OT0 <> M OT <> M QSP[:0] <> M QSN[:0] <> M Q[:0] <> SMR_VREF_Q0_M <> EEPS_E <,>.VSUS SMR_VREF_IMM_ SMR_VREF_Q0 V 0.V_R_VTT SMR_VREF_IMM_.VSUS.VSUS SMR_VREF V.VSUS 0.V_R_VTT Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 0 Monday, pril 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 0 Monday, pril 0, 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : RIII SO-IMM-0 0 Monday, pril 0, 0.u/V_ R0 K/F_ 00.u/V_ 0p/XR_ *0u/.V_ R *0_ U/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse 0 0 0/P 0 /# S0# S# K0 0 K0# 0 K 0 K# 0 KE0 KE S# RS# 0 WE# S0 S 0 SL 0 S 00 OT0 OT 0 M0 M M M M M M 0 M QS0 QS QS QS QS QS QS QS QS#0 0 QS# QS# QS# QS# QS# QS# QS# Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q0 Q Q Q Q Q Q Q 0 Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q *P0GN R 0K_.u/V_ R 0K_ 0 0u/.V_ P00 R SRM SO-IMM (0P) JIM R-IMM_H=._Reverse V V V V V V V V V V0 00 V 0 V 0 V V V V V V VSP N N NTEST EVENT# RESET# 0 VREF_Q VREF_ VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VTT 0 VTT u/.V_ R K/F_ R0 *0_ U/.V_.u/.V_ 0 0p/XR_.u/V_ 0.u/V_ R00 K/F_ 0u/.V_ 0u/.V_ U/.V_.u/V_ *0u/.V_.u/V_ TP.u/.V_ R *M@0_.u/V_ U/.V_ R K/F_

14 SO-IMM SP ddress is 0X SO-IMM TS ddress is 0X Place these aps near Memory own <R> Should be 0 Ohms -% Should be 0 Ohms -% Should be 0 Ohms -% Should be 0 Ohms -% address: WP = : WRITE ISLE / add change to K/F_ REV: dd YTE0_0- YTE_- YTE_- YTE_- YTE_- YTE_0- YTE_- YTE_- 00 Unstuff U and M M M M M 0 M M M M M M 0 M M M M M M M M M M 0 M M M M M M 0 M M M M M M S# M S#0 M S# M S# M RS# M WE# M LK0# M LK0 M KE0 M S#0 M OT0 R_RMRST# M ZQ M ZQ SMR_VREF_Q SMR_VREF_IMM SMR_VREF_IMM SMR_VREF_Q M ZQ M M M M M 0 M M M M M M 0 M M M M M SMR_VREF_IMM SMR_VREF_Q R_RMRST# M S# M S#0 M S# M S# M RS# M WE# M M M M M 0 M M M M M M 0 M M M M M M S# M S#0 M S# SMR_VREF_IMM SMR_VREF_Q M S# M RS# M WE# R_RMRST# M ZQ M QSP M QSN M QSP M QSN M LK0# M LK0 M KE0 M LK0# M LK0 M KE0 M S#0 M OT0 M S#0 M OT0 M QSP M QSN M QSP M QSN M QSN0 M QSP0 M QSP M QSN M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M QSN M QSP M QSP M QSN M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 LK_ST LK_SLK SMR_VREF_IMM SMR_VREF_Q SMR_VREF_Q_M M LK0 M LK0# SMR_VREF_Q SMR_VREF_IMM M [:0] <> M S#0 <> M S# <> M S# <> M LK0 <> M LK0# <> M KE0 <> M OT0 <> M S#0 <> M S# <> M RS# <> M WE# <> R_RMRST# <,> SMR_VREF_Q_M <> LK_SLK <,,> LK_ST <,,> EEPS_E <,> M Q[:0] <> M QSP[:0] <> M QSN[:0] <>.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS V.VSUS SMR_VREF SMR_VREF_IMM.VSUS SMR_VREF.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VREF_IMM SMR_VREF_Q.VSUS.VSUS.VSUS.VSUS.VSUS.VSUS Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Monday, pril 0, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Monday, pril 0, 0 0 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R MEMORY OWN Monday, pril 0, u/0V_ u/.v_ 0 0u/.V_ 0 u/.v_ u/.v_ u/.v_ R K/F_ 0.u/0V_ u/.v_ 0 u/.v_ 0.u/0V_ 0.u/0V_ u/.v_ 0 u/.v_ R 0/F_ 0.P/0V_ u/.v_ 0u/.V_ u/.v_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ 0 u/.v_ R00 K/F_ 0u/.V_ 0 0.u/0V_ u/.v_ 0u/.V_ 00-LL SRM R U0 RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# u/.v_ 0 u/.v_ u/.v_ u/.v_ 0 u/.v_ 0u/.V_ u/.v_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# 0.u/0V_ R *M@0_ u/.v_ *0.u/0V_ 0u/.V_ 00-LL SRM R U RM _R WE L RS J S K S L KE K K J K K QSU 0 M N P N P P R R T R 0/P L R QL0 E QL F QL F QL F QL H QL H QL G QL H VSSQ# VSS# VSS#E E VSS# N#J J V# V# VQ# VQ# VQ# VQ# N#L L N#J J VQ#E E ZQ L RESET T QSL F MU ML E VSSQ# VSSQ# VSSQ# VSSQ#E E QSU VSSQ#E E QSL G VQ#F F VSSQ#F F VSSQ#G G VQ#H H VQ#H H VSSQ#G G VREF M VSS#G G V#G G OT K 0 N P V#K K / N VSS#J J V#K K QU QU QU QU QU QU QU QU0 T T M M VREFQ H N#L L V#N N V#N N V#R R V#R R VSS#J J VSS#M M VSS#M M VSS#P P VSS#P P VSS#T T VSS#T T VQ# 0u/.V_ 0u/.V_ u/.v_ u/.v_ 0 0.u/0V_ 0 0u/.V_ u/.v_ u/.v_ u/.v_ 0.u/0V_ u/.v_ u/.v_ u/.v_ 0u/.V_ R 0/F_ u/.v_ u/.v_ R 0/F_ R 0/F_ 0 u/.v_ u/.v_ 0.u/0V_ 0 u/.v_ u/.v_ *0u/.V_ 0.u/0V_ 0u/.V_ 0 0.u/0V_ 0 0.u/0V_ 0 u/.v_ 0.u/0V_ u/.v_ 0u/.V_ 0.u/0V_ 0 0u/.V_ R K/F_ u/.v_ 0.u/0V_ 0 u/.v_ u/.v_ u/.v_ u/.v_ 0 0u/.V_ 0u/.V_ u/.v_ 0u/.V_ 0 u/.v_ 0.u/0V_ 0 u/.v_ R 0/F_ u/.v_ 00 u/.v_ u/.v_ 0u/.V_ u/.v_ u/.v_ u/.v_ R K/F_ 0.u/0V_ u/.v_ u/.v_ R *0_ u/.v_ u/.v_ 0 0u/.V_ u/.v_ u/.v_ Q0 *P0GN 0u/.V_ 0 u/.v_ 0 u/.v_ 0u/.V_ u/.v_ R0 *0_ U *M0-WMNTP 0 V SL S WP 0 u/.v_ u/.v_ R 0/F_ u/.v_ u/.v_ u/.v_