Microsoft PowerPoint - C15_LECTURE_NOTE_09

Size: px
Start display at page:

Download "Microsoft PowerPoint - C15_LECTURE_NOTE_09"

Transcription

1 MEMORY DEVICES, CIRCUITS, AND SUBSYSTEM DESIGN MEMORY DEVICES, CIRCUITS, AND SUBSYSTEM DESIGN 9.1 Program and Data Storage 9.2 Read-Only Memory 9.3 Random Access Read/Write Memories 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit 9.5 FLASH Memory 9.6 Wait-State Circuitry /8086 Microcomputer System Memory Circuitry 微處理機原理與應用 Lecture 09-2

2 9.1 Program and Data Storage The memory unit of a microcomputer is partitioned into a primary storage section and secondary storage section. Memory Unit Primary Storage Memory Program Data Storage Storage Memory Memory Secondary Storage Memory Input Unit MPU Output Unit 微處理機原理與應用 Lecture Program and Data Storage The basic input/output system (BIOS) are programs held in ROM. They are called firmware because of their permanent nature. The typical size of a BIOS ROM used in a PC today is 256 Kbytes. Programs are normally read in from the secondary memory storage device, stored in the program storage part of memory, and then run 微處理機原理與應用 Lecture 09-4

3 9.2 Read-Only Memory ROM, PROM, and EPROM Mask-programmable read-only memory (ROM) One-time-programmable read-only memory (PROM) Erasable read-only memory (EPROM) EPROM Programming unit 微處理機原理與應用 Lecture Read-Only Memory ROM, PROM, and EPROM 微處理機原理與應用 Lecture 09-6 EPROM erasing unit

4 9.2 Read-Only Memory Block diagram of a read-only memory Address bus Data bus Control bus Chip enable (CE) Output enable (OE) A 0 -A 10 Address bus ROM O 0 -O 7 Data bus CE OE Control bus 微處理機原理與應用 Lecture 09-7 Block diagram of a ROM 9.2 Read-Only Memory EXAMPLE Suppose the block diagram in the previous slide had 15 address lines and eight data lines. How many bytes of information can be stored in the ROM? What is its total storage capacity? Solution: With 8 data lines, the number of bytes is equal to the number of locations, which is 2 15 = 32,768 bytes This gives a total storage of 32,768 x 8 = 262,144 bits 微處理機原理與應用 Lecture 09-8

5 9.2 Read-Only Memory Read operation Address bus A 0 -A /8086 MPU Control bus CS Memory Interface circuits MEMR CE A 0 -A 10 OE D0 -D 7 Data bus D 0 -D 7 Read-only memory interface 微處理機原理與應用 Lecture Read-Only Memory Standard EPROM ICs EPROM C64 27C128 27C256 27C512 27C010 27C020 Density (bits) 27C040 4M Standard EPROM devices 微處理機原理與應用 Lecture K 32K 64K 128K 256K 512K 1M 2M Capacity (bytes) 2Kx8 4Kx8 8Kx8 16Kx8 32Kx8 64Kx8 128Kx8 256Kx8 512Kx8

6 9.2 Read-Only Memory Standard EPROM ICs Pin layouts of standard EPROMs 微處理機原理與應用 Lecture Read-Only Memory Standard EPROM ICs A short delay exists between address inputs and data outputs. Three important timing properties defined for the read cycle of an EPROM: Access time (t ACC ) Chip-enable time (t CE ) Chip-deselect time (t DF ) 微處理機原理與應用 Lecture 09-12

7 9.2 Read-Only Memory Standard EPROM ICs EPROM device timing characteristics 微處理機原理與應用 Lecture Read-Only Memory Standard EPROM ICs 微處理機原理與應用 Lecture EPROM switching waveforms

8 9.2 Read-Only Memory Standard EPROM ICs A complex series of program and verify operations are performed to program each storage location in an EPROM. The two widely used programming sequences are the Quick-Pulse Programming Algorithm and the Intelligent Programming Algorithm. CMOS EPROMs are designed to provide TTLcompatible input and output logic level 微處理機原理與應用 Lecture Read-Only Memory Standard EPROM ICs Quick-Pulse Programming Algorithm flowchart 微處理機原理與應用 Lecture 09-16

9 9.2 Read-Only Memory Standard EPROM ICs Intelligent Programming Algorithm flowchart 微處理機原理與應用 Lecture Read-Only Memory Standard EPROM ICs DC electrical characteristics of the 27C 微處理機原理與應用 Lecture 09-18

10 9.2 Read-Only Memory Expanding EPROM word length and word capacity 微處理機原理與應用 Lecture Expanding word length 9.2 Read-Only Memory Expanding EPROM word length and word capacity 微處理機原理與應用 Lecture Expanding word capacity

11 9.3 Random Access Read/Write Memories The memory section of a microcomputer system is normally formed from both read-only memories and random access read/write memories (RAM) RAM is different from ROM in two ways: Data stored in RAM is not permanent in nature. RAM is volatile that is, if power is removed from RAM, the stored data are lost. RAM is normally used to store data and application programs for execution 微處理機原理與應用 Lecture Random Access Read/Write Memories Static and dynamic RAMs For a static RAM (SRAM), data remain valid as long as the power supply is not turned off. For a dynamic RAM (DRAM), we must both keep the power supply turned on and periodically restore the data in each location. The recharging process is known as refreshing the DRAM 微處理機原理與應用 Lecture 09-22

12 9.3 Random Access Read/Write Memories Block diagram of a static RAM The most commonly used densities in RAM IC system designs are the 64KB and 256KB devices. The data lines are bidirectional and the read/write operations are controlled by the CE, OE, WE control signals. A 0 -A 12 Address bus CE, OE, WE Control bus SRAM I/O 0 -I/O 7 Data bus Block diagram of a static RAM 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德 9.3 Random Access Read/Write Memories A static RAM system 16K x 16-bit SRAM circuit 微處理機原理與應用 Lecture 09-24

13 9.3 Random Access Read/Write Memories Standard static RAM ICs SRAM A A Density (bits) 64K 64K 64K 256K 256K 1M Organization 64Kx1 16Kx4 8Kx8 64Kx4 32Kx8 128Kx8 Part number Read/write cycle time 100 ns 120 ns 150 ns 200 ns Speed selection for the 4364 SRAM Standard SRAM devices 微處理機原理與應用 Lecture Random Access Read/Write Memories Standard static RAM ICs (a) 4365 pin layout. (b) 43256A pin layout 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

14 9.3 Random Access Read/Write Memories DC electrical characteristics of the 微處理機原理與應用 Lecture Random Access Read/Write Memories SRAM read and write cycle operation Data valid Write-cycle timing diagram 微處理機原理與應用 Lecture 09-28

15 9.3 Random Access Read/Write Memories SRAM read and write cycle operation Read-cycle timing diagram 微處理機原理與應用 Lecture Random Access Read/Write Memories Standard dynamic RAM ICs Dynamic RAMs are available in higher densities than static RAMs. The most widely used DRAMs are the 64K-bit, 256K-bit, 1M-bit, and 4M-bit devices. Benefits of using DRAMs over SRAMs are: Cost less Consume less power The 16- and 18-pin package take up less space To maintain the data in a DRAM, each of the rows of the storage array must typically be refreshed periodically, such as every 2 ms 微處理機原理與應用 Lecture 09-30

16 9.3 Random Access Read/Write Memories Standard dynamic RAM ICs SRAM 2164B Density (bits) 64K 256K 256K 1M 1M 4M 4M 4M 16M 16M 16M 微處理機原理與應用 Lecture Organization 64Kx1 256Kx1 64Kx4 1Mx4 256Kx4 4Mx1 1Mx4 256Kx16 8Mx2 4Mx4 1Mx16 Standard DRAM devices 9.3 Random Access Read/Write Memories Standard dynamic RAM ICs (a) 2164B pin layout. (b) pin layout. (c) pin layout 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

17 9.3 Random Access Read/Write Memories Standard dynamic RAM ICs Address bus A 0 -A 7 Data input DRAM Data output Q RAS Control inputs CAS W Block diagram of the 2164 DRAM 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德 9.3 Random Access Read/Write Memories 64K x 16-bit DRAM circuit 微處理機原理與應用 Lecture 09-34

18 9.3 Random Access Read/Write Memories Evolution of RAM 1970 RAM / DRAM 4.77 MHz 1987 FPM 20 MHz 1995 EDO 20 MHz 1997 PC66 SDRAM 66 MHz 1998 PC100 SDRAM 100 MHz 1999 RDRAM 800 MHz 1999/2000 PC133 SDRAM 133 MHz 2000 DDR SDRAM 266 MHz 2001 EDRAM 450MHz 微處理機原理與應用 Lecture Random Access Read/Write Memories Evolution of RAM FPM-Fast Page Mode DRAM -traditional DRAM EDO-Extended Data Output -increases the Read cycle between Memory and the CPU SDRAM-Synchronous DRAM -synchronizes itself with the CPU bus and runs at higher clock speeds 微處理機原理與應用 Lecture 09-36

19 9.3 Random Access Read/Write Memories Evolution of RAM RDRAM-Rambus DRAM -DRAM with a very high bandwidth (1.6 GBps) EDRAM-Enhanced DRAM -(dynamic or power-refreshed RAM) that includes a small amount of static RAM (SRAM) inside a larger amount of DRAM so that many memory accesses will be to the faster SRAM. EDRAM is sometimes used as L1 and L2 memory and, together with Enhanced Synchronous Dynamic DRAM, is known as cached DRAM 微處理機原理與應用 Lecture Parity, the Parity Bit, and Parity- Checker/Generator Circuit To improve the reliability of information transfer between the MPU and memory, a parity bit can be added to each byte of data. The parity-checker/generator circuit can be set up to produce either even parity or odd parity. The parity-check/generator signals parity error to MPU by setting PE to zero. In a 16-bit microcomputer system, there are normally two 8-bit banks of DRAM ICs in the data-storage memory array. A parity bit DRAM is added to each bank 微處理機原理與應用 Lecture 09-38

20 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit Data-storage memory interface with parity-checker generator 微處理機原理與應用 Lecture Parity, the Parity Bit, and Parity- Checker/Generator Circuit (a) Block diagram of the 74AS280. (b) Function table. 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

21 9.4 Parity, the Parity Bit, and Parity- Checker/Generator Circuit 微處理機原理與應用 Lecture Even-parity checker/generator connection 9.5 FLASH Memory Flash memory devices are similar to EPROMs in that they are nonvolatile, are read like an EPROM, and program with an EPROM-like algorithm. The key difference between a FLASH memory and an EPROM is that its memory cells are erased electrically, instead of by exposure to ultraviolet light. When an erase operation is performed on a FLASH memory, either the complete memory array or a large block of storage location, not just one byte, is erased. The erase process of FLASH memory is complex and can take as long as several seconds. The FLASH memories find their widest use in microcomputer systems for storage of firmware 微處理機原理與應用 Lecture 09-42

22 9.5 FLASH Memory Block diagram of a FLASH memory Address bus A 0 -A 17 Data bus CE Control inputs FLASH D 0 -D 7 OE WE Block diagram of a FLASH memory 微處理機原理與應用 Lecture FLASH Memory Bulk-erase, boot block, and FlashFile FLASH memory FLASH memory array architectures 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

23 9.5 FLASH Memory Standard bulk-erase FLASH memories FLASH 28F256 28F512 28F010 28F020 Density (bits) 256K 512K 1M 2M Capacity (bytes) 32Kx8 64Kx8 128Kx8 256Kx8 Standard bulk-erase FLASH memory devices 微處理機原理與應用 Lecture FLASH Memory Standard bulk-erase FLASH memories The most popular package for housing FLASH memory ICs is the plastic leaded chip carrier, or PLCC. Part number 28F F F F Access time 70 ns 90 ns 120 ns 150 ns Pin layout of the 28F 微處理機原理與應用 Lecture Standard speed selection for the 28F020

24 9.5 FLASH Memory Quick-erase algorithm of the 28F 微處理機原理與應用 Lecture FLASH Memory Standard bulk-erase FLASH memories 28F020 command definitions 微處理機原理與應用 Lecture 09-48

25 9.5 FLASH Memory Quick-pulse programming algorithm of the 28F 微處理機原理與應用 Lecture FLASH Memory Standard boot block FLASH memories The boot block FLASH memories are designed for used in embedded microprocessor application. Pin-layout comparison of the TSOP 28F002, 28F004, and 28F008 IC 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

26 9.5 FLASH Memory Standard boot block FLASH memories One of the important features of boot block FLASH memory is what is known as SmartVoltage. This capability enables the device to be programmed with either a 5-V or 12-V value of V pp. The boot block devices can be organized with either 8-bit or 16-bit bus. Address bus A 0 -A 18(17) RP (F400 only) Data bus CE FLASH D 0 -D 7(15) OE WE WP BYTE (F400 only) Block diagram of the 28F004/28F400 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德 9.5 FLASH Memory Standard boot block FLASH memories Another new feature introduced with the boot block architecture is that of a hardware-lockable block. In the 28F004/28F400, the 16Kbyte boot block can be locked by applying logic 0 to the write protected input (WP). Top and bottom boot block organization of the 28F004 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

27 9.5 FLASH Memory Standard boot block FLASH memories If the 28F400 device is not in use, it can be put into the deep power-down mode to conserve power by switch RP (Reset/Deep power-down) input to logic 0. The 28F004/28F400 uses a command user interface (CUI), status register, and write-state machine to initiate an internally implemented and highly automated method of erasing and programming the blocks of the storage array. This is known as automatic erase and write 微處理機原理與應用 Lecture FLASH Memory Standard boot block FLASH memories 28F004 command bus definition 微處理機原理與應用 Lecture 09-54

28 9.5 FLASH Memory Standard boot block FLASH memories Status register bit definition 微處理機原理與應用 Lecture FLASH Memory Standard boot block FLASH memories Erase operation flowchart and bus activity 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

29 9.5 FLASH Memory Standard FlashFile FLASH memories The highest-density FLASH memories available today are those designed with the FlashFile architecture. FlashFile memories are intended for use in largecode storage applications and to implement solidstate mass-storage devices such as the FLASH card and FLASH drive. The FlashFile memories support block locking. The blocks are independently programmable as locked or unlocked 微處理機原理與應用 Lecture FLASH Memory Standard FlashFile FLASH memories RP 3/5 (SA only) Address bus A 0 -A 20 Data bus CE 0 D 28F016SA/SV 0 -D 15 CE 1 OE RY/BY WE WP BYTE Block diagram of the 28F016SA/SV 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

30 9.5 FLASH Memory Standard FlashFile FLASH memories 微處理機原理與應用 Lecture Pin lay-out of the SSOP 28F016SA/SV 9.5 FLASH Memory Standard FlashFile FLASH memories Byte-wide mode memory map of the 28F016SA/SV 微處理機原理與應用 Lecture 09-60

31 9.5 FLASH Memory FLASH packages Source: Micron Technology, Inc., 微處理機原理與應用 Lecture FLASH Memory FLASH memory applications Digital cellular phones PDAs Digital cameras LAN switches Digital set-top boxes Embedded controllers BIOS FLASH disk 微處理機原理與應用 Lecture 09-62

32 9.6 Wait-State Circuitry Depending on the access time of the memory devices used and the clock rate of the MPU, a number of wait states may need to be inserted into external memory read and write operations. CS 0 CS 1 MRDC MWTC RESET CLK Wait-state generator READY Wait-state generator circuit block diagram 微處理機原理與應用 Lecture Wait-State Circuitry Typical wait-state generator circuit 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

33 /8086 Microcomputer System Memory Circuitry Minimum-mode 8088 system memory interface 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德 /8086 Microcomputer System Memory Circuitry Minimum-mode 8086 system memory interface 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德

34 /8086 Microcomputer System Memory Circuitry Maximum-mode 8088 system memory interface 國立台灣大學生物機電系 微處理機原理與應用 Lecture 林達德 /8086 Microcomputer System Memory Circuitry Program storage memory Attaching several EPROM devices to the system bus expands the capacity of program storage memory. High-order bits of the 8088 s address are decoded to produce chip-select signals. Each chip-select is applied to the CE (chip-enable) input of the EPROM. In the maximum-mode circuit, the 8288 bus controller, rather than the 8088, produces the control signals for the address latches and data bus transceiver 微處理機原理與應用 Lecture 09-68

35 /8086 Microcomputer System Memory Circuitry Data storage memory Information that frequently changes is normally implemented with random access read/write memory (RAM). If the amount of memory required in the microcomputer is small, the memory subsystem is usually designed with SRAMs. DRAMs require refresh support circuit which is not warranted if storage requirement are small 微處理機原理與應用 Lecture /8086 Microcomputer System Memory Circuitry EXAMPLE Design a memory system consisting of 32Kbytes of R/W memory and 32Kbytes of ROM memory. Use SRAM devices to implement R/W memory and EPROM devices to implement ROM memory. The memory devices to be used are shown below. R/W memory is to reside over the address range through 07FFF 16 and the address range of ROM memory is to be F through FFFFF 16. Assume that the 8088 microprocessor system bus signals that follow are available for use: A 0 through A 19, D 0 through D 7, MEMR, MEMW 微處理機原理與應用 Lecture 09-70

36 /8086 Microcomputer System Memory Circuitry SOLUTION: First let us determine the number of SRAM devices needed. No. of SRAM devices = 32Kbyte/(16K x 4) = 4 To provide an 8-bit data bus, two SRAMs must be connected in parallel. Two pairs connected in this way are then placed in series to implement the R/W address range, and each pair implements 16Kbytes. Next let us determine the number of EPROM devices needed. No. of EPROM devices = 32Kbyte/16Kbyte = 2 These two devices must be connected in series to implement the ROM address range and each implement 16Kbytes of storage 微處理機原理與應用 Lecture /8086 Microcomputer System Memory Circuitry SOLUTION: Memory map of the system 微處理機原理與應用 Lecture 09-72

37 /8086 Microcomputer System Memory Circuitry SOLUTION: RAM memory organization for the system design 微處理機原理與應用 Lecture /8086 Microcomputer System Memory Circuitry SOLUTION: ROM memory organization for the system design 微處理機原理與應用 Lecture 09-74

38 /8086 Microcomputer System Memory Circuitry SOLUTION: Address range analysis for the design of chip select signals 微處理機原理與應用 Lecture /8086 Microcomputer System Memory Circuitry SOLUTION: 微處理機原理與應用 Lecture Chip-select logic

Microsoft PowerPoint - STU_EC_Ch08.ppt

Microsoft PowerPoint - STU_EC_Ch08.ppt 樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters

More information

Microsoft PowerPoint - C15_LECTURE_NOTE_08.ppt

Microsoft PowerPoint - C15_LECTURE_NOTE_08.ppt THE 888 AND 886 MICROPROCESSORS AND THEIR MEMORY AND INPUT/OUTPUT INTERFACES The 888 and 886 Microprocessors and Their Memory and Input/output Interfaces 8. The 888 and 886 Microprocessors 8.2 Minimum-Mode

More information

Cube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family

Cube20S small, speedy, safe Eextremely modular Up to 64 modules per bus node Quick reaction time: up to 20 µs Cube20S A new Member of the Cube Family small, speedy, safe Eextremely modular Up to 64 modules per bus de Quick reaction time: up to 20 µs A new Member of the Cube Family Murrelektronik s modular I/O system expands the field-tested Cube family

More information

2/80 2

2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application

More information

Microsoft PowerPoint - C15_LECTURE_NOTE_08.ppt

Microsoft PowerPoint - C15_LECTURE_NOTE_08.ppt The 888 and 886 Microprocessors and Their Memory and Input/output Interfaces TE 888 AND 886 MICROPROCESSORS AND TEIR MEMORY AND INPUT/OUTPUT INTERFACES 8. The 888 and 886 Microprocessors 8.2 Minimum-Mode

More information

Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11

Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11 Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs

More information

K7VT2_QIG_v3

K7VT2_QIG_v3 ............ 1 2 3 4 5 [R] : Enter Raid setup utility 6 Press[A]keytocreateRAID RAID Type: JBOD RAID 0 RAID 1: 2 7 RAID 0 Auto Create Manual Create: 2 RAID 0 Block Size: 16K 32K

More information

BC04 Module_antenna__ doc

BC04 Module_antenna__ doc http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 1 of 10 http://www.infobluetooth.com TEL:+86-23-68798999 Fax: +86-23-68889515 Page 2 of 10 http://www.infobluetooth.com TEL:+86-23-68798999

More information

P4V88+_BIOS_CN.p65

P4V88+_BIOS_CN.p65 1 Main H/W Monitor Boot Security Exit System Overview System Time System Date [ 17:00:09] [Wed 12/22/2004] BIOS Version : P4V88+ BIOS P1.00 Processor Type : Intel (R) Pentium (R) 4 CPU 2.40 GHz Processor

More information

P4VM800_BIOS_CN.p65

P4VM800_BIOS_CN.p65 1 Main H/W Monitor Boot Security Exit System Overview System Time System Date [ 17:00:09] [Fri 02/25/2005] BIOS Version : P4VM800 BIOS P1.00 Processor Type : Intel (R) Pentium (R) 4 CPU 2.40 GHz Processor

More information

1 VLBI VLBI 2 32 MHz 2 Gbps X J VLBI [3] CDAS IVS [4,5] CDAS MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz [6] CDAS VLBI CDAS 2 CDAS CDAS 5 2

1 VLBI VLBI 2 32 MHz 2 Gbps X J VLBI [3] CDAS IVS [4,5] CDAS MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz [6] CDAS VLBI CDAS 2 CDAS CDAS 5 2 32 1 Vol. 32, No. 1 2014 2 PROGRESS IN ASTRONOMY Feb., 2014 doi: 10.3969/j.issn.1000-8349.2014.01.07 VLBI 1,2 1,2 (1. 200030 2. 200030) VLBI (Digital Baseband Convertor DBBC) CDAS (Chinese VLBI Data Acquisition

More information

iml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi

iml88-0v C / 8W T Tube EVM - pplication Notes. IC Description The iml88 is a Three Terminal Current Controller (TTCC) for regulating the current flowi iml88-0v C / 8W T Tube EVM - pplication Notes iml88 0V C 8W T Tube EVM pplication Notes Table of Content. IC Description.... Features.... Package and Pin Diagrams.... pplication Circuit.... PCB Layout

More information

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin.

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin. Features Wide 3.6V to 32V Input Voltage Range Output Adjustable from 0.8V to 30V Maximum Duty Cycle 100% Minimum Drop Out 0.6V Fixed 300KHz Switching Frequency 12A Constant Output Current Capability Internal

More information

投影片 1

投影片 1 4 1 4-1 類 料, 兩 類 2 類 RAM (Random Access Memory, ) ROM (Read Only Memory, 讀 ) 兩, 類, 見 3 類 4 說 CPU, 料都, CPU 行 理 不 力 料, 料便, 料便, 料, CPU 料, 便 料, CPU 行 理 5 料 索 了 便 錄 讀 錄 度 量 量 6 (Virtual Memory) 數 Windows Linux

More information

System Design and Setup of a Robot to Pass over Steps Abstract In the research, one special type of robots that can pass over steps is designed and se

System Design and Setup of a Robot to Pass over Steps Abstract In the research, one special type of robots that can pass over steps is designed and se 8051 8051 System Design and Setup of a Robot to Pass over Steps Abstract In the research, one special type of robots that can pass over steps is designed and setup. This type of robot uses two kinds of

More information

Bus Hound 5

Bus Hound 5 Bus Hound 5.0 ( 1.0) 21IC 2007 7 BusHound perisoft PC hound Bus Hound 6.0 5.0 5.0 Bus Hound, IDE SCSI USB 1394 DVD Windows9X,WindowsMe,NT4.0,2000,2003,XP XP IRP Html ZIP SCSI sense USB Bus Hound 1 Bus

More information

Microsoft PowerPoint - ATF2015.ppt [相容模式]

Microsoft PowerPoint - ATF2015.ppt [相容模式] Improving the Video Totalized Method of Stopwatch Calibration Samuel C.K. Ko, Aaron Y.K. Yan and Henry C.K. Ma The Government of Hong Kong Special Administrative Region (SCL) 31 Oct 2015 1 Contents Introduction

More information

热设计网

热设计网 例 例 Agenda Popular Simulation software in PC industry * CFD software -- Flotherm * Advantage of Flotherm Flotherm apply to Cooler design * How to build up the model * Optimal parameter in cooler design

More information

iml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur

iml v C / 4W Down-Light EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the cur iml8683-220v C / 4W Down-Light EVM - pplication Notes iml8683 220V C 4W Down Light EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication

More information

(Load Project) (Save Project) (OffLine Mode) (Help) Intel Hex Motor

(Load Project) (Save Project) (OffLine Mode) (Help) Intel Hex Motor 1 4.1.1.1 (Load) 14 1.1 1 4.1.1.2 (Save) 14 1.1.1 1 4.1.2 (Buffer) 16 1.1.2 1 4.1.3 (Device) 16 1.1.3 1 4.1.3.1 (Select Device) 16 2 4.1.3.2 (Device Info) 16 2.1 2 4.1.3.3 (Adapter) 17 2.1.1 CD-ROM 2 4.1.4

More information

IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I

IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I 2004 5 IP TCP/IP PC OS µclinux MPEG4 Blackfin DSP MPEG4 IP UDP Winsock I/O DirectShow Filter DirectShow MPEG4 µclinux TCP/IP IP COM, DirectShow I Abstract The techniques of digital video processing, transferring

More information

iml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin

iml v C / 0W EVM - pplication Notes. IC Description The iml8683 is a Three Terminal Current Controller (TTCC) for regulating the current flowin iml8683-220v C / 0W EVM - pplication Notes iml8683 220V C 0W EVM pplication Notes Table of Content. IC Description... 2 2. Features... 2 3. Package and Pin Diagrams... 2 4. pplication Circuit... 3 5. PCB

More information

9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如

9 什 么 是 竞 争 与 冒 险 现 象? 怎 样 判 断? 如 何 消 除?( 汉 王 笔 试 ) 在 组 合 逻 辑 中, 由 于 门 的 输 入 信 号 通 路 中 经 过 了 不 同 的 延 时, 导 致 到 达 该 门 的 时 间 不 一 致 叫 竞 争 产 生 毛 刺 叫 冒 险 如 FPGA 工 程 师 面 试 试 题 一 1 同 步 电 路 和 异 步 电 路 的 区 别 是 什 么?( 仕 兰 微 电 子 ) 2 什 么 是 同 步 逻 辑 和 异 步 逻 辑?( 汉 王 笔 试 ) 同 步 逻 辑 是 时 钟 之 间 有 固 定 的 因 果 关 系 异 步 逻 辑 是 各 时 钟 之 间 没 有 固 定 的 因 果 关 系 3 什 么 是 " 线 与 " 逻 辑, 要 实

More information

Outline Speech Signals Processing Dual-Tone Multifrequency Signal Detection 云南大学滇池学院课程 : 数字信号处理 Applications of Digital Signal Processing 2

Outline Speech Signals Processing Dual-Tone Multifrequency Signal Detection 云南大学滇池学院课程 : 数字信号处理 Applications of Digital Signal Processing 2 CHAPTER 10 Applications of Digital Signal Processing Wang Weilian wlwang@ynu.edu.cn School of Information Science and Technology Yunnan University Outline Speech Signals Processing Dual-Tone Multifrequency

More information

SA-DK2-U3Rユーザーズマニュアル

SA-DK2-U3Rユーザーズマニュアル USB3.0 SA-DK2-U3R 2007.0 2 3 4 5 6 7 8 System Info. Manual Rebuild Delete RAID RAID Alarm Rebuild Rate Auto compare Temp Management Load Default Elapse time Event Log 0 2 3 4 2 3 4 ESC 5

More information

穨control.PDF

穨control.PDF TCP congestion control yhmiu Outline Congestion control algorithms Purpose of RFC2581 Purpose of RFC2582 TCP SS-DR 1998 TCP Extensions RFC1072 1988 SACK RFC2018 1996 FACK 1996 Rate-Halving 1997 OldTahoe

More information

52C-14266-5

52C-14266-5 逻 辑 分 析 仪 基 础 知 识 入 门 手 册 www.tektronix.com.cn/logic_analyzers 15 入 门 手 册 目 录 引 言 3-4 起 源 3 数 字 示 波 器 3 逻 辑 分 析 仪 4 逻 辑 分 析 仪 操 作 5-13 连 接 被 测 系 统 5 探 头 5 设 置 逻 辑 分 析 仪 7 设 置 时 钟 模 式 7 设 置 触 发 7 采 集 状

More information

NANO COMMUNICATION 23 No. 2-3D IC 29 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in

NANO COMMUNICATION 23 No. 2-3D IC 29 6T SRAM, ReRAM, sense amplifiers, analog amplifiers and gas sensors was integrated to confirm the superiority in 5 28-3D IC Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things 綉 3D IC (MOSFET) 40 50% 3D IC 3D IC IO(ultra-wide-IO)

More information

(Pattern Recognition) 1 1. CCD

(Pattern Recognition) 1 1. CCD ********************************* ********************************* (Pattern Recognition) 1 1. CCD 2. 3. 4. 1 ABSTRACT KeywordsMachine Vision, Real Time Inspection, Image Processing The purpose of this

More information

RAID RAID 0 RAID 1 RAID 5 RAID * ( -1)* ( /2)* No Yes Yes Yes A. B. BIOS SATA C. RAID BIOS RAID ( ) D. SATA RAID/AHCI ( ) SATA M.2 SSD ( )

RAID RAID 0 RAID 1 RAID 5 RAID * ( -1)* ( /2)* No Yes Yes Yes A. B. BIOS SATA C. RAID BIOS RAID ( ) D. SATA RAID/AHCI ( ) SATA M.2 SSD ( ) RAID RAID 0 RAID 1 RAID 5 RAID 10 2 2 3 4 * (-1)* (/2)* No Yes Yes Yes A. B. BIOS SATA C. RAID BIOS RAID ( ) D. SATA RAID/AHCI ( ) SATA M.2 SSD ( ) ( ) ( ) Windows USB 1 SATA A. SATASATAIntel SATA (SATA3

More information

Microsoft PowerPoint - C15_LECTURE_NOTE_11

Microsoft PowerPoint - C15_LECTURE_NOTE_11 INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR 11.1 Interrupt Mechanism, Types and Priority 11.2 Interrupt Vector Table 11.3 Interrupt Instructions

More information

PowerPoint Presentation

PowerPoint Presentation ITM omputer and ommunication Technologies Lecture #4 Part I: Introduction to omputer Technologies Logic ircuit Design & Simplification ITM 計算機與通訊技術 2 23 香港中文大學電子工程學系 Logic function implementation Logic

More information

邏輯分析儀的概念與原理-展示版

邏輯分析儀的概念與原理-展示版 PC Base Standalone LA-100 Q&A - - - - - - - SCOPE - - LA - - ( Embedded ) ( Skew ) - Data In External CLK Internal CLK Display Buffer ASIC CPU Memory Trigger Level - - Clock BUS Timing State - ( Timing

More information

1 CPU

1 CPU 2000 Tel 82316285 82317634 Mail liuxd@buaa.edu.cn 1 CPU 2 CPU 7 72 A B 85 15 3 1/2 M301 2~17 : 3/4 1/2 323 IBM PC 1. 2. 3. 1. 2. 3. 1.1 Hardware Software 1.2 M3 M2 M1 1.2 M3 M1 M2 M2 M1 M1 M1 1.2 M3 M1

More information

Tel:010-62981668-2930 1

Tel:010-62981668-2930  1 Access 93C46 with SPI function V1.0.0 Jan. 31, 2005 http://www.sunplusmcu.com Tel:010-62981668-2930 http://www.sunplusmcu.com E-mail:mcu@sunplus.com.cn 1 0 0...2 1...3 2...4 2.1...4 2.2...5 3...6 3.1 AT93C46...6

More information

(baking powder) 1 ( ) ( ) 1 10g g (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal D

(baking powder) 1 ( ) ( ) 1 10g g (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal D ( ) 4 1 1 1 145 1 110 1 (baking powder) 1 ( ) ( ) 1 10g 1 1 2.5g 1 1 1 1 60 10 (two level design, D-optimal) 32 1/2 fraction Two Level Fractional Factorial Design D-Optimal Design 1. 60 120 2. 3. 40 10

More information

投影片 1

投影片 1 2 理 1 2-1 CPU 2-2 CPU 理 2-3 CPU 類 2 什 CPU CPU Central Processing Unit ( 理 ), 理 (Processor), CPU 料 ( 例 ) 邏 ( 例 ),, 若 了 CPU, 3 什 CPU CPU 了, 行, 利 CPU 力 來 行 4 什 CPU 5 2-2-1 CPU CPU 了 (CU, Control Unit) / 邏

More information

声 明 本 人 郑 重 声 明 : 此 处 所 提 交 的 硕 士 学 位 论 文 基 于 等 级 工 鉴 定 的 远 程 考 试 系 统 客 户 端 开 发 与 实 现, 是 本 人 在 中 国 科 学 技 术 大 学 攻 读 硕 士 学 位 期 间, 在 导 师 指 导 下 进 行 的 研 究

声 明 本 人 郑 重 声 明 : 此 处 所 提 交 的 硕 士 学 位 论 文 基 于 等 级 工 鉴 定 的 远 程 考 试 系 统 客 户 端 开 发 与 实 现, 是 本 人 在 中 国 科 学 技 术 大 学 攻 读 硕 士 学 位 期 间, 在 导 师 指 导 下 进 行 的 研 究 中 国 科 学 技 术 大 学 硕 士 学 位 论 文 题 目 : 农 村 电 工 岗 位 培 训 考 核 与 鉴 定 ( 理 论 部 分 ) 的 计 算 机 远 程 考 试 系 统 ( 服 务 器 端 ) 的 开 发 与 实 现 英 文 题 目 :The Realization of Authenticating Examination System With Computer & Web for

More information

Embargoed until May 4, 2004 EXPRESS 40 NI HQ 3000 1000 5000 ~ 500 10% / 500 85% NI LabVIEW 7 Express Express EXPRESS : #1 GPS Navigation PC/WWW/Email CD+RW Mobile Phone PDA DVD+RW Satellite Car Alarm/Radio

More information

Guide to Install SATA Hard Disks

Guide to Install SATA Hard Disks SATA RAID 1. SATA. 2 1.1 SATA. 2 1.2 SATA 2 2. RAID (RAID 0 / RAID 1 / JBOD).. 4 2.1 RAID. 4 2.2 RAID 5 2.3 RAID 0 6 2.4 RAID 1.. 10 2.5 JBOD.. 16 3. Windows 2000 / Windows XP 20 1. SATA 1.1 SATA Serial

More information

逢 甲 大 學

逢  甲  大  學 益 老 年 不 易更 例 不 異 列 - I - 錄 錄 流 錄 六 來 錄 - II - 錄 錄 錄 錄 錄 錄 參 料 錄 - III - 料 讀 讀 錄 讀 數 錄 錄 錄 錄 錄 - IV - 錄 錄 行 錄 錄 錄 錄 讀 錄 錄 錄 讀 錄 錄 - V - 了 說 力 兩 了 - 1 - 列 邏 路 列 不 不 FLEX 10K Devices at a Glance Feature

More information

4. 每 组 学 生 将 写 有 习 语 和 含 义 的 两 组 卡 片 分 别 洗 牌, 将 顺 序 打 乱, 然 后 将 两 组 卡 片 反 面 朝 上 置 于 课 桌 上 5. 学 生 依 次 从 两 组 卡 片 中 各 抽 取 一 张, 展 示 给 小 组 成 员, 并 大 声 朗 读 卡

4. 每 组 学 生 将 写 有 习 语 和 含 义 的 两 组 卡 片 分 别 洗 牌, 将 顺 序 打 乱, 然 后 将 两 组 卡 片 反 面 朝 上 置 于 课 桌 上 5. 学 生 依 次 从 两 组 卡 片 中 各 抽 取 一 张, 展 示 给 小 组 成 员, 并 大 声 朗 读 卡 Tips of the Week 课 堂 上 的 英 语 习 语 教 学 ( 二 ) 2015-04-19 吴 倩 MarriottCHEI 大 家 好! 欢 迎 来 到 Tips of the Week! 这 周 我 想 和 老 师 们 分 享 另 外 两 个 课 堂 上 可 以 开 展 的 英 语 习 语 教 学 活 动 其 中 一 个 活 动 是 一 个 充 满 趣 味 的 游 戏, 另 外

More information

ICD ICD ICD ICD ICD

ICD ICD ICD ICD ICD MPLAB ICD2 MPLAB ICD2 PIC MPLAB-IDE V6.0 ICD2 usb PC RS232 MPLAB IDE PC PC 2.0 5.5V LED EEDATA MPLAB ICD2 Microchip MPLAB-IDE v6.0 Windows 95/98 Windows NT Windows 2000 www.elc-mcu.com 1 ICD2...4 1.1 ICD2...4

More information

<4D6963726F736F667420506F776572506F696E74202D20C8EDBCFEBCDCB9B9CAA6D1D0D0DEBDB2D7F92E707074>

<4D6963726F736F667420506F776572506F696E74202D20C8EDBCFEBCDCB9B9CAA6D1D0D0DEBDB2D7F92E707074> 软 件 架 构 师 研 修 讲 座 胡 协 刚 软 件 架 构 师 UML/RUP 专 家 szjinco@public.szptt.net.cn 中 国 软 件 架 构 师 网 东 软 培 训 中 心 小 故 事 : 七 人 分 粥 当 前 软 件 团 队 的 开 发 现 状 和 面 临 的 问 题 软 件 项 目 的 特 点 解 决 之 道 : 从 瀑 布 模 型 到 迭 代 模 型 解 决 项

More information

1.ai

1.ai HDMI camera ARTRAY CO,. LTD Introduction Thank you for purchasing the ARTCAM HDMI camera series. This manual shows the direction how to use the viewer software. Please refer other instructions or contact

More information

WTO

WTO 10384 200015128 UDC Exploration on Design of CIB s Human Resources System in the New Stage (MBA) 2004 2004 2 3 2004 3 2 0 0 4 2 WTO Abstract Abstract With the rapid development of the high and new technique

More information

<4D6963726F736F667420506F776572506F696E74202D20B5DAD2BBD5C228B4F2D3A1B0E6292E707074205BBCE6C8DDC4A3CABD5D>

<4D6963726F736F667420506F776572506F696E74202D20B5DAD2BBD5C228B4F2D3A1B0E6292E707074205BBCE6C8DDC4A3CABD5D> Homeworks ( 第 三 版 ):.4 (,, 3).5 (, 3).6. (, 3, 5). (, 4).4.6.7 (,3).9 (, 3, 5) Chapter. Number systems and codes 第 一 章. 数 制 与 编 码 . Overview 概 述 Information is of digital forms in a digital system, and

More information

Logitech Wireless Combo MK45 English

Logitech Wireless Combo MK45 English Logitech Wireless Combo MK45 Setup Guide Logitech Wireless Combo MK45 English................................................................................... 7..........................................

More information

Ác Åé å Serial ATA ( Sil3132) S A T A (1) SATA (2) BIOS SATA (3)* RAID BIOS RAID (4) SATA (5) SATA (a) S A T A ( S A T A R A I D ) (b) (c) Windows XP

Ác Åé å Serial ATA ( Sil3132) S A T A (1) SATA (2) BIOS SATA (3)* RAID BIOS RAID (4) SATA (5) SATA (a) S A T A ( S A T A R A I D ) (b) (c) Windows XP Serial ATA ( Sil3132)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 10 (5) S A T A... 12 Ác Åé å Serial ATA ( Sil3132) S A T A (1) SATA (2) BIOS SATA (3)* RAID BIOS

More information

PLC Simulative Control of an Elevator by PLC POWER SUPPLY ii iii ABSTRACT In the modern time, elevator is very popular and based. Most techniques of elevator are owned by foreigners. A simple introduction

More information

OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot

OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Prot OSI OSI OSI 15% 20% OSI OSI ISO International Standard Organization 1984 OSI Open-data System Interface Reference Model OSI OSI OSI OSI ISO Prototype Protocol OSI OSI OSI OSI OSI O S I 2-1 Application

More information

ebook140-8

ebook140-8 8 Microsoft VPN Windows NT 4 V P N Windows 98 Client 7 Vintage Air V P N 7 Wi n d o w s NT V P N 7 VPN ( ) 7 Novell NetWare VPN 8.1 PPTP NT4 VPN Q 154091 M i c r o s o f t Windows NT RAS [ ] Windows NT4

More information

JAEA-Technology indb

JAEA-Technology indb NBI 1 * 2 1 (2008 3 6 ) PLC 311-0193 801-1 1 2 Update of Control System for Auxiliary Pumping and Primary Water Cooling Facilities in JT-60 NBI Katsumi KIKUCHI 1, Noboru AKINO, Noboru EBISAWA, Yoshitaka

More information

SPHE8202R Design Guide Important Notice SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provi

SPHE8202R Design Guide Important Notice SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provi SPHE8202R Design Guide V2.0 JUN, 2007 19, Innovation First Road Science Park Hsin-Chu Taiwan 300 R.O.C. Tel: 886-3-578-6005 Fax: 886-3-578-4418 Web: www.sunplus.com SPHE8202R Design Guide Important Notice

More information

Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii

Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii 10384 200024024 UDC 2003 5 2003 6 2003 2003 5 i Abstract / / B-ISDN ATM Crossbar Batcher banyan N DPA Modelsim Verilog Synopsys Design Analyzer Modelsim FPGA ISE FPGA ATM ii System On-Chip Design and Performance

More information

EK-STM32F

EK-STM32F STMEVKIT-STM32F10xx8 软 件 开 发 入 门 指 南 目 录 1 EWARM 安 装... 1 1.1 第 一 步 : 在 线 注 册... 1 1.2 第 二 步 : 下 载 软 件... 2 1.3 第 三 步 : 安 装 EWARM... 3 2 基 于 STMEVKIT-STM32F10xx8 的 示 例 代 码 运 行... 6 2.1 GPIO Demo... 6 2.2

More information

!!

!! !! Noise Suppression by EMIFILr Application Guide Application Manual Cat.No.C35C !! 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 YYYYYYYYYYYYYYYYYYYYYY........................ YYYYYYYYYYYYYYYYYYYY........................

More information

SHIMPO_表1-表4

SHIMPO_表1-表4 For servo motor ABLEREDUCER SSeries Coaxial shaft series Features S series Standard backlash is 3 arc-min, ideal for precision control. High rigidity & high torque were achived by uncaged needle roller

More information

Microsoft PowerPoint - Performance Analysis of Video Streaming over LTE using.pptx

Microsoft PowerPoint - Performance Analysis of Video Streaming over LTE using.pptx ENSC 427 Communication Networks Spring 2016 Group #2 Project URL: http://www.sfu.ca/~rkieu/ensc427_project.html Amer, Zargham 301149920 Kieu, Ritchie 301149668 Xiao, Lei 301133381 1 Roadmap Introduction

More information

r_09hr_practical_guide_kor.pdf

r_09hr_practical_guide_kor.pdf PRACTICAL GUIDE TO THE EDIROL R-09HR 3 4 PRACTICAL GUIDE TO THE EDIROL R-09HR 5 Situation 1 6 1 2 3 PRACTICAL GUIDE TO THE EDIROL R-09HR WAV MP3 WAV 24 bit/96 khz WAV 16 bit/44.1 khz MP3 128 kbps/44.1

More information

SHIMPO_表1-表4

SHIMPO_表1-表4 For servo motor ABLEREDUCER L Series Features Coaxial shaft series L series Helical gears contribute to reduce vibration and noise. Standard backlash is 5 arc-min, ideal for precision control. High rigidity

More information

6-7 6-8 6-9 Process Data flow Data store External entity 6-10 Context diagram Level 0 diagram Level 1 diagram Level 2 diagram 6-11 6-12

6-7 6-8 6-9 Process Data flow Data store External entity 6-10 Context diagram Level 0 diagram Level 1 diagram Level 2 diagram 6-11 6-12 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 Process Data flow Data store External entity 6-10 Context diagram Level 0 diagram Level 1 diagram Level 2 diagram 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21

More information

AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING

AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING AN INTRODUCTION TO PHYSICAL COMPUTING USING ARDUINO, GRASSHOPPER, AND FIREFLY (CHINESE EDITION ) INTERACTIVE PROTOTYPING 前言 - Andrew Payne 目录 1 2 Firefly Basics 3 COMPONENT TOOLBOX 目录 4 RESOURCES 致谢

More information

1.1 ML_ONOFF = 1 Q 3 Q 8 C 0.3V M 2 L 1 ML_ONOFF = 0 Q 3 Q 8 C 1. + R31 VCC R21 10K ML_ONOFF R15 0:off 1:on 1K Green Light VCC=5V L1 Q VDD=12V C

1.1 ML_ONOFF = 1 Q 3 Q 8 C 0.3V M 2 L 1 ML_ONOFF = 0 Q 3 Q 8 C 1. + R31 VCC R21 10K ML_ONOFF R15 0:off 1:on 1K Green Light VCC=5V L1 Q VDD=12V C AUTOMATIC TROLLEY H K Hwang K K Chen J-S Lin S-C Wang M-L Li C-C Lin W-B Lin Dept. Of Electrical Engineering Far East College ABSTRACT This paper proposes an automatic trolley which can move automatically

More information

ARM JTAG实时仿真器安装使用指南

ARM JTAG实时仿真器安装使用指南 ARM JTAG Version 1.31 2003. 11. 12 ARM JTAG ARM JTAG.3 ARM 2.1.4 2.2.4 ARM JTAG 3.1 18 3.2 18 3.2.1 Multi-ICE Server.18 3.2.2 ADS..21 ARM JTAG 4.1 Multi-ICE Server 33 4.1.1 Multi-ICE Server..... 33 4.1.2

More information

Microsoft PowerPoint - Aqua-Sim.pptx

Microsoft PowerPoint - Aqua-Sim.pptx Peng Xie, Zhong Zhou, Zheng Peng, Hai Yan, Tiansi Hu, Jun-Hong Cui, Zhijie Shi, Yunsi Fei, Shengli Zhou Underwater Sensor Network Lab 1 Outline Motivations System Overview Aqua-Sim Components Experimental

More information

P3B-F Pentium III/II/Celeron TM

P3B-F Pentium III/II/Celeron TM P3B-F Pentium III/II/Celeron TM 1999 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 13 R PS2 KBMS USB COM1 COM2 JTPWR ATXPWR PWR_FAN CPU_FAN Row 0 1 2 3 4 5 6 7 DSW JP20

More information

致 谢 开 始 这 篇 致 谢 的 时 候, 以 为 这 是 最 轻 松 最 愉 快 的 部 分, 而 此 时 心 头 却 充 满 了 沉 甸 甸 的 回 忆 和 感 恩, 一 时 间 竟 无 从 下 笔 虽 然 这 远 不 是 一 篇 完 美 的 论 文, 但 完 成 这 篇 论 文 要 感 谢

致 谢 开 始 这 篇 致 谢 的 时 候, 以 为 这 是 最 轻 松 最 愉 快 的 部 分, 而 此 时 心 头 却 充 满 了 沉 甸 甸 的 回 忆 和 感 恩, 一 时 间 竟 无 从 下 笔 虽 然 这 远 不 是 一 篇 完 美 的 论 文, 但 完 成 这 篇 论 文 要 感 谢 中 国 科 学 技 术 大 学 博 士 学 位 论 文 论 文 课 题 : 一 个 新 型 简 易 电 子 直 线 加 速 器 的 关 键 技 术 研 究 学 生 姓 名 : 导 师 姓 名 : 单 位 名 称 : 专 业 名 称 : 研 究 方 向 : 完 成 时 间 : 谢 家 麟 院 士 王 相 綦 教 授 国 家 同 步 辐 射 实 验 室 核 技 术 及 应 用 加 速 器 物 理 2006

More information

1 o o o CPU o o o o o SQL Server 2005 o CPU o o o o o SQL Server o Microsoft SQL Server 2005

1 o o o CPU o o o o o SQL Server 2005 o CPU o o o o o SQL Server o Microsoft SQL Server 2005 1 o o o CPU o o o o o SQL Server 2005 o CPU o o o o o SQL Server o Microsoft SQL Server 2005 1 1...3 2...20 3...28 4...41 5 Windows SQL Server...47 Microsoft SQL Server 2005 DBSRV1 Microsoft SQL Server

More information

Serial ATA ( nvidia nforce4 Ultra/SLI)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A (6) Micro

Serial ATA ( nvidia nforce4 Ultra/SLI)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A (6) Micro Serial ATA ( nvidia nforce4 Ultra/SLI)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A... 11 (6) Microsoft Windows 2000... 14 Ác Åé å Serial ATA ( nvidia

More information

Microsoft Word - ChineseSATII .doc

Microsoft Word - ChineseSATII .doc 中 文 SAT II 冯 瑶 一 什 么 是 SAT II 中 文 (SAT Subject Test in Chinese with Listening)? SAT Subject Test 是 美 国 大 学 理 事 会 (College Board) 为 美 国 高 中 生 举 办 的 全 国 性 专 科 标 准 测 试 考 生 的 成 绩 是 美 国 大 学 录 取 新 生 的 重 要 依

More information

ebook140-9

ebook140-9 9 VPN VPN Novell BorderManager Windows NT PPTP V P N L A V P N V N P I n t e r n e t V P N 9.1 V P N Windows 98 Windows PPTP VPN Novell BorderManager T M I P s e c Wi n d o w s I n t e r n e t I S P I

More information

Microsoft PowerPoint - Sens-Tech WCNDT [兼容模式]

Microsoft PowerPoint - Sens-Tech WCNDT [兼容模式] X-ray data acquisition systems for NDT applications 技股份有限公司 先锋科技股份有限公司 科技股份有限公司 先锋科技股份有限公司 www Sens-Tech Ltd UK based company 40 Staff Specialise in detection and data acquisition systems for light and

More information

untitled

untitled LBS Research and Application of Location Information Management Technology in LBS TP319 10290 UDC LBS Research and Application of Location Information Management Technology in LBS , LBS PDA LBS

More information

Microsoft Word - LR1122B-B.doc

Microsoft Word - LR1122B-B.doc UNISONIC TECHNOLOGIES CO., LTD LOW NOISE ma LDO REGULATOR DESCRIPTION The UTC is a typical LDO (linear regulator) with the features of High output voltage accuracy, low supply current, low ON-resistance,

More information

(Guangzhou) AIT Co, Ltd V 110V [ ]! 2

(Guangzhou) AIT Co, Ltd V 110V [ ]! 2 (Guangzhou) AIT Co, Ltd 020-84106666 020-84106688 http://wwwlenxcn Xi III Zebra XI III 1 (Guangzhou) AIT Co, Ltd 020-84106666 020-84106688 http://wwwlenxcn 230V 110V [ ]! 2 (Guangzhou) AIT Co, Ltd 020-84106666

More information

Improved Preimage Attacks on AES-like Hash Functions: Applications to Whirlpool and Grøstl

Improved Preimage Attacks on AES-like Hash Functions: Applications to Whirlpool and Grøstl SKLOIS (Pseudo) Preimage Attack on Reduced-Round Grøstl Hash Function and Others Shuang Wu, Dengguo Feng, Wenling Wu, Jian Guo, Le Dong, Jian Zou March 20, 2012 Institute. of Software, Chinese Academy

More information

<4D6963726F736F667420576F7264202D2032303130C4EAC0EDB9A4C0E04142BCB6D4C4B6C1C5D0B6CFC0FDCCE2BEABD1A15F325F2E646F63>

<4D6963726F736F667420576F7264202D2032303130C4EAC0EDB9A4C0E04142BCB6D4C4B6C1C5D0B6CFC0FDCCE2BEABD1A15F325F2E646F63> 2010 年 理 工 类 AB 级 阅 读 判 断 例 题 精 选 (2) Computer mouse How does the mouse work? We have to start at the bottom, so think upside down for now. It all starts with mouse ball. As the mouse ball in the bottom

More information

ARM Cortex-M3 (STM32F) STMicroelectronics ( ST) STM32F103 Core: ARM 32-bit Cortex -M3 CPU 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz Single-cycle multiplica

ARM Cortex-M3 (STM32F) STMicroelectronics ( ST) STM32F103 Core: ARM 32-bit Cortex -M3 CPU 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz Single-cycle multiplica CP Chip Power ARM Cortex-M3 (STM32F) ARM Cortex-M3 (STM32F) STMicroelectronics ( ST) STM32F103 Core: ARM 32-bit Cortex -M3 CPU 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz Single-cycle multiplication and hardware

More information

ATMEL AT90S8515 AVR CPU AVR AVR AVR ATMEL RISC 32 8 r0 r X Y Z R0 R1 R2 R13 R14 R15 R16 R17 R26 R27 R28 R29 R30 R31 0x00 0x

ATMEL AT90S8515 AVR CPU AVR AVR AVR ATMEL RISC 32 8 r0 r X Y Z R0 R1 R2 R13 R14 R15 R16 R17 R26 R27 R28 R29 R30 R31 0x00 0x 115 AVR W.V. Awdrey ATMEL AVR PIC AVR PIC AVR RISC AVR PIC AVR AVR AVR AVR AVR ATtiny15 AVR AVR AVR RAM ROM 121 116 122 ATMEL AT90S8515 AVR CPU AVR AVR AVR ATMEL RISC 32 8 r0 r31 3 16 X Y Z 6-1 118 7 0

More information

Serial ATA ( Nvidia nforce430)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A (6) Microsoft Win

Serial ATA ( Nvidia nforce430)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A (6) Microsoft Win Serial ATA ( Nvidia nforce430)...2 (1) SATA... 2 (2) B I O S S A T A... 3 (3) RAID BIOS RAID... 6 (4) S A T A... 9 (5) S A T A... 11 (6) Microsoft Windows 2000... 14 Ác Åé å Serial ATA ( Nvidia nforce430)

More information

untitled

untitled EDM12864-GR 1 24 1. ----------------------------------------------------3 2. ----------------------------------------------------3 3. ----------------------------------------------------3 4. -------------------------------------------------------6

More information

第二十四屆全國學術研討會論文中文格式摘要

第二十四屆全國學術研討會論文中文格式摘要 以 田 口 動 態 法 設 計 物 理 治 療 用 牽 引 機 與 機 構 改 善 1, 2 簡 志 達 馮 榮 豐 1 國 立 高 雄 第 一 科 技 大 學 機 械 與 自 動 化 工 程 系 2 傑 邁 電 子 股 份 有 限 公 司 1 摘 要 物 理 治 療 用 牽 引 機 的 主 要 功 能 是 將 兩 脊 椎 骨 之 距 離 拉 開, 使 神 經 根 不 致 受 到 壓 迫 該 類 牽

More information

Oracle 4

Oracle 4 Oracle 4 01 04 Oracle 07 Oracle Oracle Instance Oracle Instance Oracle Instance Oracle Database Oracle Database Instance Parameter File Pfile Instance Instance Instance Instance Oracle Instance System

More information

The Development of Color Constancy and Calibration System

The Development of Color Constancy and Calibration System The Development of Color Constancy and Calibration System The Development of Color Constancy and Calibration System LabVIEW CCD BMP ii Abstract The modern technologies develop more and more faster, and

More information

USB解决方案.ppt

USB解决方案.ppt USB USB? RS232 USB USB HID U modem ADSL cable modem IrDA Silabs USB CP210x USB UART USB RS-232 USB MCU 15 USB 12 FLASH MCU 3 USB MCU USB MCU C8051F32x 10 ADC 1.5%, Vref CPU 25MIPS 8051 16KB Flash -AMUX

More information

<4D6963726F736F667420576F7264202D20C9CFBAA3BFC6BCBCB4F3D1A7D0C5CFA2D1A7D4BA32303136C4EAC7EFBCBEC8EBD1A7B2A9CABFD7CAB8F1BFBCCAD4CAB5CAA9CFB8D4F22D30343036C8B7B6A8B8E5>

<4D6963726F736F667420576F7264202D20C9CFBAA3BFC6BCBCB4F3D1A7D0C5CFA2D1A7D4BA32303136C4EAC7EFBCBEC8EBD1A7B2A9CABFD7CAB8F1BFBCCAD4CAB5CAA9CFB8D4F22D30343036C8B7B6A8B8E5> 上 海 科 技 大 学 信 息 科 学 与 技 术 学 院 年 度 博 士 资 格 考 试 实 施 细 则 一 总 则 本 细 则 由 上 海 科 技 大 学 信 息 科 学 与 技 术 学 院 ( 以 下 简 称 信 息 学 院 ) 教 学 指 导 委 员 会 讨 论 制 定, 适 用 于 信 息 学 院 2014 级 硕 士 研 究 生 的 年 度 博 士 资 格 考 试 信 息 学 院 2014

More information

OVLFx3C7_Series_A3_bgry-KB.pub

OVLFx3C7_Series_A3_bgry-KB.pub (5 mm) x High brightness with well-defined spatial radiation patterns x U-resistant epoxy lens x Blue, green, red, yellow Product Photo Here Each device in the OLFx3C7 series is a high-intensity LED mounted

More information

典型自编教材

典型自编教材 河 南 科 技 大 学 计 算 机 实 验 教 学 中 心 1. 计 算 机 文 化 基 础 实 验 指 导 书 2. 数 据 结 构 实 验 指 导 书 3. 操 作 系 统 实 验 指 导 书 4. 面 向 对 象 程 序 设 计 实 验 指 导 书 5. 数 据 库 原 理 实 验 指 导 书 6. 编 译 原 理 实 验 指 导 书 7. JAVA 程 序 设 计 实 验 指 导 书 8.

More information

Microsoft Word - 11月電子報1130.doc

Microsoft Word - 11月電子報1130.doc 發 行 人 : 楊 進 成 出 刊 日 期 2008 年 12 月 1 日, 第 38 期 第 1 頁 / 共 16 頁 封 面 圖 話 來 來 來, 來 葳 格 ; 玩 玩 玩, 玩 數 學 在 11 月 17 到 21 日 這 5 天 裡 每 天 一 個 題 目, 孩 子 們 依 據 不 同 年 段, 尋 找 屬 於 自 己 的 解 答, 這 些 數 學 題 目 和 校 園 情 境 緊 緊 結

More information

2006 6 6-186 - 2006 6 6-187 - 2006 6 6 Application of GPRS in Agricultural Monitoring System GAO Xiang-yang, WANG Ku, LI Mo-xue (College of Information and Electrical Engineering, China Agricultural University,

More information

Gerotor Motors Series Dimensions A,B C T L L G1/2 M G1/ A 4 C H4 E

Gerotor Motors Series Dimensions A,B C T L L G1/2 M G1/ A 4 C H4 E Gerotor Motors Series Size CC-A Flange Options-B Shaft Options-C Ports Features 0 0 5 5 1 0 1 0 3 3 0 0 SAE A 2 Bolt - (2) 4 Bolt Magneto (4) 4 Bolt Square (H4) 1.0" Keyed (C) 25mm Keyed (A) 1.0' 6T Spline

More information

Table of Contents A. Product Outline.. 3 B. Features.. 4 C. Block Diagram... 5 D. Pin Assignments. 6 E. Physical Specifications... 7 F. DC Characteris

Table of Contents A. Product Outline.. 3 B. Features.. 4 C. Block Diagram... 5 D. Pin Assignments. 6 E. Physical Specifications... 7 F. DC Characteris Micro SD Card TM Product Specification Version 1.0 Information in this document is provided in connection with TwinMOS products. No license, express or implied, by estoppels or otherwise, to any intellectual

More information

PowerPoint 演示文稿

PowerPoint 演示文稿 The Application & Prospect of Business Intelligence in Metallurgical Manufacturing Enterprises in China He Haoran, CTO for AP, 5 Shanghai Baosight Software Co., Ltd (China) The Informization Situation

More information

软件测试(TA07)第一学期考试

软件测试(TA07)第一学期考试 一 判 断 题 ( 每 题 1 分, 正 确 的, 错 误 的,20 道 ) 1. 软 件 测 试 按 照 测 试 过 程 分 类 为 黑 盒 白 盒 测 试 ( ) 2. 在 设 计 测 试 用 例 时, 应 包 括 合 理 的 输 入 条 件 和 不 合 理 的 输 入 条 件 ( ) 3. 集 成 测 试 计 划 在 需 求 分 析 阶 段 末 提 交 ( ) 4. 单 元 测 试 属 于 动

More information

DPJJX1.DOC

DPJJX1.DOC 8051 111 2K 1 2 3 ' ' 1 CPU RAM ROM / A/D D/A PC CPU 40 68 10 20 8 51 PIII 8051 2 MCS51 8051 8031 89C51 8051 8031 89C51? MCS51 INTEL INTEL 8031 8051 8751 8032 8052 8752 8051 8051 8051 MCS51 8031 8031

More information

Microsoft PowerPoint ARIS_Platform_en.ppt

Microsoft PowerPoint ARIS_Platform_en.ppt ARIS Platform www.ixon.com.tw ARIS ARIS Architecture of Integrated Information System Prof. Dr. Dr. h.c. mult. August-Wilhelm Scheer ARIS () 2 IDS Scheer AG International Presence >> Partners and subsidiaries

More information

Microsoft PowerPoint - AWOL - Acrobat Windows Outlook.ppt [Compatibility Mode]

Microsoft PowerPoint - AWOL - Acrobat Windows Outlook.ppt [Compatibility Mode] AWOL Windows - Tips & Tricks Resolution, color depth & refresh rate Background color Service packs Disk cleanup (cleanmgr) Disk defragmentation AWOL Windows Resolution, Color Depth & Refresh Rate The main

More information