va70_hw_mb_r20_0206_gddr5

Transcription

1 HMI PE ep Panel PE RT K/ PE lick T/P FN PE 9 Head Phone (ombo Jack) MI TPM PE PE PE PE 9 I ep x zalia odec RTK/L PE 0 V0HW LOK IRM dpu NVII NE PE E ITE PE 0~9 PIE X V zalia LP HPI PU Haswell FI x PH Lynx Point PE -0 MI x PE -9 RL /00 MHz channel RL /00 MHz channel U.0 U.0 U.0 U.0 U.0 U.0 U.0 PIE * U.0 R-III O-IMM* R-III O-IMM* amera U PORT9 U PORT U0 PORT U0 PORT U0 PORT0 U0 PORT Miniard WLN/WMX T combo PE PE PE PE PE POWER PU VORE PE 0 YTEM, +V, +V PE +VP & +VP_VT PE R & VTT PE.V &.V &.V PE MRT HRER PE POWER ETET PE 90 LO WITH PE 9 POWER PROTET PE 9 Power Rails leep tate 0 RT V VU ON ON ON ON ON ON ON ON ON / ON ON ON / ON ON OFF PIe Port PIE_P PIE_P PIE_P RREER mt Mini R (WLN) V POWER PU VORE +.0V_V +V_V +V_V LO WITH V ON OFF OFF OFF OFF PE 0 PE 9 POWER PROTET PE 9 PI ROM M (IO/E) PI ROM M (ME) PE PE 0 PI T H PE 0 T H PE 0 T O T PIE * PIE * PIE * T.0 iga LN M0 ard Reader RT09 mt/ PE PE 0 PE 0 PE RJ PE ocket 五五五 PE 0 PIE_P PIE_P PIE_P U P00 U P0 U P0 U P0 U P0 U P0 U P0 U P09 U P0 U P U P LN U0 PORT External M External M External WiFi amera External T PIE/mT PE 0 U P T PORT IO OR PWR OR T P0 H T P T P O T P U PORT HP_OUT POWER utton T P T P mt H U PORT9 MI IN POWER LE LI W U-R iv.-hw R ept. LOK IRM Wing_heng ustom V0_HW Monday, February 0, 0 ate: heet of 9.0

2 MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_YN FI_INT H9 J9 U00 MI_RXN_0 MI_RXN_ MI_RXN_ MI_RXN_ MI_RXP_0 MI_RXP_ MI_RXP_ MI_RXP_ MI_TXN_0 MI_TXN_ MI_TXN_ MI_TXN_ MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ FI_YN IP_INT Haswell rp E MI FI PE PE_ROMP PE_RXN_0 PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_9 PE_RXN_0 PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXN_ PE_RXP_0 PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_9 PE_RXP_0 PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_RXP_ PE_TXN_0 PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_9 PE_TXN_0 PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXN_ PE_TXP_0 PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_9 PE_TXP_0 PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ PE_TXP_ E M9 K M L0 M L M L E9 E 0 E E E L9 L L K0 L K L K F9 E F E0 F E F H H J H J J H H H0 0 9 PE_OMP R00 %.9Ohm PE_RXN PE_RXN PE_RXN PE_RXN[:0] 0 PE_RXN PE_RXN PE_RXN0 PE_RXN9 PE_RXN PE_RXN PE_RXN PE_RXN PE_RXN PE_RXN PE_RXN PE_RXN PE_RXN0 PE_RXP PE_RXP[:0] 0 PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP0 PE_RXP9 PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP PE_RXP0 PE_TXN0_ PE_TXN_ PE_TXN_ X00 X00 X00 0.UF/0V 0.UF/0V 0.UF/0V PE_TXN_ PE_TXN_ X00 X00 0.UF/0V 0.UF/0V PE_TXN_ PE_TXN_ X00 X00 0.UF/0V 0.UF/0V PE_TXN_ X00 0.UF/0V PE_TXN_ X009 0.UF/0V PE_TXN9_ X00 0.UF/0V PE_TXN0_ X0 0.UF/0V PE_TXN_ X0 PE_TXN_ X0 0.UF/0V 0.UF/0V PE_TXN_ X0 0.UF/0V PE_TXN_ X0 0.UF/0V PE_TXN_ X0 0.UF/0V PE_TXP0_ PE_TXP_ X0 X0 0.UF/0V 0.UF/0V PE_TXP_ X09 0.UF/0V PE_TXP_ PE_TXP_ PE_TXP_ X00 X0 X0 0.UF/0V 0.UF/0V 0.UF/0V PE_TXP_ X0 0.UF/0V PE_TXP_ X0 0.UF/0V PE_TXP_ X0 0.UF/0V PE_TXP9_ X0 0.UF/0V PE_TXP0_ X0 0.UF/0V PE_TXP_ X0 0.UF/0V PE_TXP_ X09 0.UF/0V PE_TXP_ X00 PE_TXP_ X0 0.UF/0V 0.UF/0V PE_TXP_ X0 0.UF/0V +VIO_OUT +VIO_OUT PE ompensation Enable PIE Lane Reversal Need to P F[] R. 0//9 X00~X00, X0~X0 options are changed to PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN0 0 PE_TXN9 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN 0 PE_TXN0 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP0 0 PE_TXP9 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP 0 PE_TXP0 0 +VIO_OUT, OKET_9P V0M00 If upport PIE en, change ap to 0.uF PETRON OMPUTER IN PU()_MI,PE,FI,LK,MI Wing_heng V0_HW ate: Friday, January, 0 heet of 9.0

3 +VIO_OUT +VIO_OUT +VIO_OUT,,, R. 0// reserved for 0 processor H_PEI LK_P_N LK_P_P 00 0.UF/0V +.0V P00 P00 +VIO_OUT tuff R00 +VIO_OUT Intel MOW WW: stuff H_PUPWR P 0Kohm KOhm R00 R00 KOhm R. 0//0 cost dwon 0ohm R0 R0 R00 00KOhm R. H_PEI Ohm, LK_P_N_R LK_P_P_R H_PROHOT# H_THRMTRIP# H_PM_YN H_PUPWR PM_RM_PWR PH_PLTRT_PU# R00 LK_P N LK_P P LK_EXP_N LK_EXP_P T09 T00 0KOhm TP_KTO#_R R. 0//0 cost dwon 0ohm P00 R00LK_P N_R P0 R00LK_P P_R P00 R00 LK_EXP_N_R P00 R00 LK_EXP_P_R P TP_TERR#_R N R R00 K R00 Ohm H_PROHOT#_ M0 H_THRMTRIP#_R M R00 P00 H_PM_YN_R R00 P00 R00 T R00 P00 H_PUPWR_R L P00 R00 VPWROO_R 0 P009 R00 T H F E E U00 KTO# TERR# PEI F PROHOT# THERMTRIP# PM_YN PWROO M_RMPWROK PLTRTIN# MI PLL_REF_LKN PLL_REF_LKP _PLL_REF_LKN _PLL_REF_LKP LKN LKP OKET_9P Haswell rp E THERML PWR LOK R JT M_ROMP_0 M_ROMP_ M_ROMP_ M_RMRT# PRY# PREQ# TK TM TRT# TI TO R# PM_N_0 PM_N_ PM_N_ PM_N_ PM_N_ PM_N_ PM_N_ PM_N_ P M_ROMP_0 R M_ROMP_ P M_ROMP_ N R9 T9 M N M M XP_TI_R L XP_TO_R P H_R#_R R0 N N9 P P0 N P9 P R0 % 0 R0 % Ohm R0 % 0 XP_PRY# XP_PREQ# XP_TK XP_TM XP_TRT# XP_PM0 XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM XP_PM PURMRT# T00 T00 T00 T00 T00 T00 T009 T00 T0 T0 T0 T0 T0 T0 T0 T0 +.V_VQ +VU +V +.0V +VIO_OUT +.V_VQ +VU,,,,0,,,,,9 +V,,,,9 +.0V,,,,,0, +VIO_OUT, +VIO_OUT V0M00 LK_P P_R R09 0KOhm LOK TERMINTION tuff R0 & R0 only when clock not used LK_P N_R R00 0KOhm U00H Haswell rp E R.0 PU/P for JT signals VT XP_TM R00 Ohm XP_TI_R R00 Ohm XP_PREQ# R00 Ohm XP_TK R00 Ohm XP_TRT# R00 Ohm +.0V HMI_TXN_PH HMI_TXP_PH HMI_TXN_PH HMI_TXP_PH HMI_TXN0_PH HMI_TXP0_PH HMI_LKN_PH HMI_LKP_PH T U T0 U0 U9 V9 U V T U U V U T U V P9 R9 N P P R N0 P0 I_TXN_0 I_TXP_0 I_TXN_ I_TXP_ I_TXN_ I_TXP_ I_TXN_ I_TXP_ I_TXN_0 I_TXP_0 I_TXN_ I I_TXP_ I_TXN_ I_TXP_ I_TXN_ I_TXP_ I_TXN_0 I_TXP_0 I_TXN_ I_TXP_ I_TXN_ I_TXP_ I_TXN_ I_TXP_ ep EP_UXN EP_UXP EP_HP EP_ROMP EP_IP_UTIL EP_TXN_0 EP_TXP_0 EP_TXN_ EP_TXP_ FI_TXN_0 FI_TXP_0 FI_TXN_ FI_TXP_ M N P E R P R N P P R N P P_OMP R00 EP_UXN EP_UXP EP_HP# EP_IP_UTIL EP_TXN0 EP_TXP0 EP_TXN EP_TXP +VIO_OUT R. 0/0/9 option changed from /non_fi R. 0//0 remove R0~R09 for R R0 R0 R0 R0 %.9Ohm FI_TXN0 FI_TXP0 FI_TXN FI_TXP I Port : N/ I Port : HMI I Port : P to V I signals Mapping, check 90 OKET_9P V0M00 R. 0/0/9 option changed from /FI +.V_VQ R. 0// design gude and check list use % Intel R % R0.KOhm % +VU U00 V +VU R0 0KOhm 0 VR_HOT# R0 PM_RM_PWR Intel MOW WW: change R09, R00 value R. R0 0. Volt R0 R0.KOHM % 9.09KOHM 00 0.UF/0V Y Vcc=.~. E Q00 PM UF/0V +.V_VQ R0.KOhm R0 KOhm % Intel omments H_PROHOT# 00 PF/0V Q00 N00 THRO_PU THRO_PU 0 Power good for +.V_VQ (delay > ns) Processor may be damaged if VIH exceeds the maximum voltage for extended periods. M_RMPWROK VIH MX =.0V ; VIH MIN=0.*VQ PETRON OMPUTER IN PU()_MI,PE,FI,LK,MI Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9.0

4 +.V +.V,,,, R00,R0 must be grounded. R 0. IMM_VREF_ RMRT_NTRL_PH, IMM0_VREF_Q R. 0// cost dwon 0ohm Q00 RMRT_NTRL_PH M Q[:0] R. 0//0 cost dwon 0ohm N00 Q00 UMKNTN P00 R00 P00 R00 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q R VREF R_WR_VREF0 R_WR_VREF0 R0 R009 R00 R T M N T R N M M9 N9 M N R9 T9 R T J9 K9 J K J0 K0 J K F F F F J J J H H H J H F F F E E E E M F F Haswell rp E _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q_ M_VREF _IMM_VREFQ _IMM_VREFQ U00 RV K_N_0 _K_P_0 _KE_0 _K_N K_P KE K_N K_P KE K_N K_P KE N_0 N N N OT_0 _OT OT OT 0 V _R# _WE# _# _M_0 _M M M M M M M M M_9 _M_0 _M M M M M Q_N_0 _Q_N Q_N Q_N Q_N Q_N Q_N Q_N Q_P_0 _Q_P Q_P Q_P Q_P Q_P Q_P Q_P_ OKET_9P V0M00 U V 9 U V 9 U V U V M L9 M9 M0 M L L L0 V U V0 U U U V V9 U9 V V P P J F J E P P9 K H E M 0 M M M M M M M M M 9 M 0 M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M Q[:0] M IM0_LK_R#0 M IM0_LK_R0 M IM0_KE0 M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_#0 M IM0_# M IM0_# M IM0_# M IM0_OT0 M IM0_OT M IM0_OT M IM0_OT M 0 M M M R# M WE# M # M [:0] M Q#[:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q R T M M R T N N T R N M T R M N R R M M T T N N J K J J M N K K L M L M L M L M J 9 J J9 0 J0 9 9 E 9 E9 E E _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q Q Q Q Q Q Q_9 _Q_0 _Q Q Q_ Haswell rp E U00 RV _KN0 _K0 _KE_0 _KN _K _KE KN _K _KE KN _K _KE N_0 N N N OT_0 _OT OT OT 0 V _R# _WE# _# _M_0 _M M M M M M M M M_9 _M_0 _M M M M M Q_N_0 _Q_N Q_N Q_N Q_N Q_N Q_N Q_N Q_P_0 _Q_P Q_P Q_P Q_P Q_P Q_P Q_P_ OKET_9P V0M00 Y F0 Y 0 Y 9 Y F9 P R P P R R R P R P 9 R0 R P P R Y Y0 Y Y Y 0 R9 Y9 F P9 P P P J L H9 P P P K M H 9 M 0 M M M M M M M M M 9 M 0 M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M IM0_LK_R#0 M IM0_LK_R0 M IM0_KE0 M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_LK_R# M IM0_LK_R M IM0_KE M IM0_#0 M IM0_# M IM0_# M IM0_# M IM0_OT0 M IM0_OT M IM0_OT M IM0_OT M 0 M M M R# M WE# M # M [:0] M Q#[:0] M Q[:0], RMRT_NTRL_PH IMM_VREF_Q UMKNTN Q00 P00 R00 PU driven VREF path is stuffed by default R 0. % KOhm % KOhm % KOhm R. 0// cost dwon 0ohm R.0 circuit:- RM_RT# to memory should be high during R hange R00 to K ohm R00 close to IMM +.V R00 KOhm 0-change Q00 from UMKN to N00 R00 KOhm PURMRT#_R, R_RMRT# PURMRT# R00 Q00 N00 % R00.99KOhm RMRT_NTRL_PH UF/V Reserve power reduction schematic If don't support power reduction. Unmount R00, R0, U00, R0, Q00, 00, R0, R0, 00. hange R09 to 00ohm from kohm, change R009 to 0ohm from 0ohm - esign uide.0 page 0. Unmount Q00, 00, R00, R00, R00. Mount R00, change r00 to 0ohm from kohm Unmount Q00, R00, R00, Q00. Mount R00 and short JP00. Unmount R, R, Q0 PU()_R PETRON OMPUTER IN Wing_heng V0_HW Friday, January, 0 ate: heet of 9.0

5 +.V_VQ +.V_VQ +.V +.V,,,, ecoupling guide from Intel (PE) VQ uf * pcs (stuff) 0uF * 0 pcs (stuff) 0uF * pcs (stuff) ecoupling guide from Intel (EE) VQ uf * pcs (stuff) 0uF * pcs (stuff) 0uF * pcs (stuff) +VORE +VIO_OUT +VIOPH +VIO_OUT +VORE 9,,0 +VIO_OUT,,, +VIOPH +VIO_OUT, ecoupling guide from Intel ( PE) +VORE 0uF * pcs (stuff) uf * 9pcs (stuff) 0uF * pcs (stuff) ecoupling guide from Intel ( EE) +VORE 0uF * pcs (stuff) uf * 9 pcs (stuff) 0uF * pcs (stuff) U00E Haswell rp E +VORE +VORE 0 UF/.V P_NTRL_.V +.V efault: no support power reduction 00 UF/.V 0 VR_VI_T. P_NTRL_.V_R Placement note:. R00 close to PU. R00 close to PU. R00 close to VR. R00 close to PU. R00 close to VR. R0 close to PU +VIO_OUT R00 % R. 0//0 cost dwon 0ohm 09 UF/.V +VIO_OUT 0 R00 VR_VI_LK vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small 00 UF/.V 0 UF/.V 0 UF/.V 09 UF/.V JP00 MM_OPEN_MM vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small 0 UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 0 UF/.V 0 UF/.V R00 0PF/0V 0 0 UF/.V 0 UF/.V 0 UF/.V IRP-T-E 0 UF/.V 09 UF/.V 0 UF/.V vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small Q00 JP00 MM_OPEN_MIL 0 UF/.V 0 UF/.V 0 UF/.V 00 UF/.V 009 UF/.V P E00 E UF/.V 0UF/.VUF/.V 0 UF/.V 0 UF/.V 00 UF/.V vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small 0 UF/.V 00 UF/.V Unstuff R0 0 0UF/0V vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small vx_c00_h_small R009 % 00 0UF/0V 0 UF/.V Power team suggestion 0 UF/.V 00 UF/.V 0 0UF/0V 00 UF/.V +VIO_OUT(---.0V) output from PU +VIO_OUT +VORE +VIOPH 0 UF/.V 00 UF/.V 00 0UF/0V +VORE Intel MOW WW09: renamed VIOPH to RV R. +VIO_OUT R00 0 R. 0// R. 0//0 % follow Intel R cost dwon 0ohm Place as close to PU as possible P00 V_ENE_R R00 0 VENE R. 0// follow design guide R00 +VIO_OUT_R +VIO_OUT +VIO_OUT R00 +VIOPH_R R00 +VIO_OUT_R 0 0.UF/.V R0 R0 UF/.V 0 0 T00.9Ohm Ohm 0.0UF/0V 0.0UF/0V % R. 0//0 % cost dwon 0ohm 0 VR_VI_LERT# R0 Ohm H_PU_VILRT# P00 R00 H_PU_VILK H_PU_VIT 0 0UF/0V 0 UF/.V 0 UF/.V 0 0UF/0V 0 0UF/0V 0 UF/.V 0 0UF/0V 09 UF/.V 00 0UF/0V 0 0UF/0V T00 PWR_EU T00 T00 T00 T00 If XP not implemented, then Route Processor PWR_EU as a test point. This Test point must be clearly labeled(shark bay schematic check list 90) +.V_VQ 0 UF/.V +VORE K L T V E E E E H K N N T T T T W W W W N K L K L E N F W L J L M M9 L P H P T R R L T L T M M M M0 M L9 M T Y Y Y Y Y9 Y0 Y Y Y Y Y RV RV RV RV0 VQ VQ VQ VQ0 VQ9 VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ9 VQ VQ0 RV9 V0 RV RV V_ENE RV VIO_OUT RV VOMP_OUT RV0 RV9 RV RV VILERT# VILK VIOUT V PWR_EU V RV_TP RV_TP RV_TP RV_TP V V V V V9 V0 V V V V V V V0 V9 V V V V V V V V V00 V99 V9 V9 V9 V9 V9 V9 V9 V9 V90 V9 V V V V V V V V V0 V9 V V V V V V V V V0 V9 V V V V V V V V V0 V9 V V V V V V V V V0 V9 V V0 V0 V V V V V V V V0 V9 V V V V V V V V V0 V9 V V V V V V V V V0 V9 V V V V V V V E E E E0 E F F F F F9 F0 F F F F F H H9 0 H H H H H H0 H H H J J J J J9 J0 J J J J J H J K L M N P R T U U V V W W OKET_9P V0M00 ap of 0UF or more place at power schematic PETRON OMPUTER IN PU()_PWR Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9.0

6 PETRON OMPUTER IN PU()_PWR Wing_heng V0_HW Friday, January, 0 ate: heet of 9.0

7 Placement note:. P00 close to PU R. 0//0 cost dwon 0ohm V_ENE_R VENE 0 ate: heet of 9 Friday, January, 0 PETRON OMPUTER IN PU()_F,RV,.0 V0_HW Wing_heng ate: heet of 9 Friday, January, 0 PETRON OMPUTER IN PU()_F,RV,.0 V0_HW Wing_heng ate: heet of 9 Friday, January, 0 PETRON OMPUTER IN PU()_F,RV,.0 V0_HW Wing_heng P00 R00 R00 0 % Haswell rp E U00 OKET_9P V0M00 RV K V_ENE K V W9 V W V W V W V W0 V W V V V V V V0 V0 V V V V U V U V T9 V T V T V T V0 T V9 T V T V T V T9 V T0 V T V R V R V0 R V9 R0 V R V R V R V P V P V N9 V09 N V0 N V0 N V0 N V0 N V0 N V0 N9 V00 N V99 N0 V9 N V9 M V9 M V9 M V9 M0 V9 M V9 M V90 M V9 L V L V L V K9 V K V K V K V K V0 K V9 K V K V K V K9 V K V K0 V K V J V0 J V9 J V J0 V H V H V0 H0 V9 V V 9 V V V9 V V F9 V F V F V F V F V F V F V0 F0 V F V F V F V F V F V F0 V F V F V0 F V9 F V F V F V F0 V E V E V E V0 E V9 E0 V E V V V V V V 9 V0 V09 V0 V0 9 V0 V0 V0 0 V0 V0 V00 V99 V9 0 V9 V9 V9 V9 V9 V9 9 V90 V9 V 0 V V V Y V V V V V0 N V0 N V P V9 W V W V V V J V J V H V J V H V L V F9 V T T00 Haswell rp E U00F OKET_9P V0M00 V V V0 9 V9 V V 0 V T V T V T0 V T V T V0 T V9 T V T9 V T V T V T0 V R V R V R V0 R V9 R V R V R V R V R9 V R V R V P V P9 V P V P0 V P V N V N V0 N V N0 V N V N V N V N V N9 V N V N V0 N0 V9 M V M V M V E V M9 V M V M V M0 V0 L9 V9 L V L V L V L V L V0 L V9 E V L V L V L0 V L V L V L V L V0 L V9 L V L V L0 V L V K V K V E9 V K V0 K0 V09 K9 V0 K V0 K V0 K V0 K V0 J V0 J V0 H9 V00 H V99 H V9 H V9 H V9 H V9 V9 V9 H V9 9 V9 V9 H V H0 V H V V E V V E V V V0 F V F V F V E9 V E V E V E V E V E V E0 V E V V V V0 9 V0 V9 V V0 V9 V V V V0 V9 V 0 V V0 9 V9 V V V V0 V9 V V V V 9 V0 V90 V9 V 9 V V V 0 V P V V 9 V W V9 P V0 E V9 E9 V E V R0

8 F strapping information: The F signals have a default value of '' +VORE +VORE,,0 F[:0]: Reserved configuration lane. U00I Haswell rp E F[]: PIE tatic Numbering Lane Reversal- F[] is for the x - : (efault) Normal Operation, Lane # definition matches sockect pin map definition - 0: Lane Numbers Reversed -> 0, ->,... F[]: ep enable - = isabled -0 = Enabled F[:]: PI Express Port ifurcation traps -00 = x, x PI Express* -0 = reserved -0 = x PI Express* - = x PI Express* F[9:]: Reserved configuration lane. R090 R090 W9 W RV_TP F_ROMP 9.9Ohm % H_PU_RV F_ROMP T % 9.9Ohm RV_TP9 R F T09 W TETLO F_ R F T09 L0 RV F_ P F T09 L9 RV F_ P F9 T09 F_9 +VORE F RV V0 % 9.9Ohm H_PU_RVW T090 T090 T090 T090 T090 T09 T09 T09 T09 T09 T09 T09 T09 T099 T090 T09 F0 F F F F F F F F F9 F0 F F F F F T T 0 L W0 W W T0 R0 P0 P T N T N R T N0 P P N N P RV_TP RV_TP RV RV_TP RV_TP RV_TP RV_TP RV_TP0 RV_TP RV_TP TETLO F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_9 F_0 F_ F_ F_ F_ F_ RV_TP RV_TP0 RV_TP9 RV_TP RV F RV RV RV9 RV0 RV RV RV RV N RV RV_TP RV_TP RV_TP RV RV V V9 R M M F M K E U0 P0 R E E0 P R L L F_ R090 R. 0// reserved for 0 processor R090.KOhm % PM_PWROK,0,9 R. 0// channged from.k/% R09.KOhm % F signals are signals that are available for compatibility with other processors. test point may be placed on the board for these lands. Refer to the appropriate platform design guide for implementation details.(haswell E ) OKET_9P V0M00 F R090 % KOhm F R090 % KOhm F R090 % KOhm F R090 % KOhm F R090 % KOhm F9 R0909 % KOhm PETRON OMPUTER IN PU()_F,RV, Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9 9.0

9 PETRON OMPUTER IN N()_**** Wing_heng V0_HW Friday, January, 0 ate: heet of 0 9.0

10 +.V +.V,,,, R0 R0 M Q[:0] M Q#[:0] 0PF/0V M IM0_LK_R0 M IM0_LK_R#0 0PF/0V M IM0_LK_R M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_LK_R0 M IM0_LK_R#0 M IM0_# M IM0_#0 M IM0_OT M IM0_OT0 M WE# M R# M # M M M 0 M IM0_KE M IM0_KE0 Mus lave ddress: 0H M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M [:0] M should connect to directly esign uide 0.9 p () 0KOhm 0KOhm R. 0//0 Part ref. changed H:mm M 0 M M M M M M M M M 9 M 0 M M M M M RN0 RN0 M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q0 M Q# ON /P /# K K# K0 K0# WE# R# # KE KE # 0# OT OT0 0 Q Q# Q Q# Q Q# Q Q# Q Q# Q Q# Q Q# Q0 Q#0 0 M M M M M M M M0 0 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q Q Q Q Q Q Q9 Q0 Q Q Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q9 ok ok ok ok ok ok ok ok M Q[:0] +.V Layout Note: Place these caps near O IMM 0 Reserve +.V_R T0 JP0 JP0 MM_OPEN_MIL 0 0.UF/0V +V_VREF IMM0 +V_VREF_Q_IMM0 PM_EXTT#0_IM_ 09.UF/.V MM_OPEN_MIL 0 +.V_R 0.UF/0V 0 0.UF/0V +0.V +V +.V_R R. 0//0 Part ref. changed ON0 V V V V V9 V V V V EVENT# TET N N VREF VREFQ V V V V V0 V V V V V V V V 9 V V V V V9 V0 V V V V V V V V 0 V9 V0 V V V V V V V V V9 V0 V V 0 V V V V V V V9 V0 V V V V V V 9 V V 9 V9 V0 V V NP_N NP_N VTT VTT +0.V,, +V,0,,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +.V_R VP V 0.UF/0V 0 0.UF/0V +V +.V_R 0 0.UF/0V 0.UF/.V Reference schematic have. uf cap. +.V_R + E0 0UF/.V V V_R Layout Note: Place these caps near O IMM 0 0UF/0V 0UF/0V 0UF/0V 0UF/0V 0UF/0V 0UF/0V +0.V UF/.V 9 0 UF/.V UF/.V UF/.V,,,,,,,, M_LK_ M_T_ 0 00 L R_IMM_0P REET# 0 R_RMRT#, 0.UF/.V 0 0.UF/0V V0IRM00 R0 R0 0PF/0V M IM0_LK_R M IM0_LK_R# 0PF/0V M IM0_LK_R M IM0_LK_R# Mus lave ddress: H M IM0_LK_R M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_# M IM0_# M IM0_OT M IM0_OT M IM0_KE M IM0_KE +V M should connect to directly esign uide 0.9 p () M WE# M R# M # M M M 0 M 0 M M M M M M M M M 9 M 0 M M M M M RN0 0KOhm RN0 0KOhm M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q M Q# M Q0 M Q#0 R. 0//0 Part ref. changed H:mm ON Q0 9 Q 9 Q 9 Q 9 Q 90 Q Q 0 9 Q Q 0 9 Q9 0/P Q0 Q 9 /# Q 0 Q Q Q Q 0 Q 0 K Q 0 K# Q9 0 K0 Q0 K0# Q Q # Q 0# Q 0 Q OT Q OT0 Q Q 0 WE# Q9 R# Q0 # Q 9 Q 0 Q 09 Q 0 Q Q KE Q KE0 Q 0 Q9 9 Q0 0 Q Q Q Q Q Q# Q 9 Q Q Q# Q Q Q R_IMM_0P Q# Q9 Q Q0 V0RM00 Q# Q Q Q Q# Q Q Q Q# 9 Q Q Q Q# Q 0 Q0 Q Q#0 Q9 Q0 0 M Q M Q M Q M M M M M M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q0 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q9 Layout Note: Place these caps near O IMM 0 Reserve +.V_R T0 0.UF/0V +V_VREF IMM0 +V_VREF_Q_IMM0 PM_EXTT#0_IM_ 9.UF/.V.UF/.V 0.UF/0V 0.UF/0V 0.UF/0V R. 0//0 Part ref. changed ON0 R_IMM_0P VV0IRM00 V V V V V 9 V V 00 V9 V0 0 V V V V V V V V V V V V 9 V V V V V9 V0 V V V V V V V V 0 V9 V0 V V V V V V V V V9 V0 V V 0 V V V V V V V9 V0 V V V V V V 9 V V 9 V9 V0 V V 9 EVENT# TET NP_N N NP_N N VTT VTT VREF VREFQ R_IMM_0P V0RM VP 99 0.UF/0V +0.V +V 0 0.UF/0V.UF/.V +.V_R 0.UF/0V +.V_R Layout Note: Place these caps near O IMM 0 0UF/0V 0UF/0V 0UF/0V 0UF/0V 0UF/0V 0UF/0V +0.V UF/.V 9 0 UF/.V UF/.V UF/.V M_LK_ M_T_ 0 00 L REET# 0 R_RMRT# --HW R& ept. R()_O-IMM0 Wing_heng ize Project Name V0_HW Rev.0 ate: Friday, January, 0 heet of 9

11 M should connect to directly esign uide 0.9 p () M should connect to directly esign uide 0.9 p () Reserve Reserve 0 Layout Note: Place these caps near O IMM 0-000R000 (V0IRM00) Mus lave ddress: H H:MM 0 Layout Note: Place these caps near O IMM Mus lave ddress: H H:MM ok ok ok ok ok ok ok ok Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM PM_EXTT#0_IM_ M Q# M Q# M Q# M Q# M Q# M Q#0 M Q# M Q# PM_EXTT#0_IM_ M Q# M Q# M Q# M Q# M Q# M Q#0 M Q# M Q# M_LK_ M Q M Q M Q M Q M Q M Q M Q M Q0 R_RMRT# M M M M M M 9 M M 0 M M M M M 0 M M M M WE# M # M_T_ M M 0 M M R# M Q M Q M Q M Q M Q M Q M Q M Q0 M M M M M M 9 M M 0 M M M M M 0 M M M M Q#0 M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q M Q0 M Q M Q# M Q# M Q# M Q M IM0_LK_R# M IM0_LK_R M IM0_LK_R#0 M IM0_LK_R0 M IM0_LK_R# M IM0_LK_R M IM0_LK_R# M IM0_LK_R M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q9 M Q9 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q9 M Q M Q0 M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q9 M Q M Q9 M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q9 M Q0 M Q M Q M Q M Q9 M Q9 M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q M Q M Q9 M Q M Q M Q M Q M Q M Q M Q9 M Q0 M Q M Q M Q0 M Q M Q M Q0 M Q +V,0,,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +0.V,, +.V,,,,, +.V_R M Q#[:0] M Q[:0] M Q[:0] M [:0] M_T_,,,, M_LK_,,,, M M 0 M M # M R# R_RMRT#, M IM0_OT0 M IM0_OT M WE# M IM0_LK_R M IM0_LK_R# M IM0_LK_R0 M IM0_LK_R#0 M IM0_KE0 M IM0_KE M IM0_# M IM0_#0 M IM0_LK_R# M IM0_KE M IM0_KE M IM0_LK_R M IM0_OT M IM0_OT M IM0_LK_R# M IM0_LK_R M IM0_# M IM0_# +V +0.V +.V +.V_R +0.V +.V_R +V +.V_R +V +V_VREF IMM +V_VREF_Q_IMM +0.V +.V_R +V +.V_R +V +V_VREF IMM +V_VREF_Q_IMM +0.V +.V_R +.V_R +0.V +.V_R ate: heet of 9 Friday, January, 0 --HW R& ept. R()_O-IMM.0 V0_HW Wing_heng ate: heet of 9 Friday, January, 0 --HW R& ept. R()_O-IMM.0 V0_HW Wing_heng ate: heet of 9 Friday, January, 0 --HW R& ept. R()_O-IMM.0 V0_HW Wing_heng.UF/.V 0 0PF/0V ON0 R_IMM_0P V0IM /P 0 /# # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 Q#0 0 Q# Q# Q# Q# Q# Q# 9 Q# Q0 Q 9 Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# L 0 00 REET# 0 0.UF/0V RN0 0KOhm 0 0UF/0V UF/.V.UF/.V RN0 0KOhm.UF/.V RN0 0KOhm UF/.V UF/.V 9 0.UF/0V 0UF/0V UF/.V + E0 0UF/.V V R0.UF/.V 0.UF/0V 0.UF/0V 0UF/0V 9 0UF/0V 0PF/0V 0 0.UF/0V UF/.V 0 0UF/0V T0 R0 R0 0PF/0V 0 0.UF/0V 9 UF/.V 0 0.UF/0V UF/.V 9 0PF/0V.UF/.V 0.UF/0V 0UF/0V 0UF/0V R0 0 0.UF/0V 0.UF/0V 0UF/0V 0UF/0V ON0 R_IMM_0P V0IM00 EVENT# N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VP 99 VREF VREFQ V9 V 0 V 9 V V 9 V 9 V0 90 V V9 9 V V V 9 V V V V V V0 V 9 V9 V V V V 0 V V V 9 V V0 V V9 V V V V V V V V 0 V0 V V9 V 9 V V V V V V V V0 V VTT 0 VTT 0.UF/.V T0 RN0 0KOhm UF/.V ON0 R_IMM_0P V0IM000 EVENT# N N NP_N 0 NP_N 0 TET V V0 00 V 0 V 0 V V V V V V V V V V V V 9 V 9 V9 99 VP 99 VREF VREFQ V9 V 0 V 9 V V 9 V 9 V0 90 V V9 9 V V V 9 V V V V V V0 V 9 V9 V V V V 0 V V V 9 V V0 V V9 V V V V V V V V 0 V0 V V9 V 9 V V V V V V V V0 V VTT 0 VTT UF/0V 0.UF/0V 0 0.UF/0V 0UF/0V ON0 R_IMM_0P V0IM /P 0 /# # K0# 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q 9 Q Q Q9 Q Q0 0 Q Q 0 Q Q Q 9 Q Q 9 Q Q9 Q Q0 Q 0 Q 9 Q Q Q Q 0 Q Q 0 Q9 Q Q0 Q 9 Q Q 9 Q Q Q Q 0 Q Q9 Q Q0 Q Q Q Q Q Q Q Q 9 Q9 9 Q Q0 0 Q Q 9 Q 9 Q Q Q9 Q#0 0 Q# Q# Q# Q# Q# Q# 9 Q# Q0 Q 9 Q Q Q Q Q Q # 0# OT 0 OT0 WE# R# L 0 00 REET# 0 0UF/0V 0.UF/0V 0 0UF/0V

12 RL Vref +.V_R +V_VREF IMM0 +V_VREF_Q_IMM0 +V_VREF IMM +V_VREF_Q_IMM +.V_R, +V_VREF IMM0 +V_VREF_Q_IMM0, +V_VREF IMM +V_VREF_Q_IMM, M: PU driven VREF path is stuffed be default. M: VREF_Q driven by a Voltage ivider Network during Processor power-off M +V_VREF_Q_IMM0, IMM0_VREF_Q +V_VREF_Q_IMM R0, IMM_VREF_Q +.V +.V R. 0//0 cost dwon 0ohm R. 0//0 R0 change short pin size KOhm P0 R00 nb_r00_short_mil R. 0//0 cost dwon 0ohm R. 0//0 change short pin size P0 R00 nb_r00_short_mil 0 0.0UF/V 0 0.0UF/V R0 KOhm R KOhm HKLT, 90 R0.9Ohm % M Intel 00 M+M: efault Recommendation IMM_VREF_ M +V_VREF IMM0 +V_VREF IMM P0 R00 nb_r00_short_mil P0 R00 nb_r00_short_mil +.V R0 KOhm R. 0//0 cost dwon 0ohm R. 0//0 change short pin size 0 0.UF/V R KOhm HKLT, UF/V R KOhm 0 0.UF/V 0 0.UF/V R0.9Ohm % P0 R00 nb_r00_short_mil M R09.9Ohm % PETRON OMPUTER IN R()_/Q Voltage Wing_heng ustom V0_HW ate: Friday, January, 0 heet of 9.0

13 R.-- PETRON OMPUTER IN VI ontroller Wing_heng V0_HW Friday, January, 0 ate: heet of 9 9.0

14 RT battery +RTT R. 0//0 工工工工工工 T0 R00 J00 TT_HOLER_P V0M000 T00 +RT_T KOhm +V R.0 00 增增增增增 00 V/0. +V_RT onnector Type -00L000 T0 00 UF/.V +V_RT +V +V +VU_OR +V +.V +V_RT, +V,0,,,,,9 +V,,,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +VU_OR,,,,, +V,9,,,9 +.V,,,,,,,,, +VTT_PH_VIO +VTT_PH_VIO, +V_RT RTRT# R delay should be ms~ms R0 R0 % 0KOhm MOhm % 0KOhm R0 00 UF/.V 00 UF/.V Request by for MO clear function JRT00 L_JUMP JRT00 L_JUMP TPM ettings lear ME RT Registers Keep ME RT Registers JRT00 hunt Open (efault) T00, R. 0//0 dd R0 0 T00 T00 +V_RT Z_LK_U Z_YN_U 00 _PKR Z_RT#_U Z_IN0_U PH_FLH_ERIPTOR Z_OUT_U 00 RT_X_ PF/0V 0V PF/0V R00 R0 P00 X00 % R0 R0 R0 R00.KHZ R0 0KOhm 0KOhm R00 0MOhm Ohm Ohm Ohm Ohm RT_X RT_X RT_RT# M_INTRUER# PH_INTVRMEN RT_RT# Z_LK Z_YN Z_RT# Remove TP Z_OUT H_OK_EN# L0 L K F U00 RTX RTX RTRT# INTRUER# INTVRMEN RTRT# H_LK H_YN PKR H_RT# H_I0 H_I H_I H_I H_O OKEN#/PIO RT ZLI LPT_PH_M_E T T_RXN_0 T_RXP_0 T_TXN_0 T_TXP_0 T_RXN_ T_RXP_ T_TXN_ T_TXP_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ T_RXN/PERN T_RXP/PERP T_TXN/PETN T_TXP/PETP T_RXN/PERN T_RXP/PERP E W Y 0 E0 V0 W0 9 9 Y W E R T V W E R. 0// mt move to port T_RXN0 0 T_RXP0 0 T_TXN0 0 T_TXP0 0 T_RXN 0 T_RXP 0 T_TXN 0 T_TXP 0 T_RXN T_RXP T_TXN T_TXP T_RXN 0 T_RXP 0 H O mt H MO ettings lear MO Keep MO JRT00 hunt Open (efault) 0 EXT_I# R. R0 0KOhm +VU_OR H_OK_RT#/PIO T_TXN/PETN T_TXP/PETP T_ROMP TLE# P R Y P T_OMP R0 R0.KOhm 0KOhm +.V +V T_TXN 0 T_TXP 0 T_LE# T00 PH_JT_TK_UF T T_ET0_R_N T009 JT_TK T0P/PIO T00 PH_JT_TM JT_TM TP/PIO9 U Int. PU _IT0_R P00 R00 _IT0 INTVRMEN: Integrated U.0V VRM Enables Low: Enable External VRs High:Enable Internal VRs PH_INTVRMEN 0KOhm % R0 T00 T00 R. 0// follow Intel design guide T00 R0 PH_JT_TI PH_JT_TO PM_TET_RT_N E F JT_TI JT_TO TP TP TP0 JT T_IREF TP9 TP R0 +.V HLPM 0V H_KEN : Flash escriptor ecurity Overide H = isabled (efault) L = Enabled Note : Rising edge of PWROK H_OK_EN# JRT00 MM_OPEN_MM R00 KOhm trap information: T0P 的 pull up 電電, 參參參參 (K ohm) 和 check list(0k ohm)) 寫的寫寫?? 先先參參參參 +V H_PKR: No reboot strap Low: isable (efault) High:Enable _PKR R09 KOhm +V H_O:.Flash descriptor security: ampled Low: in effect. ampled High: override Z_OUT R0 KOhm +VU_OR T_ET0_R_N R0 0KOhm.H_O which sample high on the rising edge of PWROK Will also disable Intel ME. H_OK_EN#: Reserved [0] : Z_YN strap is no longer supported on LPT, by Intel FE tu. PETRON OMPUTER IN PH()_T,IH,RT,LP Wing_heng V0_HW Friday, January, 0 ate: heet of 0 9.0

15 +V +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +.V +.V 0,,,,,,,,, +VU_OR +VU_OR 0,,,,, U00 LPT_PH_M_E +VXK_VRM +VXK_VRM LK_UF_PYLK_N LK_UF_PYLK_P 0KOhm 0KOhm RN0 RN0 T0 T0 T0 LK_PH_R0_N LK_PH_R0_P LK_REQ0# Y Y LKOUT_PIE_N_0 LKOUT_PIE_P_0 PIELKRQ0#/PIO LKOUT_PE_ LKOUT_PE P PE_LKRQ#/PIO F LK_PIE_PE#_PH_L LK_PIE_PE_PH_L LK_REQ_PE_# P P P R00 R00 R00 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 LKREQ_PE# 0 LK_UF_EXP_N LK_UF_EXP_P LK_UF_OT9_N LK_UF_OT9_P LK_UF_K_N LK_UF_K_P 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN09 RN09 RN0 RN0 RN RN LK_PIE_mT#_PH LK_PIE_mT_PH LK_REQ_PIE_mT# LK_PIE_WLN#_PH LK_PIE_WLN_PH LK_REQ_WLN# LK_PIE_LN# LK_PIE_LN LK_REQ_LN# 0 LPLK LK_KPI_PH LK_EU LK_PIE_R#_PH LK_PIE_R_PH LK_REQ_R# P0 P0 P0 P0 P0 P09 00MHz P0 P0 P0 T T T LK_PI_F R00 R00 R00 T T T T Ohm R00 R00 R00 T T T T 0 0PF/0V R00 R00 R00 /TPM P P P9 LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# LK_PH_R_N LK_PH_R_P LK_REQ# R Ohm Ohm Ohm T0 LK_PH_R_N LK_PH_R_P LK_REQ# LK_XP_N LK_XP_P R9 R R0 LK_PH_R_N LK_PH_R_P LK_PI_F_R LK_KPI_PH_R LK_EU_R LK R LK_REQ# LKOUT_PI0_R F F T F F V E E 0 9 E J J Y H H E F 0 LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO0/MI# LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_PIE_N LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_PIE_N_ LKOUT_PIE_P_ PIELKRQ#/PIO LKOUT_ITPXP LKOUT_ITPXP_P LKOUT_MHZ0 LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LKOUT_MHZ LOK INL HLPM 0V LKOUT_PE_ LKOUT_PE P PE_LKRQ#/PIO LKOUT_MI LKOUT_MI_P LKOUT_P LKOUT_P_P LKOUT_PN LKOUT_PN_P LKIN_MI LKIN_MI_P LKIN_ LKIN P LKIN_OT9N LKIN_OT9P LKIN_T LKIN_T_P REFLKIN LKIN_MHZLOOPK XTL_OUT XTL_IN LKOUTFLEX0/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO ILK_IREF TP9 TP IFFLK_IREF Y9 Y U F9 F0 J0 J9 F F Y W R T H E F L M 0 F F F9 M 9 N LK_P_N LK_P_P ILK_IREF LK_PH_PE N LK_PH_PE P LK_REQ_PE_# LK_UF_EXP_N LK_UF_EXP_P LK_UF_PYLK_N LK_UF_PYLK_P LK_UF_OT9_N LK_UF_OT9_P LK_UF_K_N LK_UF_K_P LK_UF_REF LK_PI_F LK_OUT XTL_OUT XTL_IN PU_EI_ELET# LK_OUT PU_PRNT# P0 IFFLK_IREF R N_R00_0MIL_MLL +.V R. 0// cost dwon 0ohm % T T T T.KOhm T09 T0 T0 LK_EXP_N LK_EXP_P LK_P N LK_P P LK_P_N LK_P_P R. 0//0 change short pin size +VXK_VRM 00MHz MHz MHz R MOhm P R00 0 PF/0V XTL_OUT_ X0 MHZ 0 PF/0V 0V LK_UF_REF INT_ERIRQ PU_EI_ELET# PU_PRNT# PU_PRNT# PH LKREQ etting: Not connected to device. LK_REQ_LN# LK_REQ0# LK_REQ_WLN# LK_REQ# LK_REQ# LK_REQ# LK_REQ_PE_# LK_REQ_PE_# R0 LOK TERMINTION for FIM efault power-on mode is I. R R0 R R0 R09 R R R R R R R /UM 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm +V +VU_OR R. 0// dd R PU_PWR_EN is active high U00 LPT_PH_M_E ebug L_ T onnected to device. R. 0// WLN clk pull-high 換換 +V LK_REQ_WLN# R0 0KOhm +V R. _ T LK_REQ# R9 0KOhm 0,, LP_0 0,, LP_ 0,, LP_ 0,, LP_ 0,, LP_FRME# 0,, INT_ERIRQ T NN_LP_RQ# erial Interrupt Request L L_0 L_ L_ L_ LFRME# LRQ0# LRQ#/PIO ERIRQ LP Mus MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PHHOT#/PIO MLLK/PIO MLT/PIO N R0 U N U R H K N L RMRT_NTRL_PH ML0_LK ML0_T MLLERT# ML_LK ML_T T ELN_LERT# L RMRT_NTRL_PH T0 T ML_LK ML_T L RMRT_NTRL_PH ML0_LK ML0_T RN0 RN0 R0.KOhm.KOhm.KOhm.KOhm KOhm RN0 RN0 +VU_OR LK_REQ# LK_REQ# LK_REQ_LN# LK_REQ_WLN# LK_REQ# LK_REQ# R0 R R R0 R R 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm,0 PH_PILK PH_PI0#,0 PH_PI#,0 PH_PII,0 PH_PIO,0 PI_WP_IO,0 PI_HOL#_IO PH_PI# J J L J0 H H J J PI_LK PI_0# PI_# PI_# PI_MOI PI_MIO PI_IO PI_IO PI -Link Thermal L_LK L_T L_RT# TP TP TP TP T_IREF F F0 F E E Y T T T ML_LK ML_T MLLERT# ELN_LERT# R0 R.KOhm.KOhm RN0 RN0 0KOhm 0KOhm R0.0KOhm It must be.k ohm %??? HLPM 0V PH()_PIE,LK,M,PE Wing_heng \ORE ustom V0_HW. Friday, January, 0 ate: heet of 9

16 +VU_OR +V +.V +V_RT +VU +VU +VU_OR 0,,,,, +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +.V 0,,,,,,,,, +V_RT 0, +VU,,,,0,,,,,9 +VU 0,0,,,,,,9 +VU +VU,,,0,,9 U00 LPT_PH_M_E +VW +VW MI_RXN0 MI_RXN MI_RXN MI_RXN W R0 MI_RXN_0 MI_RXN_ P V0 MI_RXN_ MI_RXN_ FI_RXN_0 FI_RXN_ J L FI_TXN0 FI_TXN +V +V 0,,0,,,,,9 MI_RXP0 MI_RXP MI_RXP MI_RXP Y P0 MI_RXP_0 MI_RXP_ R W0 MI_RXP_ MI_RXP_ MI FI FI_RXP_0 FI_RXP_ TP J L V FI_TXP0 FI_TXP MI_TXN0 MI_TXN MI_TXN MI_TXN E0 MI_TXN_0 MI_TXN_ E MI_TXN_ MI_TXN_ TP TP TP0 Y V W If UWRN #/U_K # handshake is not used, these signals are tied on the board MI_TXP0 MI_TXP MI_TXP MI_TXP +.V +.V R R.KOhm MI_IREF MI_ROMP 0 MI_TXP_0 MI_TXP_ MI_TXP_ MI_TXP_ E MI_IREF W TP V TP Y MI_ROMP FI_YN FI_INT FI_IREF TP TP FI_ROMP L9 L0 T U U R FI_YN_R FI_INT_R FI_IREF P P0 FI_ROMP R00 R0 R00 R.KOhm FI_YN FI_INT +.V +.V R. 0/0/9 option changed from /FI R. 0//9 option changed from /non_retin R. 0//0 工工工工工工 T T U_PWR_K_R UK#_PH +V Y_PWROK P0 R00 R0 0KOhm WOVREN - On ie W VR Enable R0 UK#_R R WOVREN +V_RT HIH - Enabled(EFULT) ; LOW-isabled UK# WVRMEN R0 0KOhm R0 0KOhm ystem Power PM_YRT#_R M PH_PROK PM_RMRT_R Y_REET# Management PWROK L P R00 P09 R00 Y_PWROK_R K Y_PWROK WKE# PIE_WKE#, 9,0,9 PM_PWROK PM_RMRT# has pull down 0k ohm in E PM_RM_PWR 0 PM_RMRT# P0 R00 P R00 P0 R00 PM_PH_PWROK_R PM_PWROK_R PM_RMRT_R F0 PWROK PWROK H RMPWROK J RMRT# N LKRUN# U U_TT#/PIO Y ULK/PIO Y LP_#/PIO PM_LKRUN# U_TT ULK_ LP_# T0 T0 T0 PM_LKRUN# 0 ME_UPWRNK P0 R00 U_PWR_K_R J UWRN#/UPWRNK/PIO0 LP_# LP_#_R P0 R00 PM_U# 0 0 PM_PWRTN# 0 ME PREENT T0 T0 T0 P0 R00 P R00 _PREENT_R TLOW# RI# LP_WLN# K PWRTN# E PREENT/PIO K TLOW#/PIO N RI# 0 HLPM TP LP_WLN#/PIO9 H LP_# F LP_# F LP_U# PMYNH Y LP_LN# LP_#_R P0 R00 T09 ME_PM_LP_#_R LP_W#_R R0 ME_PM_LP_LN#_R PM_U# 0 LP_U# 0 H_PM_YN T0 i-mt i-mt 0V R. 0// U0 R0 mount Y_PWROK for PH R0 +VU PM_PWROK U0 V +VU_OR 9 ELY_VR_N_LL_Y Y Vcc=~. R0 Y_PWROK PIE_WKE# ME PREENT TLOW# R 0KOhm R 0KOhm R 0KOhm +V PM_LKRUN# R /TPM.KOhm +VU +VU +VU ME_PM_LP_#_R R 0KOhm PM_PWROK R 0KOhm R 0KOhm R 0KOhm % R 00KOhm P_NTRL_.V PH_PROK ULK_ R R9 00KOhm KOhm PLL ON IE VR ENLE HIH - ENLE LOW - ILE (EFULT ME_UPWRNK RI# ME_PM_LP_LN#_R R R R0 0KOhm 0KOhm 0KOhm Q0 UMKN Q0 UMKN,0,,9,9 U_E# P0 R00 PM_U# R PETRON OMPUTER IN PH()_FI,MI,Y PWR Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9.0

17 R. 0/0/9 option changed from /non_fi_ R. 0//0 remove R~R, R9~R, JP0~JP0 for R U00E LPT_PH_M_EV +V +V +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +V,,,,9 PH PH _R_PH +V R09 R0 R0 R R RT isable: (For discrete graphic). N: RT PH RT PH RT_R_PH RT_R,RT_,RT_ 0 ohm 0 ohm 0 ohm R. 0/0/9 option changed from /FI R. 0//9 option changed from /non_retin R. 0// R~R are removed RT_HYN,RT_VYN. KΩ+-% pull-down to : lose to PU L_L_PWM_PH L_KEN_PH PU_PWM_ELET# PU_HOL_RT#_R PU_PWR_EN. onnected to : RT_ITRN _IREF. onnect to +V.: V. ohm. ohm. ohm _VYN_PH V_VYN R. 0/0/9 option changed from /FI R % 9OHM U0 _IREF R. 0//9 R. 0// R. 0//0 U9 V_IRTN follow intel design guide remove R for R option changed from /non_retin co-lay with R R. 0//9 P0 R00 option changed N from /non_retin KOhm L_V_EN_PH P0 R00 K P_UXP L_KEN_PH EP_KLTEN P_UXP K T0 KOhm KOhm 0KOhm R 0KOhm 0KOhm R9 0KOhm R0 R.KOhm.KOhm PU_ELET# _PH _PH JP0 JP0 JP0 HORT_PIN HORT_PIN HORT_PIN R0 0 R0 PU_HOL_RT# +V R0 PU_PWR_EN L_L_PWM_PH L_V_EN_PH _PH _PH _HYN_PH T0 T0 P0 P0 0KOhm 0KOhm 0KOhm 0KOhm _PH _PH R_PH P0 P0 PU_PWR_EN RN0 RN0 RN0 RN0 R00 R00 INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# PU_HOL_RT#_R PU_ELET# _IT R00 R00 Int. PU PU_PWM_ELET# TP_OVR Int. PU T U V M M N N H0 L0 K M0 0 0 L V_LUE V_REEN V_RE V LK V T V_HYN EP_KLTTL EP_VEN PIRQ# PIRQ# PIRQ# PIRQ# PIO0 PIO PIO PIO PIO PIO RT LV PI IPLY P_TRLLK P_TRLT P_TRLLK P_TRLT P_TRLLK P_TRLT P_UXN P_UXN P_UXN P_UXP P_UXP P_HP P_HP P_HP PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PME# PLTRT# R0 R9 R R N0 N H K J H J K0 K H9 F L M 0 Y P_UXN MP_PWR_TRL# T_O_# EXTT_NI_RV0_PH EXTT_NI_RV_PH PI_PME# PLT_RT# T0 HMI LK_PH 9 HMI T_PH 9 T0 R. 是否會浪費電? R. 0/0/9 option changed from /non_fi R. 0//0 remove R, R9~R, R9 for R HMI_HP_PH 9 KOhm R T_O_# 0 T0 +V 0KOhm 0KOhm 0KOhm 0KOhm R. 0// follow intel design guide R R R R T_O_# EXTT_NI_RV_PH EXTT_NI_RV0_PH MP_PWR_TRL# _IT0,_IT : oot IO trap oot IO trap _IT 0 _IT0 ampled on rising edge of PWROK oot IO Location LP Reserved (NN) Reserved PI (PH) EFULT TP_OVR: swap override trap/ Top-lock swap override jumper Low=Enabled swap override/ Top-lock swap override High=efault PLT_RT# U0 HLPM 0V V Y NLV0KR +V R +VU R trap information: There signals have a weak internal pull down P_TRLT: "0" = Port is not detected; ""= Port is detected P_TRLT: "0" = Port is not detected; ""= Port is detected P_TRLT: "0" = Port is not detected; ""= Port is detected UF_PLT_RT# 0,,0,,,,,0 0 _IT0 _IT0 _IT R0 R KOhm KOhm TP_OVR R KOhm R R 00KOhm +V R 0KOhm R. R 0KOhm +V R 0KOhm 9 V_PWRON R +VU U0 V Y R U_E#,0,,9,9 PU_PWR_EN NLV0KR R PETRON OMPUTER IN PH()_P,LV,RT Wing_heng V0_HW Friday, January, 0 ate: heet of 9.0

18 0 PIE_RXN_R 0 PIE_RXP_R 0 PIE_TXN_R 0 PIE_TXP_R PIE_RXN_mT PIE_RXP_mT PIE_TXN_mT PIE_TXP_mT PIE_RXN_WLN PIE_RXP_WLN PIE_TXN_WLN PIE_TXP_WLN PIE_RXN_LN PIE_RXP_LN PIE_TXN_LN PIE_TXP_LN +.V +.V UF/0V 0.UF/0V 0.UF/0V 0.UF/0V R. 0// cost dwon 0ohm R. 0//0 change short pin size PIE_TXN_R_ PIE_TXP_R_ PIE_TXN_mT_ PIE_TXP_mT_ PIE_TXN_WLN_ PIE_TXP_WLN_ P0 N_R00_0MIL_MLL R0 0.UF/0V 0.UF/0V 0.UF/0V 0.UF/0V.KOhm PIE_TXN_LN_ PIE_TXP_LN_ PIE_IREF PIE_ROMP U00I W Y PERN/URN PERP/URP E PETN/UTN PETP/UTP T R PERN/URN PERP/URP PETN/UTN PETP/UTP W Y PERN_ PERP_ E PETN_ PETP_ T R PERN_ PERP_ E PETN_ PETP_ W V PERN_ PERP_ PETN_ PETP_ Y W PERN_ PERP_ E PETN_ PETP_ T0 T9 PERN_ PERP_ E0 0 PETN_ PETP_ N N9 PERN_ PERP_ PETN_ PETP_ E0 PIE_IREF 0 TP 9 TP HLPM 9 0V PIE_ROMP LPT_PH_M_E PIe U UN0 UP0 UN UP UN UP UN UP UN UP UN UP UN UP UN UP UN UP UN9 UP9 UN0 UP0 UN UP UN UP UN UP URN URP UTN UTP URN URP UTN UTP URN URP UTN UTP URN URP UTN UTP URI# URI TP TP O0#/PIO9 O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO9 O#/PIO0 O#/PIO U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP F U_PN U_PP K L 9 U_PN H9 U_PP U_PN U_PP 0 U_PN9 0 U_PP9 9 U_PN0 9 U_PP0 U_PN U_PP U_PN F U_PP F R P E W V W9 V9 E R9 P9 E K K M U_I L P O0#/PIO9 V O#/PIO0 U O#/PIO P O#/PIO M O#/PIO T O#/PIO9 N O#/PIO0 M O#/PIO T0 T0 T0 T0 T0 T0 T0 T0 R0 %.Ohm U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN9 U_PP9 U_PN U_PP 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm RN0 RN0 RN0 RN0 RN0 RN0 RN0 RN0 U PORT U P00 External.0/.0 U P0 External.0/.0 U P0 External.0 U P0 U P0 U P0 WiFi U P0 U P0 amera U P09 External.0 U P0 T U P PIE/mT U P U P U_RX_N U_RX_P U_TX_N U_TX_P U_RX_N U_RX_P U_TX_N U_TX_P +VU_OR +VU +V +V +VU_OR +V +.V +VU,,,,,0,,,,,9 +V,,0,,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +V,,,,9 +VU_OR 0,,,,, +V,9,,,9 +.V 0,,,,,,,,, Place within 00 mils of PH P0 R00 U_O0# P0 R00 U_O# R0 PH()_PI,NVRM,U Wing_heng PETRON OMPUTER IN ustom V0_HW.0 Friday, January, 0 ate: heet of 9

19 +V +VU +VW +VU_OR +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +VU,,,,,0,,,,,9 +VW +VU_OR 0,,,,, R. 0//0 P_I R. +V R 0KOhm +V R9 0KOhm +V R 0KOhm P I P_I P_I0 R.0 T 0 0 R. T 0 R. T 0 R. T P_I0 P_I P_I R 0KOhm EXT_MI# PH_PIO PM_LNPHY_EN PH_PIO RIN# has pull high at E side PU_HP_INTR# PH_LERT# PU_PWROK R. 0//9 R, ep_on# pull-up is removed PIO9 R0 0KOhm R R R R0 R R R9 R0 R 0KOhm KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm +VU_OR +V, WLN_ON Q0 UMKN +V R 0KOhm Q0 UMKN +V Reserved This signal has a weak internal pull-up but requires an external pull down. PH_PIO R 0KOhm P0 WLN_ON_R 0 R00, WLN_RT#_PH 0, R. 0// ep_on# is not used PH_PIO0_R R. 0//9 PIO T0, R are removed, too T0 PU_HP_INTR# PH_PIO_R EXT_MI# T_O_PWRT OP_# 0,9 T_O_PRNT# T0 P0 P0 PU_PWROK WLN_LE O_ON T_ON_PH PH_LERT# P_I PU_PWROK R. 0//0 cost dwon 0ohm P0 P0 R00 R00 R00 P0 R PM_LNPHY_EN HOT_LERT#_R T_ET# P0 PIO change: IO_PLU_EVENT/PIE_WKE#/OP_#/R_VOLT_EL P_I R00 R00 R00 PIO9 PIO0 PIO PIO WLN_ON_R TP_PI# T_O_PRNT#_R FI_OVRVLT P_I0 P_I PH_PIO T_PWR_EN#_R RIT_TEMP_REP#_R T F Y K N Y0 R N P T K T M N K U H E E U00F MUY#/PIO0 TH/PIO TH/PIO TH/PIO PIO TH/PIO0 TH/PIO HLPM 0V LPT_PH_M_E LN_PHY_PWR_TRL/PIO PIO TP/PIO TH0/PIO LOK/PIO PIO PIO PIO PIO PIO/NMI# TP/PIO TP/PIO LO/PIO TOUT0/PIO9 TOUT/PIO TP/PIO9 PIO TH/PIO TH/PIO9 V V V V PIO NTF PU/Misc TP PEI RIN# PROPWR THRMTRIP# PLTRT_PRO# V V V V V V V0 V V9 V V V V V V V0 V9 V V V V N0 Y T V V U N0 E E E E H_PEI_R PM_THRMTRIP# TP is Intel Reserved Pin: Must have a pull up resistor to V_. tandard resistor value in the range of.k to K ok(shark bay LPT E 0) 9 % R0 R0 Ohm R0 % need close to E R0 KOhm 0TE 0 H_PEI H_PEI_E 0 RIN# 0 H_PUPWR H_THRMTRIP#, +.0V PH_PLTRT_PU# R. PIO R 0KOhm PU_PWROK R 0KOhm TP_PI# R 0KOhm PH_PIO_R R 0KOhm T_ET# PH_PIO0_R R R 0KOhm 0KOhm +VU_OR R. FI_OVRVLT +V R % KOhm R 00KOhm Functional trap efinitions Usage: TL onfidentiality(intel rypto Transport Layer ecurity) "0" = isable "" = Enable +V R % 00KOhm T_O_PRNT#_R IO Flexible: PIO0 PIO PIO0 PIO R R R9 R0 +V 0KOhm 0KOhm 0KOhm 0KOhm U Port PIE Port Mode (UP_PIEP_MOE) Up_tach_gp0 pin is a 0, then Root Port is assigned to U Port, else it is assigned to PI Express. U Port PIE Port Mode (UP_PIEP_MOE) Up_tach_gp pin is a 0, then Root Port is assigned to U Port, else it is assigned to PI Express. PIO R 0KOhm Functional trap efinitions Usage: Reserved This signal has a weak internal pull-down. NOTE:. The internal pull-down is disabled after PLTRT# deasserts.. This signal should not be pulled high when strap is sampled PIO R 0KOhm PETRON OMPUTER IN PH()_PU,PIO,MI Wing_heng ize Project Name ustom V0_HW Rev.0 Friday, January, 0 ate: heet of 9

20 U00 LPT_PH_M_E +V 9 0.0UF/0V 0 0.UF/V 0UF/0V 0 kohm/00mhz R. 0// follow intel design guide R. 0// +.V R is removed R. 0//0 remove R, R0 for R R. 0//9 option changed to N/ LPT_PH_M_E U00J L L V L V M V M V M V M V M0 V9 M V90 M V0 N V N0 V9 N V N V P V09 P V0 P V P V0 R V K V T0 V T V T V T0 V T V T9 V T V T V V0 V V V V V V9 V V9 V V V V0 V9 V V0 W V0 F V0 Y0 V Y V0 Y0 V0 Y V0 Y9 V0 Y V00 V99 V9 V9 V9 V9 V9 V9 V9 V0 V V V V V V V V V9 V0 V V V V V V V V V0 V9 V V V V V V V V V V0 V9 V V V V V V V V9 K9 L L M M N N N9 N P P P P P0 P R R R R R R R R T U0 U U U U U U V V V V W W Y Y Y Y Y Y Y0 Y +V.0V_PH_V +V.0VM_VW 0UF/0V UF/.V 0 UF/.V R0. +PH_VW 0. PU,PU( 頁 ),PU: If INTVRMEN is strapped high then power to this well is supplied internally and this pin should be left as no connect. If INTVRMEN is strapped low then power to this well must be supplied by an external.0 V suspend rail. Note: External VR mode applies to Mobile Only. (shark bay aryreff schematic ) UF/.V 0 UF/.V UF/.V.Ohm 0 UF/.V 0 UF/.V 0 E E0 E E E 0 Y U U U0 U U V V0 V V Y Y0 Y V V V9 V V0 V V V V V V V V V V V V PUYP VW VW VW VW VW VW9 VW0 VW VW VW VW VW ore RT FI HVMO U PIe/MI T VMPHY V_ V V_ VVRM VIO VIO V R0 V R PU VU VU PU_ PU_ VIO VVRM VVRM VVRM VIO VVRM VIO9 VIO VIO0 VIO VIO VIO VIO P P M N N R0 R Y J0 J J J K0 K K E K N K M M0 M P R T 0m m +V_V_IO +V._VPLL_FI +V.0_V_EXP T0 T0 09 UF/.V +V.0_V_EXP +VPLL_U +VPLL_EXP 0 0UF/0V +VPLL_T +V._ 0 UF/.V 0UF/0V 0 UF/.V 0.UF/V R0 +V +VTT_PH_VIO 0UF/0V R. 0//0 R. 0//0 N_R00_0MIL_MLL P cost dwon 0ohm change short pin size +.V 0 UF/.V R0 UF/.V N_R00_0MIL_MLL P +VU_OR +VU_VPU +.V 0UF/0V 0 UF/.V N_R00_0MIL_MLL P +.V R. 0//0 cost dwon 0ohm R. 0//0 change short pin size R. 0// R0 is removed +V N_R00_0MIL_MLL P R. 0//0 cost dwon 0ohm 0.UF/V R. 0//0 change short pin size +.V N_R00_0MIL_MLL P R. 0//0 cost dwon 0ohm R. 0//0 change short pin size HLPM 0V HLPM 0V V JP0.9 +V.0V_PH_V +V.0VM_VW +V.0VM_VW MM_OPEN_MIL JP0 MM_OPEN_MIL JP V.0VM_VW +VTT_PH_VIO +VTT_PH_VIO +.0V +.V +V +VTT_PH_VIO +.0V,,,,,0, +.V 0,,,,,,,,, +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 MM_OPEN_MIL +VU_VPU +VU_VPU \ORE PH()_POWER, Wing_heng V0_HW Friday, January, 0 ate: heet of 9.

21 U00K LPT_PH_M_E 0 V V9 V9 V9 V9 V9 V9 V V V V9 V90 V9 0 V0 V0 0 V0 V09 V0 E V E V F V F V V V V0 V00 V99 J V9 J V J0 V J V J V0 J V9 J V J V0 J V9 K V K V K V K V L V L V V V0 V0 HLPM 0V V V0 V9 V V V V V V V V V0 V9 V9 V0 V V V V V V V V V V0 V V V V V V V9 V0 V V V V V V V V V V V V Y T 9 V F F0 F9 F H0 H H H H H H H H0 H K0 K K0 K9 K R. 0//0 cost dwon 0ohm R. 0//0 change short pin size +.0V +.V +VU_OR N_R00_0MIL_MLL P0 +VU_VPU R. 0//0 cost dwon 0ohm R. 0//0 change short pin size R. 0//0 cost dwon 0ohm R. 0//0 change short pin size +.0V_VU +.0V R N_R00_0MIL_MLL +V_VU +V P UF/V 0.UF/V R. 0//0 N_R00_0MIL_MLL cost dwon 0ohm +.0V_VUORE +VTT_PH_VIO P0 R. 0//0 change short pin size +VXK_VRM 0 0.UF/V T0 N_R00_0MIL_MLL P +.0V N_R00_0MIL_MLL P +.0V_V_XK_ 0UF/0V +.0V_V_FF UF/.V 0UF/0V +V_V_FLEX0 R. 0//0 cost dwon 0ohm +V_V_FLEX R. 0//0 change short pin size +V_V_FLEX +V +V 0 0.UF/V +V_V_EPI +VLKF +.0V_V_FF +.0V_VLKF00 +.0V_VF00 +.0V_VLKF00 +.0V_VF00 R R R U M U L U0 V V0 Y0 Y F P Y M9 L9 L M U V 0 0 E0 E U00H VU 9 VU VU VU V VUPLL V VIO VIO VIO VIO PU VVRM V0 VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK VLK9 VLK0 LPT_PH_M_E U I PIO/LP zalia RT PU PI Fuse Thermal VU VU VW_ PT V V V VIO VUH VU VRT PRT PRT V_PRO_IO_ V_PRO_IO_ VPI V V9 VW VW VVRM V V R0 R E F U K P P J J P P0 L R W0 K0 K +VU_VPU N_R00_0MIL_MLL P0 R. 0//0 change short pin size +V 0 0.UF/V N_R00_0MIL_MLL +V_VPORE P0 +VTT_PH_VIO R. 0//0 N_R00_0MIL_MLL 0 cost dwon 0ohm +V.0_VUX P0 0.0UF/0V R. 0//0 +VU_OR change short pin size N_R00_0MIL_MLL +VU_VPZU P0 R. 0//0R. 0//0 +V_RT cost dwon 0ohm change short pin size 0 0.UF/V +VPRTU 0.UF/V 0.UF/VUF/.V +VRTEXT +VM_VPPI +V._VT +VW +.0V_VPPU +V_VPFUE PH_V 0 PH_V +V_VPT +VT 0.UF/V UF/V 0 0.UF/V UF/.V +VW N_R00_0MIL_MLL P0 +V.0VM_VW N_R00_0MIL_MLL P0 +V.0VM_VW N_R00_0MIL_MLL P0 +.V R. 0//0 cost dwon 0ohm R. 0//0 change short pin size N_R00_0MIL_MLL P +V R R +.0V Unstuff R, stuff R Intel MOW WW09: renamed VIOPH to RV +VU_OR +VIOPH R. 0 0.UF/V 9 UF/.V R0 +.0V R +V N_R00_0MIL_MLL P +.0V_V_FF UF/.V N_R00_0MIL_MLL P +V_V_FLEX0 9 UF/.V N_R00_0MIL_MLL P +V_V_FLEX 0 UF/.V HLPM 0V UF/V R. 0//0 cost dwon 0ohm R. 0//0 change short pin size +VU_OR +V +V N_R00_0MIL_MLL P +V_V_FLEX +V +.0V N_R00_0MIL_MLL N_R00_0MIL_MLL P +V_V_EPI P +VLKF 0m +VM_VPPI R0 +V +VPRTU R9 R UF/.V UF/.V UF/.V UF/.V R0 +VM_PI UF/.V +.0V N_R00_0MIL_MLL P9 +.0V_VLKF00 +.0V N_R00_0MIL_MLL P0 +.0V_VF00 UF/.V UF/.V +VU_OR +VU JP0 m MM_OPEN_MM +V.0VM_VW +VU +VU_OR +.V +V +.0V +VTT_PH_VIO +VXK_VRM +VU_VPU +V +V_RT +V.0VM_VW +VU,,,,0,,,,,9 +VU_OR 0,,,,, +.V 0,,,,,,,,, +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 +.0V,,,,,0, +VTT_PH_VIO +VXK_VRM +VU_VPU +V 0,0,,,,,9 +V_RT 0, +VIOPH +VIOPH PETRON OMPUTER IN PH()_POWER, Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9.0

22 PH PI ROM +V +V,,0,,,,,,,0,,,,9,0,,,,,9,,,0,,,,9,9 R V +VU +V 9,,,9 +VU,,,0,,9 +V_E +VU R0 R0 +VM_PI 0 V/0. R0 +VM_PI +VU +VM_PI +VU,,,,0,,,,,9 PH <. inch <. inch PI ROM (Mb) E,0,0,0 PH_PI# PH_PI0# PH_PIO PI_WP_IO PH_PI# PH_PI0# PH_PIO +VM_PI Ohm Ohm R KOhm +VM_PI R. 0//9 reserved for intel design guide Ohm Ohm R0 R0 R0 R R R R0 KOhm +VM_PI R. 0// follow intel design guide PI_#0 PI_O +VM_PI_WP# R KOhm 0V (Mb) R. 0// follow intel design guide PI_# PI_O +VM_PI_WP# U0 # O/IO WP#/IO MXLEMI-0 U0 # O(IO) WP#(IO) WQFVIQ 0V (Mb) V N/IO LK I/IO0 0 0.UF/V V HOL#/REET#(IO) LK I(IO0) PI_HOL# PI_LK PI_I +VM_PI 0 0.UF/V +VM_PI R. 0// follow intel design guide R. 0//9 reserved for intel design guide R0 R KOhm KOhm +VM_PI PI_HOL# PI_LK PI_I R KOhm R R09 R0 Ohm Ohm Ohm R. 0// follow intel design guide R R R Ohm Ohm Ohm PI_HOL#_IO,0 PH_PILK,0 PH_PII,0 PI ROM ( Kb) ROM setting: onfiguration. ITE HPI -> short J0 pin & and no stuff U0,U0 onfiguration. One ROM solution -> short J0 pin& and no stuff U0 ; stuff U0(IO+ME) onfiguration. Two ROM solution -> short J0 pin&, J0 pin& tuff U0(ME), tuff U0(IO) Follow Intel setting: U0: ME U0: IO PI ebug onnector PH Mus +V +V MU Link device ep WLN PU XP PH XP RN0.KOHM RN0.KOHM +VU +V L_ M_LK_,,,, PH Q0 UMKN _ M_T_,,,, Q0 UMKN R0 +VU +V 0,9, +V M_LK Q0 UMKN R9 +VU ML_LK E, V Thermal 0,9, M_T Q0 UMKN ML_T PH R. 0/0/9 option changed from /non_fi_ R. 0// R, R are removed L_V 0,9, _V 0,9, +V NX PETRON OMPUTER IN PH(9)_PI,M Wing_heng V0_HW Friday, January, 0 ate: heet of 9.0

23 PETRON OMPUTER IN LK_I9LR9 Wing_heng ustom V0_HW Friday, January, 0 ate: heet of 9 9.0

24 T00 T0 _IN_O# 90 M_VREF +V_E +V +VU +V +V_E, +V,,0,,,,,,,,,,,9,0,,,,,9,,,0,,,,9,9 +VU,,,,,,,,,9 +V 0,,,,,,9 +V L00 kohm/00mhz +V_E R. 0//0 工工工工工工 T0 R0 T0 T0 R. 0//0 工工工工工工,, LP_0,, LP_,, LP_,, LP_ LK_KPI_PH,, LP_FRME#,,0,,,,,0 UF_PLT_RT#,, INT_ERIRQ, EXT_MI# 0 EXT_I# 0TE RIN# E_RT# T0 KI0 KI KI KI KI KI KI KI KO0 KO KO KO KO KO KO KO KO KO9 KO0 KO KO KO KO KO +V_E P00 P00 P00 P00 +V +V OHM OHM OHM OHM RN00 L0 RN00 L RN00 L RN00 L R00 R00 R00 R U00 VT VTY(PLL) VTY VTY VTY VTY VTY V V RX/IN0/P0 TX/OUT0/P RIN#/PWRFIL#/ KKOUT/LPRT#/P L0/PM0 L/PM L/PM KO/MOI/P L/PM TMRI0/P LPLK/PM KO/MIO/P LFRME#/PM TMRI/P LPRT#/P PWUREQ#/O/MLKLT/P ERIRQ/PM EMI#/P EI#/P RI#/P0 0/P RI#/P KRT#/P INT/T0#/P WRT# TH0/P TH/TM/P KI0/T# KI/F# KI/INIT# KI/LIN# KI KI KI KI KO0/P0 KO/P KO/P KO/P KO/P KO/P KO/P KO/P KO/K# KO9/UY KO0/PE KO/ERR# KO/LT KO KO KO 0/PI0 /PI /PI /PI /PI /#/PI /R#/PI /T#/PI PWM0/P0 PWM/P PWM/P PWM/P PWM/P PWM/P PWM/K/P PWM/RI#/P L0HLT/O/PE0 E/PE E#/PE ELK/PE PWRW/PE RT#/PE LPP#/PE L0LLT/PE E#/FE#/P0 FIO/TR#/UY/P/I E0#/P FIO/R0#/P LKRUN#/PH0/I0 RX/IN/MLK/PH/I TX/OUT/PH/MT/I HE#/PH/I HK/PH/I HMIO/PH/I HMOI/PH/I U_PWR_R LL_YTEM_PWR_R VRM_PWR_R LP_U#_R KO KO FN0_TH VU_ON_E LN_WKE# EN_PO_PWR HPI_ HPI_LK HPI_O HPI_I P00 R0 R0 R0 R09 RF_ON_R FIO T00 FIO R0 T00 T00 R. 0//0 cost dwon 0ohm P0 P0 P0 P0 R00 R00 R00 R00 R00 H0 UP_EN PH_PI#, PH_PILK, PH_PIO, PH_PII, _IINP U_PWR,9 LL_YTEM_PWR 9 VRM_PWR 0,9 THERM_LERT#_E LP_U# WLN_WKE# VR_IMON 0 PWR_LUE_LE#, H_LE_LUE# T_OR_LE# PWR_MER_LE#, F_LMP_TL_REQ# UP0_EN E_PKR L_E_PWM LN_PWR_ON# T_ON_E PM_RMRT# KO _IN_O,,90 KO T_IN_O# 90 ME PREENT PM_U# PM_U# PM_PWROK 9,,9 FN0_TH 9 UP_EN VU_ON,,9,9 U_E#,9 U_E#,,,9,9 PU_VRON 0 PWR_W#_M RF_ET# LI_W#, For PU / P +V_E +V 00 0UF/0V R0 R00 R0 RN00 RN00 RN00 RN00 R0 PM_U# PM_U# PU_VRON PH_FLH_ERIPTOR R0 PM_RMRT# +V_E 0KOhm 0KOhm.KOHM.KOHM.KOHM.KOHM R00 R00 R009 R0 _IN_O is pulled high at power 00 0.UF/V P00 R00 KOhm 0KOhm E IN_O 00 0.UF/V T_IN_O# PWR_W#_M M0_LK M0_T M_T M_LK THERM_LERT#_E 00KOHM 00KOHM 00KOHM 00KOHM 0KOhm 00 0UF/0V R. 0//0 follow M0 +V +V +V_E +V +V_E RN00 RN00 RN00 RN UF/V R0 R0 R00 R0 R0 R0 R0 R0.KOHM.KOHM.KOHM.KOHM 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm +V P00 R00 0KOhm 0KOhm 0KOhm E_ TP_LK TP_T U_E# U_E# 0TE RIN# FN0_TH F_LMP_TL_REQ# WLN_WKE# IO_EN RF_ET# RF_ET# 00 0.UF/V 00 0.UF/V RF_ON +V_WLN Q00 UMKN R0 R00 0KOhm R. 0//0 工工工工工工 +V_WLN Q00 UMKN R0 0KOhm 0 UH_EN H_PEI_E PH_FLH_ERIPTOR RF_ON_R T0 attery Thermal sensor H_PEI_E 0PF/0V9,,,, PI_HOL#_IO, PI_WP_IO ME_UPWRNK THRO_PU T_LERN WLN_RT#_E PM_PWRTN#,,,9,,9, 0 TL_FN F_LMP PH_FLH_ERIPTOR TP_LK TP_T M0_LK M0_T M_LK M_T L_KOFF# IO_EN R0 R0 LP_E R09 T009 R. 0//0 R. 0//0 cost dwon 0ohm E# cost dwon 0ohm R. 0//0K R. 0// I remove R0 change back to 0ohm O R. 0//0 R0, R0 are replaced by P00, P0 R. 0// P00, P0 replaced by 0ohm ep_on#_e 9 90 PI_HOL#_IO_R PI_WP_IO_R LP_E_R RX0/P0 TX0/TM0/P PLK0/TM0/E/PF0 PT0/TM/PF PLK/TR0#/PF PT/RT0#/PF PLK/PF PT/PF MLK0/P MT0/P MLK/P MT/P MLK/PEI/PF MT/PEIRQT#/PF /RI0#/PJ /0#/PJ /TH/PJ /TH0/PJ HIO/PJ TH/HIO/PJ0 KK/PJ KKE/PJ FE# FK FMOI FMIO ITE/X 0V00000 V VORE V 9 V 9 V V V V R. 0//0 cost dwon 0ohm R. 0// change to ohm for Intel check list R. 0//0 R0~R09 are replaced by P0, P0, P09, P00 R. 0// P0, P0, P09, P00 are replaced by 0ohm 00 0.UF/V E_ mt_pwr_on# LN_PWR_ON# U_PWR_ON# MER_PWR_ON# O_PWR_ON# VU_ON +VU +V_E R00 00KOHM R0 00KOHM VU_ON R0 0KOhm VU_ON VU_ON efault Pull High to +VU +VU +VU +V R00 R0 0KOhm R0 0KOhm R0 R0 R0 KOhm KOhm KOhm KOhm PM_PWRTN# LN_PWR_ON# R. 0//0 R0 changed to PWR_LUE_LE# R. 0//0 cost down PWR_MER_LE# T_OR_LE# H_LE_LUE# load=.pf place close to E +V_E +V_E_PI hare ROM non-hare ROM 00 0.V/0.m 0V R09 +V_E_PI +V_E_PI R. 0// follow Intel design guide R. 0// follow Intel design guide R. 0//0 R0 90 R00 R. 0//0 cost dwon 0ohm KOhm 0.UF/V KOhm cost dwon 0ohm R. 0// R. 0// change back to 0ohm U00 change back to 0ohm E# R09 E#_ O O_ # V R09 Ohm ROM_H#_ R0 FIO FIO ROM_WP#_ O(IO) HOL#/REET#(IO) LK_ R00 Ohm K R0 WP#(IO) LK I_ R0 Ohm I I(IO0) WQFVIQ 0V (Mb) need to check ROM P/N +V_E_PI +V_E_PI R0 R00 00.KOhm.KOhm 0.UF/V U00 E# R0 E#_non O R0 Ohm O_non E# V ROM_H#_non ROM_WP#_non O HOL# K_non Ohm WP# K I_non Ohm IO PML00-E (K) R0 R0 K I U/R ITEE Wing_heng ize Project Name ustom V0_HW Rev.0 Friday, January, 0 ate: heet of 0 9