RK3036_KYLIN_0119

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1 ONTENT INEXING 0. INEX 0. MOIFY NOTE 0. LOK IGRM 0.Power Tree 0.SYSTEM POWER 0.PU(RK0) 0.R 0.EMM /TF card 0.US HOST 0.HMI OUT.udio odec-l.ethernet.p.eug.gpio LYERS P STK TOP GN Prepreg *.0MIL(0.0mm) djust Hoz(um) + plating copper(um) oz(um) POWER OTTOM Prepreg *.0MIL(0.0mm) oz(um) Hoz(um) + plating copper(um) Index RK0_KYLIN.0 reate ate: Modify ate: Wednesday, ecember, 0 Monday, ecember, 0 Page Total:

2 Version ate uthor hange Note Note V.0 00 V RK0 I pull-up resistor R R. HNGE I_SL_UIO I_S_UIO. ELETE RK0 PWRON KEY N RESET KEY. hange V_ on resistance R0 to output(/ Fixed.V output ). US OTG MIRO US. hange US OTG to US MIRRO. Update socket footprint. Update PJ- footprint. Update pcb antenna footprint 0. changed to 0 chip package.dd the pull on resistor in sd Modify note RK0_KYLIN.0 reate ate: Modify ate: Saturday, October, 00 Monday, ecember, 0 Page Total:

3 G emm R XM*bit emm NN FLSH R Interface SMM0 VS OUT R/L OUT SMM WIFI module HMI OUT RJ- Ethernet PHY HMI OUT EM PU(RK0-G) US OTG US OTG PJ- L IS US HOST US host RK0 PWR OS M RESET IR IN GPIO MHz RK0 RESET KEY V/ SYSTEM POWER lock iagram RK0_KYLIN.0 reate ate: Modify ate: Saturday, October, 00 Monday, ecember, 0 Page Total:

4 PMU TIMING V. UK V_R RK0 R-trl R V V UK UK V_PU RK0PU V.0_SYS V.0_SYS V._SYS V.0_SYS V V0 V V V V. UK 0m LO LO 0m 0m LO 00m LO LO 0m 00m LO LO 00m V._SYS V_ V_ V_0 RK0 IO RK0 US PHY EMM S ard US HU(GL0G/GLG) udio Line river I Ethernet PHY(RTL0F) SIO WIFI RK0 PLL RK0 HMI RK0 V RK0 OE udio odec-l RK0 PLL RK0 US PHY RK0 HMI 00m LO V/ V SW OVP V.0_SYS V SW V.0_SYS VRT K LKOUT WIFI+T SWITH TPS0VQ RK0 US RK0_KYLIN.0 reate ate: Modify ate: Tuesday, October, 0 Monday, ecember, 0 Page Total:

5 J0 US0_mini US-P-MI G G G G V/ V M P I GN R R % R0.uF XR 0V 00 F R0.uF 0V 00 V.0_SYS_IN V.0_SYS V.0_SYS LE_ON R K % LE R00 RE R K % LE R00 RE R 0K R00 % LE_ON, LE00 LE00 POWER LE WORK LE Q S00 SOT_ R 0K % R00 fastboot nf XR V 00 lose to RK0 fastboot R SW 00R R00 % ES00 Recovery E Z-0F fastboot key V.0_SYS V_PU V.0_SYS V.0_SYS,, V_PU PMI_INT_L RESET uf 0V 00 0.uF 0V 00 V.0_SYS.uF 0V 00 0.uF 0V 00.uF 0V 00.uF 0V 00.uF 0V 00 RK0 ORE I0_S_PMI I0_SL_PMI PMI_SLEEP R 0K R00 % RESET J0 SHIEL_P SHIEL_P J0 SHIEL_P SHIEL_P N/0pF 00 0G 0V N/0R R00 % R R 00K R00 % J0 SHIEL_P SHIEL_P IN_000 JSE00-R0MT L V_PU 0 R 00R Feedback from PU device R00 % I0_S_PMI I0_SL_PMI PMI_SLEEP J0 SHIEL_P SHIEL_P VS VSOK U RK0- QFN_R00XR00X0R0_T V_ V_ SW_ SW_ GN_ GN_ VF V_ V_ SW_ SW_ GN_ GN_ VF N N GN V V VLO V GN V V0 V V V VIO GN uck 0.V-.V uck 0.V-.V S SL SLEEP INT VS VS VSOK NRESPWRON ResetKey/VPPOTP PWRON Top LO&Switch uck..v-.v uck..0v-.v.-.v/0m.-.v/0m 0.-.V/00m low noise 0.-.V/00m low noise.-.v/0m.-.v/00m 0.-.V/0m low noise.-.v/00m 0.R Switch 0.R Switch.V----.V RT REF RK0 V SW GN VF V SW VF GN VREF VREFGN VLO VLO VLO VLO VLO VLO VLO VLO VSWOUT VSWOUT VRT 0 OSKIN OSKOUT always on LKKOUT LKKOUT GNP OOT0 OOT EXT_EN V R 00K % R00.V V 0.-.V/00M.-.V/0M.-.V/00M.-.V/0M.KHz L S-H-RM/. IN_00 L S-H-RM/. IN_00 00nF Y pf/0v 00 RT_LKOUT RT_LKOUT 0V V_R.-.V/0M VOUT VOUT VOUT VOUT pf/0v 00 RY_R0XR0XR0 R nf V V R % R00 K.K% R00 pf 00 0G uf 0V 00.V VOUT R 0K R00 % R 00K % R00.uF 0V 00 R0 00R % R00 Feedback from R device.uf 0V 00 V.0_SYS.uF V 00.uF 0V 00.uF 0V 00 V_R V_R V_.uF 0V SO PLL/M 00 US_V_V0/M R 0.0R R00 %.uf 0V 00 RT_LKOUT T TEST RT_LKOUT POWER_GOO_H.uF 0V 00.uF 0V 00 V_ VV/M V.0_SYS V.0_SYS V.0_SYS V_ V_ V V.0_SYS R0 N/00K % R00 uf/0v V 00 R M % R00 RK0 IO EMM S ard US HU(GL0G/GLG) udio Line river I(Option) Ethernet PHY(RTL0F) SIO WIFI RK0 R ontroler R RK0 PLL RK0 US PHY RK0 HMI RK0 V RK0 OE RK0 PLL RK0 US PHY RK0 HMI VOUT VOUT VOUT VOUT 0 uf.v 00 uf.v 00 I0_S_PMI I0_SL_PMI uf.v 00 uf.v 00 R K R00 R K R00 V_EFUSE U IN F/OUT GN N/uF.V 00 V.0_SYS_IN OVP OVP Recover R.K % R00 R 0K % R00 SHN P N/PT0EE- N/00nF SOT 00 0V.uF R.K 0V 0.% 00 R00 U ME0 SOT_ VOUT V GN R 0K % R00 Recover R 00R R00 nf % XR V 00 lose to RK0 SW RESET ES00 E Z-0F FN_R0XR0X0R0_T Q ON E Z-0F ES00 R 0R % R00 SW ES00 Recovery E Z-0F Recovery key RESET N/uF.V 00 RESET KEY V.0_SYS uf 0V 00 J0 SHIEL_P SHIEL_P J0 SHIEL_P SHIEL_P J0 SHIEL_P SHIEL_P J0 SHIEL_P SHIEL_P H HOLE_.0 HOLE_R00 H HOLE_.0 HOLE_R00 H HOLE_.0 HOLE_R00 H HOLE_.0 HOLE_R00 M MRK M MRK M MRK M MRK M MRK M MRK M MRK M MRK RK0_KYLIN.0 reate ate: Tuesday, July 0, 0 Modify ate: Tuesday, ecember, 0 Page Total:

6 V_PU V_PU UJ RK0-G G_R00XR00XR V_PU Power J VV L VV N VV N VV M VV L VV G VV E VV E V uf.v 00 0uF.V 00 VIO VIO VIO VIO K N0 K H 0uF.V 00 00nF 00 0V 0 uf.v 00 nf XR V 00 00nF 00 0V 00nF 00 0V.uF 0V 00 RK0 Power UK RK0-G G_R00XR00XR GN H J E0 VSS VSS M E VSS VSS M E VSS VSS M0 F VSS VSS M F VSS VSS M F VSS VSS M F VSS VSS0 M F0 VSS VSS L F VSS VSS L F VSS0 VSS L0 F VSS VSS L G VSS VSS L G VSS VSS L G VSS VSS L G VSS VSS K G0 VSS VSS K G VSS VSS0 K0 G VSS VSS K H VSS VSS K H VSS0 VSS K H VSS VSS K H VSS VSS J H0 VSS VSS J H VSS VSS J H VSS VSS J0 J VSS VSS J J VSS VSS0 J VSS VSS 00nF 00 0V 0 00nF 00 0V 00nF 00 0V 00nF 00 0V V_ V_ U RK0-G G_R00XR00XR HMI TX HMI_TX0P T HMI_TX0N U T HMI_TXP HMI_TXN U HMI_TXP T HMI_TXN U HMI_TXP T HMI_TXN U GPIO_0/HMI_E_u GPIO_/HMI_HP_d GPIO_/HMI_SL_u GPIO_/HMI_S_u HMI_EXTR R HMI_V HMI_VV_ HMI_VV_ R 0.0R R00 % HMI R0 N P R R N R R 0.0R R00 % HMI_TX0+ HMI_TX0- HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_E HMI_HP HMI_SL HMI_S V_HMI.uF 0V 00 V_HMI R KR00 % V_HMI V_HMI 00nF 00 0V 0 00nF 00 0V V_HMI S ial_switch_ sw_rxr0xr0 GPIO_0 GPIO_ GPIO_ GPIO_.uF 0V 00 GPIO_0 GPIO_ GPIO_ GPIO_ 00nF 00 0V R_0 R_ R_ R_ R_ R_ R_ R_ R_QS0P R_QS0M R_M0 R_ R_ R_0 R_ R_ R_ R_ R_ R_QSP R_QSM R_M R Interface SMM0_0/URT_RX,, SMM0_/URT_TX,, SMM0_/TK, SMM0_/TMS, SMM0_LK, SMM0_M, SMM0_ET, SMM_PWR, R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_, R_0 R_ R_ R_LK R_LKN R_KE R_S0N R_SN R_OT0 R_OT R_RSN R_SN R_WEN R_RST FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_LE/EMM_LKO FLSH_RY/EMM_M S/TF ard Interface Flash Interface US0_P, US0_M, US0_ET US_P US_M US Interface VOUT Interface R_0 R_ R_ R_ R_ R_ R_ R_ R_M0 R_QS0P R_QS0M R_ R_ R_0 R_ R_ R_ R_ R_ R_M R_QSP R_QSM V_R U RK0-G G_R00XR00XR Memory R_Q0 R_0 R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_Q R_ R_ R_M0 R_ R_0 R_QS0 R_ R_QS0N R_ E R_ G R_Q R_ R_Q R_ H R_Q0 F R_Q R_0 G R_Q R_ F R_Q R_ G R_Q R_Q R_S0N H R_SN R_M E R_OT0 E R_QS R_OT R_QSN R_LK R_LKN H G F E E E V_R R_V R_V R_V R_V R_V R_V 0uF.V 00 uf.v 00 R R_RSN R_SN R_WEN R_KE R_RESETN nf XR V nF 00 0V R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_0 R_ R_ R_S0N R_SN R_OT0 R_OT R_LK R_LKN R_RSN R_SN R_WEN R_KE R_RST R_, 00nF 00 0V 00nF 00 0V 00nF 00 0V 0 00nF 00 0V 00nF 00 0V 00nF 00 0V S/IS UI RK0-G G_R00XR00XR IS GPIO_0/IS_MLK_d GPIO_/IS_SLK_d E GPIO_/IS_LRK_RX/PWM0_d GPIO_/IS_LRK_TX_d GPIO_/IS_SI_d GPIO_/IS_SO0_d GPIO_/IS_SO_d GPIO_/IS_SO_d GPIO_/IS_SO_d SMM/IS F GPIO0_/SMM_0/IS_LRK_RX_u G GPIO0_/SMM_/IS_LRK_TX_u G GPIO0_/SMM_/IS_SI_u H GPIO0_/SMM_/IS_SLK_u F GPIO0_/SMM_LKO/IS_MLK_u G GPIO0_0/SMM_M/IS_SO_u V OUT 0 U UE RK0-G RK0-G G_R00XR00XR G_R00XR00XR V udio V_IOUTP T U OE_OL T0 V_IOUTN R OE_OR N V_IREF OE_VM U0 V_V N OE_V U T V_GN N OE_VSS J00 bga_socket IS_MLK_d IS_SLK_d IS_LRK_TX_d IS_LRK_RX_d IS_SI_d IS_SO_d UIO reuse IS_MLK_d IS_SLK_d S ial_switch_ IS_LRK_TX_d sw_rxr0xr0 IS_LRK_RX_d IS_SI_d IS_SO_d IS_MLK IS_SLK IS_LRK_TX IS_LRK_RX IS_SI IS_SO LE_ON, SMM_PWR fastboot SMM_PWR, SIO_0_WIFI SIO WIFI SIO WIFI SIO WIFI SIO_LK_WIFI SIO_M_WIFI pf 00 0G0V pf 00 0G0V V_PLL V_PLL R Y MHz GN XINM TEST RY_R0XR0X0R0 XOUTM R R % R00 lose to PIN K K V_PLL XOUTGN 00nF 00.V uf.v 00 N R00 R00 %.K R RESET,,, XIN 0 uf.v 00 00nF 00 0V R R0 00nF 00 0V RESET TEST 0.0R R00 % 0.0R R00 % U RK0-G G_R00XR00XR NPOR US L NPOR_d M L L 00nF 00.V TEST_d rystal XINM XOUTM US_V PLL Power K K PLL_V US_V PLL_V Efuse J PLL_VIO EFUSE lose to PIN J V_PLL V_US V_US 0 uf.v 00 00nF 00 0V V_EFUSE T US0_P US0_M U US0_I US0_VUS US_EXTR U T US_P US_M T N R K R M V_ V_ US0_P US0_M US0_ET US_P US_M.uF 0V 00.uF 0V 00 OS/US ontrole U R N K R 0R 00nF.V 00 00nF 00 0V % lose to PIN N R 0.0R R00 % 00nF 00 0V R R00 R N/.K % R00 0.0R R00 % V_PLL V_US US0_P, US0_M, US0_ET V_US V_US 00nF.V 00 lose to PIN M uf.v 00 uf.v 00 00nF 00 0V HMI_TX- 0 HMI_TX+ 0 HMI_TX0-0 HMI_TX0+ 0 HMI_TX- 0 HMI_TX+ 0 HMI_TX- 0 HMI_TX+ 0 HMI_E 0 HMI_HP 0 HMI_SL 0 HMI_S 0 HMIOUT Interface URT0_RX, URT0_TX, URT0_TS, URT0_RTS, IS_SO IS_SI IS_SLK IS_LRK_RX IS_MLK SIO WIFI Interface EMTX_0 EMTX_ EM_TXEN EMRX_0 EMRX_ EMRX_ERR EM_SR/VLI EM_LKO EM_MIO EM_M LN_RST EPHY Interface RESET,,, RESET Interface S/PIF Interface IS_LRK_TX, Recover, UH RK0-G G_R00XR00XR SMM0 GPIO_/SMM0_0/URT_RX_u GPIO_/SMM0_/URT_TX_u GPIO_/SMM0_/JTG_TK_u GPIO_/SMM0_/JTG_TMS_u GPIO_0/SMM0_LKO_d GPIO_/SMM0_M_u GPIO_/SMM0_ET_u WIFI J K K K H H J UG RK0-G G_R00XR00XR Nand Flash/eMM/SF GPIO_0/FLSH_0/EMM_0/SF_SIO0_u GPIO_/FLSH_/EMM_/SF_SIO_u GPIO_/FLSH_/EMM_/SF_SIO_u GPIO_/FLSH_/EMM_/SF_SIO_u GPIO_/FLSH_/EMM_/SPI_RX GPIO_/FLSH_/EMM_/SPI_TX_u GPIO_/FLSH_/EMM_/SPI_SN0_u GPIO_/FLSH_/EMM_/SPI_SN_u GPIO_0/FLSH_LE/SPI_LK_d GPIO_/FLSH_LE/EMM_LK_d GPIO_/FLSH_WRN/SF_SN0_u GPIO_/FLSH_RN/SF_SN_u GPIO_/FLSH_RY/EMM_M/SF_LK_u GPIO_/FLSH_S0_u FLSH/EUG U P T R R N P P N N M M L L SMM0_0/URT_RX SMM0_/URT_TX SMM0_/TK SMM0_/TMS SMM0_LK SMM0_M SMM0_ET sw_rxr0xr0 ial_switch_ S SMM0 复复 FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ GPIO_ GPIO_0 GPIO_ GPIO_ SPI_LK_d FLSH_LE/EMM_LKO FLSH_RY/EMM_M SMM0_0/URT_RX,, SMM0_/URT_TX,, SMM0_/TK, SMM0_/TMS, SMM0_LK, SMM0_M, SMM0_ET, VSOK GPIO_ GPIO_0 GPIO_ GPIO_ sw_rxr0xr0 S ial_switch_ PMI_INT_L T_HOST_WKE SPI_RX SPI_TX SPI_SN0 SPI_SN SPI_LK_d SPI_RX SPI_TX SPI_SN0 SPI_SN UF RK0-G G_R00XR00XR M U GPIO_/M_TX0_d T GPIO_/M_TX_d R0 GPIO_/M_RX0_d T GPIO_0/M_RX_d U GPIO_/M_M_d U GPIO_/M_RXER_d R GPIO_/M_LK_IN/M_LK_OUT_d R GPIO_/M_TXEN_d T GPIO_/M_MIO_d U GPIO_/M_RS_d I/PWM U GPIO0_0/PWM/I0_SL_u T GPIO0_/PWM/I0_S_u R GPIO0_/I_SL_u R GPIO0_/I_S_u T GPIO_/I_SL_u U GPIO_/I_S_u SPIF N GPIO0_/SPIF_d N GPIO GPIO d M GPIO_0_u L GPIO d N GPIO d E GPIO0 d E GPIO0_/IR_d T GPIO0_/RIVE_VUS_d URT GPIO0_0/URT0_TX_d GPIO0_/URT0_RX_u GPIO0_/URT0_RTSN_u GPIO0_/URT0_TSN_u P GPIO_/URT_RX_u P GPIO_/URT_TX_d GPIO EMTX_0 EMTX_ EMRX_0 EMRX_ EM_M EMRX_ERR EM_LKO EM_TXEN EM_MIO EM_SR/VLI GPIO0_0/PWM/I0_SL_u GPIO0_/PWM/I0_S_u I0_SL_PMI I0_S_PMI I_SL_UIO I_S_UIO SPIF_d PMI_SLEEP PMI_SLEEP T_WKE T_RST VS WIFI_REG_ON WIFI_HOST_WKE HP_ET URT0_TX URT0_TX, URT0_RX URT0_RX, URT0_RTS URT0_RTS, URT0_TS URT0_TS, LN_RST S sw_rxr0xr0 ial_switch_ RK0_KYLIN reate ate: Thursday, May 0, 0 Recover, URT0_TX_T URT0_RX_T URT0_TX_T URT0_RTS_T URT0_RX_T URT0_TS_T URT0_RTS_T URT0_TS_T.0 Modify ate: Monday, ecember, 0 Page Total:

7 V_R R K R00 % R_0 R_ R_ R_ R_ R_ R_ R_ R_QS0P R_QS0M R_M0 R_ R_ R_0 R_ R_ R_ R_ R_ R_QSP R_QSM R_M R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R K % R00 00nF 00 0V VREF_R nf XR V 00 R_ R_ R_ R_ R_0 R_ R_ R_LK R_LKN R_KE R_S0N R_OT0 R_RSN R_SN R_WEN R_SN R_OT R_RST 00 nf XR V 00 R 0R % R00 R_0 R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_KE R_S0N R_OT0 R_RSN R_SN R_WEN V_R VREF_R R_RST R_ E F F F H H G H K L K J K L G K K N N R R E F H H H M T L J J L L M U Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q KE0 S#0 OT0 RS# S# WE# N 0 P P N P P R R T R 0/P L R N /# T T 0 M N M K J K K# LM E UM V V LQS F G V LQS# V V UQS V UQS# V V V VSSQ VSSQ VQ VSSQ VQ VSSQ E VQ VSSQ E VQ VSSQ F VQ VSSQ G VQ VSSQ G VQ VSSQ VQ VQ VSS VSS E VREFQ VSS G VREF VSS J VSS J RESET# VSS M ZQ0 VSS M VSS P OT VSS P KE VSS0 T S# VSS T ZQ VSS R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_0 R_ R_ R_LK R_LKN R_M0 R_M R_QS0P R_QS0M R_QSP R_QSM R-M V_R 0 uf.v uF.V 00 0 nf XR V uF.V 00 0 uf.v 00 0 nf XR V nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V R RK0_KYLIN.0 reate ate: Modify ate: Tuesday, November 0, 00 Monday, ecember, 0 Page Total:

8 E SMM0_0/URT_RX, SMM0_/URT_TX, SMM0_/TK SMM0_/TMS SMM0_LK SMM0_M SMM0_ET SMM_PWR FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_LE/EMM_LKO FLSH_RY/EMM_M RESET,, FLSH_ FLSH_ 0K rp_00 FLSH_ FLSH_ R R 0K R00 % R 0K R00 %.uf 0V 00 0K rp_00 R FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_LE/EMM_LKOR RESET 00nF 00 0V FLSH_LE/EMM_LKO FLSH_RY/EMM_M R0.uF 0V 00 R % R00 R % R00 R N/0K R00 % 00nF 00 0V 00nF 00 0V FLSH_0 FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_ FLSH_RY/EMM_M emm_lk emm_rst 00nF 00 0V U G G_R00XR00XR0 H H T0 H T J T J T J T J T J T T W W U K R M LK RST_n Vi RLK M M0 VSF N0 VSF U0 VSF VSF emm VQ VQ Y VQ W VQ K VQ U V T0 V N V M V U VSS R0 VSS P VSS M VSS H VSS T VSS VSSQ VSSQ Y VSSQ Y VSSQ K VSSQ SMM0_/TK R R % R00 SMM0_/TMS R0 R % R00 SMM0_M R R % R00 SMM0_LK R V_S R % R00 R SMM0_0/URT_RX R % R00 SMM0_/URT_TX R % R00 SMM0_ET R 0K rp_00 R 0K R rp_00 SMM_PWR S R E E E E E E E0 SMM0_/TK SMM0_/TMS SMM0_M SMM0_LK SMM0_0/URT_RX SMM0_/URT_TX SMM0_ET R 0K R00 % 00nF 00 0V R SOT_ WPM0-/TR Q S ard sd- N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/0R R00 V_S lose to TF ard R.K % R00 J0 T /T M V LK VSS T0 0 T WP VSS G OM G G G G G 0.uF 0V 00 00nF 00 0V lose to S ard E FLSH_LE/EMM_LKO SW E Z-0F ES00 RESET moskrom KEY Flash/TF card RK0_KYLIN.0 reate ate: Modify ate: Thursday, October, 00 Monday, ecember, 0 Page Total:

9 OTG_PWR_V US0_P US0_M US0_ET US_P US_M V.0_SYS 0uF/00/0V 0V 00 ctive high onstant-urrent U 0 IN OUT GN ILIM 0.uF/V/00 EN FULT R0 0V 0K/00/% TPSVR- 00 R00 R 0K % R00 000m 0uF/00/0V 0V 00 0uF/00/0V 0V 00 R 0K/00/% R00 % OTG_PWR_V uf 00 0V 0.uF 00 US0_M R US0_P R00 0K/00/% US0_ET R 0nF K XR R00 V 00 If consider EMI, which requires soldering ommon mode hoke R 0R R00 N/SW0--00 F R 0R R00 US0_M US0_P IO IO J00 US0_mini US-P-MI V M P I GN G G G G G E ESVUL/Z-0S SOT_ OTG_PWR_V US0_US_F_0_00 US-HU_PORT US :V :- :+ :GN IO US_M US_P IO R 0R R00 N/SW0--00 F R0 0R R00 US_M US_P 00 uf 00 0V 00nF 00 0V G E ESVUL/Z-0S SOT_ US HOST RK0_KYLIN.0 reate ate: Modify ate: Tuesday, November, 0 Tuesday, January, 0 Page Total:

10 0 HMI_TX- HMI_TX+ HMI_TX0- HMI_TX0+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX+ HMI_HP HMI_SL HMI_S HMI_E V.0_SYS HMI_TX- HMI_TX- HMI_TX+ U0 N/Z0-0F/ESVU IN 0 OUT HMI_TX- IN OUT HMI_TX+ IN OUT HMI_TX- IN OUT HMI_TX+ HMI_TX+ HMI_TX+ HMI_TX- HMI_TX+ HMI_TX- HMI_TX0+ HMI_TX0- HMIE _SL HMIHP J HMI_ HMI_HMI_0 0 HMI OUT HMI_TX+ HMI_TX- _S GN GN 0.uF 00 V.0_SYS SLP0P R.K % R00 R.K % R00 HMI_SL HMI_S R.K % R00 Q ON0 SOT_ Q ON0 SOT_ R.K % R00 V.0_SYS _SL _S R 0K R00 % HMI_E Q ON0 SOT_ R 0K R00 % NW SO_ HMIE Maximum output voltage logic '' +.v HMI_TX- HMI_TX+ HMI_TX0- HMI_TX0+ _SL E _S E HMIHP E0 V.0_SYS E U N/Z0-0F/ESVU IN IN 0 OUT OUT HMI_TX- HMI_TX+ IN OUT HMI_TX0- IN OUT HMI_TX0+ GN GN SLP0P N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 N/Z-0F ES00 HMI_HP 0pF V 00 HMI-detect R00 R % K HMIHP HMIE E RK0_KYLIN reate ate: Modify ate: N/Z-0F ES00 HMI OUT.0 Monday, July 0, 0 0 Monday, ecember, 0 Page Total:

11 OE V_ V_OE R V 0.0R R00 % V 0.uF 00 R 0.0R R00 %.uf 00 V_ 0.uF 00 IS_MLK IS_SLK IS_SO IS_LRK_TX, IS_LRK_RX IS_SI 0 0.uF 00 0.uF 00 V_ 0.0R R00 %.uf 00 0V R R REF 0.0R R00 % 0.uF 00 0V V V 0.uF 00 N 00 N 00 IS_MLK R IS_SO R IS_SI R IS_SLK R IS_LRK_TX R IS_LRK_RX R MI_INP MIP MIN R R00 IS0_MLK R R00 IS_T R R00 IS_T R R00 IS0_SLK R R00 IS_LRK R R00 PHE_ET MIIS uf 00 uf 00 R0 0K % R00 U L qfn_r00xr00x0r0_t MIP MIP MIN MLK T T LK LRK MIIS GPIO/IRQ J REF GN MIV V PV V 0 V REF V_OE V_ V_ V V GN REF.V ~.V PV.V ~.V MIV.0V ~.V V.V ~.V V.VOUT.V V was generated by internal LO. PP PN PP PN HOP_R 0 HPO_L LOUTL/P LOUTR/N 0 PVPP PVEE PVREF VREF SL S HPO_R HPO_L.uF 00 0V.uF 00 0V.uF 00 0V.uF 00 0V R K R00.uF 00 0V R K R00 I_SL_UIO I_S_UIO HP_ET I_S_UIO I_SL_UIO MI MI MI MI-00 R0 K R00 R0 0uF 00 00pF 00 00R R00 MIIS MIP MIN ERPHONE R0 00K R00 HP_ET MI_INP HPO_R HPO_L R0 0.uF 00 K R00 MIIS R0 R0 PHE_ET 0.uF uF 00 R0 E ESN ES00 0.uF 00 K R00 R L00 R L00 E ESN ES00 E ESN ES00 E ESN ES00 PJ_R0_PJ PJ- J R0 K R00 00pF 00 E N/ESN ES00 00pF 00 E N/ESN ES00 R R R00 R R R00 udio odec-l (option) RK0_KYLIN V. reate ate: Modify ate: Thursday, October, 0 Wednesday, ecember, 0 Page Total:

12 EMTX_0 EMTX_ EM_TXEN EMRX_0 EMRX_ EMRX_ERR EM_SR/VLI EM_LKO EM_MIO EM_M LN_RST EMTX_0 EMTX_ EM_TXEN EMRX_0 EMRX_ EMRX_ERR EM_SR/VLI EM_MIO EM_M R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % R 0R R00 % RMII_TX_0 RMII_TX_ RMII_TXEN RMII_RX_0 RMII_RX_ RMII_RX_ERR RMII_SR/VLI RMII_MIO RMII_M R N/.K % R00 N/.K % R00 R V_RMII RMII REF_LK direction RMII_LK_TL Pull Low for RMII REF_LK Output mode Pull High for RMII REF_LK Input mode(default) MII/RMII Selection RMII_RXV N/.K % R00 R R.K % R00 R.K % R00 V_RMII V_RMII PHY ddress/le R R00 YE- 0R % R.K % R00 V_RMII R0.K % R00 R R00 GR+ 0R % YE+ LE/PHY LE0/PHY0 GR- N/00pF 00 N/00pF 00 EM_LKO R RMII_LK Pull High for RMII mode(default) 0R R00 % N/0pF 00 0G 0V UTP / Fiber Selection WOL/LE0 Selection LN_RST R PHY_RST RMII_RX_ERR R.K % R00 0R R00 % N/0pF 00 0G 0V Pull Low for UTP Mode(default) Pull High for Fiber Mode RMII_RX_ R.K % R00 Pull Low for LE0 Mode(default) Pull High for WOL Mode WOL:Wake-on-LN V_RMII R R K R00 K R00 RMII_TX_ RMII_TXEN PHY_RST RMII_M RMII_MIO LE0/PHY0 RMII_LK R N R00 U RMII_TX_0 V_RMII TX0 TX V RX TX TX 0 TX TXEN PHYRST M MIO LE0/PHY0/PME 0 RX/INT RX/LK_TL RX RX0 LE/PHY RS/RS_V OL RXER/FXEN V0OUT V_ KXTL-OUT KXTL-IN RMII_LK_TL RMII_INT R RMII_RX_ RMII_RX_0 E-Pad K R00 V_RMII RMII_RXV V_RMII RXN RXP TXN TXP 0.uF 00 lose to PIN R.K% R00 lose to PIN N 00 0 N 00 N 00 TXP TXN RXP RXN N 00 nf 00 U HR00 SOI 0 R R % R00 TX+ TX- RX+ RX- R R % R00 R R % R00 R R % R00 TN TN RN RN RJS 0/KV 0 XR KV YLE- YLE+ GLE- GLE+ RXV V_ MI- MI+ MI0- MI0+ V00UT RSET JP TX+ TX- RX+ RX- N N GN GN 0 YE- YE+ GR- GR+ 00nF 00 0V 00nF 00 0V RTL0F qfn_r00xr00xr00_t 0 RMII_SR/VLI RMII_RX_ERR LE/PHY KXTLOUT KXTLIN 0.uF 00 lose to PIN V_RMII R N/0R R00 N/pF 00 Y N/M-0ppm XOUTGN GN XIN RY- N/pF 00 R 0.0R R00 % V_RMII R0 0.0R R00 %.uf 0V 00 V_RMII 0 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V RTL0F KXTLIN R 0R R00 RMII_LK Ethernet RK0_KYLIN.0 reate ate: Modify ate: Friday, ugust, 0 Monday, ecember, 0 Page Total:

13 SIO_0_WIFI SIO WIFI SIO WIFI SIO WIFI SIO_M_WIFI SIO_LK_WIFI URT0_TX_T URT0_RX_T URT0_RTS_T URT0_TS_T SIO_0_WIFI SIO WIFI SIO WIFI SIO WIFI SIO_LK_WIFI SIO_M_WIFI T_WKE WIFI_REG_ON T_RST WIFI_HOST_WKE T_HOST_WKE 0K rp_00 R 0K R rp_00 SIO_0_WIFI SIO WIFI SIO WIFI SIO WIFI SIO_M_WIFI SIO_LK_WIFI R R % R R % R R % R R % R R % R R % R00 R00 R00 R00 R00 R00 pf0g0v pf0g0v 00 Note: djusted the load capacitance according to the crystal specification. WIFI_0 WIFI_ WIFI_ WIFI_ WIFI_M WIFI_LK WIFI_REG_ON WIFI_HOST_WKE WIFI_ WIFI_ WIFI_M WIFI_LK WIFI_0 WIFI_ 0 Ohm RF trace VT_WL R 00R % R00 XTL_IN pf Y XOUTGN GN XIN XTL_OUT MHz RY_R0XR0X0R0 L 0 0R-00M.uF L00.V 00 VIO_WL 0 00nF.V 00 L.uH INX 0 0.uF.V 00 U0 XTL_OUT XTL_IN 0 VT T_VIO/N_HOST_WKE WL_REG_ON WL_HOST_WKE SIO_T_ SIO_T_ SIO_T_M SIO_T_LK SIO_T_0 SIO_T_ GN VIN_LO_OUT VIO WIFIT_KIN T_HOST_WKE T_WKE T_WKE T_HOST_WKE NT N_WKE FM_RX GN WL_T_NT GN VIN_LO LPO PM_OUT PM_LK PM_IN PM_SYN V_TXO TXO_IN GN GPS_RF GN 0 pf 00 0pF 00 0G 0V 00 N_VSWP_IN N_VSWP_OUT N_VSWPIO URT_TS_N URT_RX URT_TX URT_RTS_N 0 TX TX N_REG_PU N_I_SL GN N_I_S T_RST_N P 默默默默默默 RTL, 具具默默具具具具具如如默 PXXX 模模 L0 默默默 0pF 具具默默具具具具具 URT0_RTS_T URT0_TX_T URT0_RX_T URT0_TS_T T_RST Note: RTL 时 PIN 是 WIFI S 功功. PIN 是是是是. GN NT R R00 0R % GN NT NT ant_jack small_wifi RFNT0 J00 NT GN RT_LKOUT RT_LKOUT WIFIT_KIN R 00K % R00 R 0K % R00 L 0R-00M L00 VT_WL 0 uf 0V nF.V 00 峰峰峰峰峰 00m WIFI+T-P RK0_KYLIN.0 reate ate: Modify ate: Wednesday, November, 0 Monday, ecember, 0 Page Total:

14 SMM0_0/URT_RX, SMM0_/URT_TX, SMM0_0/URT_RX SMM0_/URT_TX V_ US+V US+V 0 00nF 00 00V 00nF 00 0V R 0R R00 % R 0R R00 % R R N/0.0R R00 % N/0.0R R00 % R R 0K N/0.0R R00 % EE-LK EE-T V_URT 0 00 pf 0G 0V GNXOUT U 0 MHz TX OS RY_R0XR0X0R0 TR-N OS 00 pf 0G 0V LE RTS-N PLL-TEST US+V RE R0 V- GN-PLL.K% RX N R N R00 RI-N L-MOE R0 N 00nF GN TRI-STTE 00 US+V N GN 0 0 SR-N V-V R N V_URT 0V J -N N TS-N GN 00nF 0V 00 SHT-N V-V EE-LK M US0_mini RR00 00nF 00nF US-P-MI 0V 00 EE-T P.K 00 FTRL % R R00 0V TS_M R % TS_M V V_ TS_P R % TS_P M R R00 P N/0.0R R I R00 % GN N/0.0R R00 % R Y XIN GN IO G IO E ESVUL/Z-0S SOT_ G G G G ebug RK0_KYLIN.0 reate ate: Modify ate: Tuesday, May 0, 0 Monday, ecember, 0 Page Total:

15 V.0_SYS SPI_RX SPI_TX SPI_SN0 SPI_SN GPIO0_0/PWM/I0_SL_u GPIO0_/PWM/I0_S_u SPI_LK_d GPIO0_0/PWM/I0_SL_u GPIO0_/PWM/I0_S_u SPI_RX SPI_TX SPI_SN0 SPI_SN SPI_LK_d N *0PIN header V.0_SYS 00nF 00 0V 00nF 00 0V GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ SPIF_d E0 E E E Z-0F Z-0F Z-0F Z-0F ES00 ES00 ES00 ES00 E E E E E E E0 Z-0F Z-0F Z-0F Z-0F Z-0F Z-0F Z-0F ES00 ES00 ES00 ES00 ES00 ES00 ES00 E E E E Z-0F Z-0F Z-0F Z-0F ES00 ES00 ES00 ES00 E Z-0F ES00 V.0_SYS IS_MLK_d IS_SLK_d IS_LRK_TX_d IS_LRK_RX_d IS_SI_d IS_SO_d IS_MLK_d IS_SLK_d IS_LRK_TX_d IS_LRK_RX_d IS_SI_d IS_SO_d N V.0_SYS 00nF 00 0V VOUT VOUT VOUT VOUT VOUT 00nF 00 0V URT0_TX URT0_RX URT0_RTS URT0_TS VOUT VOUT VOUT VOUT VOUT.-.V/0M 0.-.V/00M.-.V/0M.-.V/00M.-.V/0M VOUT VOUT VOUT 00nF 00 0V 00nF 00 0V 00nF 00 0V VOUT 00nF 00 0V *0PIN header URT0_TX URT0_RX URT0_RTS URT0_TS E Z-0F ES00 E E E E E Z-0F Z-0F Z-0F Z-0F Z-0F ES00 ES00 ES00 ES00 ES00 E E E Z-0F Z-0F Z-0F ES00 ES00 ES00 E0 E Z-0F Z-0F ES00 ES00 E E E Z-0F Z-0F Z-0F ES00 ES00 ES00 RK0_KYLIN.0 reate ate: Modify ate: Wednesday, October, 0 Monday, ecember, 0 Page Total:

px3se_main_ddr3_v01_

px3se_main_ddr3_v01_ ONTENT INEXING 0. INEX 0. hange List 0. lock iagram 0. Power Tree-RK 0. RK Power 06.RK R ontroler 0.RK Flash/S ontroler 0.RK MIS&US 0.RKISPLY/GM ontroler 0.RK MER/HMI ontroler.rk OE/V.RK GPIO.RM-R.Nand