rockpro64_v

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1 ROKPro_V. ONTENT INEXING 0.Index 0.hange List 0.lock iagram 0.Power Tree 0.I Map 0.Power omain Map 0.IR Receiver 0.RK Power.RK PMU ontroler.rk R ontroler.rk Flash&SMM ontroler.rk US/USI ontroler.rk SR/Key.RK VP Interface.RK isplay Interface.RK GPIO.RK PIE 0.Power- IN.Power-PMI RK0-.US OTG/HOST Port.US Type- Port.US HU.RM-R xbit(option).rm-lpr(p) 0.Memory-eMM 0.WIFI-US(option).WIFI/T-Pxxx(option).WIFI/TMIMO-P.RJ-000M-RTLE.RJ-00M-PN(option).RJ-000M-ZX00(option).MI rray.tf ard.igital Video Output.igital Video Input.SPIF Output.PIe NGFF/M..PIe x (option) 0.FN(option).eFUSE(option) Note: :If the Value or option of the component properties is NP,indicating do not mounted Note Option escription J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P J SHIEL_P SHIEL-P PINE RockPro_RK Size ocument Number Rev Index V.0 ate: Tuesday, MR, 0 Sheet of

2 lock iagram PINE RockPro_RK Size ocument Number Rev lock iagram V.0 ate: Tuesday, MR, 0 Sheet of

3 RK POWER IGRM SY0 Switch V/,0mR 0.u shutdown VUS_TYPE VV0_TYPE0_EN VUS US.0 Type-0 port PMI RK0 UK,0.-.V T u shutdown V_ENTER V of SO center S0/OFF/OFF 00m/T/T VV0_US.V SY0 Switch V/,0mR 0.u shutdown SY0 Switch V/,0mR 0.u shutdown SY0 Switch V/,0mR 0.u shutdown VV0_HOST0 VV0_HOST_EN VV0_HOST VV0_HOST_EN VV0_HOST VV0_HOST_EN VUS US.0 port VUS US.0 port VUS US.0 port PMI RK0 UK,0.-.V T u shutdown PMI RK0 UK.,.0-.V T u shutdown PMI RK0 UK,.-.V T u shutdown PMI RK0 LO 0m,.-.V T u shutdown V_PU_L V_R V_V VV_EMM VV_WIFI VV_IO VV_R V of Quard- V of R TRL V/V of R VQ of R S0/OFF/OFF 0m/T/T S0/S/OFF S0/S/OFF 0m/.m/T S0/S/OFF V of EMM RTL,VQ of EMM FLSH IOS0/S/OFF m/<m/t VIO of WIFI+T module S0/S/OFF 0.m/.m/T S0/S/OFF 0m/0.m/T VIO/VPST of GPIO V of LPR S0/S/OFF.m/0u/T u dapter V VV_IN 0m/m/T SY UK,PWM,<u shutdown SY UK,PWM,<u shutdown EN always ON EN always ON FUS0 TYPE VONN 00m/u VV0_US.V 0m/m/T PMI RK0 LO 0m,.-.V T u shutdown PMI RK0 LO 00m,0.-.V T u shutdown VV_V V_V V of V/MIPI TX phy S0/OFF/OFF.m/T/T VV_PMUIO VIO/VPST of PMUIO S0/S/OFF m/u/t VV_PMUPLL V of PMU PLL S0/S/OFF.m/.0m/T VV_PLL V of PLL S0/S/OFF m/0.u/t VV_US V of US phy S0/S/OFF 0.m/.m/T VV_ V of SR S0/S/OFF.m/<m/T VV_PIE V of PIE phy S0/S/OFF m/<m/t VV0_SYS.0V PMI RK0 LO 0m,.-.V T u shutdown V_SIO VIO of SMM0 S0/OFF/OFF.m/T/T WPM0 P-MOSFET.,0mR@.V WS VV0_FN FN_TL_H VV0_V V of Speaker MP V of V evice S0/OFF/OFF V_T.V V_RT V of PMI RT S0/S/S.m/T/0u PMI RK0 LO 00m,.-.V T u shutdown PMI RK0 LO 0m,0.-.V T u shutdown V_V VPST of PIO/PIO S0/OFF/OFF.m/T/T SY0 UK,PWM,<u shutdown PMI_EXT_EN PMI RK0 LO 00m,0.-.V T u shutdown V0V_V V of V/MIPI TX phy S0/OFF/OFF 0.m/T/T VV_SYS RT0-0 LO.0V/00m <u shutdown TT0 J LO 0.V/00m <u shutdown VV0_S SMM0_PWR_H V_0V VV_SYS V0V_PLL V0V_PMUPLL V0V_RPLL V0V_EMM V0V_US V0V_PIE S/TF ard V of PLL V of PMU PLL V of R TRL V of EMM TRL ORE LL V of US phy V of PIE phy S0/OFF/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF T/T/T.m/0u/T.m/0u/T.m/u/T.m/<m/T 0.m/.m/T.m/T/T PMI RK0 LO 00m,.-.V T u shutdown PMI RK0 VSW,00mohm T u shutdown PMI RK0 VSW,00mohm T u shutdown V_V0 VV_S0 V of PIO/PIO/PMUIO S0/OFF/OFF.m/T/T RT0- LO.V/00m <u shutdown V_EFUSE EFUSE_VQPS_EN_H V of EFUSE User/OFF/OFF.m/T/T SYRPK Switch V/,0mR 0.u shutdown V_PU_ V_V V of ual- S0/OFF/OFF 0m/T/T VV_ VV_US VV_EMM VV_WL VV_WLIN VV_LN VV_MI VV_SPIF VV_PIE VV_IR VV_VIN VV_LE VV_HU V of FUS0 V of US phy ORE V of EMM FLSH V of WIFI module VT of WIFI+T module V/V of ethernet phy V of MI rray V of SPIF river I V of PIE evice V of IR Receiver V of PIE evice Work LE V of US HU S0/S/OFF S0/S/OFF S0/S/OFF S0/OFF/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/OFF/OFF S0/S/OFF S0/OFF/OFF S0/S/OFF S0/S/OFF.m/<0.m/T.m/0.m/T 00m/0.m/T m/.m/t 0.m/.m/T T/T/T.m/.m/T.m/.m/T T/0.m/T SYRPK Switch V/,0mR 0.u shutdown SY0 UK,PWM,<u shutdown V_GPU V_V V_LOG V_V V of Mali-T V of SO Logic S0/OFF/OFF 0m/T/T S0/S/OFF 0m/.m/T PINE RockPro_RK Size ocument Number Rev Power Tree V.0 Tuesday, MR, 0 ate: Sheet of

4 RK Power omain Map Part Port omain Pin name in datasheet I/O type Power supply Power source Part PMUIO pmuio_gpio0ab.v only VV_PMU RK0 VLO Part E PMUIO pmu0_gpioabcd.v(efault).0v VV_PMU RK0 VLO Part I PIO gmac_gpioabc.v only VV_IO VV_IO RK0 uck RK0 VSW Part L PIO bt_gpioab.v(efault).0v VV_VP RK0 VLO Part G PIO wifi/bt_gpiocd.v only VV_WIFI RK0 uck Part K PIO gpio0_gpiocd.v.0v(efault) V_V VV0_IO RK0 VLO RK0 VLO Part J PIO audio_gpiod_gpioa.v(efault).0v VV_OE RK0 VLO Part F SMM0 sdmmc_gpiob.v.0v(efault) V_SIO RK0 VLO PINE RockPro_RK Size ocument Number Rev Power omain Map V.0 ate: Tuesday, MR, 0 Sheet of

5 I MP Port Pin name omain us name Pull-up voltage Slave evice Slave ddr (MS its) Note Slave us apability Rockchip RK0 0xb PMI 00kHz,00KHz I0 GPIO_/SPI_RX/I0_S GPIO_0/SPI_TX/I0_SL PMUIO I_S_PMI I_SL_PMI V_V SYRPK 0x0 - UK 00kHz,00KHz,.MHz SYRPK 0x - UK 00kHz,00KHz,.MHz I GPIO_/I_S GPIO_/I_SL PIO I_S_VIEO I_SL_VIEO V_V TXG V Transmit I GPIO_0/VOP_0/IF_0/I_S GPIO_/VOP_/IF_/I_SL PIO RESERVE I GPIO_0/I_S/URT_RX GPIO_/I_SL/URT_TX PIO I_S_V I_SL_V V_V0 I GPIO_/I_S GPIO_/I_SL PMUIO I_S_MEMS I_SL_MEMS V_V Fairchild FUS0 0x,0x US-Type Mux 00kHz,00KHz,MHz I GPIO_/M_RXER/I_S PIO Other pin function GPIO_/M_LK/I_SL I GPIO_/SPI_RX/IF_HREF/I_S GPIO_/SPI_TX/IF_LKIN/I_SL PIO RESERVE I GPIO_/VOP_/IF_/I_S GPIO_0/VOP_LK/IF_VSYN/I_SL PIO RESERVE PINE RockPro_RK Size ocument Number Rev I Map V.0 ate: Tuesday, MR, 0 Sheet of

6 IR Receiver VV_SYS HETSINK/FN (option) IR_INT V_V R.K R00 % IN SO R 00R R00 % VV_IR IR_RX.uF 0V 00 00nF V 00 IRM_ IR IR G V FN_TL_H VV_IN R R00.R % R R00 K % 0 IN SO Q0 S00 SOT_ J ON.MM--SMT ON_0MM--SMT SPIF OUT SPIF_TX VV_SYS R R % R00 R 0R % R00 pf 00 0G 0V 0uF 00.V SPIF_OUT VV_SPIF 00nF 00 V J0 LT0 ON_0MM--SMT LE rive I 预留复位, 开机键扩展连接座 XH_.mm/N ON PINE ate: Tuesday, MR, 0 Sheet of RESET_L PMI_PWRON RockPro_RK Size ocument Number Rev ustom IR SPIF V.0 J Radiator/N heat-sink-mm

7 I> I> I> I>. I> lose to SO lose to SO lose to SO lose to SO lose to SO Note:Power filter P please place back of SO or close to SO PINE Tuesday, MR, 0 V_GPU V_PU_L V_LOG V_PU_L V_PU_ V_GPU V_LOG V_PU_ V_ENTER V_ENTER V_GPU_F V_PU F Size ocument Number Rev ate: Sheet of Rk Power V.0 RockPro_RK Size ocument Number Rev ate: Sheet of Rk Power V.0 RockPro_RK Size ocument Number Rev ate: Sheet of Rk Power V.0 RockPro_RK 00nF 00 0V 00nF 00 0V 00nF 00 0V nf 00 V 00nF 00 0V 0 0uF 00 V 00nF 00 0V 00nF 00 0V uf 00 _V uf 00 _V 00nF 00 0V uf 00 0V 0 0uF 00 V 00nF 00 0V nf 00 V 00nF 00 0V uf 00 0V uf 00 _V uf 00 _V 0 nf 00 V uf 00 0V uf 00 _V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 0 uf 00 _V 00nF 00 0V uf 00 _V 00nF 00 0V 0uF 00 V 0uF 00 V 00nF 00 0V uf 00 _V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 0uF 00 V 00nF 00 0V 0uF 00 V 00nF 00 0V UW RK IGPU_V_ M IGPU_V_ M IGPU_V_ L IGPU_V_ N IGPU_V_0 N0 IGPU_V_ L IGPU_V_OM N LITPU_V_ P0 LITPU_V_ R LITPU_V_ R0 LITPU_V_ P LITPU_V_ T LITPU_V_ T0 LITPU_V_ R ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ N ENTERLOGI_V_ N ENTERLOGI_V_ P ENTERLOGI_V_ P ENTERLOGI_V_0 P GPU_V_ W GPU_V_ W GPU_V_ W GPU_V_ V GPU_V_ V GPU_V_ V GPU_V_ U GPU_V_ R GPU_V_ R GPU_V_0 T GPU_V_ T GPU_V_ T GPU_V_ R GPU_V_ T GPU_V_ V GPU_V_ V GPU_V_ V GPU_V_ W GPU_V_ W GPU_V_0 W0 GPU_V_OM T IGPU_V_ L IGPU_V_ L IGPU_V_ M IGPU_V_ M IGPU_V_ M0 LOGI_V_ V LOGI_V_ V LOGI_V_ V0 LOGI_V_ V LOGI_V_ V LOGI_V_ W0 LOGI_V_ U LOGI_V_ U LOGI_V_ M LOGI_V_0 L LOGI_V_ T LOGI_V_ U0 IGPU_V_ K IGPU_V_ K UX RK VSS_ Y VSS_ F VSS_ F VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ VSS_ F VSS_ F VSS_ G VSS_0 H VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ W VSS_ J VSS_ U VSS_0 V VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ F VSS_ Y VSS_ VSS_0 F0 VSS_ VSS_ VSS_ 0 VSS_ E VSS_ Y0 VSS_ VSS_ VSS_ VSS_ 0 VSS_0 F VSS_ G VSS_ J VSS_ L VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ VSS_ VSS_ 0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_ E VSS_0 E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ E VSS_ F VSS_ F VSS_0 F VSS_ F0 VSS_ F VSS_ G VSS_ G VSS_ G VSS_ G VSS_ H VSS_ H VSS_ H0 VSS_0 H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ H VSS_ J VSS_ J VSS_0 J VSS_ J VSS_ J VSS_ J0 VSS_ K VSS_ K VSS_ K0 VSS_ K VSS_ K VSS_ K VSS_0 K VSS_ W VSS_ K0 VSS_ N VSS_ K VSS_ L VSS_ L VSS_ L VSS_ L VSS_ L VSS_0 L VSS_ L VSS_ L VSS_ L VSS_ N VSS_ Y VSS_ L0 VSS_ L VSS_ N VSS_ L VSS_00 M VSS_0 M VSS_0 M0 VSS_0 M VSS_0 M VSS_0 N VSS_0 P VSS_0 P VSS_0 N VSS_0 N VSS_0 N VSS_ N VSS_ P VSS_ P VSS_ P VSS_ P VSS_ P0 VSS_ P VSS_ Y VSS_ P VSS_0 R VSS_ P VSS_ T VSS_ R VSS_ R VSS_ R VSS_ U VSS_ U VSS_ W VSS_ R VSS_0 R VSS_ R VSS_ VSS_ R VSS_ T VSS_ T0 VSS_ Y VSS_ U VSS_ T VSS_ T VSS_0 VSS_ U VSS_ U VSS_ U VSS_ U VSS_ VSS_ U VSS_ U VSS_ V VSS_ U VSS_0 U VSS_ V VSS_ V VSS_ V VSS_ V0 VSS_ Y VSS_ Y VSS_ Y VSS_ W VSS_ W VSS_0 W0 VSS_ W VSS_ W VSS_ VSS_ Y VSS_ R VSS_ Y VSS_ W VSS_ T VSS_ VSS_ VSS_ VSS_ 0 VSS_ VSS_ J VSS_0 Y0 VSS_ W VSS_ J VSS_ J VSS_ J VSS_ J VSS_ J VSS_ L VSS_0 J0 0 uf 00 0V 0uF 00 V uf 00 _V

8 Y MHz RY_R0XR0X0R0 00nF 00 0V RESET_L pf 00 0G 0V XIN GN GNXOUT pf 00 0G 0V V_0V V_V TP VV_EFUSE R0 R R00 % Note:RK part is.v Only U RK NP 00 T0 U R 0R R00 % npor_u GPIO0_0/TEST_LKOUT0/LKK_IN_u RT_LKO_SO R GPIO0_/RIO_PWROFF/TP EN_u SMM0_PWR_H N IY_LE GPIO0_/WIFI_MHz_d V WIFI_HOST_WKE_L Y GPIO0_/SIO0_WRPT_d XIN_OS GPIO0_/SIO0_INTn_d T_HOST_WKE_L V GPIO0_/EMM_PWRON_u PWR_KEY_L P IR_INT R GPIO0_/PWM_IR_d V SMM0_ET_L M GPIO0_/SMM0_ET_u R00 U GPIO0_0/SMM0_WRPT/TEST_LKOUT_u HP_ET_H % V0 T_REG_ON_H Y0 GPIO0_/PMUIO_VOLSEL_d W XOUT_OS GPIO0 d WIFI_REG_ON_H U0 WORK_LE GPIO0 d V R 0R % GPIO0_/TP_VUS_IS_d VP_PN P GPIO0_/TP_VUS_FIS/TP_VUS_SOURE_d WIFI_PWR Y VSS_ R P P PLL_V_0V PLL_V_V PLL_VSS EFUSE_VQPS PMUIO_V_V PMU_V_0V PMU_V_V R T U V_V V_0V V_V Note: GPIO0_/PMUIO_VOLSEL defined as a set pin for PMUIO part voltage domain after power-on reset.it is pull-down for.v or pull-up for.0v,and later changed to output mode by software R0 mounted for PMUIO domain.0v mode ristal selection requirements:.nominal Frequency is MHz;.Frequency tolerance is +/-0ppm;.Operating Temperature range is -0~0 ;.Equivalent resistance < 0ohm; LE VV_SYS VV_SYS T_REG_ON_H R 0K % R00 R0 N % R00 V_V R0 mounted for PMUIO domain.v mode LE0 LE_White LE00 LE0 LE_Red LE00 V_0V V_V VV_EFUSE WORK_LE R0 0K R00 % R0 0K R00 % R0 0K R00 % SOT_ 00 Q IY_LE R0 0K R00 % R0 0K R00 % R0 0K R00 % SOT_ 00 Q 00nF 00 0V 00nF 00 0V uf 00 0V 0 00nF 00 0V 00nF 00 0V PINE ate: Tuesday, MR, 0 Sheet of 00nF 00 0V R 00R R00 % RockPro_RK Note: R0 must always be mounted Size ocument Number Rev RK PMU ontroler V.0

9 R FILTER R FILTER Note:R0 cannot be deleted Note:R0 cannot be deleted PINE Tuesday, MR, 0 V_R V_R V_R V_R V_0V V_R_LK V_0V V_R0_LK V_R V_R_LK V_R V_R0_LK V_0V V_0V R0_RST R_ R_ R_ R_ R_ R_ R_0 R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_M0 R_M R_M R_M R_QSM R_QSP R_QSM R_QSP R_QSM R_QSP R_QS0M R_QS0P R_LKP R_LKN R_0 R_ R_ R_ R_ R_ R_LK0P R_LK0N R_KE0 R_KE R_S0N R_SN R_SN R_SN R_RST R0_QSM R0_QSP R0_QSM R0_QSP R0_QSM R0_QSP R0_QS0M R0_QS0P R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_M0 R0_M R0_M R0_M R0_LKP R0_LKN R0_0 R0_ R0_ R0_ R0_ R0_ R0_LK0P R0_LK0N R0_S0N R0_SN R0_KE0 R0_KE R0_SN R0_SN Size ocument Number Rev ate: Sheet of RK R ontroler V.0 RockPro_RK Size ocument Number Rev ate: Sheet of RK R ontroler V.0 RockPro_RK Size ocument Number Rev ate: Sheet of RK R ontroler V.0 RockPro_RK 0uF 00 V 00nF 00 0V 00nF 00 0V 00nF 00 0V R 0R R00 % 00nF 00 0V TP 00nF 00 0V R 0R R00 % 0 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V 0 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V TP0 uf 00 _V uf 00 _V R 0R R00 % 00nF 00 0V uf 00 0V 0uF 00 V uf 00 0V 00nF 00 0V 00nF 00 0V TP R 0R R00 % TP U RK R_Sn R_0 R_ R_ R_ R_ R_0 0 R_Q 0 R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_0 R_ R_ R_ R_Sn0 F R_ R_ 0 R_Q R_Q R_Q 0 R_Q R_Q0 R_Q R_Q R_Q R_Q R_ R_ R_M E0 R_M0 E R_M E R_M E R_ R_LK0N R_LK0P R_QSN 0 R_QSP R_ R_ R_Sn F R_ R_ G R_RSn R_WEn F R_LK_V G R_RESET G R_PZQ G RPLL_V_0V H R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_QS0N R_QS0P R_QSN R_QSP R_QSN R_QSP R_KE0 R_KE E R_OT E R_OT0 R_LKP E R_LKN E R_Sn F R_Sn R_T0 F R_T G R_PLL_TESTOUT_N G R_PLL_TESTOUT_P F R_V_ J R_V_ J R_V_ J R_V_ J R_V_ J R_V_ J R_V_ J R_V_ J R_V_ K R_V_0 K R_V_ K R_V_ K 00nF 00 0V U RK R0_Q0 R0_Q R0_Q R0_Q R0_Q Y R0_Q Y R0_Q W R0_Q W R0_Q F R0_Q E R0_Q0 F R0_Q R0_Q E R0_Q R0_Q R0_Q R0_Q V R0_Q V R0_Q U R0_Q U R0_Q0 T R0_Q T R0_Q R R0_Q R R0_Q P R0_Q P R0_Q N R0_Q M R0_Q N R0_Q L R0_Q0 M R0_Q L R0_LK0P H R0_LK0N J R0_QS0P Y R0_QS0N R0_QSP R0_QSN R0_QSP U R0_QSN V R0_QSP P R0_QSN R R0_Sn0 M R0_Sn R0_KE0 E R0_KE F R0_0 R0_ F R0_ M R0_M0 Y R0_M R0_M U R0_M P R0_Sn H R0_RSn F R0_0 F R0_ F R0_ G R0_ G R0_ H R0_ H R0_ J R0_ J R0_ K R0_ K R0_0 R0_ E R0_ R0_ R0_ R0_ H R0_RESET L R0_WEn G R0_PZQ R R0PLL_V_0V R R0_LK_V M R0_OT0 L R0_OT L R0_T0 U R0_T U R0_LKP H R0_LKN J R0_Sn M R0_Sn R0_PLL_TESTOUT_N V R0_PLL_TESTOUT_P V R0_V_ L R0_V_ L0 R0_V_ M R0_V_ N R0_V_ N0 R0_V_ P R0_V_ R R0_V_ R0 R0_V_ T R0_V_0 U R0_V_ U0 R0_V_ V

10 UH RK EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ EMM_LK EMM_M EMM_STR EMM_LIO EMM_TP EMM_ORELL_0V EMM_V_V J J J0 J J J L K0 L J K L L0 L K EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ R R % R00 EMM_LKO EMM_M EMM_STR R 0K % R00 V_0V V_V EMM design rule:.ata[0:] cmd strobe 走线做为一组, 并行走线并整组包地, 组内等长要求为 +/-00mil;.lk 需要单独走线并包地处理, 与 data 间的延时小于 0ps;.Max trace length <. inchs;.trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ;.R00 靠近 SO 放置 ; V_0V 00nF 00 0V V_V 00nF 00 0V EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ EMM_ EMM_LKO EMM_M EMM_STR UF RK SMM0_0 SMM0_ SMM0_ SMM0_ SMM0_M SMM0_LK GPIO_0/SMM0_0/URT_RX_u GPIO_/SMM0_/URT_TX_u GPIO_/SMM0_/PJTG_TK_u GPIO_/SMM0_/PJTG_TMS_u GPIO_/SMM0_LKOUT/MUJTG_TK_d GPIO_/SMM0_M/MUJTG_TMS_u Y Y Y U V V SMM0_0 SMM0_ SMM0_ SMM0_ SMM0_LK SMM0_M SMM0_VPST SMM0_VPST SMM0_V U T 00 00nF 00 0V 内部产生电压 V_SIO 00nF 00 0V SMM design rule:.ata[0:] cmd 走线做为一组, 并行走线并整组包地, 组内等长要求为 +/-00mil;.lk 需要单独走线并包地处理, 与 data 间的延时小于 0ps;;.Max trace length <. inchs;.trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; PINE RockPro_RK Size ocument Number Rev RK FLSH&SMM V.0 ate: Tuesday, MR, 0 Sheet 0 of

11 IN&SYSTEM Power J -0-0 VV_IN uF/V MTM- SVPF V R000 NP R00 To avoid the noise issue 00 0uF/V 00 V 00 00nF/V 00 V.V<VIN<V R00 0K R00 % U000 TS SOT-.V/ VV0_SYS VIN LX L000 GN S nF/V.uH V IN_X R00 00pF/0V uf/v 0uF/0V. 0.0ohm K EN F/OUT R00 0G SY % 0V 0V 0V 00 00nF 00 V R00 NP R00 XH_.mm 000 ESW-/TR SO_ R00 0K R00 % ON VV_IN VV_IN To avoid the noise issue 00 0uF/V 00 V 00 00nF/V 00 V.V<VIN<V R00 0K R00 % U00 TS SOT- VIN GN EN SY F/OUT LX S 00 00nF/V 00 V L00.uH IN_X. 0.0ohm R00 K R00 % R00 0K R00 %.V/ pF/0V uf/v G 0V 0V VV0_US 0 0uF/0V 00 0V 0 00nF 00 V R00 NP R00 LE0 LE_GREEN LE00 电源指示灯 ( 绿色 ) 00nF/N 0V 00 NP R.K % R00 VV0_SYS PINE RockPro_RK Size ocument Number Rev RK US/USI ontroler V.0 ate: Tuesday, MR, 0 Sheet of

12 UU RK USI_STROE USI_T J0 J USI_V_0V USI_V_V US.0 US.0 U RK US RK UT RK HOST0_P HOST0_M TYPE0_P TYPE0_M TYPE0_I TYPE0_UVUSET US0_RIS US.0 PHY0 HOST_P HOST_M TYPE_P TYPE_M TYPE_I TYPE_UVUSET US_RIS US.0 PHY US_V_0V US_V_V US_V_V 0 G H L0 K0 0 G H E K 0 V U Y V_0V V_V VV_S HOST0_P HOST0_M TYPE0_P TYPE0_M TYPE0_I TP TYPE0_UVUSET R R R00 % HOST_P HOST_M US_P US_M TYPE_UVUSET R R R00 % US.0 PHY0 TYPE0_TXP L TYPE0_TXM K TYPE0_RXP K TYPE0_RXM L TYPE0_TXP L TYPE0_TXM K TYPE0_RXP K TYPE0_RXM L TYPE0_RLKP E TYPE0_RLKM H TYPE0_ H0 TYPE0_ TYPE0_UXP K0 TYPE0_UXM L0 TYPE0_UXP_P_PU H TYPE0_UXM_PU_P G TYPE0_UVUSET TYPE0_REXT G TYPE0_REXT_ G0 Y TYPE0_V_0V_ Y TYPE0_V_0V_ TYPE0_V_V TYPE0_V_V V_0V V_V VV_S TYPE0_TXP TYPE0_TXN TYPE0_RXP TYPE0_RXN US.0 PHY TYPE_TXP L TYPE_TXM K TYPE_RXP K TYPE_RXM L V_0V V_V VV_S US_SSTXP US_SSTXN US_SSRXP US_SSRXN TYPE0_TXP TYPE_TXP L TYPE0_TXN TYPE_TXM K TYPE0_RXP TYPE_RXP K TYPE0_RXN TYPE_RXM L TYPE_RLKP E0 TYPE_RLKM 0 H TYPE_ F TYPE_ TYPE0_SU TYPE_UXP K TYPE0_SU TYPE_UXM L TYPE0_SU_ TYPE_UXP_P_PU E TYPE0_SU_ TYPE_UXM_PU_P F TYPE_UVUSET R0 R00 % R R/N R00 % TYPE_REXT E R R R00 % NP TYPE_REXT_ G Y TYPE_V_0V_ Y TYPE_V_0V_ TYPE_V_V TYPE_V_V V_0V 0 00nF 00 0V V_V 0 00nF 00 0V VV_S 0 00nF 00 0V V_0V 0 00nF 00 0V V_V 0 00nF 00 0V VV_S 0 00nF 00 0V P design rule:.max intra-pair skew < ps;.max trace length < inchs;.max allowed via < ;.Trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; US.0 design rule:.max intra-pair skew < ps;.max trace length < inchs;.max allowed via < ;.Trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; US.0 design rule:.max intra-pair skew < ps;.max length skew between TX and RX <. ns;.max trace length < inchs;.max allowed via < ;.Trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; PINE RockPro_RK Size ocument Number Rev RK US/USI ontroler V.0 ate: Tuesday, MR, 0 Sheet of

13 E UV RK _IN0 _IN _IN _IN _IN G H G G H KEY_IN HP_HOOK RM_I HP_HOOK RM_I R 00K% R00 R 0K % R nF 00 0V V_V E _V V_V V_V 0 00nF 00 0V R/RL LPR RM I R0 PU R0 P 0.V 00K 00K 0.V 0K 0K LPR.V 00K K 调试升级按键 Note: 系统上电时, 如果 KEY_IN 电平为 0V, 则 RK 进入 Recovery 模式 ; KEY_IN 0 nf 00 XR 0V R 0K % R00 V_V SW00 R 0R R00 % TS-0 ts-0s PINE RockPro_RK Size ocument Number Rev RK SR/KEY V.0 ate: Tuesday, MR, 0 Sheet of

14 UL RK GPIO_0/VOP_0/IF_0/I_S_u GPIO_/VOP_/IF_/I_SL_u GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF_/I_S_u GPIO_0/VOP_LK/IF_VSYN/I_SL_u GPIO_/SPI_RX/IF_HREF/I_S_u GPIO_/SPI_TX/IF_LKIN/I_SL_u GPIO_/SPI_LK/VOP_EN/IF_LKOUT_u GPIO_/SPI_Sn0_u G H H0 F H F H G0 H F0 H H F IF_LK_O IF_0 IF_ IF_ IF_ IF_ IF_ IF_ IF_ IF_VSYN IF_HREF IF_LKI VP_PN0_H IF_LK_O R 0R R00 IF_LKO % R 0R R00 MIPI_MLK0 % MIPI_MLK0 IF_LKO PIO_VPST PIO_V J K 0 00nF 00 0V VV_VP VV_VP UR RK UP RK MIPI_RX0_0P MIPI_RX0_0N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_LKP MIPI_RX0_LKN MIPI_RX0_P MIPI_RX0_N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_REXT K L K L K L K L K L F MIPI_RX0_0P MIPI_RX0_0N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_LKP MIPI_RX0_LKN MIPI_RX0_P MIPI_RX0_N MIPI_RX0_P MIPI_RX0_N R.0K R00 % MIPI_TX/RX_0P MIPI_TX/RX_0N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_LKP MIPI_TX/RX_LKN MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_REXT K L K L K L K L K0 L0 F MIPI_RX_0P MIPI_RX_0N MIPI_RX_P MIPI_RX_N MIPI_RX_LKP MIPI_RX_LKN MIPI_RX_P MIPI_RX_N MIPI_RX_P MIPI_RX_N R0.0K R00 % MIPI_RX0_V_V VV_VP 00nF 00 0V MIPI_TX/RX_V_V 0 VV_VP 00nF 00 0V PINE RockPro_RK Size ocument Number Rev RK VP Interface V.0 ate: Tuesday, MR, 0 Sheet of

15 UN RK V_TX0P V_TX0N V_TXP V_TXN V_TXP V_TXN V_TP V_TN V_HP V_REXT V_V_0V_ V_V_0V_ V_V_V K L K L K L K L E F V_HP VV_VP V_TX0P V_TX0N V_TXP V_TXN V_TXP V_TXN V_TXP V_TXN R K R00 R.K R00 % igital Video design rule:.max intra-pair skew < ps;.max length skew between clk and data < 0 ps;.max trace length <. inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%;. 与其他信号间距遵循 W 原则 ; 00nF 00 0V 00nF 00 0V % PORT_HP V_0V UM RK EP_TX0P EP_TX0N EP_TXP EP_TXN EP_TXP EP_TXN EP_TXP EP_TXN EP_UXP EP_UXN EP TP EP_LKM_IN EP_REXT EP_V_0V EP_V_V_ EP_V_V_ EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ G0 H G H0 J J0 H J EPTX0P EPTX0N EPTXP EPTXN Placed close to the transmitter side EPUXP EPUXN TP TP R.0K R00 % 00nF 00 0V VV_VP 00nF 00 0V 00nF 00 0V 00nF 00 0V 00nF 00 0V V_0V EP_TX0P EP_TX0N EP_TXP EP_TXN UQ RK MIPI_TX0_0P MIPI_TX0_0N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_REXT MIPI_TX0_V_V G H G H G H G H G H F MIPI_TX0_P MIPI_TX0_N R.0K R00 % VV_VP 00nF 00 0V MIPI_TX0_0P MIPI_TX0_0N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N ep design rule:.max intra-pair skew < ps;.max trace length < inchs;.max allowed via < ;.Trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; MIPI design rule:.max intra-pair skew < ps;.max length skew between clk and data < ps;.max trace length <. inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%;. 与其他信号间距遵循 W 原则 ; PINE RockPro_RK Size ocument Number Rev RK isplay Interface V.0 ate: Tuesday, MR, 0 Sheet of

16 UI Note:RK part I is.v only RK UE Note:RK part E is.v/.0v mode RK GPIO_0/M_TX/SPI_RX_d GPIO_/M_TX/SPI_TX_d GPIO_/M_RX/SPI_LK_u GPIO_/M_RX/SPI_Sn0_u GPIO_/M_TX0/SPI0_RX_d GPIO_/M_TX/SPI0_TX_d GPIO_/M_RX0/SPI0_LK_u GPIO_/M_RX/SPI0_Sn0_u F H E0 E G E F M_TX M_TX M_TX0 M_TX % R R R00 % R R R00 % R R R00 % R R R00 PHY_TX PHY_TX M_RX M_RX PHY_TX0 PHY_TX M_RX0 M_RX GPIO_0/ISP0_SHUTTER_EN/ISP_SHUTTER_EN/TP_VUS_SINK_EN_d GPIO_/ISP0_SHUTTER_TRIG/ISP_SHUTTER_TRIG/TP_0_VONN_EN_d GPIO_/ISP0_FLSHTRIGIN/ISP_FLSHTRIGIN/TP VONN_EN_d GPIO_/ISP0_FLSHTRIGOUT/ISP_FLSHTRIGOUT_d GPIO_/ISP0_PRELIGHT_TRIG/ISP_PRELIGHT_TRIG_d GPIO_/P_PWROFF_d GPIO_/TS_INT_z GPIO_/SPI_RX/URT_RX_u R T R R R R0 P P L_EN PU_GPIO_ TYPE0 INT_L VV0_TYPE0_EN PU_GPIO_ PMI_SLEEP_H OTP_OUT_H SPI_RX_M GPIO_0/M_M/SPI0_Sn_u GPIO_/M_RXV_d GPIO_/M_RXER/I_S_u GPIO_/M_LK/I_SL_u GPIO_/M_TXEN/URT_RX_u GPIO_/M_MIO/URT_TX_u GPIO_/M_RXLK/URT_RX_u GPIO_/M_RS/IF_LKOUT/URT_TX_u E F G H G F M_TXEN % R R R00 % R0 R R00 M_M M_RXV PMI_INT_L Note:PMU 终断 GPIO_ 更改至此 M_LK PHY_TXEN M_MIO M_RXLK NP PHY_RST 00 GPIO_0/SPI_TX/URT_TX_u GPIO_/SPI_LK/PMU_JTG_TK_u GPIO_/SPI_Sn0/PMU_JTG_TMS_u GPIO_/I_S_u GPIO_/I_SL_u GPIO d GPIO_/PWM_IR_d GPIO_/SPI_RX/I0_S_u R P P P P0 M M M SPI_TX_M SPI_LK_M SPI_SN0_M I_S I_SL PU_GPIO_ GPU_SLEEP_H I0_S_PMI GPIO_0/M_OL/URT_TSn/SPIF_TX_u GPIO_/M_TXLK/URT_RTSn_u PIO_VPST PIO_V E J J M_TXLK % R R R00 V_V VIO_PHY SPIF_TX PHY_TXLK GPIO_0/SPI_TX/I0_SL_u GPIO_/SPI_LK_d GPIO_/SPI_Sn0_u GPIO_/PWM_d GPIO_/I_S_u GPIO_/I_SL_u GPIO_/TP_VUS_SOURE0_d GPIO_/TP_VUS_SOURE_d N0 M N M M M0 L M I0_SL_PMI PU SLEEP_H PU_GPIO_ LOG_VS_PWM I_S I_SL PU_GPIO_ VP_PWR GPIO_0/TP_VUS_SOURE_d L PIE_PWR VIO_PHY V_V FTJTG_TMS_u FTJTG_TRSTn_d PMUIO_VPST N V_V 0 00nF 00 0V 00nF 00 0V.V Only VPST=VIO=.V PMUIO_V P R0 0K V_V0 I0_S_PMI I0_SL_PMI I_S % R.K R00 % R.K R00 % R.K R00 V_V0 V_V0.V Only VPST=.V,VIO=.V V_V V_V0 I_SL I_S % R.K R00 % R 0R R00 I_S_TYPE UG Note:RK part G is.v only RK other.0v mode:vpst=.v,vio=.0v.v mode:vpst=.v,vio=.v 00nF 00 0V 00nF 00 0V I_SL I_S I_SL % R 0R R00 % R 0R R00 % R 0R R00 I_SL_TYPE I_S_TP I_SL_TP GPIO_0/URT0_RX_u GPIO_/URT0_TX_u GPIO_/URT0_TSn_u GPIO_/URT0_RTSn_u GPIO_/SIO0_0/SPI_RX_u GPIO_/SIO0_/SPI_TX_u GPIO_/SIO0_/SPI_LK_u GPIO_/SIO0_/SPI_Sn0_u GPIO_0/SIO0_M_u GPIO_/SIO0_LKOUT/TEST_LKOUT_u GPIO_/SIO0_ETN/PIE_LKREQn_u GPIO_/SIO0_PWREN_d GPIO_/SIO0_KPWR_d PIO_V_V SIO design rule: E URT0_RX H.ata[0:] cmd 走线做为一组, URT0_TX G 并行走线并整组包地, 组内等长要求为 +/-00mil; URT0_TS L URT0_RTS.lk 需要单独走线并包地处理, 与 data 间的 SIO0_0 延时小于 0ps;; K SIO0_ G.Max trace length <. inchs; SIO0_ E SIO0_.Trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; H SIO0_M F SIO0_LK L PIE_LKREQ_L T_WKE_L F R 0R % R00 PIE_PERST_L VIO_WL VIO_WL 00nF 00 0V PI-US SPI_LK SPI_SN0 SPI_TX SPI_RX R % R R % R R % R R % R SPI_LK_M SPI_SN0_M SPI_TX_M SPI_RX_M SPI FLSH M R0 R R 0K 0K 0K SPI_SN0_M SPI_RX_M U /S O /WP GN V /HOL LK IO GQSIG 0.uF SPI_LK_M SPI_TX_M V_V0 R R R 0K 0K 0K UK Note:RK part J is.v/.0v mode RK UJ Note:RK part J is.v/.0v mode RK G GPIO_0/IS0_SLK_d IS0_SLK_PM F GPIO_/IS0_LRK_RX_d IS0_LRK_RX_PM J GPIO_/IS0_LRK_TX_d IS0_LRK_TX_PM Y GPIO_/IS0_SI0_d IS0_SI0_PM E GPIO_/IS0_SISO_d IS0_SO_PM GPIO_/IS0_SISO_d IS0_SO_PM H GPIO_/IS0_SISO_d IS0_SO_PM H GPIO_/IS0_SO0_d IS0_SO0_PM GPIO_0/IS_LK_d IS_LK G GPIO_/I_S_u I_S Y GPIO_/I_SL_u I_SL F GPIO_/IS_SLK_d IS_SLK GPIO_/IS_LRK_RX_d IS_LRK_RX J GPIO_/IS_LRK_TX_d IS_LRK_TX GPIO_/IS_SI0_d IS_SI0 GPIO_/IS_SO0_d IS_SO0 PIO_VPST V_V PIO_V Y V_V0 I_SL V_V0 V_MIPI R0.K R00 R0 K/N R00 Q00 SK0/N SOT R R R00 V_IO V_MIPI I_SL_M 0 GPIO_0/I_S/URT_RX_u GPIO_/I_SL/URT_TX_u GPIO_/PWM0/VOP0_PWM/VOP_PWM_d GPIO_/URT_RX_u GPIO_/URT_TX_u GPIO_/SPIF_TX_d GPIO_/PWM_d GPIO_/V_EINOUT/EP_HOTPLUG_u GPIO_0/PIE_LKREQn_u GPIO_/P_HOTPLUG_d GPIO d GPIO d GPIO d GPIO d GPIO d PIO_VPST PIO_V G L F K J K L E K H K H J G I_S_V I_SL_V L_L_PWM URTG_RX URTG_TX PU_GPIO_ TP FN_TL_H V_E TP PU_GPLK PU_GPIO_ VV0_HOST_EN PU_GPIO_ PU_GPIO_ TOUH_INT TOUH_RST V_V V_V0 V_V V_V0 V_V0 00nF 00 0V R.K R00 R0 K/N R00 I_S I_S_M 0 Q0 SK0/N SOT R R R00 00nF 00 0V 00nF 00 0V PINE RockPro_RK Size ocument Number Rev ustom RK GPIO V.0 ate: Tuesday, MR, 0 Sheet of

17 UO RK PIE_TX0_P PIE_TX0_N PIE_RX0_P PIE_RX0_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_RLK_00M_P PIE_RLK_00M_N E0 E F0 F G0 G H0 H F F 0 PIE_TX0P PIE_TX0N PIE_RX0_P PIE_RX0_N PIE_TXP PIE_TXN PIE_RX_P PIE_RX_N PIE_TXP PIE_TXN PIE_RX_P PIE_RX_N PIE_TXP PIE_TXN PIE_RX_P PIE_RX_N PIE_REF_LK_P PIE_REF_LK_N PIE design rule:.max intra-pair skew < ps;.max inter-pair skew <. ns;.max trace length < inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%;. 与其他信号间距遵循 W 原则 ; PIE_V_0V PIE_V_V W Y V_0V V_V V_0V V_V 00nF 00 0V 0 00nF 00 0V PINE RockPro_RK Size ocument Number Rev RK PIE V.0 ate: Tuesday, MR, 0 Sheet of

18 PMI I>. I> E ESN ES00 Option ** 支架 0GF 不锈钢弹片 Use power button for boot/shutdown,sleep and wakeup, it can be delete if no need; V_LOG power VV0_SYS LOG_VS_PWM V_LOG: Min=0.V; efault=0.v; Max=.V; V_ENTER 0uF 00 _V L uh IN_X uf uf..mohm R 0 00R V_ENTER 0V 0V R00 % VV0_SYS V_PU_L uf 00 0V L uh..mohm uf uf IN_X R 00R V_PU_L 0V 0V R00 % V_RT PWR_KEY_L V_V0 0uF 00 R K 0V R00 % VV0_SYS VV0_SYS uf 00 0V VV0_SYS uf 00 0V VV0_SYS VV0_SYS uf 00 0V uf 00 0V uf 00 0V uf 00 0V VV_SYS 0 uf 00 0V VV_SYS uf V V_V0 uf 00 0V 0 I0_S_PMI I0_SL_PMI PMI_SLEEP_H PMI_INT_L V_V R 0K R00 % RESET_L 0 00nF 00 V 0 00nF 00 V % R0 0K R00 R K R00 % R00 0K R00 % 00nF 00 V VPP_OTP PMI_PWRON WS SO_ U SY0/TS0 SOT VIN LX GN EN F/OUT R0 0K R00 % 0 0 V V uck SW Max SW 0.V-.V GN GN VF V V SW SW GN GN VF Note: The PWM parameter needs to be modified according R0 00K to the LOG_VS_PWM R00 power supply,please refer % to RK design guide VV0_SYS L.uH V_V VV_R IN_X. 0.0ohm R 0R % R00 uf 00 uf VV0_SYS 00 0V I>. 0V V_R V_R L.uH 0 R 0R % R00 R:.V IN_X pf RL:.V. 0.0ohm 00 R LPR:.V 0G 0V 00R 0uF uf efault:lpr R R0 R % _V 0V R0 R0 00K K V_R R 00K 00K R00 R00 Feedback from R device RL K 0K % % LPR K 00K 00nF 00 V RT hoose one of the following options: VV_VP N GN N REF VREF GN LO&Switch VREFGN.-.V/0m 00nF V VLO VV0_TOUH 00 V Option.-.V/0m.uF V VLO V_V 00 0V an keep system time after shutdown; 0.-.V/00m.uF VLO low noise VLO VV_OE 00 0V U 0.-.V/00m 0.uF R0-V V low noise VLO V_SIO 00 0V.-.V/0m.uF GN VLO VV0_OE 00 0V T V_RT.-.V/00m 00nF SOT_ V VLO V_V 00 V % V_TTERY 0.-.V/0m.uF R 0.R R00 V0 low noise VLO V_V0 00 0V VV0_SYS.-.V/00m.uF V VLO VV_S 00 0V 0.R Switch 00nF 00 V VSWOUT VV_S0 VV0_SYS 00 V V 0.R Switch.uF WS/N VSWOUT V_RT 00 0V SO_ uf VIO VRT 00 0V Option GN OSKIN 0 pf 00 0G 0V an't keep system time after shutdown; GNP Y.KHz S 0 pf R_M SL OSKOUT 00 0G 0V SLEEP RT_LKO_SO R 0K % R00 VV0_SYS INT always on LKKOUT V_V RT_LKO_WIFI R 0K % R00 VS LKKOUT V_V VS V_RT 0 VSOK OOT0 uf NRESPWRON OOT EXT_EN 00 ResetKey/VPPOTP EXT_EN PMI_V R K % R00 0V PWRON V SW KEY_X T- nf 00 V uck Max 0.V-.V Top U RK0- QFN_R00XR00X0R0_T L.uH IN_X. 0.0ohm R K R00 % R 00K R00 % RT R 00R R00 % V_LOG 00pF 00 0G 0V uck. Max.V-.V uck Max.0V-.V uf _V 00 V SW GN VF V SW VF 0 V_LOG 00nF 00 V 0 nf 00 XR 0V V_0V power VV_SYS R uf K 00 R00 0V % U TT0 SOT IN F/OUT GN SHN P TT0_J R 0K R00 % ZTV0 SO_ NP R M R00 % uto-boot when plug in, can be shutdown both by power button or power-off pf 00 0G 0V R 0K R00 % R K R00 % - +.uf 00 0V V_0V 00nF 00 V Over-temperature Protection 复位电路修改 V_PU_ power V_V R 0K % R00 0.mS PU SLEEP_H 00 00nF 00 V V_GPU power V_V R 0K % R00 0.mS GPU_SLEEP_H 00nF 00 V VV_SYS power VV0_SYS 0uF 0V 00 OTP_OUT_H EXT_EN VV0_S power VV0_SYS VV0_SYS VV_SYS.uF 00 0V 0uF 0V 00 I0_S_PMI I0_SL_PMI 0 0uF 0V 00 I0_S_PMI I0_SL_PMI E E 0K/N % R R00 NP R0 0K% R00 00 WS SO_ E E R 0K/N R00 %.uf 00 0V U TS WLSP-0 VIN_ SW_ VIN_ SW_ VIN_ SW_ VIN_ SW_ VOUT EN GN VSEL GN S GN SL GN GN GN GN SYRPK U TS WLSP-0 VIN_ SW_ VIN_ SW_ VIN_ SW_ VIN_ SW_ VOUT EN GN VSEL GN S GN SL GN GN GN GN SYRPK 00nF 00 V SMM0_PWR_H V_RT SW0 VPP_OTP KEY_X T- Q0 WPM-/TR SOT_ R0 00K% R00 R 00R R0 K R00 % Q00 S00 SOT_ % R00 V_PU F V_GPU_F L0.uH U0 IN_X TS0/SY0/PT0. 0.0ohm SOT VIN LX GN EN F/OUT R 0R % R00 U TS-E0/N SOT IN OUT % R0 0K R00 GN EN E E E E P R 00R L 0.uH IN_ ohm L 0.uH IN_ ohm % R nF/N 00 V VV0_S.uF 00 0V 00pF 0G 0V 00 R0 K R00 % uf _V 00 uf 00 _V uf _V 00 uf 00 _V R 0K R00 % uf/n _V 00 uf 00 _V RT_LKO_SO RT_LKO_WIFI I0_SL_PMI I0_S_PMI PMI_SLEEP_H PWR_KEY_L RESET_L PMI_PWRON V_PU_ V_GPU uf 00 _V VV_SYS 0 0uF _V 00 uf _V 00 00nF 00 V V_V0 PINE RockPro_RK Size ocument Number Rev ustom PMI RK0- V.0 Tuesday, MR, 0 ate: Sheet of

19 VV0_US VV0_HOST_EN R 00K R00 % U SY0/TS0 SOT IN VOUT EN GN O VV0_HOST0 R.K R00 % 0uF 00 0V VV0_HOST0 00nF 00 V uf 00 0V HOST0_M HOST0_P E ESN ES00 R0 0R R00 0R-00M/N F RP_00 R0 0R R00 US.0 port VV0_US VV0_HOST_EN U SY0/TS0 SOT IN VOUT EN GN O VV0_HOST R.K R00 % 0uF 00 0V VV0_HOST 00nF 00 V uf 00 0V HOST_M HOST_P E ESN ES00 R0 0R R00 F 0R-00M/N RP_00 U ES0F SOT_ R0 0R R00 U ES0F SOT_ US US_F_U US_F_U PINE ate: Tuesday, MR, 0 Sheet of VUS M P GN VUS M P GN0 SHELL SHELL SHELL SHELL 0 RockPro_RK VV0_HOST_EN HOST0_P HOST0_M HOST_P HOST_M Size ocument Number Rev ustom US HOST.0 V.0

20 US Type- port I_SL_TYPE I_S_TYPE TYPE0 INT_L TYPE0_SU TYPE0_SU TYPE0_SU_ TYPE0_SU_ 00nF 00 0V 00nF 00 0V R 00K% R00 00K% R R00 TYPE0_M TYPE0_P TYPE_UXP TYPE_UXM R M R00 % R0 M R00 % VUS_TYPE TYPE_ TYPE_ % R.R R00 F 0R-00M/NNP RP_00 % R.R R00 US US_TYPE_H0 US_TYPE_H0 VUS_ VUS_ VUS_ VUS_ SU SU M P M P TYPE0_M TYPE0_P VV0_TYPE0_EN TYPE0_UVUSET TYPE0_SU TYPE0_SU TYPE0_SU_ TYPE0_SU_ VUS_TYPE % R 0K R00 R K R00 % TYPE0_UVUSET 00nF 00 V TYPE0_TXN TYPE0_TXP TYPE0_RXN TYPE0_RXP TYPE0_TXN TYPE0_TXP TYPE0_RXN TYPE0_RXP 0 00nF 00 0V TYPE0TXN 00nF 00 0V TYPE0TXP 00nF 00 0V 00nF 00 0V TYPE0TXN TYPE0TXP 0 0 SSTX_N SSTX_P SSRX_N SSRX_P SSTX_N SSTX_P SSRX_N SSRX_P GN GN GN GN HOLE_ HOLE_ GN_E GN_E GN_E GN_E GN_E GN_E GN_E GN_E H H E E E E E E E E TRL U FUS0MPX MLP_R0XR0X0R0 Limit switch TYPE_ TYPE_ 0pF 00 0G 0V 0pF 00 0G 0V 0 _0 _ N N GN ep VUS VONN_ VONN_ V SL S INT# VUS_TYPE VV0_US VV_SYS I_SL_TYPE I_S_TYPE TYPE0 INT_L VV0_US 0 uf 0V 00 00nF 00 V VV0_US 0uF 0V 00 uf 00 0V U SY0 SOT IN VOUT GN VV0_TYPE0_EN EN O R.K R00 %.uf 00 V VUS_TYPE 0uF 00 0V ES TYPE0TXN IN OUT 0 TYPE0TXN TYPE0TXN IN OUT 0 TYPE0TXN TYPE0_M TYPE0_P TYPE_ TYPE_ TYPE_UXP TYPE_UXM TYPE0TXP TYPE0_RXP TYPE0_RXN IN OUT IN IN GN GN OUT OUT TYPE0TXP TYPE0_RXP TYPE0_RXN U TPE0U0 SON0_R0XR00X0R0 TYPE0TXP TYPE0_RXP TYPE0_RXN IN OUT IN IN GN GN OUT OUT TYPE0TXP TYPE0_RXP TYPE0_RXN U0 TPE0U0 SON0_R0XR00X0R0 U U ES0F ES0F SOT_ SOT_ U ES0F SOT_ US.0 port VV0_US VV0_HOST_EN US_SSRXN US_SSRXP U SY0/TS0 VV0_HOST SOT IN VOUT GN EN O U TPE0U0 SON0_R0XR00X0R0 0 IN OUT IN OUT R.K % R00 US_SSRXN US_SSRXP 0uF 00 0V R0 0R R00 F0R-00M/N US_M RP_00 VV0_HOST US_P R0 0R R00 US_SSRXN US_SSRXP US_SSTXN 00nF 00 0V US_SSTXP 00nF 00 0V U ES0F SOT_ 0uF 00 0V E ESN ES00 US F_IP VUS - + GN RX- RX+ GN TX- TX+ 0 SHELL SHELL SHELL SHELL US0_F_IP US VV0_HOST_EN TYPE_UVUSET US_P US_M US_SSTXP US_SSTXN US_SSRXP US_SSRXN US_SSTXP US_SSTXN IN IN GN GN OUT OUT US_SSTXP US_SSTXN PINE RockPro_RK Size ocument Number Rev ustom US.0 V.0 Tuesday, MR, 0 ate: Sheet of 0

21 00 LX 00 LX 00 LX 00 LX 00 LX PINE Tuesday, MR, 0 R_OT0 R_OT0 R0_OT0 R0_OT0 V_R V_R VV_R VV_R V_R V_R VV_R V_R V_R V_R V_R V_R V_R VV_R V_R V_R V_R R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_QS0P R0_QS0M R0_QSP R0_QSM R0_M0 R0_M R0_LK0P R0_LK0N R0_KE0 R0_KE R0_0 R0_ R0_ R0_ R0_ R0_ R0_S0N R0_SN R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_M R0_QSP R0_QSM R0_QSP R0_QSM R0_M R0_KE0 R0_KE R0_RST R_ R_ R_0 R_ R_ R_ R_LK0P R_LK0N R_S0N R_SN R_KE0 R_KE R_QSM R_QSP R_QSM R_QSP R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_0 R_ R_ R_ R_KE0 R_KE R_M R_M R_0 R_ R_ R_ R_ R_ R_ R_ R_QS0M R_QS0P R_M0 R_0 R_ R_ R_ R_ R_ R_ R_ R_QSM R_QSP R_M R_RST R0_LKP R0_LKN R0_SN R0_SN R_LKP R_LKN R_SN R_SN Size ocument Number Rev ate: Sheet of RM-LPR V.0 RockPro_RK Size ocument Number Rev ate: Sheet of RM-LPR V.0 RockPro_RK Size ocument Number Rev ate: Sheet of RM-LPR V.0 RockPro_RK 0 00nF 00 V 00nF 00 V 00nF 00 V R0 0K/N R00 % NP H H U LPR_bitX_00p G00_R00X0R00X0R0 _a H ZQ_a Q_a Q_a E MI_a 0 QS_c_a E0 Q0_a E Q_a _a H0 _a J ZQ0_a Q_a Q_a F QS_t_a 0 Q_a F Q_a _a H K_c_a J K_t_a J KE0_a J KE_a J S0_a H S_a H _a J 0_a H OT a G Q_a Q_a Q_a E Q_a F MI0_a QS0_c_a E Q_a F QS0_t_a Q_a E Q_a Q0_a Q0_b Q_b Y Q_b V Q_b U QS0_t_b W QS0_c_b V MI0_b Y Q_b V Q_b U Q_b Y Q_b 0_b R OT b T _b P S_b R KE_b P S0_b R KE0_b P K_t_b P _b R K_c_b P _b R0 _ P Q_b Y MI_b Y0 QS_t_b W0 Q_b U Q_b Y _b R Q_b Q_b V Q_b U QS_c_b V0 Q0_b V Q_b RESET_n T uf 00 V R0 0R R00 % 00nF 00 V 00nF 00 V 00nF 00 V 00nF 00 V 00nF 00 V R0 0R R00 % 00nF 00 V R0 0R R00 % 0 0uF 00.V 0 00nF 00 V 00nF 00 V 00nF 00 V 0 00nF 00 V 0 00nF 00 V 00nF 00 V 0 uf 00.V R0 0R R00 % 00nF 00 V 00nF 00 V 0uF 00.V 00 uf 00.V H H U LPR_bitX_00p G00_R00X0R00X0R0 _a H ZQ_a Q_a Q_a E MI_a 0 QS_c_a E0 Q0_a E Q_a _a H0 _a J ZQ0_a Q_a Q_a F QS_t_a 0 Q_a F Q_a _a H K_c_a J K_t_a J KE0_a J KE_a J S0_a H S_a H _a J 0_a H OT a G Q_a Q_a Q_a E Q_a F MI0_a QS0_c_a E Q_a F QS0_t_a Q_a E Q_a Q0_a Q0_b Q_b Y Q_b V Q_b U QS0_t_b W QS0_c_b V MI0_b Y Q_b V Q_b U Q_b Y Q_b 0_b R OT b T _b P S_b R KE_b P S0_b R KE0_b P K_t_b P _b R K_c_b P _b R0 _ P Q_b Y MI_b Y0 QS_t_b W0 Q_b U Q_b Y _b R Q_b Q_b V Q_b U QS_c_b V0 Q0_b V Q_b RESET_n T 0 00nF 00 V 00nF 00 V 00nF 00 V U LPR_bitX_00p G00_R00X0R00X0R0 VSS_ V_ F VQ_ VQ_ V_ V_ VQ_ VQ_ 0 VSS_ 0 V_ F VQ_ VQ_ V_ F V_ F VQ_ VQ_ V_ G VSS_ V_ H VSS_ J V_0 K VSS_ J0 VQ_ F VSS_ K VQ_ U VSS_ K VQ_ W VSS_ N V_ G V_ K VSS_ N VQ_ W VSS_ P VQ_ VSS_ T VQ_ VSS_ T V_ N VSS_ T0 V_ N VSS_ V V_ R VSS_ V VSS_ V VSS_ V VSS_ W VSS_ W VSS_ W VSS_0 W V_ R VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ 0 V_0 R VSS_ V_ H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ E V_ H VSS_ E VSS_ E VSS_ E VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G0 V_ H VSS_0 G V_ K VSS_ J V_ K0 VSS_ J VQ_0 F0 VSS_ K VQ_ U0 VSS_ K VQ_ W VSS_0 N V_ N VSS_ N VQ_ W VSS_ P VQ_ VSS_ T VQ_0 0 NU_ NU_ VSS_0 T V_ N0 VSS_ T V_ R V_ U V_ U V_ V_ NU_ NU_ NU_ NU_ V_ U V_ U V_ T V_ T NU_ K NU_ K NU_0 N NU_ N NU_ NU_ NU_ NU_ NU_ NU_ NU_ G VSS_ P0 VSS_ P 0uF 00.V 00nF 00 V U LPR_bitX_00p G00_R00X0R00X0R0 VSS_ V_ F VQ_ VQ_ V_ V_ VQ_ VQ_ 0 VSS_ 0 V_ F VQ_ VQ_ V_ F V_ F VQ_ VQ_ V_ G VSS_ V_ H VSS_ J V_0 K VSS_ J0 VQ_ F VSS_ K VQ_ U VSS_ K VQ_ W VSS_ N V_ G V_ K VSS_ N VQ_ W VSS_ P VQ_ VSS_ T VQ_ VSS_ T V_ N VSS_ T0 V_ N VSS_ V V_ R VSS_ V VSS_ V VSS_ V VSS_ W VSS_ W VSS_ W VSS_0 W V_ R VSS_ Y VSS_ Y VSS_ Y VSS_ Y VSS_ VSS_ VSS_ VSS_ 0 V_0 R VSS_ V_ H VSS_ VSS_ VSS_ VSS_ VSS_ VSS_0 VSS_ E V_ H VSS_ E VSS_ E VSS_ E VSS_ G VSS_ G VSS_ G VSS_ G VSS_ G0 V_ H VSS_0 G V_ K VSS_ J V_ K0 VSS_ J VQ_0 F0 VSS_ K VQ_ U0 VSS_ K VQ_ W VSS_0 N V_ N VSS_ N VQ_ W VSS_ P VQ_ VSS_ T VQ_0 0 NU_ NU_ VSS_0 T V_ N0 VSS_ T V_ R V_ U V_ U V_ V_ NU_ NU_ NU_ NU_ V_ U V_ U V_ T V_ T NU_ K NU_ K NU_0 N NU_ N NU_ NU_ NU_ NU_ NU_ NU_ NU_ G VSS_ P0 VSS_ P 00nF 00 V 0 00nF 00 V 00nF 00 V 0 00nF 00 V R0 0K R00 % 0 00nF 00 V R0 0K/N R00 % NP 0 uf 00 V 0 uf 00 V uf 00 V 0uF 00.V 00nF 00 V 00nF 00 V 0 00nF 00 V 00nF 00 V 00nF 00 V R00 0K R00 % 00nF 00 V 00nF 00 V 00nF 00 V

22 emm Port U ON G0-P-H0 EMM_ EMM_ EMM_0 EMM_LKO EMM_ EMM_STR EMM_ EMM_ EMM_ EMM_ EMM_M VV_S V_V VV_S V_V TP SW ON/OFF_KEY IE_H_P Note: Reserve P for Update. EMM_LKO TP.uF 00 0V 00nF 00 V.uF 00 0V 00nF 00 V PINE RockPro_RK Size ocument Number Rev emm OM V.0 ate: Tuesday, MR, 0 Sheet of

23 SIO WIFI/T MOULE-MIMO WL_SIO_LK WL_SIO_M WIFI_REG_ON_H WIFI_HOST_WKE_L VIO_WL U0 ON IP 0_X 0 U ON IP 0_X 0 WL_SIO_0 WL_SIO_ WL_SIO_ WL_SIO_ RT_LKO_WIFI VIO_WL SIO0_0 SIO0_ SIO0_ SIO0_ SIO0_M SIO0_LK URT0_RTS URT0_TX URT0_RX URT0_TS T_HOST_WKE_L T_WKE_L T_REG_ON_H WIFI_REG_ON_H WIFI_HOST_WKE_L RT_LKO_WIFI WIFI_PWR T_WKE_L T_REG_ON_H 0 0 URT0_RX URT0_TX URT0_TS URT0_RTS T_HOST_WKE_L V_WL Note:VT 电压范围.0V~.V, 供电电流至少 00m VV_SYS V_WL NP NP NP NP NP NP WL_SIO_0 R R % R00 WL_SIO_ R R % R00 WL_SIO_ R WL_SIO_ R WL_SIO_M R0 R % R % R % R00 R00 R00 WL_SIO_LK R R % R00 SIO0_0 SIO0_ SIO0_ SIO0_ SIO0_M SIO0_LK R0 0R R00 0.uF 00 R 00K R00 Q00 WPM0/TS0 SOT R 0K R00 VIO_WL V_WL WIFI_PWR V_V R 0R R00 uf 00.V 00nF 00 V 0 0uF 00.V 00 00nF 00 V PINE RockPro_RK Size ocument Number Rev WIFI OM V.0 ate: Tuesday, MR, 0 Sheet of

24 RJ & Transformer U _- MI- J - _+ MI+ J + _- MI- J - _+ MI+ J - _- MI- J + PHY_TX0 PHY_TX PHY_TX PHY_TX PHY_TXEN PHY_TXLK M_RX0 M_RX M_RX M_RX M_RXV M_RXLK M_LK M_M M_MIO PHY_RST GM_TX0 GM_TX GM_TX GM_TX GM_TXEN GM_TXLK GM_RX0 GM_RX GM_RX GM_RX GM_RXV GM_RXLK GM_LK PHY_TX0 PHY_TX PHY_TX PHY_TX PHY_TXEN PHY_TXLK M_RX0 M_RX M_RX M_RX M_RXV M_RXLK M_LK M_MIO PHY_RST % R R R00 R R R00 % R0 R R00 % R R R00 % R R % R00 R R % R00 R lose to PU 0R % R00 PHY_TX0_0 PHY_TX_ PHY_TX_ PHY_TX_ PHY_TXEN_ PHY_TXLK_ NP 00 R.K % VIO_PHY R00 EPHY_RSTn PHYRST is.v IO R.K % R00 R.K % R00 R.K % R00 R.K % R00 Y PHY_XTLOUT XIN GN GNXOUT MHz pf RY_R0XR0X0R0 0G 0V 00 GM_LK R VIO_PHY PHY_XTLIN pf 0G 0V 00 R % PHY_LKOUT R00 NP M <----- PHY 00 _- _+ _- _+ _- _+ _- _+ MI- R 0R % R00 MI+ R 0R % R00 MI- R 0R % R00 MI+ R 0R % R00 MI- R 0R % R00 MI+ R 0R % R00 MI0- R 0R % R00 MI0+ R 0R % R00 NP NP NP NP NP NP NP NP ESN ESN ESN ESN ES00 ES00 ES00 ES00 0 ESN ESN ESN ESN ES00 ES00 ES00 ES00 L LMPGSN L V 0.uF _+ MI+ _- MI0- _+ MI V TT 0 0nF 0 Earth LE/FG_LO0 G+ R0 0R% RGMII_GR- G- V_LN Y+ LE/FG_LO RGMII_YE- Y- R 0R% GN PGN HY0 J + J - J + Gap > mm High-tension area Low-tension area V0_EPHY V0_EPHY MI0+ MI0- MI+ MI- MI+ MI- MI+ MI- R.K R00 V_LN 0 U MI[0]+ MI[0]- V0 MI[]+ MI[]- MI[]+ MI[]- V0 MI[]+ MI[]- E_Pad V0_EPHY % RSET PHY_XTLOUT PHY_XTLIN PHY_LKOUT LE/FG_LO LE/FG_LO0 LE0/FG_EXT 0 V RSET V0 XTL_OUT/EXT_LK XTL_IN LKOUT LE/FG_LO LE/FG_LO0 LE0/FG_EXT INT/PME PHY_INT/PME 0 REG_OUT V V_RG RX/PHY RXTL/PHY RX0/RXLY RX/TXLY RX/PLLOFF RX/PHY0 V0 REG_OUT R.K % R00 PHY_RXLK/PHY PHY_RXV/PHY PHY_RX0/RXLY PHY_RX/TXLY PHY_RX/PLLOFF PHY_RX/PHY0 V_LN V_LN VIO_PHY V0_EPHY R NP.K/N% LE0/FG_EXT R.K % V_LN R00 R00 R.K/N% LE/FG_LO0 R00 R0.K % LE/FG_LO R N % R00 R00 VIO_PHY Voltage onfig PHY_RX/PHY0 R.K % VIO_PHY R00 R.K % PHY_RXLK/PHY R00 R.K % PHY_RXV/PHY R00 PHY ddress PHY[:0] PHY ddress onfig (default) 'b00 R.K % PHY_RX0/RXLY R NP.K/N% VIO_PHY R00 R00 Pull-up for additional ns delay to RX for data latching R.K % PHY_RX/TXLY R NP.KIN% VIO_PHY R00 R00 Pull-up for additional ns delay to TX for data latching RGMII Power Source FG_EXT FG_LO[:0] External.V 'b 'b00 External.V (default) 'b 'b0 Internal.V 'b0 'b0 close to PIN,0 VV_S V_LN 00nF 00nF R 0R % 0V 0V R uF 0V 0 00.uF 00nF 0V 0V VIO_PHY close to PIN close to PIN V PHYRST M MIO TX TX TX TX0 TXTL TX PHY_RX/PLLOFF R0.K % R00 Pull-up to disable LPS mode VIO_PHY.uF 0V 00 00nF 0V 00 V_LN 0 EPHY_RSTn M_M M_MIO PHY_TX_ PHY_TX_ PHY_TX_ PHY_TX0_0 PHY_TXEN_ PHY_TXLK_ RTLF-G QFN0_X_0MM RTLF-G(SW Mode) RTLFI-G(SW Mode)Industrial VV_S VIO_PHY V_LN R PHY_RX0/RXLY PHY_RX/TXLY PHY_RX/PLLOFF PHY_RX/PHY0 PHY_RXLK/PHY PHY_RXV/PHY lose to PHY NP.K/N % R00 00nF 0V 00 R R % R00 GM_RX0 R R % R00 GM_RX R R % R00 GM_RX R R % R00 GM_RX R R % R00 GM_RXLK R00 R % R00 GM_RXV NP 00 V0_EPHY REG_OUT L.uH IN_00.uF 00nF 0V 0V close to PIN RTLF-G(SW Mode) RTLFI-G(SW Mode)Industrial close to PIN 00nF 0V nF 0V 00 00nF 0V 00 00nF 0V 00 close to PIN,, uf 0V 00 R 0R % R00 PINE uf 0V 00 RockPro_RK Size ocument Number Rev ustom 000M-RTLF-G V.0 Tuesday, MR, 0 ate: Sheet of

25 TF R SMM0_ SMM0_ SMM0_M SMM0_LK SMM0_0 SMM0_ SMM0_ET_L R0 R R00 % R0 R R00 % R0 R R00 % R0 0R R00 % R0 R R00 % R0 R R00 % R0 R R00 % VV0_S J TF-KT0-00 TF-R T /T M V LK VSS T0 T 0 G G G G E ESN ES00 E ESN ES00 E ESN ES00 E0 ESN ES00 E ESN ES00 E ESN ES00 E ESN ES00 VV0_S 0uF 00.V 00nF 00 V PINE RockPro_RK Size ocument Number Rev TF R V.0 ate: Tuesday, MR, 0 Sheet of

26 igital Video Output V_TXP V_TXN V_TX0P V_TX0N PORT_E _SL PORT_HP 0 0 J Video_ V-_X_-P VV0_SYS V_TXP V_TXN V_TXP V_TXN _S 00nF 00 V VV0_V uf 00 0V V_TXP V_TXN V_TXP V_TXN U TPE0U0 SLP0P NP IN OUT IN OUT IN OUT IN OUT GN GN 0 V_TX0P V_TX0N V_TXP V_TXN V_TXP V_TXN V_TXP V_TXN V_E PORT_HP I_SL_V I_S_V P_PWR_RET V_TXP V_TXN V_TXP V_TXN I_SL_V I_S_V V_V0 V_V0 R0.K R00 % R0.K R00 % Q SK0 SOT_ WS SO_ R0.K R00 % _SL VV0_V V_V0 VV_SYS R R R.K K K R00 R00 R00 % % % _S V_E PORT_E WS SO_ V_TX0P V_TX0N V_TXP V_TXN PORT_E _SL _S PORT_HP U TPE0U0 SLP0P NP IN OUT IN OUT IN OUT IN OUT GN GN U TPE0U0 SLP0P NP IN OUT IN OUT IN OUT IN OUT GN GN 0 0 V_TX0P V_TX0N V_TXP V_TXN PORT_E _SL _S PORT_HP Q SK0 SOT_ Q SK0 SOT_ PINE RockPro_RK Size ocument Number Rev ustom V.0 IGITL VIEO PORT V.0 ate: Tuesday, MR, 0 Sheet of

27 PIe x PIE_PWR VV_PIE PIE_TX0P PIE_TX0N PIE_TXP PIE_TXN PIE_TXP PIE_TXN PIE_TXP PIE_TXN I>. VV_IN uf 00.V 00 0uF 00 V 0 0uF 00.V VV_PIE 0 PIE_WKE_V_L 00nF 00 V PIE_LKREQ_V_L 00nF 00 0V PIE_TX0_P 00nF 00 0V PIE_TX0_N PIE_PRSNT_V_H U0 R 0K % R nF EN V00 SS PG TS IN GN S OMP SW F R.K % R nF 00 V L00 0uH/ ind-x R K % R00 R0 0K % R N V00 J PIE-PINX PIE_IP +V_ +V_ +V_ GN_ SMLK SMT GN_ +.V_ JTG_TRST.VUX WKE# RSV_ GN_ HSOp(0) HSOn(0) GN_ PRSNT#_ GN_ 00nF 00 0V PIE_TX_P 00nF 00 0V PIE_TX_N 0 HSOp() HSOn() GN_ 00nF 00 0V PIE_TX_P GN_ 00nF 00 0V PIE_TX_N HSOp() HSOn() GN_ 00nF 00 0V PIE_TX_P GN_ 0 00nF 00 0V PIE_TX_N HSOp() HSOn() 0 GN_ PIE_PRSNT_V_H RSV_0 PRSNT#_ GN_ 00 00nF 00 V 00.nF V00 x x VV_PIE 00 uf 00.V PRSNT# +V_ +V_ GN_ JTG_TK JTG_TI JTG_TO JTG_TMS +.V_ +.V_0 PERST# GN_ REFLK_P REFLK_N GN_ HSIp(0) HSIn(0) GN_ RSV_ GN_0 HSIp() HSIn() GN_ GN_ HSIp() HSIn() GN_ GN_ HSIp() HSIn() GN_ RSV_ 00 uf 00.V PIE_PWR R 0R R00 VV_PIE VV_PIE PIE_PERST_V_L PIE_RXP PIE_RXN VV_IN 00nF 00 V PIE_REF_LK_P PIE_REF_LK_N PIE_RX0_P PIE_RX0_N PIE_RX_P PIE_RX_N PIE_RX_P PIE_RX_N R 0K % R00 R0 00K R00 % VV_PIE R0 0R R00 % R 0K R00 % WIFI_HOST_WKE_L Q WPM0-/TR SOT_ R0 R R00 % Q S00 SOT_ WIFI_REG_ON_H PIE_PERST_L PIE_LKREQ_L uf 0uF V.V PINE R0 0R R00 % R R R00 % ate: Tuesday, MR, 0 Sheet of V_V V_V V_V VV_PIE 00 00nF 00 V RockPro_RK VV_PIE VV_PIE VV_PIE V_V VV_PIE Q R WNM0-/TR K SOT_ R00 % PIE_WKE_V_L PIE_RX_P PIE_RX_N Size ocument Number Rev PIE-X V.0 Q0 R WNM0-/TR K SOT_ R00 % PIE_PRSNT_V_H Q R WNM0-/TR K SOT_ R00 % PIE_PERST_V_L R0 0R nF 0V R0 0R nF 0V Q R WNM0-/TR K SOT_ R00 % PIE_LKREQ_V_L 00 00nF 00 V

28 OE I_S I_SL VV_OE R NP R00 R 0R R00 % HP_INP 00nF 00 V HP_INN 00nF V_MIIS 00 V 0uF 00 0V 0.uF 00 0V MI_INP close to ES I_S I_SL IS_LK IS_SLK IS_LRK_RX IS_LRK_TX IS_SI0 IS_SO0 HP_ET_H HP_HOOK IS_LK IS_SLK IS_SO0 IS_LRK_TX IS_LRK_RX IS_SI0 E-P T E 0 LIN RIN LIN RIN MIIS R R R00 % LK VREF VV_OE MLK GN VV0_OE V_V0 V V 0uF PV VREF 0 HPOL 00 R R R00 % GN LOUT HPOR 0V R R R00 % SLK ROUT HPGN R0 R R00 % SIN PGNREF R0 0R R00 % LRK PGN R R R00 % R R R00 % VMI SOUT GPIO GPIO GPIO PVSSP PV PTOP POT U 0uF 00 0V HP_ET_H MI_INP R 0K R00 % R K R00 % R K R00 % GPIO_HP_INSERT_ET GPIO_HPM_ET TP0 TP_.0 0 VV_OE VV0_OE Head phone HP_ET_H HPOL HPOR PHONE_ET 0nF 00 V V_MIIS E ESN ES00 ES QFN_X_0MM 0uF VV_OE 00 0V 00nF 00 V 0uF 00 0V E ESN ES00 00nF 00 V.uF 00 0V R K R00 % R 0K R00 % HPGN 0R R0R00 % R00 % 0R R R 0K HP_HOOK R00 MI_INP % R.K R00 % 0 00nF 00 V R 0R R00 % E ESN ES00 0uF 00 0V 00nF 00 V 00nF 00 V E ESN ES00 J pj_0 pj_0 PINE RockPro_RK Size ocument Number Rev OE-ES V.0 ate: Tuesday, MR, 0 Sheet of

29 I_S I_SL R.K % R00 R.K % R00 V_V0 VV_SYS R 0R R00 PI-.V U ON0 IE_H_0P VV0_SYS I_S I_S I_SL PU_GPLK PU_GPIO_ PU_GPIO_ PU_GPIO_ PI-.V SPI_TX SPI_RX SPI_LK R 0R % R00 PU_GPIO_ PU_GPIO_ IS0_SO_PM IS0_LRK_TX_PM IS0_LRK_RX_PM IS-S IS-SL URTG_TX URTG_RX IS0_SLK_PM PU_GPIO_ PU_GPIO_ PU_GPIO_ SPI_SN0 PU_GPIO_ R 0R % R00 IS0_SO_PM IS0_SO_PM IS0_SI0_PM IS0_SO0_PM I_SL RockPro_RK Size ocument Number Rev ustom PI- US V.0 ate: Sheet of

30 dual MIPI SI ports Parallel SI port V_MIPI 全部切换为.V U 由 TSE 更改为 TSE PINE Tuesday, MR, 0 IF_LK VP_PN0_H IF_RST IF_RST VP_PN0_H MIPI_RST MIPI_RST MIPI_RST I_S_M I_SL_M I_S_M I_SL_M I_S_M I_SL_M IF_LK VV_VP VV_VP F_ VV_VP V_MIPI F_ V_V V_MIPI VV0_SYS V_MIPI V_MIPI F_ V_V V_MIPI VV0_SYS V_MIPI V_MIPI V_MIPI VV0_SYS V_MIPI VV_SYS F_ VV0_SYS V_V VV_SYS VV_VP V_MIPI VV_VP V_MIPI V_MIPI V_MIPI V_MIPI F_ F_ MIPI_RX0_0P MIPI_RX0_0N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_P MIPI_RX0_N IF_0 IF_ IF_ IF_ IF_ IF_ IF_ IF_VSYN IF_ IF_HREF IF_LKO MIPI_MLK0 MIPI_RX_0P MIPI_RX_0N MIPI_RX_LKP MIPI_RX_LKN MIPI_RX_P MIPI_RX_N MIPI_RX_P MIPI_RX_N MIPI_RX_P MIPI_RX_N VP_PN MIPI_MLK0 VP_PN VP_PN0_H IF_LKI VP_PWR VP_PWR VP_PWR VP_PWR MIPI_RX0_P MIPI_RX0_N MIPI_RX0_LKP MIPI_RX0_LKN Size ocument Number Rev ate: Sheet of M V.0 RockPro_RK 0 Size ocument Number Rev ate: Sheet of M V.0 RockPro_RK 0 Size ocument Number Rev ate: Sheet of M V.0 RockPro_RK 0 R 0K R00 % 0.uF 00 0V 00nF 00 V 0.uF 00 0V.uF 00 0V.uF 00 0V U TSE SOT IN GN EN P OUT.uF 00 0V U0 TSE SOT IN GN EN P OUT.uF 00 0V 00nF 00 V.uF 00 0V 0 00nF 00 V 00nF 00 V 00nF 00 V.uF 00 0V J 0--TG FP00_P_F N GN S V V SK RESET VSYN PWN HREF V V 0 OV V Y XLK Y GN Y PLK Y Y Y 0 Y Y Y Y0 GN0 GN U TSE SOT IN GN EN P OUT U TSE SOT IN GN EN P OUT 00.uF 00 0V.uF 00 0V.uF 00 0V 0.uF 00 0V 0 00nF 00 V J 0--TG FP00_0P_F hanel0/ +V +V +V_VIO V GN0 + V GN S SK 0 RST PN-0 GN MLK GN SI-P SI-N GN SI-P SI-N 0 GN SI-LKP SI-LKN GN SI-P SI-N GN SI-0P SI-0N GN 0 P GN R0 0R 00nF 00 V 00nF 00 V.uF 00 0V J 0--TG FP00_0P_F hanel0/ +V +V +V_VIO V GN0 + V GN S SK 0 RST PN- GN MLK GN SI-P SI-N GN SI-P SI-N 0 GN SI-LKP SI-LKN GN SI-P SI-N GN SI-0P SI-0N GN 0 P GN 0 00nF 00 V 00nF 00 V R 0K R00 % 0 00nF 00 V 0 00nF 00 V R R 00nF 00 V R 0K R00 % R 0K R00 % 0.uF 00 0V 00nF 00 V 0.uF 00 0V 0.uF 00 0V 00nF 00 V

31 ep Panel EP_TX0N EP_TX0P EP_TXN EP_TXP EPUXN EPUXP L_L_PWM L_EN L_RST L_EN VV_IN 00 00nF 00 V R 0K % R00 Q0 WPM0-/TR R 00K SOT_ R00 % R 0K R00 % Q0 S00 SOT_ 0 0 0uF 00 uf/v 00.V V_V 0 0/V 00 VV_S0 EPUXP 00nF 00 0V NP00K/N R % R00 VV_S0 NPR 00K/N % R00 00nF 00 EPUXN 0V 0uF 00.V 0 00nF 00 V EP_UXP EP_UXN VV_S0 V_V TP00 L_EN L_L_PWM EP_TXN EP_TXP EP_TX0N EP_TX0P EP_HP N H_GN ML- ML+ H_GN ML0- ML0+ H_GN UX+ UX- H_GN VS VS N0 GN GN HP L_GN L_GN L_GN L_GN LE_EN LE_PWM N N LE_VS LE_VS LE_VS LE_VS N J MFI0-0 FP00_0P_F PINE RockPro_RK Size ocument Number Rev L EP V.0 ate: Tuesday, MR, 0 Sheet of

32 MIPI Panel KLIGHT L_L_PWM VV0_SYS biasing circuit R 0K R00 0.uF 00 VV_S0 V 0uF 00 U LP0S/RT EN V OVP GN SOT.uF 00 0V LX F L.uH. IN_x 0.0ohm 0.uF L 00 uh IN_X SK SO 限流电阻需要依据实际使用的显示屏背光电流进行调整 V V V_LE.uF 00 V V_LE VGL VGH R K R00 V VV_S0 VV_S0 V SHLR VV_S0 L_RST uf 00 GPIO 不够, 硬件上下拉控制 VV_S0 N OVP N N 0 R N R EN F R V_LEK N 0K R00 R00 00K R00 % R 0R R00 % 00nF 00 V U SY0 dfn0_xmm IN LX LX GN 0.uF 00 0 N\TS SOT N/0.uF 00 N SO R 0K % R pF 00 R 00K % R00 TS SOT TS SOT 0uF/V 00 R 0R R00 N\uF/V 00 uf/v 00 R.R R00 % R uf/v 00 R uf/v 00 R.R/N R00 % 0R R00 K R00 0.uF 00 uf/v 00 uf 00 V V 0 V 0 R K R00 0uF 00 R0 0K R00 R K R00 R K R00 R 00K R00 0.uF 00 uf 00 PINE UPN R N R00 0 uf 00 VV_S0.0V VOM R0 0K RES00 uf 00 STY V_LE L_L_PWM MIPI_TX0_0P MIPI_TX0_0N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N MIPI_TX0_P MIPI_TX0_N VGH VGL UPN SHLR V_LEK V L_RST MIPI_TX0_P MIPI_TX0_N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N MIPI_TX0_0P MIPI_TX0_0N STY L_RST VV_S0 RockPro_RK VOM ate: Tuesday, MR, 0 Sheet of L_L_PWM L_RST MIPI_TX0_0P MIPI_TX0_0N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N MIPI_TX0_P MIPI_TX0_N LE+ LE+ VGH VGL UP/OWN L/R LE- LE- V GN0 SI-P SI-N GN SI-P SI-N GN SI-KP SI-KN GN SI-P SI-N GN SI-0P SI-0N GN Standby RST V0 V VOM J 0--TG FP00_0P Size ocument Number Rev ustom L MIPI V.0

33 Touch Panel connector I_SL_TP I_S_TP TOUH_RST TOUH_INT ON Touch_screen TOUH_RST TOUH_INT I_SL_TP I_S_TP VV0_TOUH RST INT SK S V GN VV0_TOUH.uF 00 0.uF 00 PINE RockPro_RK Size ocument Number Rev TP PORT V.0 ate: Sheet of

rockpro64_v

rockpro64_v RK_MI_REF_V. ONTENT INEXING 0.Index 0.hange List 0.lock iagram 0.Power Tree 0.I Map 0.Power omain Map 0.IR Receiver 0.RK Power.RK PMU ontroler.rk R ontroler.rk Flash&SMM ontroler.rk US/USI ontroler.rk