ROC-RK3328-CC-V1.0-A

Transcription

1 ontent Indexing PF Number of pages 0.Index 0.hange List 0.lock iagram 0.Power tree-rk0-0.system Power-PMI RK0-0.RK Power 0.RK OS/PLL/OTP/SR 0.RK R ontroler 0.RK emm ontroler/tf/spi 0.RK US PHY/US PHY.RK SIO/URT/I/IS/IR.RK HMI PHY.RK V Interface.RK FEPHY.RM R xbit._in/reower.tf/s ard/t.flash-emm.us Port 0.HMI OUT Port.V OUT Port.0/00M-Embed PHY.WIFI+T_TR.onnector Note: omponent parameter description. NP stands for component not mounted temporarily. If Value or option is NP, which means the area is reserved without being mounted <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

2 Version ate uthor hange Note pproved V00 00 LZZ First edictor <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

3 0/00M US OTG.0 HMI OUT V OUT 0/00M US OTG.0 HMI OUT V OUT RJ- RJ- Transformer MHz US.0/US.0 Transformer MHz US.0/US.0 ata0- R 0*it ata0- ata- R/RL *it ata- R 0*it Opt Opt S/PIF 光光 S/PIF 光光 ata- R 0*it TF 卡 SMM0 bit ata- ata~ R/RL *it TF 卡 SMM0 bit ata~ R 0*it V to V dapter RK0- WIFI Module Reset I0 Sleep Int bit emm IRM URT ebug URT ommand,ontrol, lock SIO WIFI+URT T, TR R support G 00M Ethernet efault config V to V dapter onfig RK0- WIFI Module Reset I0 Sleep Int bit emm IRM URT ebug URT SIO WIFI+URT T,TR R support up to G 00M Ethernet ommand,ontrol, lock 0/00 /000M 0/00M US OTG.0 HMI OUT V OUT 0/00M US OTG.0 HMI OUT V OUT RJ- RJ- RJ- Transformer 000M PHY Module Opt S/PIF 光光 TF 卡 Transformer US WIFI Module SMM0 bit MHz US.0/US.0 ata0- ata- ata- ata~ R/RL *it R/RL *it R/RL *it R/RL *it Opt S/PIF 光光 TF 卡 Transformer SMM0 bit MHz US.0/US.0 ata0- ata- ata- ata~ R/RL *it R/RL *it R/RL *it R/RL *it V to V dapter RK0- RGMII Reset I0 Sleep Int bit emm IRM URT ebug URT US WIFI/T, R support up to G 00M+000M Ethernet ommand,ontrol, lock V to V dapter onfig onfig RK0- WIFI Module Reset I0 Sleep Int bit emm IRM URT ebug URT SIO WIFI+URT T, TR R support up to G 00M Ethernet ommand,ontrol, lock <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

4 V_IO option LO 00m V_0 RK PLL_V_V0,V_PMU RK US0_V_V0,US0_V_V0 RK HMI_V_V0 RK EPHY_V_V0 UK. UK. V_LOG V_RM RK Logic RK GPU RK RM ore Power Timing TYPE VOLT STEP PowerName UK.V V_LOG dapter V -> V V_SYS V/ UK. V_R RK R PHY R evice RK PLL_V_V UK UK UK LO.V F=0.V.V.V V_RM V_R V_IO V_ RK US0_V_V,US0_V_V LO.V V_eMM V_IO LO 00m V_ RK HMI_V_V,V_V_V RK OE_V_V LO.0V V_0 RK SR,OTP RK EPHY_V_V RK US_V_V RK VIO,VIO,VIO_PMU Poweromain UK. V_IO RK VIO,VIO Poweromain TF ard V_IO LO 00m V_eMM emm V RK VIO Poweromain emm VQ RK0- V_IO Option V_ WiFI Module VT RK VIO Poweromain S/PIF optical fiber Port udio Line river I Infrared Receiver Module RESET System reset signal urrent limiting I V US0 OTG urrent limiting I V US0 HOST HMI V(.-.V) <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, ecember, 0

5 IR V_IO R 00R R00.uF 00 0.uF 00 IR_RX IR_V V G IR IR FT-00 IR_REEIVE R K R00 V_IO efault:r=.v R RL R V_R.V R V_SYS 00nF 00 0V NP PWRON M0 test 00nF 00 0V.V 00K % K % R 0K % K % V_IO 00nF 00 0V uf V_SYS V_R PWRON V_R uf 00 0V.V K % 00K % 00 0V uf 00.V L0.0uH V_IO V_SYS RK0_KOUT IN_0 _R<0mohm L0.0uH V_SYS IN_0 _R<0mohm 0G 0V pf 00 R K R0 N R00 % R00 R 0R R00 R NP R00 V_IO R 00K % R00 SW SW F V_SYS PWREN PMI_SLEEP V_0 0 00nF 0V 00 U0 LKK F SW V V SW F ep PWRON LO EN uf 0V 00 R0 0k R00 PWREN M0 test V SLEEP V_ uf 0V 00 V_SYS RK0- QFN_R00XR00X0R0_T V LO.uF 0V 00 uf 0V 00 REFGN V R0 0K % R00 0 V_IO VREF LO 0 uf 0V 00 00nF 0V 00 XOUT INT V_EMM 0pF 0G0V 00 0pF 0G0V 00 Y00.KHz RY_M XIN SL.uF 0V 00 OUT S OUT F SW V V SW F RESET 0 Work/Standby NET_LE V_LOG SW SW V_SYS V_RM 00nF 0V 00 IN_0 _R<0mohm IN_0 _R<0mohm V_IO R 00R % R00 L0.0uH uf L0.0uH R 00R % R00 R 0K % R00 F UK V_IO OUT 00 0V 00R F UK R.K % R00 OUT V_LOG 0uF 00.V V_RM 0uF 00.V 00R R0.K % R00 uf 00.V V_SYS uf 00.V 00nF 00 0V 00nF 00 0V V_LOG RK Power pin 00nF 0V 00 NP V_RM RK Power pin RESET I_S_PMI, I_SL_PMI, PMI_INT LE ISPLY M00 MRK MRK Work/Standby 默默 =0 NET_LE 默默 =0 M0 MRK MRK U LOGO LOGO M0 MRK MRK V_IO V_IO <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, ecember, 0 LE0 LE_GREEN LE_00 R 0R R00 % LE0 LE_RE LE_00 R 0R R00 % M0 MRK MRK M0 MRK MRK M0 MRK MRK

6 >00Mil >00Mil V_RM V_LOG reate ate: Modify ate: <oc> <oc> <oc> <oc> Thursday, March 0, 0 Monday, ecember, 0 reate ate: Modify ate: <oc> <oc> <oc> <oc> Thursday, March 0, 0 Monday, ecember, 0 reate ate: Modify ate: <oc> <oc> <oc> <oc> Thursday, March 0, 0 Monday, ecember, 0 0uF 00.V 0 uf 00.V U00O RK G_R00XR00XR E E E E E E E0 E E E E E E E E F F F F F F F F0 G G G G G G G G G G 0 0uF 00.V 0 00nF 00 0V 0.uF 00 0V 0uF 00.V uf 00.V 0 0nF 00 V 0 00nF 00 0V 0 uf 00.V U00P RK G_R00XR00XR G H H H H0 H H H H H H J J J J0 J J J J J J0 K K K K K0 K K K K K L L L L L L L0 L L L L L L L L M M 0.uF 00 0V 00.uF 00 V uf 00.V 0.uF 00 0V RM GPU/Logic U00N RK G_R00XR00XR V_LOGI N V_LOGI N0 V_LOGI N V_LOGI P V_LOGI P0 V_LOGI P V_LOGI R V_LOGI R0 V_LOGI R V_ORE P V_ORE P V_ORE R V_ORE R V_ORE T V_ORE T V_ORE T U00Q RK G_R00XR00XR M M0 M M M M N N N N N N N P P P P P R R R R R R T T T T T0 T T U U U U U U U V V V W W W W W W W

7 U00 OS XOUTM T XINM R R00 R0 M % R00 R % R00 00 pf 0G 0V 00 Y00 XOUTGN GN XIN MHz RY_R0XR0X0R0 0 pf 0G 0V 00 PLL Power PLL_V_V0 PLL_V_V H H VPLL/US0_V0 >Mil 0 00nF 0V 00 0.uF.V 00 L00 0R-00M L00 V_0 0.uF.V 00 SR OTP/eFUSE RK G_R00XR00XR SR_IN0 SR_IN SR_V_V OTP_V EFUSE_VP M M M N P REOVER REOVER, SR_IN SR_IN V_ 0 00nF 0V 00 VPLL/US0_V >Mil 0 00nF 0V 00 0.uF.V 00 L0 0R-00M L00 V_ 0.uF.V 00 V_ R0 0K % R00 SR_IN R0 N/0K % R00 NP <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, ecember, 0

8 U00M R/R R_0 R_ R_ R_ R_ R_ R_ R_ R_M0 R_QS0P R_QS0N R_ R_ R_0 R_ R_ R_ R_ R_ R_M R_QSP R_QSN R_ R_ R_ R_ R_0 R_ R_ R_ R_M R_QSP R_QSN R_0 R_ R_ R_ R_ R_ R_ R_ R_M0 R_ R_ R_0 R_ R_ R_ R_ R_ R_M R_ R_ R_ R_ R_0 R_ R_ R_ R_M R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_QM0 R_QS0_P R_QS0_N R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_QM R_QS_P R_QS_N R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_QM R_QS_P R_QS_N G R_0/R_0 K R_/R_ H R_/R_ E0 R_/R_ H R_/R_ R_/R_ H0 R_/R_ 0 R_/R_ K R_/R_ F R_/R_0 K R_0/R_S0n G0 R_/R_ J R_/R_ F R_/R_ G R_/R_ J R_/R_OT0 R_0/R_G0 K0 R_/R_Sn/R_ E R_/R_0 0 R_SN0/R_Tn R_SN/R_SN L E R_OT0/R_Wen/R_ L R_OT/R_OT 0 R_LKP/R_LKP R_LKN/R_LKN 0 L0 R_KE/R_RSn/R_ R_RSn/R_KE J R_Sn/R_ H R_WEn/R_G R_RESETn/R_RESETN R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_S0n R_ R_ R_ R_ R_OT0 R_G0 R_Sn/ R_0 R_Tn R_Sn R_WEn/ R_OT R_LKP R_LKN R_RSn/ R_KE R_ R_RST V_R R_ R_ R_ R_ R_ R_ R_0 R_ R_M R_QSP R_QSN R_ R_ R_ R_ R_ R_ R_0 R_ 0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_QM R_QS_P R_QS_N RK G_R00XR00XR V_RIO F0 V_RIO F V_RIO F V_RIO F V_RIO G0 V_RIO G V_RIO G V_RIO G V_RIO H V_RIO J V_RIO J V_RIO K V_RIO K 000 0nF V nF 0V nF 0V 00 0uF 0V 00 0uF 0V <oc> reate ate: Friday, March, 0 Modify ate: Monday, September, 0

9 U00 GPIO0_/EMM_0_u U U0 GPIO_/EMM u U GPIO_/EMM u V GPIO_/EMM u U GPIO_/EMM u W GPIO_0/EMM u T GPIO_/EMM u T GPIO_/EMM u GPIO_/EMM_M_u R0 GPIO_/EMM_LKOUT_u R R GPIO_/EMM_PWREN_d emm_0 emm_ emm_ emm_ emm_ emm_ emm_ emm_ emm_m emm_lko emm_rst RK G_R00XR00XR U00 GPIO_0/SMM0_0/URT_TX_M0_u U0 GPIO_/SMM0_/URT_RX_M0_u W GPIO_/SMM0_/JTG_TK_u W GPIO_/SMM0_/JTG_TMS_u RK G_R00XR00XR U00G VIO GPIO_/SMM0_M_u Y GPIO_/SMM0_LK/TEST_LK0_d W GPIO_/SMM0_ETN_u V0 VIO T U 0 00nF 0V nF 0V 00 VIO_FLSH SMM0_0 SMM0_ SMM0_/JTG_TK SMM0_/JTG_TMS SMM0_M SMM0_LK SMM0_ET VIO_S GPIO_/TSP_0/IF_0/SMM0EXT_0/URT_TX/USPHY_EUG_u E GPIO_/TSP_/IF_/SMM0EXT_/URT_RTSN/USPHY_EUG_u GPIO_/TSP_/IF_/SMM0EXT_/URT_RX/USPHY_EUG_u F GPIO_/TSP_/IF_/SMM0EXT_/URT_TSN/USPHY_EUG_u F GPIO_0/TSP_VLI/IF_VSYN/SMM0EXT_M/SPI_LK_M/USPHY_EUG/IS_SLK_M_u E GPIO_/TSP_LK/IF_LKIN/SMM0EXT_LK/SPI_RX_M/USPHY_EUG/IS_SI_M_d E GPIO_/TSP_FIL/IF_HREF/SMM0EXT_ET/SPI_TX_M/USPHY_EUG/IS_SO_M_u GPIO_0/TSP_/IF_/SPI_SN0_M/IS_LRK_TX_M/USPHY_EUG/IS_LRK_RX_M_d F V_SYS URT_TX URT_RTSN URT_RX URT_TSN GPIO_0_U/SPI_LK GPIO /SPI_RX GPIO U/SPI_TX GPIO_0_/SPI_SN0 SIO_PER V_IO IN OUT V_IO 0 GN uf R0 XR EN P V 0K % R TT0 uf V_IO SOT XR V 00 R 0K % R00 R0 K R00 % R0 N R00 % U0 R0 K R00 % Q0 S00 SOT R0 R00 R R0 % K R00 % R0 00K R00 % R K R00 % R0.K R00 % Q0 S00 SOT VIO_S 0 00nF XR V 00 VIO H V_IO RK G_R00XR00XR <oc> reate ate: Thursday, March 0, 0 Modify ate: Tuesday, October, 0

10 U00K V_IO US.0 US0_M Y US0_P US0_VUS T OTG0_M OTG0_P OTG_ET R 0K R00 OTG_ET US_M Y US_P US0_HOST_M US0_HOST_P US0_EXTR W R00 R % R00 V_IO RK G_R00XR00XR U00L US0_V_V US0_V_V US0_V_V0 T U V US0/FEPHY_V 0 00nF 0V 00 US0/FEPHY_V0 0 00nF 0V 00 0.uF.V 00 0.uF.V nF 0V 00 L0 0R-00M L00 NP L0 N/0R-00M L00 V_0 0.uF.V 00 V_ 0.uF.V 00 US.0 US0_RXP J US0_RXN J US0_TXP H US0_TXN H US0_M K K US0_P US0_RXP US0_RXN US0_TXP US0_TXN US0_M US0_P L0 0R-00M L00 V_LOG US0_VUS K V_IO US0_EXTR G R0 K % R00 V_IO US0_V_V J VPLL/US0_V US0_V_V US0_V_V0 RK G_R00XR00XR J J VPLL/US0_V0 0 00nF 0V nF 0V nF 0V 00 <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0 0

11 U00F NPOR_u TEST_d GPIO_/EFUSE_PWREN/POWERSTTE_u P M GPIO_/SPI_SN_M0/FLSH_VOL_SEL_u T U GPIO_/I0_S/FEPHY_LE_T_M_u R GPIO_0/I0_SL/FEPHY_LE_LINK_M_u P GPIO_/IS_MLK/TSP_SYN_M/IF_LKOUT_M_d N GPIO_/IS_SLK/PM_LK_M0/TSP M/IF M_d R GPIO_/IS_LRK_TX/SPIF_TX_M/TSP M/IF M_u P GPIO_0/IS_LRK_RX/TSP M/IF M_u V GPIO_/IS_SO/PM_FSYN_M0_u N GPIO_/IS_SIO/PM_SI_M0/R_RST_M_u V GPIO_/IS_SIO/PM_SI_M0/R_ET_M_u V GPIO_/IS_SIO/PM_SI_M0/R_IO_M_u V GPIO_/IS_SI/PM_SI0_M0/R_LK_M_u U M0 GPIO_/US0_RV_d GPIO_/PWM0/I_S_u N N0 GPIO_/PWM/I_SL_u M GPIO_/PWM_u GPIO_/IR_RX/POWERSTTE_u M GPIO_/URT_RX_M/POWERSTTE_u P0 GPIO_0/URT_TX_M/POWERSTTE0_d P 00 00nF 0V 00 RESET IR_RX V_IO GPIO /IS_MLK GPIO /IS_SLK GPIO U/IS_LRK_TX GPIO_0_U/IS_LRK_RX GPIO U/IS_SO GPIO U/IS_SO GPIO U/IS_SO GPIO U/IS_SO GPIO U/IS_SI PMI_SLEEP I_S_PMI, I_SL_PMI, GPIO U/PWM URT_RX URT_TX R0 N % GPIO_/SPI_SN_M0/FLSH_VOL_SEL I0_S, I0_SL, M0 test U00E RK G_R00XR00XR GPIO_0/URT0_RX/GM_TX_M_u Y GPIO_/URT0_TX/GM_TX0_M_u GPIO_/URT0_RTSN/GM_RX_M_d W GPIO_/URT0_TSN/GM_RX0_M_d V GPIO_/SMM_LK/GM_TXLK_M_d 0 GPIO_/SMM_M/GM_RXLK_M_u Y0 GPIO_/SMM_0/GM_RX_M_u W GPIO_/SMM_/GM_RX_M_u W GPIO_0/SMM_/GM_TX_M_u GPIO_/SMM_/GM_TX_M_u Y GPIO_/SMM_PWREN/GM_RS_M_d W0 GPIO_/SMM_ET/GM_MIO_M/PM_FSYN_M_u Y GPIO_/IS_MLK/GM_LK_M_d W GPIO_/IS_SLK_M0/GM_RXV_M/PM_LK_M_u W GPIO_/IS_LRK_TX_M0/GM_M_M/PM_SI0_M_d W GPIO_/IS_LRK_RX_M0/LKOUT_GM_M/PM_SI_M_d V GPIO_0/IS_SI_M0/GM_RXER_M/PM_SI_M_d GPIO_/IS_SO_M0/GM_TXEN_M/PM_SI_M_d Y GPIO_/LKKOUT_M_d VIO V U URT0_RX/GM_TX URT0_TX/GM_TX0 URT0_RTSN/GM_RX URT0_TSN/GM_RX0 SMM_LK/GM_TXLK SMM_M/GM_RXLK SMM_0/GM_RX SMM_/GM_RX SMM_/GM_TX SMM_/GM_TX WIFI_REG_ON/GM_RS WIFI_WKE_HOST/GM_MIO T_REG_ON/GM_LK GM_RXV/PM_LK GM_M/PM_SYN GM_TXEN/PM_TX VIO 0 00nF 0V 00 GPIO_/LKOUT M_TX M_TX0 M_RX M_RX0 M_TXLK M_RXLK M_RX M_RX M_TX M_TX PHY_RST M_MIO M_LK M_RXV M_M US_HOSTV_EN PMI_INT M_TXEN RK G_R00XR00XR VIO R 0 00nF 0V 00 V_IO VIOR 0R % V_IO U00 GPIO0_/LKOUT_GM_M0/SPIF_TX_M_d R N GPIO_MUTE_d GPIO0_0/LKOUT_WIFI_M0_d L U GPIO0_/HMI_HP_d V HMI_E_u V I_SL/HMI_SL_od I_S/HMI_S_od V GPIO/LKOUT/SPIF_TX_M SIO_PER GPIO0_0/LKOUT HMI_HP 0 HMI_E 0 HMI_SL 0 HMI_S 0 V0_HMI/PMU V_PMU M VIO_PMU K GPIO0_/SPIF_TX_M0_d V GPIO0_/FEPHY_LE_SPEE0/SMM0_PWREN_M_d W0 SPIF_TX_M0 SMM0_PWREN V_IO 0 00nF 0V nF 0V 00 RK G_R00XR00XR VIO T 0 00nF 0V 00 V_IO <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, ecember, 0

12 U00I HMI.0 out HMI_TXLKN W HMI_TXLKP Y HMI_TX0N Y HMI_TX0P HMI_TXN Y HMI_TXP Y HMI_TXN HMI_TXP Y HMI_TXLKN R 0R % R00 HMI_TXLKP R 0R % R00 HMI_TX_0-0 HMI_TX_0+ 0 HMI_TX_- 0 HMI_TX_+ 0 HMI_TX_- 0 HMI_TX_+ 0 HMI_TX_- 0 HMI_TX_+ 0 HMI TMS trace 00 Ohm +-0% HMI_EXTR M R00 K % R00 V_HMI/V HMI_V_V P V0_HMI/PMU >0Mil L0 0R-00M L00 V_ HMI_V_V0 M RK G_R00XR00XR 00 00nF 0V 00 0.uF.V 00 0 nf 0V nF 0V 00 >Mil 0 uf.v 00 R0 R R00 V_0 <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

13 U00H R/L out OE_VM T 00.uF.V 00 OE_OL P OE_OR N OL OR V_OE OE_V_V OE_ N R >Mil 0 00nF 0V 00 0.uF.V 00 L0 0R-00M L00 V_ VS out V_IOUT M V_OUT V_IREF P R0 K % R00 V_V_V N V_HMI/V RK G_R00XR00XR 0 00nF 0V 00 <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

14 U00J 0/00M Ethernet PHY FEPHY_TXP Y FEPHY_TXN FEPHY_RXP Y FEPHY_RXN FEPHY_EXTRES V R00.K % R00 US0/FEPHY_V FEPHY_V_V U FEPHY_V_V0 V RK G_R00XR00XR 00 00nF 0V 00 US0/FEPHY_V0 Embed FEPHY 0 00nF 0V 00 <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

15 R FILTER cs0 cs Xbit R V_R VREF_R_ V_R V_R VREF_R_ V_R V_R V_R VREF_R_ V_R VREF_R_ V_R V_R V_R VREF_R_ V_R V_R V_SYS R_ R_ R_ R_0 R_ R_ R_ R_QS0N R_QS0P R_M0 R_ R_ R_M R_QSN R_QSP R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_0 R_M R_ R_ R_ R_ R_0 R_QSP R_QSN R_ R_ R_ R_ R_QSP R_M R_ R_ R_QSN R_Sn R_OT0 R_OT R_ R_ R_ R_ R_ R_ R_ R_S0n R_0 R_G0 R_0 R_ R_ R_WEn/ R_ R_0 R_LKN R_ R_ R_RSn/ R_LKP R_RST R_ R_Sn/ R_KE R_Tn reate ate: Modify ate: <oc> <oc> <oc> <oc> Friday, July, 0 Monday, ecember, 0 reate ate: Modify ate: <oc> <oc> <oc> <oc> Friday, July, 0 Monday, ecember, 0 reate ate: Modify ate: <oc> <oc> <oc> <oc> Friday, July, 0 Monday, ecember, 0 0 nf 00 0V R00.R R00 % 00 00nF 00 0V 00.uF 00.V 00 00nF 00 0V 0 00nF 00 0V RP00 R RP_00 % 0 00nF 00 0V 0 00nF 00 0V R00 K R00 % R00 K R00 % 0 nf 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 uf 00.V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 00.uF 00.V 00 NP nF 00 0V 0 00nF 00 0V R00 0K R00 % 0 00nF 00 0V 00 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V RP000 R RP_00 % 00 00nF 00 0V R00 R R00 % 00 NP 00 0 nf 00 0V 0 00nF 00 0V R0 R R00 % R00 0R R00 % RP00 R RP_00 % 0 00nF 00 0V 00 00nF 00 0V 0 00nF 00 0V 0 nf 00 0V 0 00nF 00 0V 0 00nF 00 0V U00 RX FG_R00XR00XR0 ML_n/IL_n E QSL_P G QSL_N F N T K_N K K_P K OT K S_n L KE K G0 M N 0 N QU0 QU QU QU QU QU QU QU QL0 G QL F QL H QL H QL H QL H QL J QL J MU_n/IU_n E QSU_P QSU_N 0 P P R N N P P R R R 0/P M T /_n M T WE_n/ L S_n/ M RS_n/ L VREF M TEN N RESET_n P LERT_n P PR T T_n L ZQ F VQ VQ VQ VQ VQ F VQ F VQ G VQ G VQ J VQ0 J V V V V G V J V J V L V L V R V0 T VPP VPP R Q Q Q Q Q Q E Q E Q F Q H Q0 H E E G K K M N T 0 00nF 00 0V 00 00nF 00 0V R0 R R00 % RP00 R RP_00 % 0 nf 00 0V 0 00nF 00 0V U00 TT_.V SOT IN GN EN P OUT 0 nf 00 0V 00 00nF 00 0V 0 uf 00.V RP00 R RP_00 % U00 RX FG_R00XR00XR0 ML_n/IL_n E QSL_P G QSL_N F N T K_N K K_P K OT K S_n L KE K G0 M N 0 N QU0 QU QU QU QU QU QU QU QL0 G QL F QL H QL H QL H QL H QL J QL J MU_n/IU_n E QSU_P QSU_N 0 P P R N N P P R R R 0/P M T /_n M T WE_n/ L S_n/ M RS_n/ L VREF M TEN N RESET_n P LERT_n P PR T T_n L ZQ F VQ VQ VQ VQ VQ F VQ F VQ G VQ G VQ J VQ0 J V V V V G V J V J V L V L V R V0 T VPP VPP R Q Q Q Q Q Q E Q E Q F Q H Q0 H E E G K K M N T 00 00nF 00 0V 00 00nF 00 0V R00 R R00 % 0 00nF 00 0V U000 RX FG_R00XR00XR0 ML_n/IL_n E QSL_P G QSL_N F N T K_N K K_P K OT K S_n L KE K G0 M N 0 N QU0 QU QU QU QU QU QU QU QL0 G QL F QL H QL H QL H QL H QL J QL J MU_n/IU_n E QSU_P QSU_N 0 P P R N N P P R R R 0/P M T /_n M T WE_n/ L S_n/ M RS_n/ L VREF M TEN N RESET_n P LERT_n P PR T T_n L ZQ F VQ VQ VQ VQ VQ F VQ F VQ G VQ G VQ J VQ0 J V V V V G V J V J V L V L V R V0 T VPP VPP R Q Q Q Q Q Q E Q E Q F Q H Q0 H E E G K K M N T 0 uf 00.V 00 00nF 00 0V 0 00nF 00 0V R000 0R R00 % R00.R R00 % RP00 R RP_00 % 0 00nF 00 0V 0 00nF 00 0V 00 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00pF 00 0G 0V NP 0 nf 00 0V 0 00nF 00 0V 00 00nF 00 0V 000 uf 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V R00 0R R00 % U00 RX FG_R00XR00XR0 ML_n/IL_n E QSL_P G QSL_N F N T K_N K K_P K OT K S_n L KE K G0 M N 0 N QU0 QU QU QU QU QU QU QU QL0 G QL F QL H QL H QL H QL H QL J QL J MU_n/IU_n E QSU_P QSU_N 0 P P R N N P P R R R 0/P M T /_n M T WE_n/ L S_n/ M RS_n/ L VREF M TEN N RESET_n P LERT_n P PR T T_n L ZQ F VQ VQ VQ VQ VQ F VQ F VQ G VQ G VQ J VQ0 J V V V V G V J V J V L V L V R V0 T VPP VPP R Q Q Q Q Q Q E Q E Q F Q H Q0 H E E G K K M N T 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 uf 00.V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V R00 0R R00 % 0 uf 00.V 0 00nF 00 0V 0 nf 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 uf 00.V 0 00nF 00 0V 0 00nF 00 0V R- R_ R-0 R- R-0 R- R_ R_0 R_ R_0 R_KE R- R_ R- R_ R-G0 R_G0 R- R_ R-S0n R_S0n R-Sn R_Sn R-RSn/ R_RSn/ R-KE R-LKP R-LKN R-OT0 R_OT0 R- R_ R- R_ R- R_ R-TN R_TN R-WEn/ R_WEn/ R-0 R_0 R-SN/ R_SN/ R_LKP R_RST R_KE R_Sn R_OT R_Tn R_ R_0 R_0 R_ R_LKN R_ R_ R_ R_ R_ R_G0 R_ R_ R_0 R_ R_ R_ R_WEn/ R_Sn/ R_RSn/ R_ R_QSP R_QSN R_ R_QSN R_QSP R_M R_M R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R-Sn R-KE R_RST R-LKP R- R-0 R-0 R- R-Tn R-OT R- R- R- R- R-LKN R-0 R- R- R-G0 R- R-RSn/ R-Sn/ R-WEn/ R- R- R- R- R_ R_M0 R_QS0N R_QS0P R_ R_ R_ R_QSP R_M R_ R-OT R_OT R_ R_ R_0 R_ R_QSN R_ R_ R_ R_ R_ R_ R_0 R_LKN R_LKP R-LKN R-LKP R_LKP R_RST R_KE R_S0n R_OT0 R_Tn R_ R_0 R_0 R_ R_LKN R_ R_ R_ R_ R_ R_G0 R_ R_ R_0 R_ R_ R_ R_WEn/ R_Sn/ R_RSn/ R_ R_QSP R_QSN R_ R_QSN R_QSP R_M R_M R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_0 R_ R_QSN R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_QS0P R_QS0N R_M0 R_ R_0 R_ R_ R_ R_ R_ R_ R_QSP R_M R_ R_ R_ R_ R_ R_ R_ R_ R_M R_ R_QSN R_QSP R_0 R_ R_ R_ R_ R_M R_QSP R_QSN R_0 R-S0n R-KE R_RST R-LKP R- R-0 R-0 R- R-Tn R-OT0 R- R- R- R- R-LKN R-0 R- R- R-G0 R- R-RSn/ R-Sn/ R-WEn/ R- R- R- R- R_ R_M0 R_QS0N R_QS0P R_ R_ R_ R_QSP R_M R_ R_ R_ R_ R_0 R_QSN R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R- R- R- R-

16 US V VUS0 V_SYS 0 0 V M- P+ I GN F MSM00/ E E00 Z-0F ES00 0 0uF/0V 00 0.uF 00 MSM00 uf/0v 00 0.uF 00 ESR US US-M-00-0 MIRO_US_NEW, V_ REOVER R0 0K% R00 R00 0 nf 00 R R00 E ESN ES00 KEY ST-R ST-R <oc> reate ate: Saturday, March, 0 Modify ate: Monday, September, 0

17 V_IO V_S SMM0_0 SMM0_ SMM0_/JTG_TK SMM0_/JTG_TMS SMM0_M SMM0_LK SMM0_ET SMM0_PWREN SMM0_PWREN R0 0K % R00 R0 00K % R00 R nF 0V 00 N % R00 Q00 WPM0-/TR SOT 00 ESN ES00 R0 0K % R00 V_S 0 00nF 0V 00 SMM0_/JTG_TK SMM0_/JTG_TMS SMM0_M SMM0_LK SMM0_0 SMM0_ SMM0_ET 0 0uF 0V 00 R0 R% R00 R0 R% R00 R0 R% R00 R0 R% R00 R0 R% R00 R0 R% R00 R0 R% R00 0 ESXVU ES00 0 ESXVU ES00 0 ESXVU ES00 0 ESXVU ES00 0 ESXVU ES00 0 ESXVU ES00 0 ESXVU ES00 0 T /T M V LK T0 T G G G G J TF-KT0-00 TF_S_SOKET lose to TF T GPIO0_0/LKOUT R0 V_IO U N/T V R0 0R % P P0 0.uF R00 00 R0 0R % P P R00 T_RST N R00 P P I0_SL, I0_S, <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

18 VIO_FLSH V_EMM VIO_FLSH emm_lko VIO_FLSH 00nF 0V 00 R0.uF 0V 00 0R % R00 R0 0K % R00 R 0K % R00 R R% R00 R NP.K% R00 emm_0 emm_m emmlk emm_rst VIO_FLSH V_IO J emm_m emm_ emm_ emm_0 emm_ emm_ emm_ emm_ emm_ emm_rst emmlk emm_0 emm_ emm_ emm_ emm_ emm_ emm_ emm_ emm_m emm_lko emm_rst ON_0PIN_0_SMT TP00 emmlk TP0 Note: emm Update. <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

19 V_SYS V_OTG_V V_OTG_V 00 uf 0V 00 US_HOSTV_EN R0 NP R00 U00 SY0 IN EN SOT VOUT GN O R0.K % R00 M0 + uf/0v 00 M0 + uf/0v 00 J US_JK US-U0G 0 :V :- :+ :GN :V :- :+ :GN E ESN R00.R% R00 L00 N L00 R0.R% R00 R0.R% R00 L0 N L00 R0.R% R00 US0_HOST_M 0 US0_HOST_P 0 OTG0_M 0 OTG0_P 0 US_HOSTV_EN U ES0 SLP0P IN IN IN IN GN GN OUT OUT OUT OUT 0 OTG_ET 0 US0M US0P US0HOSTM US0HOSTP OTG0_M OTG0_P US0_HOST_M US0_HOST_P 0 00nF 0V 00 M00 + uf/0v 00 US0M US0P US0HOSTM US0HOSTP US0M US0P US0HOSTM US0HOSTP <oc> reate ate: Thursday, March 0, 0 Modify ate: Monday, September, 0

20 V_SYS HMI_SL R0 R % R00 VV_HMI 00 W SO_ R0.K % R00 VV_HMI 00 uf 0V 00 _SL HMI_HP Q0 00 SOT R0 R0 K % R00 R0 0K % R00 K % R00 HMIE _SL HMIHP 0 0 J00 HMI_ HMI_ HMI OUT HMI_TX_+ HMI_TX_- HMI_TX_0+ HMI_TX_0- HMI_TX_+ HMI_TX_- HMI_TX_+ HMI_TX_- _S VV_HMI 0 00nF 0V 00 HMI_S R0 R R00 % R0.K % R00 _S HMI_TX_+ HMI_TX_- HMI_TX_+ HMI_TX_- U00 IN IN GN IN IN ES0 SLP0P OUT OUT OUT OUT 0 GN HMI_TX_+ HMI_TX_- HMI_TX_+ HMI_TX_- j<=0.pf R0 K % R00 HMI_E V_IO V_SYS Q0 SK0 SOT HMIE HMIE _SL _S HMIHP HMI_TX_0+ HMI_TX_+ HMI_TX_- U0 IN IN GN IN IN U0 IN IN GN IN IN ES0 SLP0P ES0 SLP0P OUT OUT OUT OUT OUT OUT OUT OUT 0 GN 0 GN HMIE _SL _S HMIHP HMI_TX_0+ HMI_TX_0- HMI_TX_0- HMI_TX_+ HMI_TX_- j<=0.pf j<=0.pf reate ate: Modify ate: <oc> HMI_TX_+ HMI_TX_- HMI_TX_0+ HMI_TX_0- HMI_TX_+ HMI_TX_- HMI_TX_+ HMI_TX_- HMI_HP HMI_E HMI_S HMI_SL Thursday, March 0, 0 Monday, September, 0 0

21 V_IO V_OUT R00 0R % R00 00 N/0pF 00 L00 0 N/.uH N/0pF % 0G L00 0V 00 0 N/0pF 0G 0V N/TS SOT R0 VS_OUT VS N R00 % ROUT LOUT J PJ-00-M 0 N/ESN ES00 R0 0R % R00 0 ESN ES00 0 ESN ES00 V OUT OL 0.uF 0V 00 -Vrms udio Line river R0.K% R00 R0 K % R00 0.nF 0V 00 TPF=0R R0 K % R00 0 pf 0G 0V R0 00.K% 0 R00 nf 0V 00 U00 RVPW /RVPW/ioH /TPF TSSOP-0.MM R0 R R OR 0.uF 0V.K% K % R00.K% 00 R00 R00 pf.nf 0V nf 0V 00 R 0G 0V K % R00 +INL -INL OUTL N PGN 0 PV P +INR -INR OUTR SGN EN P N V_MP R0 R0 0K % R00 0 uf V_MP 当当当当当当 V 时时,R0 R0 阻阻阻阻阻阻 0V 否否否否否否当否 00 0 uf 0V 00 R00 0K % R nF 0V 00 R R% R00 R % R00 R0 0K % R00 V_IO nf 0V 00 NP 0 nf 0V 00 NP ROUT LOUT R 0K % R00 R0 0K % R00 reate ate: Modify ate: V_MP <oc> 0uF V 00 V_OUT OL OR MUTE_TL V_IO Thursday, March 0, 0 L0 0R-00M L00 00nF 0V 00 Monday, September, 0

22 V_SYS 0 0uF/0V 0V nF 00 V US_HOSTV_EN U SY0 SOT IN EN VOUT US_HOSTV_EN GN O R0.K/% R00 0 uf/0v 00 0V 0 00nF 00 V 0 uf/0v 00 0V 0 uf/0v 00 0V 0 uf/0v 00 0V 0 uf/0v 00 0V VV0_HOST ES00 ESN E 0 SHELL SHELL VUS - + GN RX- RX+ GN TX- TX+ VV0_HOST US_M US_P R 0R R 0R US_SSRXN R 0R US_SSRXP R 0R US_SSTXN US_SSTXP 0.uF 0 0.uF US0_M 0 US0_P 0 US0_RXN 0 US0_RXP 0 US0_TXN 0 US0_TXP 0 US0 US0_F_SMT_THF US0_F_P IO IO G E0 ES0F SOT US_SSRXN US_SSRXP US_SSTXN US_SSTXP U ES0 SLP0P IN IN IN IN GN GN OUT OUT OUT OUT 0 US_SSRXN US_SSRXP US_SSTXN US_SSTXP <oc> reate ate: Tuesday, May, 0 Modify ate: Monday, September, 0

23 M_TX0 M_TX M_TX M_TX M_TXEN M_TXLK R00 R % R00 R0 R % R00 R0 R % R00 R0 R % R00 R0 R % R00 R R % R00 M_RX0 M_RX M_RX M_RX M_RXV M_RXLK M_LK M_M M_MIO PHY_RST PHY_TX0 PHY_TX PHY_TX PHY_TX PHY_TXEN PHY_TXLK R0.K % R00 R0.K % R00 R0.K % R00 R0.K % R00 V_LN L LMPGSN L00 0.uF 00 V_LN MI+ MI0- MI- MI+ MI- MI+ MI- MI0+ 0nF 00 R 0R R00 % LE0_0R 0R R00 LINK&T % LE_ RGMII_GR- RGMII_YE- J MI+ MI- MI+ MI0- MI- MI+ MI- MI0+ TT 0 Earth G+ G- Y+ Y- HR0 HR0 PHY_PME PHY_INT M_MIO R K R00 V_LN R K R00 M_RXV R K R00 LE_ V0_EPHY V_LN V0_EPHY MI0+ MI0- MI+ MI- MI+ MI- MI+ MI- U MI[0]+ MI[0]- V0 MI[]+ MI[]- V MI[]+ MI[]- 0 V0 MI[]+ MI[]- N REGOUT GN(EP) REGOUT V_LN PHY_LKOUT VREG GN LK VREG PHY_XTL PHY_XTL V0_EPHY RSET ENSWREG VREG KXTL KXTL V 0 V0 RSET ENSWREG V RXTL/PHY RX0/SELRGV V RX/TXLY RX/N0 RX/N RX INT V TX TX0 TX R V_LN V0 LE/PHY LE0/PHY0 PME LE_RXLY MIO M 0 PHYRST V0 TXTL TX TX.K% R00 LE_ LE0_0 PHY_PME LE_RXLY M_MIO M_M PHY_RST PHY_TXEN PHY_TX PHY_TX PHY_RST 0nF 00 V0_EPHY V0_EPHY R R R PHY ddress=00(rtle) M_RX R M_RX R onfig for all capability K R00 K R00 LE0_0 LE_RXLY Without RX elay M_RX Without TX elay PHY_PME R PHY_INT ENSWREG R R K R00 K R00 K R00 K R00 K R00 0R R00 onnect ENSWREG to V to enable Switching regulator or connect ENSWREG to GN to disable Switching regulator. V_LN V_LN V_LN V_LN V_LN M_LK Y PHY_XTL XOUTGN GN XIN PHY_XTL pf 00 R0 MHz-0ppm RY- R R00 M_RX0 R 0 pf 00 PHY_LKOUT K R00 Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only) V_LN 0 Inductance close to PIN RTLE-V-G PHY_RXV PHY_RX0 PHY_RX PHY_RX PHY_RX PHY_RXLK PHY_INT PHY_TXLK PHY_TX0 PHY_TX REGOUT L.uH/ IN_X V0_EPHY 0uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 V_LN.uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 0.uF 00 V_LN 0 N 00 PHY_RX0 PHY_RX PHY_RX PHY_RX PHY_RXLK PHY_RXV R R R R R R lose to PHY R R00 R R00 R R00 R R00 R R00 R R00 M_RX0 M_RX M_RX M_RX M_RXLK M_RXV VREG lose to PIN. V_LN.uF 00 0.uF 00 V_IO V_LN L LMPGSN L00 <oc> reate ate: Modify ate: Friday, July, 0 Monday, September, 0

24 J ON_X0PIN IP R0 R00 N RK0_KOUT R0 R00 0R GPIO_/LKOUT V_IO, I0_S, I0_SL GPIO U/IS_SO GPIO U/IS_SO GPIO U/IS_SO V_IO GPIO U/SPI_TX GPIO /SPI_RX GPIO_0_U/SPI_LK R0 R00 0R%, I_S_PMI GPIO U/IS_SI GPIO U/IS_SO GPIO_0_U/IS_LRK_RX R 0R % GPIO U/IS_LRK_TX R 0R % R 0R % GPIO /IS_SLK R 0R % GPIO /IS_MLK I_S I_SL EUG_TX EUG_RX /0 V_SYS V_SYS GPIO U/PWM GPIO_0_/SPI_SN0 GPIO_/SPI_SN_M0/FLSH_VOL_SEL R0 0R % URT_TX URT_RX URT_TSN URT_RTSN GPIO/LKOUT/SPIF_TX_M I_SL_PMI, GPIO0_0/LKOUT SPIF_TX_M0 PWRON PWREN J R0 V_IO 0K % 0 URT_RX SO_ N EUG_RX ON-PIN- SIP-P- V_IO REOVER SR_IN J ON-PIN- SIP-P- URT_TX /0 R0 N SO_ R N SO_ % EUG_TX <oc> reate ate: Friday, March, 0 Modify ate: Monday, ecember, 0