hange List Version ate uthor hange Note pproved V harlie First edition ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet:

Transcription

1 RK99_Rock960_V.0 ONTENT INEXING 0.Index 0.hange List 0.Power Tree 0.I Map 0.Power omain Map 06.RK99 Power 07.RK99 PMU ontroler 08.RK99 R ontroler 09.RK99 Flash&SMM ontroler 0.RK99 US/USI ontroler.rk99 SR/Key.RK99 VP Interface.RK99 isplay Interface.RK99 GPIO.RK99 PIE 6.Power- IN 7.Power-PMI RK808-8.US OTG/HOST Port 9.US Type- Port 0.RM-LPR(78P).Memory-eMM.WIFI/TMIMO-P6.TF ard.hmi Output.PIe NGFF/M. 6.ONNETOR TOP GN 6 LYERS P STK(e. g. P=. 6 mm) POWER SIGNL GN OTTOM Prepreg 080* (7um) Prepreg 6* (um) djust ore (6um) Prepreg 6* (um) Prepreg 080* (7um) N o t e : 器件参数说明 : 如果 V a lu e 为 NP, 说明暂时 不 贴 : 如果 Op t io n 有 NP, 说明预留 先 不 贴 H00 H0 H0 H0 HOLE HOLE HOLE HOLE HOLE/PTH/R6. HOLE/PTH/R6. HOLE/PTH/R6. HOLE/PTH/R6. M00 MRK MRK M0 MRK MRK M0 MRK MRK M0 MRK MRK M0 MRK MRK Silkscreen(um) oz(um) Hoz(8um) Hoz(8um) Hoz(8um) Hoz(8um) oz(um) Silkscreen(um) M0 MRK MRK ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet: of 6

2 hange List Version ate uthor hange Note pproved V harlie First edition ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet: of 6

3 RK99 POWER IGRM SY680 Switch V/,80mR 0.u shutdown VUS_TYPE VV0_TYPE0_EN VUS US.0 Type-0 port PMI RK808 UK,0.7-.V T u shutdown V_ENTER V of SO center S0/OFF/OFF 00m/T/T VV0_US.V SY680 Switch V/,80mR 0.u shutdown SY680 Switch V/,80mR 0.u shutdown SY680 Switch V/,80mR 0.u shutdown VV0_HOST0 VV0_HOST_EN VV0_HOST VV0_HOST_EN VV0_HOST VV0_HOST_EN VUS US.0 port VUS US.0 port VUS US.0 port PMI RK808 UK,0.7-.V T u shutdown PMI RK808 UK.,.0-.8V T u shutdown PMI RK808 UK,.8-.V T u shutdown PMI RK808 LO 0m,.8-.V T u shutdown V_PU_L V_R V_V8 VV8_EMM VV8_WIFI VV8_IO VV8_R V of Quard- V of R TRL V/V of R VQ of R V of EMM RTL,VQ of EMM FLSH IO VIO of WIFI+T module VIO/VPST of GPIO S0/OFF/OFF 80m/T/T S0/S/OFF S0/S/OFF 0m/.m/T S0/S/OFF S0/S/OFF m/<m/t S0/S/OFF 0.6m/.m/T S0/S/OFF 0m/0.m/T V of LPR S0/S/OFF 9.7m/90u/T u dapter V VV_IN 0m/m/T SY8 UK,PWM,<u shutdown SY8 UK,PWM,<u shutdown EN always ON EN always ON FUS0 TYPE VONN 00m/u VV0_US.V 0m/8m/T PMI RK808 LO 0m,.8-.V T u shutdown PMI RK808 LO 00m,0.8-.V T u shutdown VV8_HMI V_V8 VV8_PMUIO VV8_PMUPLL VV8_PLL VV8_US VV8_ VV8_PIE V of HMI/MIPI TX phy S0/OFF/OFF.7m/T/T S0/S/OFF m/u/t VIO/VPST of PMUIO S0/S/OFF 9.6m/.0m/T V of PMU PLL S0/S/OFF 8m/0.u/T V of PLL V of US phy S0/S/OFF 0.m/.79m/T V of SR S0/S/OFF.m/<m/T V of PIE phy S0/S/OFF m/<m/t VV0_SYS.0V PMI RK808 LO 0m,.8-.V T u shutdown V_SIO VIO of SMM0 S0/OFF/OFF.m/T/T V_RT V of PMI RT S0/S/S 7.6m/T/0u PMI RK808 LO 00m,.8-.V T u shutdown 89WS VV0_HMI V of HMI evice V_T.V PMI RK808 LO6 0m,0.8-.V T u shutdown V_V VPST of PIO/PIO S0/OFF/OFF 7.m/T/T SY8089 UK,PWM,<u shutdown PMI_EXT_EN PMI RK808 LO7 00m,0.8-.V T u shutdown V0V9_HMI V of HMI/MIPI TX phy S0/OFF/OFF 0.m/T/T VV_SYS RT90-0 LO.0V/00m <u shutdown TT0 J LO 0.9V/00m <u shutdown VV0_S SMM0_PWR_H V_0V9 VV_SYS V0V9_PLL V0V9_PMUPLL V0V9_RPLL V0V9_EMM V0V9_US V0V9_PIE S/TF ard V of PLL V of PMU PLL V of R TRL V of EMM TRL ORE LL V of US phy V of PIE phy S0/OFF/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF S0/S/OFF T/T/T.m/08u/T.m/60u/T.m/8u/T.m/<m/T 0.6m/.m/T 6.m/T/T PMI RK808 LO8 00m,.8-.V T u shutdown PMI RK808 VSW,00mohm T u shutdown PMI RK808 VSW,00mohm T u shutdown V_V0 VV_S0 V of PIO/PIO/PMUIO S0/OFF/OFF.m/T/T RT90-8 LO.8V/00m <u shutdown V_EFUSE EFUSE_VQPS_EN_H V of EFUSE User/OFF/OFF.7m/T/T SYR87PK Switch V/,80mR 0.u shutdown V_PU_ V_V8 V of ual-7 S0/OFF/OFF 0m/T/T VV_ VV_US VV_EMM VV_WL VV_WLIN V of FUS0 V of US phy ORE V of EMM FLSH V of WIFI module VT of WIFI+T module S0/S/OFF S0/S/OFF S0/S/OFF S0/OFF/OFF S0/S/OFF 8.6m/<0.m/T 7.7m/0.m/T 00m/0.m/T 86m/.m/T SYR88PK Switch V/,80mR 0.u shutdown V_GPU V_V8 V of Mali-T86 S0/OFF/OFF 880m/T/T VV_SPIF VV_PIE V of SPIF river I V of PIE evice S0/S/OFF S0/OFF/OFF T/T/T SY8089 UK,PWM,<u shutdown V_LOG V_V8 V of SO Logic S0/S/OFF 90m/7.m/T VV_LE Work LE S0/S/OFF.m/.m/T RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 6

4 I MP Port Pin name omain us name Pull-up voltage Slave evice Slave ddr (MS 7its) Note Slave us apability Rockchip RK808 0xb PMI 00kHz,00KHz I0 GPIO_7/SPI_RX/I0_S GPIO_0/SPI_TX/I0_SL PMUIO I_S_PMI I_SL_PMI V_V8 SYR87PK 0x0 - UK 00kHz,00KHz,.MHz SYR88PK 0x - UK 00kHz,00KHz,.MHz I GPIO_/I_S GPIO_/I_SL PIO V_V8 Low Speed ONNETOR I GPIO_0/VOP_0/IF_0/I_S GPIO_/VOP_/IF_/I_SL PIO V_V8 High Speed ONNETOR I GPIO_0/I_S/URT_RX GPIO_/I_SL/URT_TX PIO I_S_HMI I_SL_HMI V_V0 I GPIO_/I_S GPIO_/I_SL PMUIO I_S_MEMS I_SL_MEMS V_V8 Fairchild FUS0 0x,0x6 US-Type Mux 00kHz,00KHz,MHz I GPIO_/M_RXER/I_S PIO Other pin function GPIO_/M_LK/I_SL I6 GPIO_/SPI_RX/IF_HREF/I6_S GPIO_/SPI_TX/IF_LKIN/I6_SL PIO V_V8 Low Speed ONNETOR I7 GPIO_7/VOP_7/IF_7/I7_S GPIO_0/VOP_LK/IF_VSYN/I7_SL PIO V_V8 High Speed ONNETOR RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

5 Power omain Map Part Port omain Pin name in datasheet I/O type Power supply Power source Part PMUIO pmuio_gpio0ab.8v only V_V8 RK808- VLO Part E PMUIO pmu80_gpioabcd.8v(efault).0v V_V8 RK808- uck Part I PIO gmac_gpioabc.v only V_V8 VV_SYS RK808- uck Part L PIO bt66_gpioab.8v(efault).0v V_V8 RK808- VLO Part G PIO wifi/bt_gpiocd.8v only V_V8 RK808- uck Part K PIO gpio80_gpiocd.8v.0v(efault) V_V V_V0 RK808- VLO6 RK808- VLO8 Part J PIO audio_gpiod_gpioa.8v(efault).0v V_V8 RK808- uck Part F SMM0 sdmmc_gpiob.8v.0v(efault) V_SIO RK808- VLO RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

6 I> I> I> I>. I> lose to SO lose to SO lose to SO lose to SO lose to SO Note:Power filter P please place back of SO or close to SO V_GPU V_PU_L V_LOG V_PU_L V_PU_ V_GPU V_LOG V_PU_ V_ENTER V_ENTER V_GPU_F [7] V_PU F [7] ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 6 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 6 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 6 6 V.0 00 uf 060 6_V 0 uf 060 6_V 09 nf 00 V 0 00nF 00 0V 0 uf 00 0V 000 0uF 00 V 0 uf 060 6_V 0 00nF 00 0V 0 uf 060 6_V 00 0uF 00 V 0 00nF 00 0V 08 nf 00 V 07 00nF 00 0V 00 nf 00 V 00 uf 060 6_V 07 00nF 00 0V U000W RK99 IGPU_V_6 M IGPU_V_7 M IGPU_V_8 L8 IGPU_V_9 N IGPU_V_0 N0 IGPU_V_ L IGPU_V_OM N8 LITPU_V_ P0 LITPU_V_ R9 LITPU_V_ R0 LITPU_V_ P LITPU_V_ T LITPU_V_6 T0 LITPU_V_7 R ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_ M ENTERLOGI_V_6 N ENTERLOGI_V_7 N ENTERLOGI_V_8 P ENTERLOGI_V_9 P ENTERLOGI_V_0 P GPU_V_ W GPU_V_ W GPU_V_ W GPU_V_ V GPU_V_ V GPU_V_6 V GPU_V_7 U GPU_V_8 R GPU_V_9 R GPU_V_0 T GPU_V_ T GPU_V_ T GPU_V_ R GPU_V_ T GPU_V_ V GPU_V_6 V GPU_V_7 V6 GPU_V_8 W6 GPU_V_9 W GPU_V_0 W0 GPU_V_OM T IGPU_V_ L9 IGPU_V_ L IGPU_V_ M8 IGPU_V_ M9 IGPU_V_ M0 LOGI_V_ V LOGI_V_ V LOGI_V_ V0 LOGI_V_ V9 LOGI_V_ V8 LOGI_V_6 W0 LOGI_V_7 U8 LOGI_V_8 U7 LOGI_V_9 M7 LOGI_V_0 L7 LOGI_V_ T7 LOGI_V_ U0 IGPU_V_ K9 IGPU_V_ K 09 00nF 00 0V 00 uf 060 6_V 07 00nF 00 0V 00 0uF 00 V nF 00 0V 0 uf 060 6_V nF 00 0V 0 uf 00 0V 0 nf 00 V 00 00nF 00 0V 00 0uF 00 V 0 00nF 00 0V 0 uf 060 6_V 09 uf 060 6_V 0 00nF 00 0V 0 00nF 00 0V 006 0uF 00 V 06 00nF 00 0V 06 00nF 00 0V 0 uf 00 0V 00 nf 00 V 06 00nF 00 0V U000X RK99 VSS_ Y VSS_ F VSS_ F VSS_ VSS_ VSS_6 6 VSS_7 9 VSS_8 VSS_9 VSS_0 VSS_ VSS_ 0 VSS_ VSS_ 6 VSS_ 9 VSS_6 7 VSS_7 VSS_8 6 VSS_9 VSS_0 9 VSS_ E VSS_ E VSS_ E VSS_ E7 VSS_ E7 VSS_6 VSS_7 F7 VSS_8 F9 VSS_9 G9 VSS_0 H9 VSS_ J6 VSS_ J8 VSS_ J9 VSS_ J VSS_ J VSS_6 J VSS_7 J VSS_8 J7 VSS_9 J8 VSS_0 6 VSS_ 6 VSS_ VSS_ 7 VSS_ VSS_ VSS_6 W VSS_7 J9 VSS_9 U VSS_0 V VSS_ VSS_ 7 VSS_ VSS_ VSS_ VSS_6 9 VSS_7 F8 VSS_8 Y VSS_9 9 VSS_0 F0 VSS_ VSS_ VSS_ 0 VSS_ E VSS_ Y0 VSS_6 VSS_7 VSS_8 VSS_9 0 VSS_0 F9 VSS_ G VSS_ J VSS_ L VSS_ VSS_ 8 VSS_6 9 VSS_7 VSS_8 VSS_9 VSS_0 VSS_ 7 VSS_ 8 VSS_ 0 VSS_ VSS_ VSS_6 VSS_7 6 VSS_8 VSS_9 E VSS_0 E VSS_ E7 VSS_ E VSS_ E VSS_ E8 VSS_ E VSS_6 E VSS_7 E VSS_8 F8 VSS_9 F VSS_0 F8 VSS_ F0 VSS_ F VSS_ G VSS_ G9 VSS_ G8 VSS_6 G7 VSS_7 H VSS_8 H9 VSS_9 H0 VSS_60 H VSS_6 H VSS_6 H VSS_6 H VSS_6 H6 VSS_6 H7 VSS_66 H8 VSS_67 H6 VSS_68 J VSS_69 J6 VSS_70 J7 VSS_7 J8 VSS_7 J9 VSS_7 J0 VSS_7 K8 VSS_7 K9 VSS_76 K0 VSS_77 K VSS_78 K VSS_79 K6 VSS_80 K8 VSS_8 W VSS_8 K0 VSS_8 N9 VSS_8 K VSS_8 L VSS_86 L6 VSS_87 L8 VSS_88 L VSS_89 L VSS_90 L VSS_9 L VSS_9 L VSS_9 L6 VSS_9 N7 VSS_9 Y7 VSS_96 L0 VSS_97 L VSS_98 N VSS_99 L7 VSS_00 M VSS_0 M8 VSS_0 M0 VSS_0 M6 VSS_0 M VSS_0 N8 VSS_06 P VSS_07 P VSS_08 N VSS_09 N VSS_0 N VSS_ N6 VSS_ P VSS_ P6 VSS_ P7 VSS_ P8 VSS_6 P0 VSS_7 P6 VSS_8 Y6 VSS_9 P9 VSS_0 R VSS_ P VSS_ T9 VSS_ R VSS_ R VSS_ R6 VSS_6 U VSS_7 U VSS_8 W VSS_9 R VSS_0 R VSS_ R6 VSS_ VSS_ R VSS_ T8 VSS_ T0 VSS_6 Y VSS_7 U VSS_8 T6 VSS_9 T VSS_0 9 VSS_ U VSS_ U8 VSS_ U VSS_ U6 VSS_ 8 VSS_6 U9 VSS_7 U VSS_8 V7 VSS_9 U VSS_0 U9 VSS_ V VSS_ V VSS_ V8 VSS_ V0 VSS_ Y VSS_6 Y VSS_7 Y VSS_8 W VSS_9 W7 VSS_60 W0 VSS_6 W8 VSS_6 W9 VSS_6 VSS_6 Y VSS_6 R8 VSS_66 Y9 VSS_67 W9 VSS_68 T8 VSS_ VSS_ 7 VSS_ VSS_79 0 VSS_77 VSS_7 J8 VSS_70 Y0 VSS_69 W8 VSS_7 J VSS_7 J VSS_7 J VSS_7 J6 VSS_76 J7 VSS_78 L VSS_80 J0 007 uf 00 0V 09 00nF 00 0V 0 uf 060 6_V 0 uf 060 6_V 0 0uF 00 V 0 uf 060 6_V 00 0uF 00 V 08 00nF 00 0V 08 00nF 00 0V 0 uf 00 0V 06 00nF 00 0V 0 uf 060 6_V 0 uf 060 6_V 08 00nF 00 0V 0 00nF 00 0V 07 00nF 00 0V 0 uf 060 6_V

7 [7,6] Y00 MHz RY_R0XR0X0R80 RESET_L 0 pf 00 0G 0V XIN 00 00nF 00 0V GN GNXOUT 0 pf 00 0G 0V TP00 V_0V9 V_V8 VV8_EFUSE R0 R R00 % T0 Y R0 M R00 % Y0 Y9 R7 P8 P7 U000 RK99 npor_u XIN_OS Note:RK99 part is.8v Only GPIO0_0/TEST_LKOUT0/LKK_IN_u GPIO0_/RIO_PWROFF/TP EN_u GPIO0_/WIFI_6MHz_d GPIO0_/SIO0_WRPT_d GPIO0_/SIO0_INTn_d GPIO0_/EMM_PWRON_u GPIO0_6/PWM_IR_d GPIO0_7/SMM0_ET_u GPIO0_0/SMM0_WRPT/TEST_LKOUT_u GPIO0_/PMUIO_VOLSEL_d XOUT_OS GPIO0 d GPIO0 d GPIO0_/TP_VUS_IS_d GPIO0_/TP_VUS_FIS/TP_VUS_SOURE_d VSS_8 PLL_V_0V9 PLL_V_V8 PLL_VSS EFUSE_VQPS PMUIO_V_V8 PMU_V_0V9 PMU_V_V8 U R9 N V V7 P V8 U8 V0 W U0 V6 P R T U 0 NP 00 R00 0R R00 % RT_LKO_SO [7] SMM0_PWR_H [7] GPIO0_ [6] WIFI_HOST_WKE_L [] T_HOST_WKE_L [] PWR_KEY_L [7] GPIO0_6 [6] TP0 SMM0_ET_L [] R0 00K% R00 NP V_V8 V_0V9 V_V8 T_REG_ON_H [] WIFI_REG_ON_H [] V_0V9 V_V8 VV8_EFUSE 0 00nF 00 0V 0 00nF 00 0V 06 uf 00 0V 07 00nF 00 0V 08 00nF 00 0V 09 00nF 00 0V R0 K R00 % ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet: 7 of 6

8 R FILTER R FILTER Note:R0 cannot be deleted Note:R0 cannot be deleted V_R V_R V_R V_R V_0V9 V_0V9 V_R0_LK V_0V9 V_R_LK V_R V_R0_LK V_R V_R_LK V_0V9 R_6 [0] R_ [0] R_ [0] R_ [0] R_ [0] R_ [0] R_0 [0] R_ [0] R_0 [0] R_9 [0] R_8 [0] R_6 [0] R_7 [0] R_ [0] R_ [0] R_ [0] R_ [0] R_ [0] R_0 [0] R_9 [0] R_8 [0] R_7 [0] R_6 [0] R_ [0] R_ [0] R_ [0] R_ [0] R_ [0] R_0 [0] R_9 [0] R_8 [0] R_7 [0] R_M0 [0] R_M [0] R_M [0] R_M [0] R_QSM [0] R_QSP [0] R_QSM [0] R_QSP [0] R_QSM [0] R_QSP [0] R_QS0M [0] R_QS0P [0] R0_QSM [0] R0_QSP [0] R0_QSM [0] R0_QSP [0] R0_QSM [0] R0_QSP [0] R0_QS0M [0] R0_QS0P [0] R0_6 [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_0 [0] R0_ [0] R0_0 [0] R0_9 [0] R0_8 [0] R0_6 [0] R0_7 [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_0 [0] R0_9 [0] R0_8 [0] R0_7 [0] R0_6 [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_0 [0] R0_9 [0] R0_8 [0] R0_7 [0] R0_M0 [0] R0_M [0] R0_M [0] R0_M [0] R_0 [0] R_ [0] R_ [0] R_ [0] R_ [0] R_6 [0] R_ [0] R_7 [0] R_8 [0] R_9 [0] R_LK [0] R_LKN [0] R_KE0 [0] R_KE [0] R_S0N [0] R_SN [0] R_OT0 [0] R0_0 [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_ [0] R0_6 [0] R0_7 [0] R0_8 [0] R0_9 [0] R0_LK [0] R0_LKN [0] R0_S0N [0] R0_SN [0] R0_KE0 [0] R0_KE [0] R0_OT0 [0] R_0 R_ R_ R_ R_ R_ R0_0 R0_ R0_ R0_ R0_ R0_ R_0 R_ R_ R_SN R_RSN R_WEN R0_0 R0_ R0_ R0_SN R0_RSN R0_WEN R_RST R0_RST R_OT R0_OT ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 8 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 8 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 8 6 V.0 00nF 00 0V 0 0uF 00 V 06 00nF 00 0V 09 uf 060 6_V R00 0R R00 % 00nF 00 0V 8 00nF 00 0V 00nF 00 0V 00 uf 060 6_V 0 0uF 00 V 00nF 00 0V 00nF 00 0V 07 00nF 00 0V 9 00nF 00 0V uf 00 0V 6 00nF 00 0V 0 00nF 00 0V 08 00nF 00 0V 0 uf 00 0V 7 00nF 00 0V 0 00nF 00 0V 00nF 00 0V 0 00nF 00 0V U000 RK99 R_Sn R_0 R_7 7 R_6 7 R_ 8 R_ 9 R_0 0 R_Q8 0 R_Q7 9 R_Q0 R_Q R_Q R_Q 6 R_Q 7 R_Q6 8 R_Q0 R_Q9 R_Q R_Q R_Q R_Q7 R_Q0 R_Q9 6 R_0 R_ R_8 6 R_ 8 R_Sn0 F R_ 9 R_ 0 R_Q R_Q6 9 R_Q9 0 R_Q R_Q0 R_Q 6 R_Q8 R_Q R_Q R_9 6 R_ 6 R_M E0 R_M0 E7 R_M E R_M E R_ R_LK0N 8 R_LK0P 9 R_QSN 0 R_QSP R_ R_ R_Sn F9 R_ R_ G8 R_RSn 6 R_WEn F7 R_LK_V G R_RESET G R_PZQ G RPLL_V_0V9 H R_Q6 R_Q8 R_Q R_Q R_Q7 8 R_Q 7 R_Q 6 R_QS0N 7 R_QS0P 8 R_QSN R_QSP R_QSN R_QSP R_KE0 R_KE E6 R_OT E R_OT0 R_LKP E9 R_LKN E8 R_Sn F R_Sn R_T0 F7 R_T G7 R_PLL_TESTOUT_N G R_PLL_TESTOUT_P F R_V_ J R_V_ J R_V_ J R_V_6 J6 R_V_ J R_V_ J R_V_7 J7 R_V_8 J8 R_V_9 K R_V_0 K R_V_ K R_V_ K7 00nF 00 0V R0 0R R00 % 0 00nF 00 0V R0 0R R00 % R0 0R R00 % U000 RK99 R0_Q0 R0_Q R0_Q R0_Q R0_Q Y R0_Q Y R0_Q6 W R0_Q7 W R0_Q8 F R0_Q9 E R0_Q0 F R0_Q R0_Q E R0_Q R0_Q R0_Q R0_Q6 V R0_Q7 V R0_Q8 U R0_Q9 U R0_Q0 T R0_Q T R0_Q R R0_Q R R0_Q P R0_Q P R0_Q6 N R0_Q7 M R0_Q8 N R0_Q9 L R0_Q0 M R0_Q L R0_LK0P H R0_LK0N J R0_QS0P Y R0_QS0N R0_QSP R0_QSN R0_QSP U R0_QSN V R0_QSP P R0_QSN R R0_Sn0 M6 R0_Sn R0_KE0 E R0_KE F R0_0 R0_ F R0_ M R0_M0 Y R0_M R0_M U R0_M P R0_Sn H6 R0_RSn F R0_0 F R0_ F R0_ G R0_ G R0_ H R0_ H R0_6 J R0_7 J R0_8 K R0_9 K R0_0 R0_ E R0_ R0_ R0_ R0_ H7 R0_RESET L7 R0_WEn G6 R0_PZQ R7 R0PLL_V_0V9 R8 R0_LK_V M7 R0_OT0 L R0_OT L R0_T0 U6 R0_T U7 R0_LKP H R0_LKN J R0_Sn M R0_Sn R0_PLL_TESTOUT_N V7 R0_PLL_TESTOUT_P V6 R0_V_ L9 R0_V_ L0 R0_V_ M9 R0_V_ N9 R0_V_ N0 R0_V_6 P9 R0_V_7 R9 R0_V_8 R0 R0_V_9 T9 R0_V_0 U9 R0_V_ U0 R0_V_ V9

9 U000H RK99 EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_6 EMM_7 EMM_LK EMM_M EMM_STR EMM_LIO EMM_TP EMM_ORELL_0V9 EMM_V_V8 J8 J9 J0 J J6 J7 L K0 L8 J K L9 L0 L K EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_6 EMM_7 R00 R % R00 EMM_LKO EMM_M EMM_STR R0 0K % R00 V_0V9 V_V8 EMM design rule:.ata[0:7] cmd strobe 走线做为 一 组, 并行走线并整组包地, 组内等长要求为 + / - 00mil;. l k 需要单独走线并包地处理, 与 d a t a 间的 延时小 于 0ps;.Max trace length <.9 inchs;.trace impedance 0ohm+/-0%;. 与其他信号间距遵循 W 原则 ; 6. R 0 0 靠近 S O 放置 ; V_0V nF 00 0V V_V8 0 00nF 00 0V EMM_0 [] EMM_ [] EMM_ [] EMM_ [] EMM_ [] EMM_ [] EMM_6 [] EMM_7 [] EMM_LKO [] EMM_M [] EMM_STR [] U000F RK99 GPIO_0/SMM0_0/URT_RX_u GPIO_/SMM0_/URT_TX_u GPIO_/SMM0_/PJTG_TK_u GPIO_/SMM0_/PJTG_TMS_u GPIO_/SMM0_LKOUT/MUJTG_TK_d GPIO_/SMM0_M/MUJTG_TMS_u Y7 Y6 Y8 U7 V9 V SMM0_0 SMM0_ SMM0_ SMM0_ SMM0_LK SMM0_M SMM0_VPST SMM design rule:. a t a [ 0 : ] c m d 走线做为一组, 并行走线并整组包地, 组内等长要求为 + / - 00mil;. l k 需要单独走线并包地处理, 与 d a t a 间的延时小于 0ps; ;.Max trace length <.9 inchs;.trace impedance 0ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; SMM0_0 [] SMM0_ [] SMM0_ [] SMM0_ [] SMM0_M [] SMM0_LK [] SMM0_VPST SMM0_V U6 T 内部产生电压 0 00nF V_SIO V 00nF 00 0V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: 9 of 6

10 U000U RK99 USI_STROE USI_T J0 J USI_V_0V9 USI_V_V US.0 US.0 U000 RK99 U000S RK99 U000T RK99 HOST0_P HOST0_M TYPE0_P TYPE0_M TYPE0_I TYPE0_UVUSET US0_RIS US.0 PHY0 HOST_P HOST_M TYPE_P TYPE_M TYPE_I TYPE_UVUSET US_RIS US.0 PHY US_V_0V9 US_V_V8 US_V_V 0 G H L0 K0 0 G H E6 K 0 V U Y TYPE0_I R00 R R00 % R0 R R00 % V_0V9 V_V8 VV_SYS HOST0_P HOST0_M TYPE0_P [9] TYPE0_M TP00 [9] TYPE0_UVUSET [9] HOST_P [6] HOST_M [6] US_P US_M US.0 PHY0 TYPE0_TXP L TYPE0_TXM K TYPE0_RXP K TYPE0_RXM L TYPE0_TXP L TYPE0_TXM K TYPE0_RXP K TYPE0_RXM L TYPE0_RLKP E8 TYPE0_RLKM 8 H8 TYPE0_ H0 TYPE0_ TYPE0_UXP K0 TYPE0_UXM L0 TYPE0_UXP_P_PU H7 TYPE0_UXM_PU_P G7 9 TYPE0_UVUSET G8 TYPE0_REXT TYPE0_REXT_ G0 Y9 TYPE0_V_0V9_ Y8 TYPE0_V_0V9_ TYPE0_V_V8 TYPE0_V_V 8 8 V_0V9 V_V8 VV_SYS TYPE0_TXP [9] TYPE0_TXN [9] TYPE0_RXP [9] TYPE0_RXN [9] TYPE0_TXP [9] TYPE0_TXN [9] TYPE0_RXP [9] TYPE0_RXN [9] TYPE0_SU [9] TYPE0_SU [9] R0 99R R00 % R0 99R R00 % NP TYPE0_SU_ [9] TYPE0_SU_ [9] US.0 PHY TYPE_TXP TYPE_TXM TYPE_RXP TYPE_RXM TYPE_TXP TYPE_TXM TYPE_RXP TYPE_RXM TYPE_RLKP TYPE_RLKM TYPE_ TYPE_ TYPE_UXP TYPE_UXM TYPE_UXP_P_PU TYPE_UXM_PU_P TYPE_UVUSET TYPE_REXT TYPE_REXT_ TYPE_V_0V9_ TYPE_V_0V9_ TYPE_V_V8 TYPE_V_V L6 K6 K L L8 K8 K7 L7 E0 0 H F K9 L9 E F 9 E G Y Y V_0V9 V_V8 VV_SYS US_SSTXP US_SSTXN US_SSRXP US_SSRXN R0 99R R00 % V_0V9 V_V8 VV_SYS V_0V9 V_V8 VV_SYS 00 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V 0 00nF 00 0V US.0 design rule:.max intra-pair skew < ps;.max trace length < 6 inchs;.max allowed via < 6;.Trace impedance 90ohm+/-0%;. 与其他信号间距遵循 W 原则 ; US.0 design rule:.max intra-pair skew < ps;.max length skew between TX and RX <.6 ns;.max trace length < 6 inchs;.max allowed via < ;.Trace impedance 90ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; P design rule:.max intra-pair skew < ps;.max trace length < 6 inchs;.max allowed via < ;.Trace impedance 90ohm+/-0%;. 与其他信号间距遵循 W 原则 ; RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 0 6

11 U000V RK99 E _IN0 _IN _IN _IN _IN G6 H6 G G8 H7 KEY_IN RM_I RM_I R00 00K% R00 R0 00K% R00 V_V8 E _V V_V nF 00 0V V_V8 0 00nF 00 0V R/RL LPR RM I R0 PU R0 P 0.6V 00K 00K 0.V 0K 0K LPR.V 00K 99K KEY OR N o t e : 系统上电时, 如果 KE Y _IN 电平为 0 V, 则 R K 9 9 进入 R e c o v ery 模式 ; 量产时 R 0, S W 0 0, E 0 可以不用贴片 KEY_IN R0 0K % R00 V_V8 RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

12 U000L RK99 GPIO_0/VOP_0/IF_0/I_S_u GPIO_/VOP_/IF_/I_SL_u GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_/VOP_/IF d GPIO_6/VOP_6/IF_6_d GPIO_7/VOP_7/IF_7/I7_S_u GPIO_0/VOP_LK/IF_VSYN/I7_SL_u GPIO_/SPI_RX/IF_HREF/I6_S_u GPIO_/SPI_TX/IF_LKIN/I6_SL_u GPIO_/SPI_LK/VOP_EN/IF_LKOUT_u GPIO_/SPI_Sn0_u PIO_VPST PIO_V G H H0 F8 H9 F9 H7 G0 H8 F0 H H F J K IF_LKO I7_SL [6] I6_S [6] I6_SL R60 R MIPI_MLK0 [6] R00 R60 R MIPI_MLK R00 VV8_VP 60 00nF 00 0V I_S [6] I_SL [6] PIE_PERST_L [] PIE_PWR [] I7_S [6] MIPI_MLK0 [6] MIPI_MLK [6] U000R RK99 U000P RK99 MIPI_RX0_0P MIPI_RX0_0N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_LKP MIPI_RX0_LKN MIPI_RX0_P MIPI_RX0_N MIPI_RX0_P MIPI_RX0_N MIPI_RX0_REXT K L K L K L K L K L F R600.0K% R00 MIPI_RX0_0P [6] MIPI_RX0_0N [6] MIPI_RX0_P [6] MIPI_RX0_N [6] MIPI_RX0_LKP [6] MIPI_RX0_LKN [6] MIPI_RX0_P [6] MIPI_RX0_N [6] MIPI_RX0_P [6] MIPI_RX0_N [6] MIPI_TX/RX_0P MIPI_TX/RX_0N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_LKP MIPI_TX/RX_LKN MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_REXT K6 L6 K7 L7 K8 L8 K9 L9 K0 L0 F R60.0K% R00 MIPI_TX/RX_0P [6] MIPI_TX/RX_0N [6] MIPI_TX/RX_P [6] MIPI_TX/RX_N [6] MIPI_TX/RX_LKP [6] MIPI_TX/RX_LKN [6] MIPI_TX/RX_P [6] MIPI_TX/RX_N [6] MIPI_TX/RX_P [6] MIPI_TX/RX_N [6] ual MIPI Right MIPI_RX0_V_V8 VV8_VP nF 00 0V MIPI_TX/RX_V_V nF 00 0V VV8_VP ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet: of 6

13 U000N RK99 HMI_TX0P HMI_TX0N HMI_TXP HMI_TXN HMI_TXP HMI_TXN HMI_TP HMI_TN HMI_HP HMI_REXT HMI_V_0V9_ HMI_V_0V9_ HMI_V_V8 K7 L7 K8 L8 K9 L9 K6 L6 E F VV8_HMI HMI_TX0P [] HMI_TX0N [] HMI_TXP [] HMI_TXN [] HMI_TXP [] HMI_TXN [] HMI_TXP [] HMI_TXN [] HMI_HP R700 K R00 % R70.6K R00 % nF 00 0V 70.7uF 060 0V 70 00nF 00 0V PORT_HP [] V0V9_HMI 70.7uF 060 0V U000M RK99 EP_TX0P EP_TX0N EP_TXP EP_TXN EP_TXP EP_TXN EP_TXP EP_TXN EP_UXP EP_UXN EP TP EP_LKM_IN EP_REXT EP_V_0V9 EP_V_V8_ EP_V_V8_ G0 H G H0 J9 J0 HMI design rule:.max intra-pair skew < ps;.max length skew between clk and data < 80 ps;.max trace length < 9.8 inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ EP_VSS_ H9 J U000Q RK99 MIPI_TX0_0P MIPI_TX0_0N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_LKP MIPI_TX0_LKN MIPI_TX0_P MIPI_TX0_N MIPI_TX0_P MIPI_TX0_N MIPI_TX0_REXT MIPI_TX0_V_V8 G H G H G H G H G9 H9 F R70.0K% R00 VV8_VP 70 00nF 00 0V MIPI_TX_0P [6] MIPI_TX_0N [6] MIPI_TX_P [6] MIPI_TX_N [6] MIPI_TX_LKP [6] MIPI_TX_LKN [6] MIPI_TX_P MIPI_TX_N MIPI_TX_P MIPI_TX_N ual MIPI Left ep design rule:.max intra-pair skew < ps;.max trace length < 6 inchs;.max allowed via < ;.Trace impedance 90ohm+/-0%;. 与其他信号间距遵循 W 原则 ; MIPI design rule:.max intra-pair skew < ps;.max length skew between clk and data < 7ps;.Max trace length < 7. inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; ate: RK99_ROK960 Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

14 U000I RK99 Note:RK99 part I is.v only U000E RK99 Note:RK99 part E is.8v/.0v mode GPIO_0/M_TX/SPI_RX_d GPIO_/M_TX/SPI_TX_d GPIO_/M_RX/SPI_LK_u GPIO_/M_RX/SPI_Sn0_u GPIO_/M_TX0/SPI0_RX_d GPIO_/M_TX/SPI0_TX_d GPIO_6/M_RX0/SPI0_LK_u GPIO_7/M_RX/SPI0_Sn0_u F H E0 E 6 G E6 F7 SPI_RX [,6] SPI_TX [,6] SPI_LK [,6] SPI_S [,6] SPI0_RX [,6] SPI0_TX [,6] SPI0_LK [,6] SPI0_S [,6] GPIO_0/ISP0_SHUTTER_EN/ISP_SHUTTER_EN/TP_VUS_SINK_EN_d GPIO_/ISP0_SHUTTER_TRIG/ISP_SHUTTER_TRIG/TP_0_VONN_EN_d GPIO_/ISP0_FLSHTRIGIN/ISP_FLSHTRIGIN/TP VONN_EN_d GPIO_/ISP0_FLSHTRIGOUT/ISP_FLSHTRIGOUT_d GPIO_/ISP0_PRELIGHT_TRIG/ISP_PRELIGHT_TRIG_d GPIO_/P_PWROFF_d GPIO_6/TS_INT_z GPIO_7/SPI_RX/URT_RX_u R T R6 R7 R8 R0 P6 P7 TYPE0 INT_L [9] VV0_TYPE0_EN [9] PMI_SLEEP_H [7] OTP_OUT_H [7] URT_RX [6] GPIO_0/M_M/SPI0_Sn_u GPIO_/M_RXV_d GPIO_/M_RXER/I_S_u GPIO_/M_LK/I_SL_u GPIO_/M_TXEN/URT_RX_u GPIO_/M_MIO/URT_TX_u GPIO_6/M_RXLK/URT_RX_u GPIO_7/M_RS/IF_LKOUT/URT_TX_u E9 7 F G H G6 F 7 M_M [] M_RXV [] M_RXER [] M_LK [] M_TXEN [] M_MIO [] URT_RX [,6] URT_TX [,6] GPIO_0/SPI_TX/URT_TX_u GPIO_/SPI_LK/PMU_JTG_TK_u GPIO_/SPI_Sn0/PMU_JTG_TMS_u GPIO_/I_S_u GPIO_/I_SL_u GPIO d GPIO_6/PWM_IR_d GPIO_7/SPI_RX/I0_S_u R P8 P9 P P0 M M M6 URT_TX [6] GPIO_ [6] GPIO_ [6] I_S_TYPE [9] I_SL_TYPE [9] GPU_SLEEP_H [7] I_S_PMI [7] GPIO_0/M_OL/URT_TSn/SPIF_TX_u GPIO_/M_TXLK/URT_RTSn_u PIO_VPST PIO_V 7 E8 J J URT_TS [,6] URT_RTS [,6] V_V8 VV_SYS GPIO_0/SPI_TX/I0_SL_u GPIO_/SPI_LK_d GPIO_/SPI_Sn0_u GPIO_/PWM_d GPIO_/I8_S_u GPIO_/I8_SL_u GPIO_6/TP_VUS_SOURE0_d GPIO_7/TP_VUS_SOURE_d N0 M7 N M8 M9 M0 L M I_SL_PMI [7] PU SLEEP_H [7] GPIO_ [6] LOG_VS_PWM [7] PMI_INT_L [7] GPIO_7 [6] GPIO_0/TP_VUS_SOURE_d L6 VV_SYS V_V8 FTJTG_TMS_u FTJTG_TRSTn_d PMUIO_VPST N V_V nF 00 0V 80 00nF 00 0V PMUIO_V P V_V8 V_V8 I_S_PMI % R8.K R00 V_V8 U000G Note:RK99 part G is.8v only RK99 E9 GPIO_0/URT0_RX_u H8 GPIO_/URT0_TX_u G8 GPIO_/URT0_TSn_u L GPIO_/URT0_RTSn_u 8 GPIO_/SIO0_0/SPI_RX_u K GPIO_/SIO0_/SPI_TX_u G7 GPIO_6/SIO0_/SPI_LK_u E8 GPIO_7/SIO0_/SPI_Sn0_u H6 GPIO_0/SIO0_M_u F7 GPIO_/SIO0_LKOUT/TEST_LKOUT_u L GPIO_/SIO0_ETN/PIE_LKREQn_u 9 GPIO_/SIO0_PWREN_d F8 GPIO_/SIO0_KPWR_d 8 PIO_V_V8 V_V8 URT0_RX SIO design rule: []. a t a [ 0 : ] c m d 走线做为一组, URT0_TX [] 并行走线并整组包地, 组内等长要求为 + / - 00mil; URT0_TS []. l k 需要单独走线并包地处理, 与 d a t a 间的 URT0_RTS SIO0_0 [] [] 延时小 于 0ps; ; SIO0_ [].Max trace length <.9 inchs; SIO0_ SIO0_ [] [].Trace impedance 0ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; SIO0_M [] SIO0_LK [] PIE_LKREQ_L [] T_WKE_L [] V_V nF 00 0V U000K RK99.8V Only VPST=VIO=.8V.V Only other VPST=.8V,VIO=.V.0V mode:vpst=.v,vio=.0v.8v mode:vpst=.8v,vio=.8v Note:RK99 part J is.8v/.0v mode GPIO_0/I_S/URT_RX_u GPIO_/I_SL/URT_TX_u GPIO_/PWM0/VOP0_PWM/VOP_PWM_d GPIO_/URT_RX_u GPIO_/URT_TX_u GPIO_/SPIF_TX_d GPIO_6/PWM_d GPIO_7/HMI_EINOUT/EP_HOTPLUG_u GPIO_0/PIE_LKREQn_u GPIO_/P_HOTPLUG_d GPIO d GPIO d GPIO d GPIO d GPIO_6_d G6 L F K J K L 7 E6 K H K H J G USER_LE URTG_RX URTG_TX USER_LE USER_LE USER_LE WIFI_LE T_LE 80 00nF 00 0V I_S_HMI [] I_SL_HMI [] HMI_E [] VV0_HOST_EN URTG_RX URTG_TX I_SL_PMI I_S_TYPE I_SL_TYPE % R89 R R00 % R80 R R00 E800 ESN ES00 % R86.K R00 % R87.K R00 % R88.K R00 E80 ESN ES00 J800 ON_P IP ON_P IP V_V8 U000J Note:RK99 part J is.8v/.0v mode RK99 PIO_VPST PIO_V 8 9 V_V V_V0 GPIO_0/IS0_SLK_d GPIO_/IS0_LRK_RX_d GPIO_/IS0_LRK_TX_d GPIO_/IS0_SI0_d GPIO_/IS0_SISO_d GPIO_/IS0_SISO_d GPIO_6/IS0_SISO_d GPIO_7/IS0_SO0_d GPIO_0/IS_LK_d GPIO_/I_S_u GPIO_/I_SL_u GPIO_/IS_SLK_d GPIO_/IS_LRK_RX_d GPIO_/IS_LRK_TX_d GPIO_6/IS_SI0_d GPIO_7/IS_SO0_d PIO_VPST PIO_V G F J Y7 E 6 H H 7 G Y6 F 7 J Y8 V_V8 V_V8 IS0_SLK [6] GPIO_ [6] IS0_LRK_TX [6] IS0_SI0 [6] GPIO_ [6] GPIO_ [6] GPIO_6 IS0_SO0 [6] GPIO_0 [6] I_S [6] I_SL [6] GPIO_ [6] GPIO_ [6] GPIO_ V_V nF 00 0V USER_LE USER_LE USER_LE USER_LE WIFI_LE T_LE R8 K % R00 R8 K % R00 R8 K % R00 R8 K % R00 R8 K % R00 R86 K % R00 LE70 LE_GREEN LE060 LE70 LE_GREEN LE060 LE706 LE_GREEN LE060 LE707 LE_GREEN LE060 LE708 LE_YELLOW LE060 LE709 LE_LUE LE060 V_V V_V nF 00 0V nF 00 0V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 6

15 U000O RK99 PIE_TX0_P PIE_TX0_N PIE_RX0_P PIE_RX0_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_TX_P PIE_TX_N PIE_RX_P PIE_RX_N PIE_RLK_00M_P PIE_RLK_00M_N E0 E F0 F G0 G H0 H F7 F8 0 PIE_TX0P [] PIE_TX0N [] PIE_RX0_P [] PIE_RX0_N [] PIE_TXP [] PIE_TXN [] PIE_RX_P [] PIE_RX_N [] PIE_TXP [] PIE_TXN [] PIE_RX_P [] PIE_RX_N [] PIE_TXP [] PIE_TXN [] PIE_RX_P [] PIE_RX_N [] PIE_REF_LK_P [] PIE_REF_LK_N [] PIE design rule:.max intra-pair skew < ps;.max inter-pair skew <.6 ns;.max trace length < inchs;.max allowed via < ;.Trace impedance 00ohm+/-0%; 6. 与其他信号间距遵循 W 原则 ; PIE_V_0V9 PIE_V_V8 W Y V_0V9 V_V8 V_0V9 V_V nF 00 0V 90 00nF 00 0V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

16 IN&SYSTEM Power J VV_IN R009 0R TP009 VV R06 TP00 To avoid the noise issue 00 0uF 080 V 00 00nF 00 V.V<VIN<8V R00 0K R00 % U000 SY8 SOT 6 VIN GN EN F/OUT LX 6 S nF 00 V L000.uH IN-X. 0.0ohm R00 7K R00 % 00 00pF 00 0G 0V.V/ 00 uf 080 0V VV0_SYS 006 0uF 080 0V nF 00 6V 000 SMFJ8 SO_ R00 0K R00 % To avoid the noise issue 009 0uF 080 V 00 00nF 00 V.V<VIN<8V R00 0K R00 % U00 SY8 SOT 6 VIN GN EN F/OUT LX 6 S nF 00 V L00.uH IN-X. 0.0ohm R006 7K R00 % R008 0K R00 % 0 00pF 00 0G 0V.V/ 0 uf 080 0V VV0_US 0 0uF 080 0V 0 00nF 00 6V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: 6 of 6

17 PMI I>. I> V_ENTER V_PU_L 0 uf 080 0V 0 uf 080 0V [,7] [,7] [,7] [] [7,6] VV0_SYS 0uF 6_V L0 uh 06 IN-X uf..9mohm 080 R0 0 00R V_ENTER9 0V R00 % VV0_SYS uf 0V L0 0 uh..9mohm 6 uf IN-X R0 8 00R V_PU_L9 0V R00 % 7 uf 0V uf 0V uf 0V uf 0V uf 0V uf 0V uf 0V uf 0V uf 0V I_S_PMI I_SL_PMI PMI_SLEEP_H PMI_INT_L RESET_L 00nF 00 6V VV0_SYS VV0_SYS VV0_SYS VV0_SYS VV_SYS V_V VV0_SYS L00 60.uH V_V8 VV8_R V V IN-X V uck uck ohm R00 0R % R060 SW Max. Max SW 07 SW 0.7V-.V.8V-.V 6 uf GN GN GN6 6 uf VF VF VV0_SYS 080 0V 0V 9 V_R I>. LPR:.V V V L0 V uck 8.uH 08 SW6 Max SW IN-X 7pF SW 0.7V-.V uck ohm 00 R GN7 Max 6 0G 0V 00R 0uF uf GN.0V-.8V VF R VF R07 R08 % 6_V 0V 00K K V_R N R00 R00 Feedback from R device 7 % % GN N 7 00nF REF VREF 00 6V GN LO&Switch VREFGN 6 VV8_VP 00nF V.8-.V/0m VLO VV8_HMI 00 6V 6.uF V6.8-.V/0m VLO V_V V 关机可保持系统时间 ; U V/00m 7.7uF VLO low noise VLO V0V9_HMI 060 0V SM-P-. SM-P V/00m 9.uF V7 low noise VLO7 V_SIO 060 0V.8-.V/0m 0.uF 0 GN VLO VV8_MIPI 060 0V T V_RT V9.8-.V/00m 00nF SOT_ VLO V_V 00 6V % V_TTERY 0.8-.V/0m.7uF R0 0R R00 GN V0 low noise VLO6 V_V V VV0_SYS 7.8-.V/00m.uF 6 V VLO V NP 7 0.R Switch 00nF 060 V8 VSWOUT VV_S0 00 6V 6 0.R Switch.uF V VSWOUT V_RT 060 0V VIO VRT 9 8 uf 00 0V GN OSKIN 6 0 pf 00 0G 0V GNP 69 Y00.768KHz S 66 pf M-6 SL OSKOUT 00 0G 0V SLEEP 68 RT_LKO_SO R 0K % R00 VV0_SYS INT always on LKKOUT RT_LKO_WIFI V_V8 67 R 0K % R00 VS LKKOUT V_V8 VS V_RT VSOK OOT0 用于插电开机 uf NRESPWRON OOT EXT_EN 00 ResetKey/VPPOTP EXT_EN PMI_V R 7K % R00 0V PWRON V Top RT Over-temperature Protection [] OTP_OUT_H 00 89WS SO_ V_PU_ power L0 0.uH U0 IN-0 V_V8 VV0_SYS SYR87PK ohm SP0_R96XR6X0R66 8 VIN_ SW_ R09 0uF E VIN_ SW_ E 0 0K E VIN_ SW_ E uf % 0V VIN_ SW_ R R VOUT 00R % R00 6_V 0.6mS EN 060 GN [] PU SLEEP_H I_S_PMI VSEL GN V_PU F [6] 9 00nF I_SL_PMI S GN 00 SL GN 6V GN GN GN6 V_GPU power.uf 060 0V V_RT R0 00K% R00 % R0 0K R00 R06 7K R00 % Q0 O0 SOT_ Q00 S800 SOT_ VPP_OTP uf 6_V 060 RT_LKO_SO [7] RT_LKO_WIFI [] I_SL_PMI [,7] I_S_PMI [,7] PMI_SLEEP_H [,7] PWR_KEY_L [7] uf 6_V 060 V_PU_ uf 6_V 060 V_RT 00 PWR_KEY_L 00nF 6V % R7 0K R00 VPP_OTP PMI_PWRON 0 89WS SO_ U00 RK808- QFN68_7R00X7R00X0R80_T PMI_PWRON [6] V_V8 R 0K R00 % RESET_L SW00 T-6E T-6E nf 00 X7R 0V R6 M R00 % VV_SYS [] R8 0K % R00 0.6mS GPU_SLEEP_H 00nF 00 6V VV0_SYS 6 0uF 0V 080 I_S_PMI I_SL_PMI E E U0 SYR88PK SP0_R96XR6X0R66 VIN_ SW_ VIN_ SW_ E VIN_ SW_ E VIN_ SW_ VOUT EN GN VSEL GN S GN SL GN GN GN GN6 R9 00R L0 0.uH IN ohm % R00 V_GPU_F [6] 7 uf 6.V uf 6.V uf 6.V 060 V_GPU 0 uf 6.V 060 V_0V9 power U06 VV_SYS LP98SF-08/SGM06-J SOT IN F/OUT 68 R8 uf 7K 00 R00 0V % GN SHN P TT0_J R 8K R00 % 6 7pF 00 0G 0V R9 0K R00 % R 8K R00 % 6.7uF 060 0V V_0V9 6 00nF 00 6V V_LOG power [] VV0_SYS V_V8 LOG_VS_PWM V_LOG: Min=0.8V; efault=0.9v; Max=.V; E00 ESN ES00 0uF 080 0V R0 7K R00 % V_V8 R 8K R00 % R7.9K R00 % 00nF 00 6V U0 SY8088/PT09/ SOT VIN LX GN EN F/OUT R8 K R00 % L06.uH IN-X. 0.08ohm R6 8K R00 % 6 nf 00 V R 00R R00 % V_LOG R 00K R00 % R9 00K R00 % 6 00pF 00 0G 0V uf 6_V 060 V_LOG 00nF 00 6V VV_SYS power VV0_SYS VV0_S power VV_SYS 7 0uF R 0V 080 EXT_EN U0 SY8089 SOT VIN LX % GN N/60K R00 NP EN F/OUT 6 00nF R K% 6V R00 U07 SGM08-.0/LP987H0F VV0_S SOT IN OUT 66 R0.7uF 0K GN 060 R00 % EN P 0V SMM0_PWR_H [7] 69 00nF 00 6V 67.7uF 060 0V L07.uH IN-X. 0.08ohm 8 00pF 0G 0V 00 R K R00 % R 0K R00 % VV_SYS 9 0uF 6_V nF 00 6V 70 0uF 6_V 060 RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 7 6

18 US.0 port HOST0_P [0] HOST0_M [0] VV0_HOST_EN [] VV0_US VV0_HOST_EN U0 SY680 SOT IN EN VOUT GN O VV0_HOST R0.7K R00 % 0 0uF 080 0V VV0_HOST 0 00nF 00 6V 0 0uF 080 0V HOST0_M HOST0_P E0 ESN ES00 F0 90R-00M OMMON-OILP U0 ES0F SOT_ US0 US-HU_PORT US0_US_F_0_00 6 :V :- :+ :GN US_P [0] US_M [0] US_SSTXP [0] US_SSTXN [0] US_SSRXP [0] US_SSRXN [0] US.0 port VV0_US VV0_HOST_EN U0 SY680 SOT IN EN VOUT GN O R0.7K % R00 VV0_HOST 06 0uF 080 0V US_M US_P US_SSRXN US_SSRXP F0 90R-00M OMMON-OILP US_SSTXN07 00nF 00 0V US_SSTXP08 00nF 00 0V VV0_HOST U0 ES0F SOT_ 09 0uF 080 0V E0 ESN ES VUS - + GN RX- RX+ GN TX- TX+ SHELL SHELL 0 US0 US0_ US0_F_9P US_SSRXN US_SSRXP US_SSTXN US_SSTXP U06 TPE0U06 SON0_R0XR00X0R0 IN IN OUT OUT 0 9 US_SSRXN US_SSRXP IN IN OUT OUT 7 6 US_SSTXN US_SSTXP GN GN 8 RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: 8 of 6

19 US Type- port VUS_TYPE R606 K % R00 R607 8K R00 % TYPE0_UVUSET 60 00nF 00 6V TYPE0_SU nF 00 0V TYPE0_SU 60 00nF 00 0V TYPE0_SU_ R60 00K% R00 TYPE0_SU_ [0] [0] [0] [0] [0] [0] [0] [0] R60 00K% R00 TYPE0_TXN TYPE0_TXP TYPE0_RXN TYPE0_RXP TYPE0_TXN TYPE0_TXP TYPE0_RXN TYPE0_RXP TYPE_UXP TYPE_UXM R60 M R00 % R600 M R00 % VUS_TYPE R60 N/.R/% R00 TYPE0_M F600 90R-00M TYPE0_P OMMON-OILP R60 R00 N/.R/% 60 00nF 00 0V 60 00nF 00 0V 60 00nF 00 0V nF 00 0V TYPE_ TYPE_ TYPE0TXN TYPE0TXP TYPE0TXN TYPE0TXP J600 US_TYPE_H0 US_TYPE_H0 9 VUS_ VUS_ 9 VUS_ VUS_ 8 8 SU SU 7 6 M 7 P 6 M P SSTX_N SSTX_P 0 SSRX_N SSRX_P SSTX_N SSTX_P 0 SSRX_N SSRX_P GN GN GN GN HOLE_ HOLE_ GN_E GN_E GN_E GN_E GN_E GN_E6 GN_E7 GN_E8 H H E E E E E E6 E7 E8 I_SL_TYPE [] I_S_TYPE [] TYPE0 INT_L [] TYPE0_M [0] TYPE0_P [0] VV0_TYPE0_EN [] TYPE0_UVUSET [0] TYPE0_SU [0] TYPE0_SU [0] TYPE0_SU_ [0] TYPE0_SU_ [0] TRL U600 FUS0MPX MLP_R0XR0X0R80 Limit switch TYPE_ TYPE_ 607 0pF 00 0G 0V 608 0pF 00 0G 0V _0 _ N N GN ep VUS VONN_ VONN_ V 6 SL S 7 INT# VUS_TYPE VV0_US VV_SYS I_SL_TYPE I_S_TYPE TYPE0 INT_L VV0_US 6 uf 0V nF 00 6V VV0_US 609 0uF 0V uf 080 0V VV0_TYPE0_EN EN U60 SY680 SOT IN VOUT GN O R608.7K R00 % 6 0uF 080 V VUS_TYPE 6 uf 080 0V ES TYPE0TXN TYPE0TXP TYPE0_RXP TYPE0_RXN IN IN IN IN GN GN 8 OUT OUT OUT OUT TYPE0TXN TYPE0TXP TYPE0_RXP TYPE0_RXN U60 TPE0U06 SON0_R0XR00X0R0 TYPE0TXN TYPE0TXP TYPE0_RXP TYPE0_RXN IN IN IN IN GN GN 8 OUT OUT OUT OUT TYPE0TXN TYPE0TXP TYPE0_RXP TYPE0_RXN U60 TPE0U06 SON0_R0XR00X0R0 TYPE0_M TYPE0_P U60 ES0F SOT_ TYPE_ TYPE_ U60 ES0F SOT_ TYPE_UXP TYPE_UXM U606 ES0F SOT_ RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 9 6

20 LPR R_LK R_LKN R0_LK R0_LKN V_R V_R VV8_R VV8_R V_R VV8_R V_R V_R V_R VV8_R V_R VREFQ_R VREFQ_R0 VREFQ_R V_R V_R V_R VREF_R VREF_R0 V_R V_R VREF_R V_R VREF_R0 VREFQ_R0 R_QS0P R_QS0M R_QSP R_QSM R_M0 R_M R_0 R_ R_ R_ R_ R_ R_6 R_7 R_ R_ R_6 R_7 R_8 R_9 R_0 R_ R0_M R0_ R0_ R0_6 R0_7 R0_8 R0_9 R0_0 R0_0 R0_ R0_ R0_ R0_ R0_ R0_6 R0_7 R0_ R0_QS0P R0_QS0M R0_QSP R0_QSM R0_M0 R_ R_ R_0 R_ R_ R_ R_7 R_6 R_9 R_8 R_LK R_LKN R_S0N R_SN R_KE0 R_KE R_OT0 R0_0 R0_ R0_ R0_ R0_ R0_ R0_6 R0_7 R0_9 R0_8 R0_LK R0_LKN R0_S0N R0_SN R0_KE0 R0_KE R0_OT0 R0_8 R0_6 R0_7 R0_9 R0_0 R0_ R0_ R0_ R0_ R0_8 R0_9 R0_0 R0_ R0_ R0_ R0_ R_8 R_9 R_0 R_ R_ R_ R_ R_ R_8 R_6 R_7 R_9 R_0 R_ R_ R_ R_QSP R_QSM R_QSP R_QSM R_M R_M R0_QSP R0_QSM R0_QSP R0_QSM R0_M R0_M ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 0 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 0 6 V.0 ate: esigned by: Sunday, November, 07 RK99_ROK960 <designer> 0 6 V nF 00 6V R60 0R R00 % 6 00nF 00 6V R606 0K R00 % 66 nf 00 X7R 0V 66 00nF 00 6V 69 00nF 00 6V 68 NP nF 00 6V R600 0R R00 % R6 R R00 % 67 00nF 00 6V 69 00nF 00 6V 66 0uF 060 6_V 69 00nF 00 6V 6 00nF 00 6V 68 00nF 00 6V 66 0uF 060 6_V 6 00nF 00 6V 6 0uF 060 6_V R6 K R00 % 60 00nF 00 6V 68 00nF 00 6V R608 0K R00 % nF 00 6V 60 uf 00 0V R60 0K R00 % R6 R R00 % U600 FG78_R00XR0XR0 KE8E0EE-EGE R_0 P9 R_ N9 R_ N0 R_ N R_ M8 R_ M9 R_6 M0 R_7 M R_8 F R_9 F0 R_0 F9 R_ F8 R_ E R_ E0 R_ E9 R_ 9 R_6/N T8 R_7/N T9 R_8/N T0 R_9/N T R_0/N R8 R_/N R9 R_/N R0 R_/N R R_/N R_/N 0 R_6/N 9 R_7/N 8 R_8/N R_9/N 0 R_0/N 9 R_/N 8 R_QS0 L0 R_QS0n L R_QS G0 R_QSn G R_QS P0 R_QSn P R_QS 0 R_QSn R_M0 L8 R_M G8 R_M/N P8 R_M/N 8 R_0 R R_ P R_ N R_ N R_ M R_ F R_6 E R_7 E R_8 R_9 R_LK J R_LKn J R_S0 L R_S L R_VREF H R_ZQ0 R_KE0 K R_KE K NU NU NU NU NU NU6 V_0 8 V_ V_ VQ_7 VQ_6 V_9 9 VQ_ E8 VQ_ E VQ_ G V_8 VQ_ H8 VQ_ H9 V_7 R_VREFQ J VQ_0 H VQ_9 J9 VQ_8 J0 V_6 6 VQ_7 K8 V_ VQ_6 K VQ_ L NU7 T V_ G V_ 6 NU8 T NU9 U NU0 U NU U NU U R_ZQ V_ 0 V_6 U V_7 U V_8 U V_9 U6 V_0 U0 VQ_ N8 VQ_ N VQ_ R VQ_ U V_8 K6 V_9 K V_0 J6 V_ J V_ H V_ H6 V_ H V_ U9 V_ U8 V_ P6 V_ P V_ P V_6 L V_7 K V M V L V H V G V F VSS VSS VSS VSS E VSS E VSS6 F VSS7 H VSS8 J VSS9 K VSS0 L6 VSS M VSS N VSS N VSS R VSS R VSS6 T VSS7 T VSS8 T VSS9 T VSSQ 6 VSSQ VSSQ 6 VSSQ VSSQ E6 VSSQ6 F6 VSSQ7 F VSSQ8 G6 VSSQ9 G9 VSSQ0 H0 VSSQ K0 VSSQ L9 VSSQ M6 VSSQ M VSSQ N6 VSSQ6 P VSSQ7 R6 VSSQ8 T6 VSSQ9 T VSS VSS VSS F VSS G VSS G VSS6 J VSS7 M VSS8 P R_OT J8 N N K9 N R 6 0uF 060 6_V 66 00nF 00 6V 6 nf 00 X7R 0V 6 00nF 00 6V R R R00 % R609 K R00 % 608 0uF 060 6_V U60 FG78_R00XR0XR0 KE8E0EE-EGE R_0 P9 R_ N9 R_ N0 R_ N R_ M8 R_ M9 R_6 M0 R_7 M R_8 F R_9 F0 R_0 F9 R_ F8 R_ E R_ E0 R_ E9 R_ 9 R_6/N T8 R_7/N T9 R_8/N T0 R_9/N T R_0/N R8 R_/N R9 R_/N R0 R_/N R R_/N R_/N 0 R_6/N 9 R_7/N 8 R_8/N R_9/N 0 R_0/N 9 R_/N 8 R_QS0 L0 R_QS0n L R_QS G0 R_QSn G R_QS P0 R_QSn P R_QS 0 R_QSn R_M0 L8 R_M G8 R_M/N P8 R_M/N 8 R_0 R R_ P R_ N R_ N R_ M R_ F R_6 E R_7 E R_8 R_9 R_LK J R_LKn J R_S0 L R_S L R_VREF H R_ZQ0 R_KE0 K R_KE K NU NU NU NU NU NU6 V_0 8 V_ V_ VQ_7 VQ_6 V_9 9 VQ_ E8 VQ_ E VQ_ G V_8 VQ_ H8 VQ_ H9 V_7 R_VREFQ J VQ_0 H VQ_9 J9 VQ_8 J0 V_6 6 VQ_7 K8 V_ VQ_6 K VQ_ L NU7 T V_ G V_ 6 NU8 T NU9 U NU0 U NU U NU U R_ZQ V_ 0 V_6 U V_7 U V_8 U V_9 U6 V_0 U0 VQ_ N8 VQ_ N VQ_ R VQ_ U V_8 K6 V_9 K V_0 J6 V_ J V_ H V_ H6 V_ H V_ U9 V_ U8 V_ P6 V_ P V_ P V_6 L V_7 K V M V L V H V G V F VSS VSS VSS VSS E VSS E VSS6 F VSS7 H VSS8 J VSS9 K VSS0 L6 VSS M VSS N VSS N VSS R VSS R VSS6 T VSS7 T VSS8 T VSS9 T VSSQ 6 VSSQ VSSQ 6 VSSQ VSSQ E6 VSSQ6 F6 VSSQ7 F VSSQ8 G6 VSSQ9 G9 VSSQ0 H0 VSSQ K0 VSSQ L9 VSSQ M6 VSSQ M VSSQ N6 VSSQ6 P VSSQ7 R6 VSSQ8 T6 VSSQ9 T VSS VSS VSS F VSS G VSS G VSS6 J VSS7 M VSS8 P R_OT J8 N N K9 N R R60 0R R00 % 6 0uF 060 6_V 600 0uF 060 6_V nF 00 6V 67 nf 00 X7R 0V 67 00nF 00 6V 60 00nF 00 6V 6 nf 00 X7R 0V 6 00nF 00 6V R60 768R R00 % 6 uf 00 0V 60 00nF 00 6V 67 NP nf 00 X7R 0V 60 nf 00 X7R 0V 607 nf 00 X7R 0V 60 00nF 00 6V 6 00nF 00 6V 60 00nF 00 6V 6 00nF 00 6V 6 uf 00 0V R6 R R00 % 68 00nF 00 6V 60 00nF 00 6V 67 uf 00 0V 6 0uF 060 6_V 6 00nF 00 6V 6 nf 00 X7R 0V 6 nf 00 X7R 0V 6 nf 00 X7R 0V R60 0R R00 % 6 00nF 00 6V R60 0K R00 % 6 nf 00 X7R 0V 6 00nF 00 6V 60 00nF 00 6V R6 R R00 % 69 00nF 00 6V 60 nf 00 X7R 0V 6 0uF 060 6_V

21 emm FLSH U000 KLM8GGE-0 INN_69 V_V8 EMM_0 EMM_M TP000 TP00 [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] EMM_0 EMM_ EMM_ EMM_ EMM_ EMM_ EMM_6 EMM_7 EMM_M EMM_LKO V_V8 EMM_STR R000 0K % R uF 060 0V H H H J J J J J6 W W6 U K R M9 M0 N0 U0 T0 T T T T T T6 T7 M LK RST_n Vi RLK VSF VSF VSF VSF VQ VQ VQ VQ VQ V V V V VSS VSS VSS VSS VSS VSS6 VSSQ VSSQ VSSQ VSSQ VSSQ Y W K6 U9 T0 N M6 U8 R0 P M7 H6 T 6 Y Y K VV_SYS VV_SYS VV_SYS V_V8 006 uf V 00.7uF 060 0V 00 00nF 00 6V 00.7uF 060 0V 00 00nF 00 6V SW00 T-6E T-6E Note: Reserve P for Update. EMM_LKO TP007 TP008 RK99_ROK960 E00 ESN ES00 ate: esigned by: Sunday, November, 07 V.0 <designer> Sheet: of 6

22 J600 W006 NT GN NT0 NT60 GN GN NT NT_IPEX NT_ON 6 NP pF 00 0G 0V SIO WIFI/T MOULE-MIMO RF Microstrip Z0= 0 ohm RF Microstrip Z0= 0 ohm 60 0pF 00 0G 0V 60 NP 00 NT60 NT GN GN NT_IPEX NT_ON J60 W006 NT GN NT0 SIO0_0 [] SIO0_ [] SIO0_ [] SIO0_ [] SIO0_M [] SIO0_LK [] URT0_RTS [] URT0_TX [] URT0_RX [] URT0_TS [] T_HOST_WKE_L [7] T_WKE_L [] T_REG_ON_H [7] WIFI_REG_ON_H [7] WIFI_HOST_WKE_L [7] RT_LKO_WIFI [7,] U600 /P66S P66S P GN_9 GN_8 WL_NT GN_7 GN_6 GN_ GN_ GN_ GN_ WL/T_NT0 GN_ 606 8pF 00 0G 0V Y600 7.MHz RY_R0XR0X0R80 GNXOUT XIN GN R600 R % R pF 00 0G 0V WIFI_REG_ON_H WIFI_HOST_WKE_L 6 /SIO_M 7 /SIO_LK 8 /SIO_ 9 /SIO_ 0 /SIO_0 /SIO_ P_PU/PIE_PERST XTL_OUT XTL_IN WL_REG_ON WL_HOST_WKE SIO_T_M SIO_T_LK SIO_T_ SIO_T_ SIO_T_0 SIO_T_ GN_0 N/PIE_PME_L VIN_LO T_HOST_WKE 0 T_WKE 9 8 GPIO8_9/MOE SEL PIE_TP/N 7 PIE_TN/N 6 PIE_RP/N PIE_RN/N URT_TS_N URT_RTS_N URT_RX URT_TX 0 9 GN_ T_REG_ON 8 7 PIE_LKREQ_L/P_P T_HOST_WKE_L T_WKE_L URT0_RTS URT0_TS URT0_TX URT0_RX T_REG_ON_H 608.7uF 060 0V VIN_LO_OUT PM_SYN PM_IN PM_OUT PM_LK LPO GN_ N/PIE_REFLK_N VIO N/PIE_REFLK_P VT /SIO_0 /SIO_ /SIO_ R60 R % R00 R60 R % R00 R60 R % R00 SIO0_0 SIO0_ SIO0_ [7,] RT_LKO_WIFI L600.7uH IN_ ohm up to V_V8 6.7uF 060 0V 66 00nF 00 6V 67 0uF V VV_SYS 68 0uF V 69 00nF 00 6V 6 00 NP /SIO_ /SIO_MR60 R % R00 /SIO_LK R60 R % R00 R606 R % R00 SIO0_ SIO0_M SIO0_LK RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

23 TF R [9] SMM0_ [9] SMM0_ [9] SMM0_M [9] SMM0_LK [9] SMM0_0 [9] SMM0_ [7] SMM0_ET_L R800 R R00 % R80 R R00 % R80 R R00 % R80 0R R00 % R80 R R00 % R80 R R00 % R806 R R00 % VV0_S J800 TF-KT0-009 TFK_ T /T M V LK VSS T0 T G G G G E800 ESN ES00 E80 ESN ES00 E80 ESN ES00 E80 ESN ES00 E80 ESN ES00 E80 ESN ES00 E806 ESN ES00 VV0_S 800 0uF V 80 00nF 00 6V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

24 HMI Output HMI_TXP HMI_TXN HMI_TX0P HMI_TX0N PORT_E _SL PORT_HP J800 HMI_ HMI9S HMI_TXP HMI_TXN HMI_TXP HMI_TXN _S nF 00 6V VV0_HMI 80 uf 00 0V HMI_TXP HMI_TXN HMI_TXP HMI_TXN U800 TPE0U06 SLP0P8 NP IN IN IN IN GN GN OUT OUT OUT OUT HMI_TX0P [] HMI_TX0N [] HMI_TXP [] HMI_TXN [] HMI_TXP [] HMI_TXN [] HMI_TXP [] HMI_TXN [] HMI_E [] PORT_HP [] I_SL_HMI [,] I_S_HMI [,] HMI_TXP HMI_TXN HMI_TXP HMI_TXN V_V0 VV0_SYS WS SO_ VV0_HMI HMI_TX0P HMI_TX0N HMI_TXP HMI_TXN U80 TPE0U06 SLP0P8 NP IN IN IN IN GN GN OUT OUT OUT OUT HMI_TX0P HMI_TX0N HMI_TXP HMI_TXN 8 [,] I_SL_HMI V_V0 R800.7K R00 % Q800 SK08 SOT_ VV_SYS 8 VV_SYS R80.K R00 % _SL 80 89WS SO_ PORT_E _SL _S PORT_HP U80 TPE0U06 SLP0P8 NP IN IN IN IN GN GN OUT OUT OUT OUT PORT_E _SL _S PORT_HP [,] I_S_HMI R80.7K R00 % R80 R80 R80.K 6K 6K R00 R00 R00 % % % _S HMI_E PORT_E 8 Q80 SK08 SOT_ Q80 SK08 SOT_ RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

25 PIe NGFF/M. U800 M. NGFF MKEY SOKET [] [] [] PIE_RX_N [] PIE_RX_P [] PIE_TXN [] PIE_TXP [] PIE_RX_N [] PIE_RX_P [] PIE_TXN [] PIE_TXP [] PIE_RX_N [] PIE_RX_P [] PIE_TXN [] PIE_TXP [] PIE_RX0_N [] PIE_RX0_P [] PIE_TX0N [] PIE_TX0P PIE_REF_LK_N PIE_REF_LK_P 8 00nF 00 0V 8 00nF 00 0V 8 00nF 00 0V 8 00nF 00 0V 8 00nF 00 0V 80 00nF 00 0V nF 00 0V 80 00nF 00 0V [] M_MIO GN GN PERn PERp GN PETn PETp GN PERn PERp GN PETn PETp GN PERn PERp GN PETn PETp GN PERn0/ST-+ PERp0/ST-- GN PETn0/ST-- PETp0/ST-+ GN REFLKN REFLKP GN N PEET GN GN GN PIE M. NGFF M-KEY SOKET GN GN.V.V N 6 N 8 0 S/SS#.V.V.V 6.V 8 N 0 N N N 6 N 8 N 0 N N N 6 EVSLP 8 N 0 N N N 6 N 8 0 PERST# LKREQ# PEWake# N 6 N 8 SUSLK 68.V 70.V 7.V 7 VV_PIE R807 N R00 R808 N R00 R809 N R00 R80 N R00 R8 N R00 R8 N R00 R8 N R00 R8 N R00 R86 N R00 R87 N R00 R88 N R00 R89 N R00 R80 N R00 PIE_PERST_V_L PIE_LKREQ_V_L VV_PIE M_LK [] SPI_RX [,6] SPI_TX [,6] SPI_LK [,6] SPI_S [,6] SPI0_RX [,6] SPI0_TX [,6] SPI0_LK [,6] SPI0_S [,6] M_RXER [] M_M [] URT_TS [,6] URT_RTS [,6] URT_RX [,6] URT_TX [,6] M_TXEN [] M_RXV [] [] PIE_PERST_L V_V8 VV_PIE Q80 R8 WNM0-/TR 7K SOT_ R00 % PIE_PERST_V_L 77 V_V8 VV_PIE 76 VV_SYS 86 uf V VV_SYS 80 00nF 00 6V R80 00K R00 % Q80 O0 SOT_ VV_PIE 80 0uF V 80 00nF 00 6V VV_PIE N o t e :. V 供电电流至少. [] PIE_LKREQ_L Q80 R806 WNM0-/TR 7K SOT_ R00 % PIE_LKREQ_V_L [] PIE_PWR R8 0K % R00 Q80 MMT90 SOT_ 80 uf V 806 uf V 807 0uF V nF 00 6V nF 00 6V RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> Sheet: of 6

26 注意 : 需要电压 V > = V V_V8 ON8600 URT_TS- GN GN URT_TX- URT0-TS PWR-TN-N PMI_PWRON [7] URT_RX- URT0-TX RST-TN-N 6 SPI0_LK- RESET_L [7,7] 7 URT_RTS- URT0-RX SPI0-SLK 8 9 SPI0_RX- URT0-RTS SPI0-IN 0 SPI0_S- [] URT_TX URT-TX SPI0-S SPI0_TX- [] URT_RX [] I6_SL URT-RX SPI0-OUT I0-SL PM-FS/IS-W 6 IS0_LRK_TX [] [] I6_S 7 I0-S PM-LK/IS- 8 IS0_SLK [] [] I_SL 9 I-SL PM-O/IS-O 0 IS0_SO0 [] [] I_S IS0_SI0 [] [7] IR GPIO0_6 I-S PM-I/IS-I GPIO- GPIO- GPIO0_ [7] [] GPIO_ GPIO- GPIO- 6 GPIO_ [] [] GPIO_ 7 8 GPIO_0 [] [] GPIO_ 9 GPIO-E GPIO-F GPIO-G GPIO-H 0 GPIO_ [] [] GPIO_ GPIO_ [] [] GPIO_ GPIO-I GPIO-J GPIO-K GPIO_7 [] V_V8 GPIO-L +V8 SYS-IN 6 VV_IN VV0_SYS 7 +V SYS-IN 8 9 GN GN 0 SPI0_RX- SPI0_TX- SPI0_LK- SPI0_S nF 00 GN V GN U80 V PIULSV0GEX VV_SYS V_V8 OE SPI0_RX [,] SPI0_TX [,] SPI0_LK [,] SPI0_S [,] GN 86 00nF 00 V_V8 VV_SYS X0-F-MM SPI_RX- SPI_TX- SPI_LK- SPI_S nF 00 V_V8 URT_RX- URT_TX- URT_TS- URT_RTS nF 00 GN GN V GN U80 V PIULSV0GEX V GN U80 V PIULSV0GEX V_V8 OE VV_SYS V_V8 OE SPI_RX [,] SPI_TX [,] SPI_LK [,] SPI_S [,] GN GN URT_RX [,] URT_TX [,] URT_TS [,] URT_RTS [,] nF nF 00 [] [] [] [] [] [] [] [] [] [] [] [] [0] [0] MIPI_MLK0 MIPI_MLK MIPI_TX/RX_LKP MIPI_TX/RX_LKN MIPI_TX/RX_0P MIPI_TX/RX_0N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_P MIPI_TX/RX_N HOST_P HOST_M GN SPI_S- SPI_LK- SPI_RX- SPI_TX- SI0-+ SI0-- GN 6 8 SI SI0-0- GN SI0-+ 6 SI0-- GN 8 0 SI0-+ SI0-- GN 6 SI0-+ 8 SI0-- GN 0 I-SL I-S 6 I-SL I-S 8 GN 0 SI-0+ SI-0- GN 6 8 SI-+ 0 SI-- GN SI-+ 6 SI-- GN 8 RESERVE 60 ON860 S-0/SPI-OUT S- 7 S- 9 S-/SPI-S S-LK/SPI-SLK S-M/SPI-IN GN 7 LK0/SI0-MLK 9 LK/SI-MLK GN SI-LK+ SI-LK- 7 GN 9 SI-0+ SI-0- GN SI-+ 7 SI-- 9 GN SI-+ SI-- GN 7 SI-+ 9 SI-- GN US-+ US-- 7 GN 9 HSI-STR HSI-T GN MIPI_RX0_LKP [] MIPI_RX0_LKN [] MIPI_RX0_0P [] MIPI_RX0_0N [] MIPI_RX0_P [] MIPI_RX0_N [] MIPI_RX0_P [] MIPI_RX0_N [] MIPI_RX0_P [] MIPI_RX0_N [] I_SL [] I_S [] I7_SL [] I7_S [] MIPI_TX_0P [] MIPI_TX_0N [] MIPI_TX_P [] MIPI_TX_N [] MIPI_TX_LKP [] MIPI_TX_LKN [] GN X0-F-0.8MM GN RK99_ROK960 ate: Sunday, November, 07 V.0 esigned by: <designer> 6 6