rk3288
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- 导 徐
- 5 years ago
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1 V_SYS G G G G J V M P I GN HUM0--S MIRO_PINNIUJIO F R00 E E /ESV /ESV E00N E00N R R00 F /SW0--00 R R00 OTG_M OTG_P OTG_ET OTG_M OTG_P OTG_M OTG_P OTG_ET M + 0uF R0 /0K OTG_ET R0 /K / LE_TL Working LE R 0K LE_TL 0K R Q 00 SOT R0 LE G_LE R LE G_LE V/ SYSTEM POWER V_SYS 0 0uF/0V 0 V_R 00 efault.v L.uH/. IN-X V_R R uf V_R_F:.K% R 00 Feedback from 0K% R device V_0 efault.0v R 0K U RESET R0 /Reset Vcc GN E0M SOT 如果使用 MU, 需用外部的复位 I R0 不贴. I0_S_PMI I0_SL_PMI PMI_INT PMI_SLEEP RESET 0 0uF 00 R K 0 V_0 R K L.uH/. IN-X V_SYS.uF 00 V_SYS.uF 00 V_SYS.uF 00 PWRHOL / PMI_RSTOUT PMI_INT I0_S_PMI I0_SL_PMI PWRHOL.uF 00 nf 0 R R 0K POWER ON U TQM0-T VP SW OUT GP SW OUT VP INL INL INL.-.V.0-.V.-.V npin npstt PWREN (_EN) PWRHL nrtso nirq S SL REFP G EP QFN-X K.. V_SYS.. 0m 0m 0m 0m 0m 0m 0m 0m 0m VP VP SW SW OUT GP VP VP SW SW OUT GP OUT OUT OUT OUT OUT OUT0 OUT OUT OUT VSELR GPIO/VSELR GPIO/VSELR GPIO GPIO GPIO GPIO 0 pf Y.KHz RY_M 0 0 L.uH/. IN-X _0 _LOG 0_L V_ V_L U0 HYM OSI OSO INT L.uH/. IN-X VIO_S V_ V_LN R V_ LKOUT SL S MSOP RT I V_SYS 0uF/0V 00 efault.v 0uF 00 V_SYS _LOG 0.uF 00 0 uf VIO_PMU 0 uf uf uf VTT 0uF/0V 00 uf 00 0 uf 0 uf.uf 00.uF 00 R 00K PMI_VSEL Q T SOT I0_SL_PMI I0_S_PMI SLVE RESS RE WRITE 0 efault.v _LOG_F: Feedback from RK R 0K efault ON:.V efault OFF efault OFF efault OFF efault ON:.V efault ON:.0V efault ON:.V efault OFF RT_LKOUT ZZ:00 V_R V_SYS U L SYR SWP00SRNT/ SW_LX VIN SW E VIN SW IN-X R 0uF/0V E VIN SW E 0K 00 VIN SW E _PU_F R 0 VOUT EN _PU_F: PMI_SLEEP GN 0 Feedback from I0_S_PMI VSEL GN RK I0_SL_PMI S GN SL GN GN GN GN _PU efault.0v 0 uf uf WLSP-0 _PU_F _PU_F SYR I ddress: 0x0h _GPU_F _GPU_F SYR I ddress: 0xh _GPU V_R V_SYS U L ZZ:00 SYR SWP00SRNT/ efault.0v SW_LX VIN SW E VIN SW IN-X R0 0uF/0V E VIN SW E 0K 00 VIN SW E _GPU_F R 0 VOUT uf uf EN _GPU_F: PMI_SLEEP GN Feedback from I0_S_PMI VSEL GN RK I0_SL_PMI S GN SL GN GN GN GN WLSP-0 J HEERx V_SYS Fans R R 0K R00 FNS_TL FNS_TL 0K R Q 00 SOT T T T T T T MRK MRK MRK MRK MRK MRK System Power RK_OX_Ref. reate ate: Sunday, January, 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
2 UE MU_RK OTG_M OTG_P OTG_I OTG_VUS OTG_EXTR HOST_M HOST_P HOST_EXTR HOST_M HOST_P HOST_EXTR US V0 US V US V US_ US_ US_ US_ G E F0 H OTG_M OTG_P OTG_ET R 0 HOST_M HOST_P R 0 HOST_M HOST_P R 0 OTG_M OTG_P OTG_ET HOST_M HOST_P _0 V 0 V_ GN HU-V 0 uf HU- HU-M HU-P M R0 P uf HU- RREF HU-X HU-X XTL HU-M XTL HU-P M uf HU- 0 P HU-M HU-P M HU-RST#HU-RST# P RESET# TEST 0K uf R0 R 0K U GL0G SSOP GN GN GL0G P M P0 M0 V V PWREN OVUR# 0 PWREN OVUR# PGNG PSELF GN SSOP HU HU-P F HU-M 0-00M HOST_P HOST_M L00 0uF 00 R F L00 HU-V OVUR# R0 - PGNG R0 00K PSELF R0 K HU-V GN GN GN M HU- 0 OVUR# V_SYS GN R K R K RK_E UU MU_RK OTG_ET HSI_STROE HSI_T R H0 HSI V _0 0K HU-X 0pF R Y XIN GN XOUT M-0ppm RY- GN GN HU-X 0pF 00 0uF/0V E US_HOST J :V :- :+ :GN :V :- :+ :GN HOST-PWR HOST-PWR F /SW0--00 R R00 HU-M HU-P HU-M RK_U GN GN E uF/0V + R R00 R R00 F 0 /SW0--00 R0 R00 HU-P 0 V_SYS uf F R uF/0V E HOST-PWR + R R00 F HU-M U SY0/WS0 R IN OUT GN HOST_VUS_RV EN SET R SOT K HOST_VUS_RV HOST_VUS_RV R K HOST-PWR 0 US_HOST J :V :- :+ :GN :V :- :+ :GN E 0uF/0V 00 + HOST-PWR /SW0--00 R R00 R R00 F /SW0--00 R0 R00 HU-P HU-M HU-P RK US/HSI ontroler RK_OX_Ref. reate ate: Monday, February, 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
3 UK MU_RK UL MU_RK R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ F F E 0 0 E F F E F E R0_Q0 R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q0 R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q0 R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q R0_Q0 R0_Q R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_LK R0_LKn R0_0 R0_ R0_ R0_OT0 R0_OT R0_Sn0 R0_Sn R0_KE0 R0_KE 0 0 E F F E E E F R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_LK R0_LKN R0_0 R0_ R0_ R0_OT0 R0_OT R0_S0N R0_SN R0_KE0 R0_KE R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ W V Y U W Y V Y E E F H H J J T R T R U V U V E G E F H R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q R_Q0 R_Q R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_LK R_LKn R_0 R_ R_ R_OT0 R_OT R_Sn0 R_Sn R_KE0 R_KE L K K M M M M M N P N P P P P R L L L J L P R H J F H R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_LK R_LKN R_0 R_ R_ R_OT0 R_OT R_S0N R_SN R_KE0 R_KE R0_QS0P R0_QS0M R0_QSP R0_QSM R0_QSP R0_QSM R0_QSP R0_QSM 0 0 R0_QS0 R0_QS0n R0_QS R0_QSn R0_QS R0_QSn R0_QS R0_QSn R0_RSn R0_Sn R0_WEn R0_RESET R0_VREF R0_VREFO E H H R0_RSN R0_SN R0_WEN R0_RST VREF_R0 R_QS0P R_QS0M R_QSP R_QSM R_QSP R_QSM R_QSP R_QSM G G U U R_QS0 R_QS0n R_QS R_QSn R_QS R_QSn R_QS R_QSn R_RSn R_Sn R_WEn R_RESET R_VREF R_VREFO L H J F M L R_RSN R_SN R_WEN R_RST VREF_R R0_M0 R0_M R0_M R0_M V_R E F G G H H G R0_M0 R0_M R0_M R0_M R0_RETLE R0_TO R0_TO R0_TO0 R0_PZQ R0_ R0_ R0_ R0_ R0_ R0_O G G G H J J J J H V_R R_M0 R_M R_M R_M V_R U G R H M R U U R_M0 R_M R_M R_M R_RETLE R_TO R_TO R_TO0 R_PZQ R_ R_ R_ R_ R_ R_O P R L J L M P R P V_R R % RK_K % R RK_L hannel 0 hannel V_R R K% V_R 0uF 00 VREF_R0 R0 K% nf nf nf R0_LK R0_LKN R 0 Note: These termination resistors must be placed in the middle of trace, and the termination resistor of LK must be placed in thebifurcation point. V_R R K% V_R 0uF 00 VREF_R R0 K% nf 0 nf 0 nf R_LK R_LKN R 0 Note: These termination resistors must be placed in the middle of trace, and the termination resistor of LK must be placed in thebifurcation point. R0 FILTER R FILTER RK RM ontroler RK_OX_Ref. reate ate: Monday, February, 0 Modify ate: Friday, November 0, 0 Page Total:
4 R R0 FILTER R Option Option Option Option R FILTER R0_RST R0_RSN R0_SN R0_WEN R0_OT0 R0_KE0 R0_S0N R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_LKN R0_LK R0_M0 R0_QS0M R0_QS0P R0_RST R0_RSN R0_SN R0_WEN R0_S0N R0_OT0 R0_KE0 R0_ R0_M R0_QSP R0_QSM R0_QSM R0_QSP R0_M R0_QSM R0_QSP R0_M R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_0 R0_ R0_LKN R0_LK R0_OT R0_KE R0_SN R0_OT R0_KE R0_SN R0_ R0_ R_RST R_ R_0 R_S0N R_KE0 R_OT0 R_WEN R_SN R_RSN R_ R_0 R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_QS0P R_QS0M R_M0 R_LK R_LKN R_QSM R_QSP R_M R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_OT R_SN R_KE R_ R_RST R_ R_QSM R_QSP R_M R_QSM R_QSP R_M R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_OT R_SN R_KE R_S0N R_KE0 R_OT0 R_WEN R_SN R_RSN R_ R_0 R_ R_0 R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_LKN R_LK V_R V_R VREF_R0 VREF_R0 V_R VREF_R0 V_R V_R V_R VREF_R VREF_R V_R V_R V_R V_R VREF_R R0_ R0_0 R0_RST R0_ R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_LKN R0_LK R0_ R0_ R0_OT0 R0_ R0_ R0_0 R0_KE0 R0_SN R0_S0N R0_OT R0_WEN R0_SN R0_RSN R0_KE R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_M0 R0_M R0_M R0_QSM R0_QSP R0_QSM R0_QSM R0_QSP R0_QS0M R0_M R0_ R0_0 R0_ R0_QSP R0_ R0_ R0_ R0_QS0P R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_0 R0_ R0_ R0_ R0_ R0_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_M0 R_QSM R_QSM R_M R_M R_M R_QSP R_QSM R_QSP R_QSP R_QS0M R_QS0P R_ R_ R_ R_ R_ R_0 R_ R_0 R_ R_ R_ R_ R_ R_ R_LK R_LKN R_0 R_ R_ R_OT0 R_OT R_ R_SN R_KE0 R_KE R_ R_RSN R_SN R_WEN R_S0N R_RST reate ate: Page Total: Modify ate: RM-R-Xbit Tuesday, November 0, 00 Friday, November 0, 0. RK_OX_Ref reate ate: Page Total: Modify ate: RM-R-Xbit Tuesday, November 0, 00 Friday, November 0, 0. RK_OX_Ref reate ate: Page Total: Modify ate: RM-R-Xbit Tuesday, November 0, 00 Friday, November 0, 0. RK_OX_Ref R /% R /% U R_MXIT U R_MXIT Q0 E Q F Q F Q F Q H Q H Q G Q H Q Q Q0 Q Q Q Q Q KE K S# L OT K RS# J S# K WE# L G K K OT J KE J 0 N P P N P P R R T R 0/P L R /# N T 0 M N M K J K# K LM E UM LQS F LQS# G UQS UQS# Q Q VREFQ H G J E J M M P P T T Q Q Q E Q E Q F Q G Q G E F N N R R S# L ZQ L ZQ L M VREF M RESET# T T H H R K% R K% U R_MXIT U R_MXIT Q0 E Q F Q F Q F Q H Q H Q G Q H Q Q Q0 Q Q Q Q Q KE K S# L OT K RS# J S# K WE# L G K K OT J KE J 0 N P P N P P R R T R 0/P L R /# N T 0 M N M K J K# K LM E UM LQS F LQS# G UQS UQS# Q Q VREFQ H G J E J M M P P T T Q Q Q E Q E Q F Q G Q G E F N N R R S# L ZQ L ZQ L M VREF M RESET# T T H H nf nf R % R % U R_MXIT U R_MXIT Q0 E Q F Q F Q F Q H Q H Q G Q H Q Q Q0 Q Q Q Q Q KE K S# L OT K RS# J S# K WE# L G K K OT J KE J 0 N P P N P P R R T R 0/P L R /# N T 0 M N M K J K# K LM E UM LQS F LQS# G UQS UQS# Q Q VREFQ H G J E J M M P P T T Q Q Q E Q E Q F Q G Q G E F N N R R S# L ZQ L ZQ L M VREF M RESET# T T H H uf uf R % R % nf nf nf nf nf nf R /% R /% 0 0 0uF 00 0uF 00 0 uf 0 uf R % R % 0 0 0uF 00 0uF 00 R /% R /% 0 0 R K% R K% nf nf U R_MXIT U R_MXIT Q0 E Q F Q F Q F Q H Q H Q G Q H Q Q Q0 Q Q Q Q Q KE K S# L OT K RS# J S# K WE# L G K K OT J KE J 0 N P P N P P R R T R 0/P L R /# N T 0 M N M K J K# K LM E UM LQS F LQS# G UQS UQS# Q Q VREFQ H G J E J M M P P T T Q Q Q E Q E Q F Q G Q G E F N N R R S# L ZQ L ZQ L M VREF M RESET# T T H H nf nf 0uF 00 0uF R /% R /% R % R % nf nf 0 0 R K% R K% nf 0 nf R K% R K% uF uF 00
5 U MU_RK G SMM_0 JTG_TMS/SMM0_0/GPIO_0_u H SMM_ JTG_TRSTN/SMM0_/GPIO u SMM_ JTG_TI/SMM0_/GPIO u SMM_ JTG_TK/SMM0_/GPIO u G SMM_LK JTG_TO/SMM0_LKOUT/GPIO d SMM_M SMM0_M/GPIO u H SMM_ET SMM0_ET/GPIO u SMM0_ VIO_S RK_ SMM_PWR SMM_PWR VIO_S R /0K R0 /0K R /0K R /0K R /0K R 0K SMM_PWR ZZ:00 R R 0K 00K ZZ:00 SMM_0 SMM_ SMM_ SMM_ SMM_M SMM_ET Q WPM0 SOT V_S 0uF 00 lose to TF SMM_ R R SMM_ R R SMM_M R R SMM_LK SMM_0 SMM_ SMM_ET R R R R R R TF ard J T /T M LK T0 T 0 G G G G TF_S_SOKET S_F0 UP MU_RK FLSH0_0/EMM_0/GPIO_0_u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u FLSH0_RY/GPIO_0_u FLSH0_WP/EMM_PWREN/GPIO d FLSH0_RN/GPIO u FLSH0_LE/GPIO d FLSH0_LE/GPIO d FLSH0_WRN/GPIO u FLSH0_Sn0/GPIO u FLSH0_Sn/GPIO u FLSH0_Sn/EMM_M/GPIO_0_u FLSH0_Sn/EMM_RSTNOUT/GPIO u FLSH0_QS/EMM_LKOUT/GPIO d FLSH0_VOLTGE_SEL/GPIO d E F F F G G G H H Y F H G Y Y FLSH0_0 FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_WP/EMM_PWREN FLSH0_S/EMM_M FLSH0_QS/EMM_LKO emm(default) Note: Reserve a P. FLSH0_QS/EMM_LKO T TEST T-0. T TEST T-0. FLSH0_0 FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_S/EMM_M H H H J J J J J W U emm T0 T T T T T T T M VQ VQ VQ VQ VQ V V V V V_Flash Y W K U T0 N M RK_P FLSH0_ V_Flash Y ZZ:0 R0 / 接.V:.V 悬空 :.V V_Flash.uF 00 FLSH0_QS/EMM_LKO V_Flash.uF 00 R R ZZ:00 R 00K emm_lk W FLSH0_WP/EMM_PWRENU K LK RST_n i Q Q Q Q Q U R0 P M H T Y Y K V_Flash V_Flash R 0.uF 00 0K R U IN F/OUT GN SHN P PT0EE- SOT.uF 00 RP 0K S RP 0K S R 0K FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_0 FLSH0_ FLSH0_ FLSH0_ FLSH0_S/EMM_M /uf Pull-up select Flash Power Nand FLSH/eMM/TF ard RK_OX_Ref. reate ate: Sunday, January, 0 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
6 RK_R RK FILTER RK_M RK_ RK_T RK_G RK_F REOVERY KEY For debug(efault) efuse_power Place the omponent if need to write efuse OS_X OS_X PWM0 I_SL I_S URT_TX URT_RX URT_TX URT_RX efuse_pwr efuse_pwr REOVER HP_ET SPI_LK SPI_S SPI_TX SPI_RX I_SL I_S URT_TX URT_RX GPIO_ GPIO_ L_EN I_S I_SL SPI_LK SPI_S SPI_TX SPI_RX URT_RX URT_TX GPIO_ GPIO_ PWM0 _LOG _GPU _PU _GPU _PU _LOG _0 _0 _0 V_ V_ V_eFUSE V_eFUSE _0 _PU _GPU VTT _GPU_F _PU_F PMI_INT RT_LKOUT RESET HOST_VUS_RV I0_S_PMI I0_SL_PMI HMI_E I_S_HMI I_SL_HMI PMI_VSEL SMM_PWR 0 PMI_SLEEP LE_TL HP_ET PHONE_TL PHY_PME PHY_INT FNS_TL reate ate: Page Total: Modify ate: RK GPIO/POWER Sunday, January, 0 Wednesday, ecember 0, 0. RK_OX_Ref reate ate: Page Total: Modify ate: RK GPIO/POWER Sunday, January, 0 Wednesday, ecember 0, 0. RK_OX_Ref reate ate: Page Total: Modify ate: RK GPIO/POWER Sunday, January, 0 Wednesday, ecember 0, 0. RK_OX_Ref uf uf uf 00 uf 00 pf pf UT MU_RK UT MU_RK _IN0 P REOVER/_IN P _IN P V R0 nf nf U MU_RK U MU_RK NPOR M LKIN_K P OS_XO N OS_XI N GLOL_PWROFF/PMUGPIO0_0_d J RIO_PWROFF/PMUGPIO0 d J PUMIO_ P0 PMU V0 M0 PMUGPIO0 u K PMUGPIO0 u L PMUGPIO0 u L PMUGPIO0 u L PMUGPIO0_0_u L PMUGPIO0 u L OTP_OUT/PMUGPIO0 d L PMUGPIO0 d L PMUGPIO0 d M LKM_IN/PMUGPIO0 d L PMUGPIO0 d M I0_S/PMUGPIO0 u M EFUSE_VQPS P PLL V0 P PLL_ P RIO_RETEN/PMUGPIO0 u J EFUSE_PWREN/PMUGPIO0 u K TEST M I0_SL/PMUGPIO0_0_u M TEST_LKO/LK_M_T/PMUGPIO0 d M PMUGPIO0 u M OS_X P 0uF 00 0uF 00 UM MU_RK UM MU_RK E0 U 0 Y F J J U J W0 K0 K 0 K K K K K K K K J L0 0 L L L L M M0 M M M Y 0 N0 N N N N P0 P P P P 0 P P P R R0 R R R R R 0 T0 R T Y0 T T T T T V 0 U0 R U V V0 V V V W W 0 W W W W W W W uf uf R 0K R 0K uf uf Y M-0ppm RY- Y M-0ppm RY- XIN GN XOUT GN uf 00 uf 00 Q /00 SOT Q /00 SOT nf nf U /PT0EE- SOT U /PT0EE- SOT IN GN SHN P F/OUT R 0K R 0K R R uf 00 uf 00 REOVER SW REOVER SW uf 00 uf uf 00 uf 00 J HEERx J HEERx uf 00 uf 00 0 nf 0 nf uf 00 uf 00 T T R /0K R /0K 0uF 00 0uF 00 UR MU_RK UR MU_RK PU_ U PU_ U PU_ U PU_ U PU_ U PU_ U PU_ V PU_ V PU_ V PU_0 V PU_ V PU_ V PU OM T GPU_ L GPU_ L GPU_ L GPU_ L GPU_ M GPU_ M GPU_ M GPU_ M GPU_ N GPU_0 N GPU_ N GPU_ N GPU OM M LOGI_ L LOGI_ M LOGI_ N LOGI_ P LOGI_ R LOGI_ T LOGI_ U LOGI_ R LOGI_ T LOGI_0 U L_ V0 0 0 nf nf nf nf 0 0 0uF 00 0uF 00 R R R R uf uf uf 00 uf 00 J HEERx J HEERx 0 R R uf uf 0 0 pf pf R /00K R /00K UG MU_RK UG MU_RK S_JTG_TMS G0 S_JTG_TI F S_JTG_TRSTn E S_JTG_TK E S_JTG_TO F PS_LK/GPIO_0_u PS_T/GPIO u S_ET/GPIO u G SPI_Sn/S_IO/GPIO u I_S/S_RST/GPIO u I_SL/S_LK/GPIO u E SPI_LK/S_IO_T/GPIO d SPI_Sn0/S_ET_T/GPIO u SPI_RX/S_RST_T/GPIO_0_d F SPI_TX/S_LK_T/GPIO d PIO_ J0 T T /uf /uf E0 /ESV E00N E0 /ESV E00N R K R K UF MU_RK UF MU_RK PWM0/GPIO_0_d H PWM/GPIO d G GPIO d GPIO d F GPIO u E GPIO d G GPIO u F GPS_MG/HS_0_T/URT_RX/GPIO u E GPS_SIG/HS T/URT_TX/GPIO_0_d J GPS_RFLK/GPS_LK_T/URT_TSn/GPIO u H URT_RTSn/GPIO u F ep_hotplug/gpio d E ISP_SHUTTEREN/SPI_LK/GPIO d J ISP_FLSHTRIGOUT/SPI_SN0/GPIO u H ISP_PRELIGHTTRIG/SPI_RX/GPIO d F ISP_SHUTTERTRIG/SPI_TX/GPIO d G ISP_FLSHTRIGIN/EPHMI_E_T/GPIO_0_u G I_S/GPIO u H I_SL/GPIO u J I_S/EPHMI_I_S/GPIO u H I_SL/EPHMI_I_SL/GPIO u J GPIO d H URT_RX/IR_RX/PWM/GPIO u J URT_TX/IR_TX/PWM/EPHMI_E/GPIO u H PIO_ L0 R M R M 0 0 uf 00 uf 00 R R
7 UO MU_RK J 0 HMI_HP_d HMI_TXP HMI_TXN HMI_TX0P HMI_TX0N HMI_TXP HMI_TXN HMI_TXP HMI_TXN HMI_EXTR HMI V0 HMI V G H G0 H0 G H G H 0 F F F F 0 F TX_+ TX_- TX_0+ TX_0- TX_+ TX_- TX_+ TX_- R0 R K 0.K% 0.uF 00 HMI_HP R 0 0_L V_L 0.uF 00 0 HMI_ HMI_ HMI OUT TX_+ TX_- TX_+ TX_- TX_0+ TX_0- HMIE _SL HMI_HP TX_+ TX_- TX_+ TX_- TX_+ TX_- _S V_SYS 0 U /Rlamp0P/ES0 0 TX_+ IN OUT IN IN IN OUT OUT OUT TX_- TX_- TX_+ RK_O I_S_HMI I_SL_HMI HMI_E I_S_HMI I_SL_HMI HMI_E TX_0+ TX_0- TX_+ TX_- U /Rlamp0P/ES0 IN IN IN OUT OUT OUT 0 TX_0+ TX_0- TX_+ IN OUT TX_- GN GN I_SL_HMI _SL GN GN R K V_SYS N SO R K R /0K /N SO R00 /0K HMI_E HMIE Q /WNM0/SK0 SOT Q WNM0/SK0 SOT R K R K I_S_HMI _S Q WNM0/SK0 SOT _SL E _S E HMI_HP E HMIE E /ESVL E00N /ESVL E00N /ESVL E00N /ESVL E00N HMI OUT RK_OX_Ref. reate ate: Modify ate: Sunday, January, 0 Friday, November 0, 0 Page Total:
8 U MU_RK L domain L0_HSY/GPIO_0_d L0_VSY/GPIO d L0_EN/GPIO d L0_LK/GPIO d TRE_0/L0_0/LVS_0P T TRE_/L0_/LVS_0N T TRE_/L0_/LVS_P U TRE_/L0_/LVS_N U TRE_/L0_/LVS_P W TRE_/L0_/LVS_N W TRE_/L0_/LVS_P Y TRE_/L0_/LVS_N Y TRE_/L0_/LVS_P TRE_/L0_/LVS_N TRE_0/L0_0/LVS_LK0P V TRE_/L0_/LVS_LK0N V TRE_/L0_/LVS_P U TRE_/L0_/LVS_N U TRE_/L0_/LVS_P V TRE_/L0_/LVS_N V TRE_LK/L0_/LVS_P TRE_TL/L0_/LVS_N L0_/LVS_P L0_/LVS_N L0_0/LVS_P L0_/LVS_N L0_/LVS_LKP Y L0_/LVS_LKN Y LVS_EXTR V LVS domain 0 LVS V0 LVS V LVS V RK_ UI MU_RK R0 K% 0_L V_L R0 V_ R0 建议预留不能删除 J0 HEERx IS_SLK IS_LRK_TX IS_SO0 I_SL_UIO 0 SPIF_TX IS_SI IS_LRK_RX IS_MLK I_S_UIO IS_SLK/GPIO_0_d IS_LRK_RX/GPIO d IS_LRK_TX/GPIO d IS_SI/GPIO d IS_SO0/GPIO d IS_SO/GPIO d IS_SO/GPIO d IS_SO/GPIO d IS_LK/GPIO_0_d I_S/GPIO u I_SL/GPIO u SPIF_TX/GPIO d G F E G H G H F E IS_SLK IS_LRK_RX IS_LRK_TX IS_SI IS_SO0 IS_MLK I_S_UIO I_SL_UIO SPIF_TX MI RK_I PIO_ Y V_ RK L/IS ontroler RK_OX_Ref. reate ate: Monday, February, 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
9 UQ MU_RK M_TX HOST_0/M_TX/SIO_0/FLSH_0/GPIO_0_u Y R M_TX HOST_/M_TX/SIO_/FLSH_/GPIO u V R HOST_/M_RX/SIO_/FLSH_/GPIO u HOST_/M_RX/SIO_/FLSH_/GPIO u M_TX0 HOST_/M_TX0/SIO_ET/FLSH_/GPIO u R M_TX HOST_/M_TX/SIO_WRPRT/FLSH_/GPIO u R HOST_/M_RX0/SIO_KPWR/FLSH_/GPIO u HOST_/M_RX/SIO_INTn/FLSH_/GPIO u HOST_KOUTP/M_M/FLSH_RY/GPIO_0_u HOST_KOUTN/M_RXV/FLSH0_Sn/FLSH_WP/GPIO u HOST_/M_RXER/FLSH0_Sn/FLSH_RN/GPIO u E HOST_/M_LK/FLSH0_Sn/FLSH_LE/GPIO u E M_TXEN R HOST_0/M_TXEN/FLSH0_Sn/FLSH_LE/GPIO u HOST_/M_MIO/FLSH_WRN/GPIO u Y HOST_/M_RXLK/SIO_M/FLSH_Sn0/GPIO u HOST_/M_RS/SIO_LKOUT/FLSH_Sn/GPIO u HOST_/M_OL/FLSH_QS/FLSH_Sn/GPIO_0_u M_TXLK HOST_/M_TXLK/SIO_PWREN/FLSH_Sn/GPIO u V R0 V_LN FLSH_ V RK_Q R R R R R R PHY_TX PHY_TX M_RX M_RX PHY_TX0 PHY_TX M_RX0 M_RX M_M M_RXV M_RXER M_LK PHY_TXEN M_MIO M_RXLK M_RS PHY_RST PHY_TXLK PHY_TX PHY_TX M_RX M_RX PHY_TX0 PHY_TX M_RX0 M_RX M_M M_RXV M_LK PHY_TXEN M_MIO M_RXLK PHY_RST PHY_TXLK M_MIO R K V_LN PHY_TX0 R K V_LN PHY_TX R K M_RXER T PHY_TX PHY_TX R R K K M_RS T RK EthernetM ontroler RK_OX_Ref. reate ate: Modify ate: Monday, February, 0 Friday, November 0, 0 Page Total:
10 PHY_TX0 PHY_TX PHY_TX PHY_TX PHY_TXEN PHY_TXLK M_RX0 M_RX M_RX M_RX M_RXV M_RXLK M_LK Y PHY_XTL XOUT GN PHY_XTL GN XIN pf MHz-0ppm RY- pf If use external clock then the XTL need connect to GN for RTLE. MI0+ MI0- MI+ MI- MI+ MI- MI+ MI- J P GLE+ N GLE- P YLE+ N YLE- GN GN P N GN 0 P GN N KLS0-LF 0.u EGN M_M M_MIO GN GN PHY_RST M_LK R PHY_XTL R R PHY_LKOUT R K PHY_RXV R V_LN R K LE_ R V_LN V_LN U0 REGOUT V_LN PHY_LKOUT REG PHY_XTL PHY_XTL 0_EPHY RSET ENSWREG GN(EP) REGOUT GN LK REG REG KXTL KXTL 0 0 RSET ENSWREG R V_LN PHY_RST R.K% PHYRST V_LN R 0nF LE0_0 PHY ddress=00(rtle) R R R R R PHY_RX PHY_RX onfig for all capability K LE_RXLY R Without RX elay K PHY_RX Without TX elay R0 K R K R K R0 V_LN V_LN V_LN V_LN.uF 00 0_EPHY V_LN 0_EPHY MI0+ MI0- MI+ MI- MI+ MI- MI+ MI- 0 MI[0]+ MI[0]- 0 MI[]+ MI[]- MI[]+ MI[]- 0 MI[]+ MI[]- RXTL/PHY RX0/SELRGV RX/TXLY RX/N0 RX/N RX INT TX TX0 TX 0 LE/PHY LE0/PHY0 PME LE_RXLY MIO M 0 PHYRST 0 TXTL TX TX LE_ LE0_0 PHY_PME LE_RXLY M_MIO M_M PHYRST PHY_TXEN PHY_TX PHY_TX 0_EPHY 0_EPHY R PHY_PME PHY_INT PHY_PME PHY_INT ENSWREG R K R K R onnect ENSWREG to to enable Switching regulator or connect ENSWREG to GN to disable Switching regulator. V_LN V_LN V_LN R PHY_RX0 R K Pull down for.v RGMII(RTL/E) Pull up for.v RGMII (RTL/E) Pull up. /.V RGMII (RTLE-VL only) V_LN RTLE-V-G 0 PHY_RXV PHY_RX0 PHY_RX PHY_RX PHY_RX PHY_RXLK PHY_INT PHY_TXLK PHY_TX0 PHY_TX 0_EPHY REGOUT L.uH/ IN_X 0 Inductance close to PIN 0uF 00 V_LN PHY_RX0 PHY_RX PHY_RX PHY_RX R R R0 R R R R R M_RX0 M_RX M_RX M_RX V_LN PHY_RXLK R PHY_RXV R lose to PHY R R M_RXLK M_RXV REG lose to PIN. 0.uF 00 0/00/000M-PHY RK_OX_Ref. reate ate: Sunday, January, 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
11 UH MU_RK URT0_RX/GPIO_0_u URT0_TX/GPIO d URT0_TSn/GPIO u URT0_RTSn/GPIO u SIO0_0/GPIO u SIO0_/GPIO u SIO0_/GPIO u SIO0_/GPIO u SIO0_M/GPIO_0_u SIO0_LKOUT/GPIO d SIO0_ET/GPIO u SIO0_WP/GPIO d SIO0_PWR/GPIO d SIO0_KPWR/GPIO d SIO0_INTn/GPIO u GPIO u PIO_ RK_H H G0 H H0 G H H G F E F E VIO_WL R0 V_ RK SIO0 ontroler RK_OX_Ref. reate ate: Modify ate: Monday, February, 0 Wednesday, ecember 0, 0 Page Total:
12 U MU_RK Y HOST_0/TS_0/IF_/GPIO_0_d Y HOST_/TS_/IF_/GPIO d Y HOST_/TS_/IF_/GPIO d V HOST_/TS_/IF_/GPIO d U HOST_KINP/TS_/IF_/GPIO d U HOST_KINN/TS_/IF_/GPIO d U HOST_/TS_/IF_/GPIO d V HOST_/TS_/IF_/GPIO d R HOST_/TS_SY/IF_VSY/GPIO_0_d R HOST_/TS_VLI/IF_HREF/GPIO d HOST_WKK/GPS_LK/TS_LKOUT/IF_LKIN/GPIO d V R HOST_WKREQ/TS_FIL/IF_LKOUT/GPIO d R IF_0/GPIO d R IF_/GPIO d R IF_0/GPIO d R IF_/GPIO d P I_SL/GPIO_0_u R I_S/GPIO u VPIO_ U0 RK_ UW MU_RK UX MU_RK MIPI_RX_0P MIPI_RX_0N MIPI_RX_P MIPI_RX_N MIPI_RX_LKP MIPI_RX_LKN MIPI_RX_P MIPI_RX_N MIPI_RX_P MIPI_RX_N MIPI_RX_REXT G H G H G H G H H H MIPI_TX/RX_0P E0 MIPI_TX/RX_0N F0 MIPI_TX/RX_P E MIPI_TX/RX_N F MIPI_TX/RX_LKP E MIPI_TX/RX_LKN F MIPI_TX/RX_P E MIPI_TX/RX_N F MIPI_TX/RX_P F MIPI_TX/RX_N MIPI_TX/RX_REXT MIPI_RX V 0 MIPI_TX/RX V RK_W RK_X UN MU_RK ep_tp_out/st_extr ep_lkm_in/mipi_lli_extr ep_tx0p ep_tx0n ep_txp ep_txn ep_txp ep_txn ep_txp ep_txn ep_xup ep_xun G H G H G H G H G H UV MU_RK MIPI_TX_0P MIPI_TX_0N MIPI_TX_P MIPI_TX_N MIPI_TX_LKP MIPI_TX_LKN MIPI_TX_P MIPI_TX_N MIPI_TX_P MIPI_TX_N MIPI_TX_REXT G G F F E E E ep_extr MIPI_TX V RK_N ep V0 ep V Y RK_V amera Interface RK_OX_Ref. reate ate: Sunday, January, 0 Modify ate: Wednesday, ecember 0, 0 Page Total:
13 UJ MU_RK URT_RX/TS0_0/GPIO_0_u URT_TX/TS0_/GPIO d URT_TSn/TS0_/GPIO u URT_RTSn/TS0_/GPIO u SPI0_LK/URT_TSn/TS0_/GPIO u SPI0_Sn0/URT_RTSn/TS0_/GPIO u SPI0_TX/URT_TX/TS0_/GPIO d SPI0_RX/URT_RX/TS0_/GPIO u SPI0_Sn/TS0_SY/GPIO_0_u TS0_VLI/GPIO d TS0_LK/GPIO d TS0_ERR/GPIO d F H E F G E PIO_ Y RK_J TV-(Reserve) RK_OX_Ref. reate ate: Modify ate: Monday, February, 0 Friday, November 0, 0 Page Total:
Version ate uthor hange Note pproved 008 HWQ First edictor Modify note FR_RK88 reate ate: Modify ate: Saturday, October, 0 Thursday, ecember, 0 8
ontent Indexing 0.Index 0.Modify note 0.lock iagram 0.Power Tree 0.System Power 0.RK88 US/HSI ontroler 07.RK88 RM ontroler 08.RM-LPR(P) 0.eMM/TF ard.rk88 GPIO/POWER.HMI interface.rk88 L/IS ontroler.rk88
ROC-RK3328-CC-V1.0-A
ontent Indexing PF Number of pages 0.Index 0.hange List 0.lock iagram 0.Power tree-rk0-0.system Power-PMI RK0-0.RK Power 0.RK OS/PLL/OTP/SR 0.RK R ontroler 0.RK emm ontroler/tf/spi 0.RK US PHY/US PHY.RK
px3se_main_ddr3_v01_
ONTENT INEXING 0. INEX 0. hange List 0. lock iagram 0. Power Tree-RK 0. RK Power 06.RK R ontroler 0.RK Flash/S ontroler 0.RK MIS&US 0.RKISPLY/GM ontroler 0.RK MER/HMI ontroler.rk OE/V.RK GPIO.RM-R.Nand
rock64_rk3328_demo1_v20_
ontent Indexing 0. Index 0. hange List 0. Pi- & Pi-+ 0. lock iagram 0. Power tree-rk80-06. System Power-PMI RK80-07. RK8 Power 08. RK8 OS/PLL/OTP/SR 09. RK8 R ontroler 0. RK8 emm ontroler/tf. RK8 US PHY/US
RK I MP Port Pin name omain us name Pull-up voltage Slave evice Slave ddr (MS its) Note Slave us apability I0 GPIO_/SPI_RX/I0_S GPIO_0/SPI_TX/I0_SL PM
Modify note Version ate uthor hange Note pproved V00 00 hwq First edictor Modify note Firefly-RK reate ate: Monday, March, 0 Modify ate: Tuesday, January 0, 0.0 0 RK I MP Port Pin name omain us name Pull-up
RK3036_KYLIN_0119
ONTENT INEXING 0. INEX 0. MOIFY NOTE 0. LOK IGRM 0.Power Tree 0.SYSTEM POWER 0.PU(RK0) 0.R 0.EMM /TF card 0.US HOST 0.HMI OUT.udio odec-l.ethernet.p.eug.gpio LYERS P STK TOP GN Prepreg *.0MIL(0.0mm) djust
hange List Version ate uthor hange Note pproved V harlie First edition ate: esigned by: RK99_ROK960 Sunday, November, 07 V.0 <designer> Sheet:
RK99_Rock960_V.0 ONTENT INEXING 0.Index 0.hange List 0.Power Tree 0.I Map 0.Power omain Map 06.RK99 Power 07.RK99 PMU ontroler 08.RK99 R ontroler 09.RK99 Flash&SMM ontroler 0.RK99 US/USI ontroler.rk99
radxa_ver2
ONTENT INEXING P POWER WIRE WITH INITE 0. INEX 0.lock iagram 0.System Power 0.US OTG/HU 0.R 0.Flash/TF card 0.GPIO 08. HMI 09.LVS 0.amera/TP.RK000_S.RMII_00M No indicate above 80 miles above 0 miles above
aio_3399j_v10_ _a
Modify note Version ate uthor hange Note pproved V00 000 LZZ First edictor Modify note IO_J reate ate: Monday, November, 0 Modify ate: Wednesday, November 0, 0 REV: V0 RK I MP Port Pin name omain us name
tiny6410sdk
oreoard S RST V_V [] V [] V [] V [] V [] V [] V [] V [] V [] V [] VEN [] VSYN [] VLK [] VUS [] OTGI [] OTGM [] OTGP [,] IN [,] IN [] IN0 [] WIFI_IO [] S_LK [] S_n [] S_T0 [] S_T [] OUT0 [] XEINT0 [] XEINT
q918_0422
M P POWER WIRE WITH INITE above miles above miles above miles above miles No indicate Under needs (,) T_HOST_WKE WIFI_ WIFI_ WIFI_ WIFI_ WIFI_LK WIFI_M WIFI_HOST_WKE WIFI_REG_ON U RK/RK SIO_ SIO_ SIO_
WiFi 模组 (SIO ) U L-W0MS.V 0uF/0V R 0 0uF/0V WiFi_V 0.uF S0_LK R S0_ S0_ S0_M S0_0 S0_ T T M LK T0 T WKEUP_OUT WKEUP_IN NT 0 PN POWER Thermal P WKEUP_O
VIO URT0_IN URT0_OUT R0.K R.K 0.uF 0.uF IS_ IS_ IS_ IS_ IS_HS IS_VS IS_PLK IS_SL IS_S SPI0_LK SPI0_TX SPI0_S0 SPI0_RX VIO VK U IS_ IS_ IS_ IS_ IS_HSY IS_VSY IS_PLK IS_SL IS_S 0 SSI0_LK SSI0_TX SSI0_S0
rockpro64_v
RK_MI_REF_V. ONTENT INEXING 0.Index 0.hange List 0.lock iagram 0.Power Tree 0.I Map 0.Power omain Map 0.IR Receiver 0.RK Power.RK PMU ontroler.rk R ontroler.rk Flash&SMM ontroler.rk US/USI ontroler.rk
rockpro64_v
ROKPro_V. ONTENT INEXING 0.Index 0.hange List 0.lock iagram 0.Power Tree 0.I Map 0.Power omain Map 0.IR Receiver 0.RK Power.RK PMU ontroler.rk R ontroler.rk Flash&SMM ontroler.rk US/USI ontroler.rk SR/Key.RK
stm32_mini_v2
US Mirco S SIO US Power:V Power:.V STMF0VET GPIO TFT SPI URT RJ ENJ0SS SPI Flash lock iagram Size ocument Number Rev STM-Lite-V.0 Ver.0 ate: Friday, June 0, 0 Sheet of 0.0uF R M V - + S J MP-0 V_PWR R
LLW2273C(158)-7寸_V4
MU REVISION REOR LTR EO NO: PPROVE: TE: L_HSYN L_ L_ L_ L_ Q Q Q Q Q Q0 Q Q QS QM KN K R_KE R_0 R_ R_ R_ R_ R_ R_ R_ R_ R_ R_REF R_WE Voltage & Max urrent & Min Linewidth Netlist V urrent > 00m > 00m Linewidth
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