Version ate uthor hange Note pproved 008 HWQ First edictor Modify note FR_RK88 reate ate: Modify ate: Saturday, October, 0 Thursday, ecember, 0 8

Transcription

1 ontent Indexing 0.Index 0.Modify note 0.lock iagram 0.Power Tree 0.System Power 0.RK88 US/HSI ontroler 07.RK88 RM ontroler 08.RM-LPR(P) 0.eMM/TF ard.rk88 GPIO/POWER.HMI interface.rk88 L/IS ontroler.rk88 EthernetM ontroler./0/00m-phy.rk88 SIO0 ontroler.isplay/vp Interface 7.TV /SPI Interface 8.MXM onnector Index FR_RK88 reate ate: Modify ate: Sunday, January, 0 Thursday, ecember, 0 8

2 Version ate uthor hange Note pproved 008 HWQ First edictor Modify note FR_RK88 reate ate: Modify ate: Saturday, October, 0 Thursday, ecember, 0 8

3 Nand or ts or emm *8M*bit *8M*bit amera(reserve) RJ- /0/00M RGMII PHY RTL8E-V-G FLSH0 emm R bit 0 hannel R bit hannel SMM0 V.0 IF or TS R/L OUT VS RK00-S GM L0 IS SIO0 V.0 URT0 HSI WIFI T Module efault P(.a/b/g/n/ac) V OUT I HMI OUT RK88 US OTG US HOST HMI output SPIF TX US HOST US HOST Opt URT US HOST US WIFI Optical SPIF EUG URT I0 PWR Supply OS M K LKIN RESET IR IN GPIO Overtemperature protection US WIFI (Reserve) MHz PMI EX / Reset OUT V/ RT I.78KHz OUT.78KHz lock iagram FR_RK88 reate ate: Wednesday, March 8, 0 Modify ate: Thursday, ecember, 0 8

4 T88QM8 VP UK V_R RK88 R-trl R evice PowerName PMI hannel timer(ms) efault voltage Working voltage V/ V_SYS VP VP VP INL UK UK UK OUT OUT OUT7 V_IO _LOG V_0 VIO_S _L V_8 RK88 IO Supply FLSH RK88 US PHY PU Logic Supply RK88 SIO-trl RK88 ep RK88 LVS RK88 HMI RK00-S V_0 _ V_R _PU _GPU _LOG V_8 OUT EX EX OUT Solt:0 Solt: Solt: Solt: Solt: Solt: Solt:.0V.0V.V (F=.V).0V.0V.V.8V.0V.0V.V(R) VFS VFS VFS.8V V_0 INL INL OUT8 OUT OUT OUT OUT V_ V_LN _ V_8 V8_L L/IS ontroler RK00-S LN PHY RK88 PLL RK88 US PHY RK88 SR- RK88 US PHY RK88 MIPI TX RK88 MIPI TX/RX V_LN V_IO VIO_S V_ V_8 _L V8_L OUT OUT OUT8 OUT7 OUT OUT Solt: Solt: Solt: OFF OFF OFF OFF.V.V.V OFF OFF OFF OFF.V.V S.0:.V S.0:.8V.V.8V.0V.8V RK88 ep RK88 LVS RK88 HMI / SYR87 _PU PU / SYR88 _GPU GPU Switch US HOST V_IO RT I K LKOUT RK88 WIFI+T LO LO V8_VP V8_VP MER MOS V_S S R Power Tree FR_RK88 reate ate: Modify ate: Sunday, January, 0 Thursday, ecember, 0 8

5 SYSTEM POWER V_IO.7uF/.V 00 uf 00 V_R V_R uf 00 U8 uf 00 TT880 SOT V_0 /Reset Vcc GN.7uF/.V 00 efault.v uf 00 V_IO 7 efault.0v uf 00 V_0 R0 K RESET R V_SYS uf/v 0 00 L.uH/. 8 IN-X V_R R08.K% R0 0K% V_R_F: Feedback from R device 7 V_SYS 00.7uF uF 00 V_SYS 0.7uF 00.7uF 00 V_SYS.7uF 00 8 POWER_ON PWR_KEY 8, N/0R PWR_EN PMI_INT L7.uH/. IN-X.7uF 00 I0_S_PMI I0_SL_PMI 0 7nF 00 PowerName V_IO V_0 VIO_L V_LOG V_R _RM _GPU V_LN V_S VIO_WL _L VIO_S V8_L _ V_8 VIO_PMU V_ RESET U7 T88QM0-T VP SW OUT GP SW OUT VP.-.V INL 8.0-.V INL.7-.V INL npin npstt PWREN(_EN) PWRHL nrtso nirq S SL 7 0 REFP G EP QFN8-X PMU TIMER OutPut hannel (ms) voltage solt:.v solt:0.0v ExMos OFF.V solt:.0v solt:.v Ex solt:.0v Ex solt:.0v OUT8 OFF.V ExMos solt:.v ExMos OFF.8V OUT OFF.0V OUT solt:.v OUT OFF.8V OUT solt:.0v OUT solt:.8v OUT OUT7 solt: OFF.V.V solt:+0ms m 0m 0m 0m 0m 0m 0m 0m 0m 8 VP VP SW SW OUT GP OUT OUT OUT7 OUT8 OUT PWR_HOL PWR_EN_SYS 8 VP 7 VP SW SW OUT GP OUT OUT OUT OUT VSELR GPIO/VSELR GPIO/VSELR GPIO GPIO GPIO GPIO T TEST T7 TEST L7.uH/. IN-X L.uH/. IN-X LOG _L V_LN V8_L R R VIO_S V_ VIO_PMU V_8 K V_SYS K N8 SO_ N8 SO_ uf/v 00 V_SYS uf/v 00 uf 00 V_IO uf 00 0 uf 00 V_SYS uf/v 00 _LOG 7 uf 00 8 uf 00 uf uF 00.7uF 00.7uF 00.7uF 00 uf.7uf uF 00 uf uF 00 R07 0K R0 00K efault.v efault.0v _LOG_F: Feedback from RK88 PMI_VSEL PWR_EN 8, efault ON:.V efault OFF efault OFF efault OFF efault ON:.V efault ON:.0V efault ON:.8V efault OFF V_R R K 0 N V_R V_SYS R7 K N,8,8 PMI_SLEEP I0_S_PMI I0_SL_PMI V_SYS,8 88 uf/v 080 SYR87 SYR88 PMI_SLEEP I0_S_PMI I0_SL_PMI I0_S_PMI I0_SL_PMI PMI_INT PMI_SLEEP 8 uf/v 080 RESET U SYR87 VIN E VIN E VIN VIN VSEL S SL V_IO R K I ddress: 0x0h I ddress: 0xh U SYR88 VIN E VIN E VIN VIN EN VSEL S SL EN GN WLSP-0 GN WLSP-0 R K SW SW SW E SW E VOUT GN GN GN GN GN GN SW SW SW E SW E VOUT GN GN GN GN GN GN SW_LX _PU_F SW_LX _PU_F: Feedback from RK88 _GPU_F _PU_F _GPU_F _GPU_F: Feedback from RK88 R8 L7 SWP00SRNT/ IN-X R U0 Firefly T-HIP_LOGO MSK MSK MSK MSK MSK MSK MSK MSK MSK MSK MSK MSK _PU L SWP00SRNT/ IN-X 0R 0R _PU_F _GPU_F _GPU efault.0v uf uf efault.0v 8 uf uf If you use the MU_JL80 - double code - V.0, need to use external reset I,R don't paste. System Power FR_RK88 reate ate: Modify ate: Monday, May, 0 Wednesday, ecember, 0 8

6 UE MU_RK88 OTG_M OTG_P OTG_I OTG_VUS OTG_EXTR HOST_M HOST_P HOST_EXTR HOST_M HOST_P HOST_EXTR OTG_M OTG_P OTG_I OTG_ET R 00R% R 00R% R 00R% OTG_M 8 OTG_P 8 OTG_I 8 OTG_ET 8 HOST_M 8 HOST_P 8 HOST_M 8 HOST_P 8 OTG_ET OTG_I R R N/K K V_IO V_IO US V0 US V8 US V US_ US_ US_ US_ G8 E F0 H8 _ V_8 V_IO V_8 V_IO _ 7 T8 TEST P_0 T TEST P_0 T0 TEST P_0 OTG_M OTG_P RK88_E UU MU_RK88 HSI_STROE 7 HSI_T 7 HSI_STROE 8 HSI_T 8 HSI V H0 _ RK88_U RK88 US/HSI ontroler FR_RK88 reate ate: Modify ate: Monday, May, 0 Thursday, ecember, 0 8

7 RK88_K hannel 0 RK88_L hannel R0_RETLE R_RETLE RIO_RETEN R0_RETLE R_RETLE V_R V_R V_R VREFO_R0 V_R VREF_R0 V_R V_R VREFO_R V_R V_R VREF_R VREFO_R0 VREF_R0 V_R V_R VREFO_R VREF_R V_R V_R RIO_RETEN R0_ R0_ R0_ R0_ R0_ R0_ R0_0 R0_RST R0_0 R0_ R0_ R0_ R0_ R0_ R0_ R0_7 R0_8 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_LK R0_LKN R0_0 R0_ R0_ R0_OT0 R0_OT R0_S0N R0_SN R0_KE0 R0_KE R0_RSN R0_SN R0_WEN R0_M0 R0_M R0_M R0_M R0_QSM R0_QSP R0_QSM R0_QSP R0_QSM R0_QSP R0_QS0M R0_QS0P R0_ R0_0 R0_ R0_8 R0_ R0_7 R0_ R0_ R0_ R0_ R0_ R0_0 R0_ R0_8 R0_7 R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_ R0_8 R0_7 R_ R_ R_ R_ R_ R_ R_0 R_M0 R_M R_M R_M R_QSM R_QSP R_QSM R_QSP R_QSM R_QSP R_QS0M R_QS0P R_ R_0 R_ R_8 R_ R_7 R_ R_ R_ R_ R_ R_0 R_ R_8 R_7 R_ R_ R_ R_ R_ R_ R_ R_ R_8 R_7 R_0 R_ R_ R_ R_ R_ R_ R_7 R_8 R_ R_ R_ R_ R_ R_ R_ R_LK R_LKN R_0 R_ R_ R_OT0 R_OT R_S0N R_SN R_KE0 R_KE R_RSN R_SN R_WEN R_RST reate ate: Modify ate: RK88 RM ontroler FR_RK88 Monday, February 7, 0 Thursday, ecember, reate ate: Modify ate: RK88 RM ontroler FR_RK88 Monday, February 7, 0 Thursday, ecember, reate ate: Modify ate: RK88 RM ontroler FR_RK88 Monday, February 7, 0 Thursday, ecember, nf 07 nf R K% R K% 0 0 T TEST T TEST 0 uf 0 uf nf 0 nf nf nf R07 8K R07 8K T TEST T TEST R K% R K% R K% R K% R K% R K% R K% R K% R08 K% R08 K% UL MU_RK88 UL MU_RK88 R_Q0 W R_Q V R_Q Y R_Q U R_Q W R_Q Y R_Q V R_Q7 Y R_Q8 E R_Q E R_Q R_Q F R_Q H R_Q H R_Q J R_Q J R_Q T R_Q7 R R_Q8 T R_Q R R_Q0 U R_Q V R_Q U R_Q V R_Q R_Q R_Q E R_Q7 G R_Q8 E R_Q F R_Q0 R_Q H R_QS0 R_QS0n R_QS G R_QSn G R_QS U R_QSn U R_QS R_QSn R_M0 U R_M G R_M R R_M R_PZQ U7 R_RETLE H7 R_TO M7 R_TO R8 R_TO0 U8 R_0 L R_ K R_ K R_ M R_ M R_ M R_ M R_7 M R_8 N R_ P R_ N R_ P R_ P R_ P R_ P R_ R R_LK L R_LKn L R_0 L R_ J R_ L R_OT0 P R_OT R R_Sn0 H R_Sn J R_KE0 F R_KE H R_RSn L R_Sn H R_WEn J R_RESET F R_VREF M8 R_VREFO L8 N P7 N R7 N L7 R_ J8 R_ L R_ M R_ P R_ R R_O P8 T TEST T TEST R K% R K% 0 0 R00 0R% R00 0R% R0 0K R0 0K UK MU_RK88 UK MU_RK88 R0_Q0 R0_Q 8 R0_Q F7 R0_Q F8 R0_Q R0_Q E8 R0_Q 0 R0_Q7 0 R0_Q8 R0_Q R0_Q R0_Q R0_Q E8 R0_Q R0_Q R0_Q F8 R0_Q R0_Q7 R0_Q8 F R0_Q R0_Q0 7 R0_Q 8 R0_Q 7 R0_Q 8 R0_Q R0_Q R0_Q R0_Q7 E R0_Q8 R0_Q F7 R0_Q0 R0_Q E7 R0_QS0 0 R0_QS0n 0 R0_QS 7 R0_QSn 7 R0_QS 7 R0_QSn 7 R0_QS R0_QSn R0_M0 E7 R0_M F R0_M R0_M R0_PZQ G7 R0_RETLE G8 R0_TO G R0_TO H R0_TO0 H7 R0_0 R0_ R0_ R0_ E R0_ F R0_ R0_ R0_7 R0_8 R0_ R0_ R0_ R0_ F R0_ R0_ R0_ R0_LK R0_LKn R0_0 8 R0_ R0_ E R0_OT0 E R0_OT E R0_Sn0 8 R0_Sn F R0_KE0 R0_KE 8 R0_RSn R0_Sn 8 R0_WEn R0_RESET E R0_VREF H R0_VREFO H N G N G N G R0_ H R0_ J R0_ J R0_ J R0_ J R0_O H T TEST T TEST 0 nf 0 nf R0 8K R0 8K R0 0R% R0 0R% 00 uf uf 00 nf nf 0 nf 0 nf R0 0K R0 0K R0 K% R0 K%

8 R0 FILTER R FILTER R hannel-0 R hannel- R0_SN R0_KE R0_OT R0_ R_RST R_OT R_SN R_KE R_ R0_LKN R0_LK R_LK R_LKN V_R V_R VREFO_R0 V_R VREFO_R0 V_R VREFO_R V_R VREFO_R V_R VREFO_R0 VREFO_R R0_KE0 R0_S0N R0_OT0 R0_RSN R0_SN R0_WEN R0_RST R0_ R0_ R0_ R0_ R0_0 R0_ R0_7 R0_ R0_ R0_ R0_7 R0_0 R0_ R0_ R0_ R0_8 R0_ R0_ R0_0 R0_ R0_ R0_7 R0_ R0_ R0_ R0_ R0_8 R0_ R0_ R0_ R0_ R0_0 R0_LK R0_ R0_ R0_LKN R0_M R0_QSM R0_QSP R0_M R0_QSM R0_QSP R0_ R0_ R0_ R0_8 R0_ R0_ R0_ R0_ R0_0 R0_ R0_7 R0_ R0_ R0_8 R0_ R0_ R0_KE0 R0_S0N R0_OT0 R0_RSN R0_SN R0_WEN R0_ R0_ R0_ R0_0 R0_ R0_ R0_ R0_ R0_7 R0_ R0_ R0_8 R0_ R0_ R0_ R0_ R0_LK R0_0 R0_LKN R0_ R0_M R0_M0 R0_QS0M R0_QS0P R0_QSM R0_QSP R_0 R_7 R_ R_ R_ R_ R_ R_ R_8 R_7 R_0 R_ R_ R_ R_ R_ R_KE0 R_S0N R_OT0 R_RSN R_SN R_WEN R_ R_ R_ R_0 R_ R_ R_ R_ R_7 R_ R_ R_8 R_ R_ R_ R_ R_LK R_0 R_LKN R_ R_QS0M R_M0 R_QSP R_QSM R_M R_QS0P R_ R_ R_ R_ R_ R_ R_0 R_ R_ R_7 R_ R_ R_ R_ R_8 R_LKN R_0 R_LK R_ R_QSP R_M R_QSM R_ R_QSP R_M R_QSM R_ R_ R_ R_ R_ R_ R_ R_8 R_ R_7 R_ R_0 R_ R_ R_8 R_ R_RSN R_OT0 R_S0N R_KE0 R_WEN R_SN R0_RST R0_OT R0_KE R0_SN R0_ R_RST R_OT R_KE R_SN R_ reate ate: Modify ate: RM-LPR-P FR_RK8 Tuesday, November 0, 0 Thursday, ecember, reate ate: Modify ate: RM-LPR-P FR_RK8 Tuesday, November 0, 0 Thursday, ecember, reate ate: Modify ate: RM-LPR-P FR_RK8 Tuesday, November 0, 0 Thursday, ecember, nf 0 nf R00 N/0R% R00 N/0R% R008 0R R008 0R 0 nf 0 nf R00 0R% R00 0R% R00 0R% R00 0R% 0 uf 0 uf R00 N/0R% R00 N/0R% R007 N/0R% R007 N/0R% 00 uf 00 uf 0 0 R00 N/0R% R00 N/0R% 0 nf 0 nf 0 nf 0 nf R000 0R% R000 0R% R00 0R% R00 0R% U000 R-M U000 R-M Q0 E Q F7 Q F Q F8 Q H Q H8 Q G Q7 H7 Q8 7 Q Q 8 Q Q 7 Q Q 8 Q KE0 K S#0 L OT0 K RS# J S# K WE# L G7 K K8 Q Q 8 OT J KE J 0 N P7 P N P8 P R8 7 R 8 T8 R /P L7 R7 /# N7 T 0 M N8 M K J7 K# K7 LM E7 UM LQS F LQS# G UQS 7 UQS# 7 Q Q VREFQ H G8 J E J8 M M P P T T Q Q 8 Q E Q E8 Q F Q G Q G Q Q Q Q E Q F N N R R S# L ZQ L ZQ0 L8 M7 VREF M8 RESET# T T7 Q H Q H nf 0 nf 07 nf 07 nf uf uf nf 08 nf U00 R-M U00 R-M Q0 E Q F7 Q F Q F8 Q H Q H8 Q G Q7 H7 Q8 7 Q Q 8 Q Q 7 Q Q 8 Q KE0 K S#0 L OT0 K RS# J S# K WE# L G7 K K8 Q Q 8 OT J KE J 0 N P7 P N P8 P R8 7 R 8 T8 R /P L7 R7 /# N7 T 0 M N8 M K J7 K# K7 LM E7 UM LQS F LQS# G UQS 7 UQS# 7 Q Q VREFQ H G8 J E J8 M M P P T T Q Q 8 Q E Q E8 Q F Q G Q G Q Q Q Q E Q F N N R R S# L ZQ L ZQ0 L8 M7 VREF M8 RESET# T T7 Q H Q H R00 0R R00 0R nf 00 nf 0 uf 00 0 uf uf uf U00 R-M U00 R-M Q0 E Q F7 Q F Q F8 Q H Q H8 Q G Q7 H7 Q8 7 Q Q 8 Q Q 7 Q Q 8 Q KE0 K S#0 L OT0 K RS# J S# K WE# L G7 K K8 Q Q 8 OT J KE J 0 N P7 P N P8 P R8 7 R 8 T8 R /P L7 R7 /# N7 T 0 M N8 M K J7 K# K7 LM E7 UM LQS F LQS# G UQS 7 UQS# 7 Q Q VREFQ H G8 J E J8 M M P P T T Q Q 8 Q E Q E8 Q F Q G Q G Q Q Q Q E Q F N N R R S# L ZQ L ZQ0 L8 M7 VREF M8 RESET# T T7 Q H Q H U00 R-M U00 R-M Q0 E Q F7 Q F Q F8 Q H Q H8 Q G Q7 H7 Q8 7 Q Q 8 Q Q 7 Q Q 8 Q KE0 K S#0 L OT0 K RS# J S# K WE# L G7 K K8 Q Q 8 OT J KE J 0 N P7 P N P8 P R8 7 R 8 T8 R /P L7 R7 /# N7 T 0 M N8 M K J7 K# K7 LM E7 UM LQS F LQS# G UQS 7 UQS# 7 Q Q VREFQ H G8 J E J8 M M P P T T Q Q 8 Q E Q E8 Q F Q G Q G Q Q Q Q E Q F N N R R S# L ZQ L ZQ0 L8 M7 VREF M8 RESET# T T7 Q H Q H uf uf

9 TF ard U MU_RK88 JTG_TMS/SMM0_0/GPIO_0_u G7 JTG_TRSTN/SMM0_/GPIO u H JTG_TI/SMM0_/GPIO u 8 JTG_TK/SMM0_/GPIO u JTG_TO/SMM0_LKOUT/GPIO d G SMM0_M/GPIO u 8 SMM0_ET/GPIO u H SMM0_ SMM_0 SMM_ SMM_ SMM_ SMM_LK SMM_M SMM_ET VIO_S SMM_0 SMM_ SMM_ SMM_ SMM_LK SMM_M SMM_ET SMM_0 8 SMM_ 8 SMM_ 8 SMM_ 8 SMM_LK 8 SMM_M 8 SMM_ET 8 Z Z Z Z Z Z RK88_ emm V_Flash V_Flash FLSH0_RY FLSH0_RN FLSH0_LE FLSH0_LE FLSH0_WRN FLSH0_S0 FLSH0_S FLSH0_S FLSH0_RY 8 FLSH0_RN 8 FLSH0_LE 8 FLSH0_LE 8 FLSH0_WRN 8 FLSH0_S0 8 FLSH0_S 8 FLSH0_S 8 V_IO V_IO 0.7uF 00 R IN GN SHN U F/OUT TT8-8 SOT N/0R P N.7uF uF 00 V_IO 8 7 UP MU_RK88 FLSH0_0/EMM_0/GPIO_0_u E FLSH0_/EMM_/GPIO u FLSH0_/EMM_/GPIO u F FLSH0_/EMM_/GPIO u F FLSH0_/EMM_/GPIO u F FLSH0_/EMM_/GPIO u G FLSH0_/EMM_/GPIO u G FLSH0_7/EMM_7/GPIO_7_u G FLSH0_RY/GPIO_0_u H FLSH0_WP/EMM_PWREN/GPIO d H FLSH0_RN/GPIO u Y FLSH0_LE/GPIO d F FLSH0_LE/GPIO d H G FLSH0_WRN/GPIO u FLSH0_Sn0/GPIO u FLSH0_Sn/GPIO_7_u FLSH0_Sn/EMM_M/GPIO_0_u FLSH0_Sn/EMM_RSTNOUT/GPIO u Y7 FLSH0_QS/EMM_LKOUT/GPIO d FLSH0_VOLTGE_SEL/GPIO d Y8 RK88_P FLSH0_ Y V_Flash R0 FLSH0_0 FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_7 FLSH0_RY FLSH0_WP/EMM_PWREN FLSH0_RN FLSH0_LE FLSH0_LE FLSH0_WRN FLSH0_S0 FLSH0_S FLSH0_S/EMM_M FLSH0_S FLSH0_QS/EMM_LKO 0R V_Flash FLSH0_QS/EMM_LKO R Note: Reserve a P. FLSH0_QS/EMM_LKO V_IO R R8 FLSH0_0 FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_ FLSH0_7 FLSH0_S/EMM_M T TEST P_0 T TEST P_0 K N/uF H H T0 H T J T J T J T J T J T T7 W M R emm_lk W LK FLSH0_WP/EMM_PWRENU RST_n 0K K i U7 emm VQ VQ VQ Y VQ W VQ K V U V T V N V M U8 R P M7 H T Q Q Q Y Q Y Q K V_Flash V_IO.7uF 00 V_Flash R R R R7 R8 R R0 R R 7 K K K K K K K K K 7 FLSH0_ FLSH0_ FLSH0_ FLSH0_7 FLSH0_0 FLSH0_ FLSH0_ FLSH0_ 8 FLSH0_S/EMM_M emm/tf ard FR_RK88 reate ate: Monday, May, 0 Modify ate: Thursday, ecember, 0 8

10 U 0 MU_RK88 8, RESET M7 NPOR GLOL_PWROFF/PMUGPIO0_0_d J8 8 RT_LKOUT R K7 P RIO_PWROFF/PMUGPIO0 d J7 LKIN_K RIO_RETEN/PMUGPIO0 u J 7 0pF V_eFUSE P EFUSE_PWREN/PMUGPIO0 u K7 EFUSE_VQPS K8 R8 R M PMUGPIO0 u L TEST PMUGPIO0 u L PMUGPIO0 u L N7 PMUGPIO0_7_u L OS_XI PMUGPIO0_0_u L pf OS_X PMUGPIO0 u R8 OTP_OUT/PMUGPIO0 d L L7 Y M PMUGPIO0 d M8 XOUT GN PMUGPIO0 d LK7M_IN/PMUGPIO0 d L8 M GN XIN R8 R N8 PMUGPIO0 d OS_XO I0_S/PMUGPIO0_7_u M M-0ppm RY- I0_SL/PMUGPIO0_0_u M pf OS_X TEST_LKO/LK_7M_T/PMUGPIO0 d M P M OS_X PMUGPIO0 u R8 N PLL_ 8 uf PLL_ 80 P8 P7 PLL V0 PLL_ L LM8PG8SN L00 nf RK88 UG MU_RK88 V_IO S_JTG_TMS G0 F S_JTG_TI E S_JTG_TRSTn S_JTG_TK E S_JTG_TO F PS_LK/GPIO8_0_u PS_T/GPIO8 u 7 G S_ET/GPIO8 u SPI_Sn/S_IO/GPIO8 u 8 I_S/S_RST/GPIO8 u 8 I_SL/S_LK/GPIO8 u E SPI_LK/S_IO_T/GPIO8 d SPI_Sn0/S_ET_T/GPIO8_7_u 7 SPI_RX/S_RST_T/GPIO8_0_d F SPI_TX/S_LK_T/GPIO8 d 8 PUMIO_ P0 PMU V0 M0 78 _ V_IO _ PMI_SLEEP RIO_RETEN 7 efuse_pwr 8 PMI_INT PWR_KEY PWR_HOL GPIO0_7_U 8 PHY_PME PHY_INT PHONE_TL 8 VP_PWR 8 OTG_VUS_RV 8 PMU_GPIO0 8 HOST_VUS_RV 8 I0_S_PMI 8, I0_SL_PMI 8, XNN_PWN 8 GPIO0 U 8 Note:S_JTG_TRSTn must connected to and PIO_ must be power supply S_JTG_TMS 8 S_JTG_TI 8 S_JTG_TK 8 S_JTG_TO 8 GPIO8_0_U 8 WORK_LE 8 POWER_LE 8 HU_RST 8 I_S 8 I_SL 8 SPI_LK 8 SPI_SN0 8 GPIO8_0_ 8 GPIO8 8 UT MU_RK88 RK88_T _PU _PU_F V_IO RK88_R P _IN0 REOVER/_IN P P _IN V_8 V8 R0 uf 00 8 RK88 FILTER UR MU_RK88 U U PU_ U PU_ U7 PU_ U8 PU_ U PU_ V PU_ V PU_7 V PU_8 V7 PU_ V8 PU_ V PU_ PU_ T V0 PU OM L IN0 8 REOVER 8 _IN 8 REOVER L GPU_ L7 GPU_ L8 GPU_ L GPU_ M GPU_ M7 GPU_ M8 GPU_7 M GPU_8 N GPU_ N7 GPU_ N8 GPU_ N GPU_ GPU OM M L LOGI_ M LOGI_ N LOGI_ P LOGI_ R LOGI_ T LOGI_ U LOGI_7 R LOGI_8 T LOGI_ U LOGI_ R K% V_8 _GPU uf 00 _GPU_F _LOG 7 uf 00 UM MU_RK88 8 E0 U 7 8 Y F J J U J7 W K 7 K 8 K K 0 K K K K7 K8 K J8 7 L 8 L L 0 L L M M M M M 7 Y8 8 N N 0 N N N P RK88_M P P P P P P7 P8 R R R R R7 R8 R T R T Y0 T T T7 T8 T V U R U V V V V V W W W W W W W7 W8 W PIO_ J0 V_IO RK88_G _LOG _PU UF MU_RK88 88 uf nf uf 00 8 uf uf 080 uf 080 RK88_F H PWM0/GPIO7_0_d G PWM/GPIO7 d 8 GPIO7 d F GPIO7 d E GPIO7 u G GPIO7 d F GPIO7 u GPS_MG/HS_0_T/URT_RX/GPIO7_7_u E7 GPS_SIG/HS T/URT_TX/GPIO7_0_d J GPS_RFLK/GPS_LK_T/URT_TSn/GPIO7 u H URT_RTSn/GPIO7 u F7 ep_hotplug/gpio7 d E8 ISP_SHUTTEREN/SPI_LK/GPIO7 d J ISP_FLSHTRIGOUT/SPI_SN0/GPIO7 u H ISP_PRELIGHTTRIG/SPI_RX/GPIO7 d F8 ISP_SHUTTERTRIG/SPI_TX/GPIO7_7_d G7 ISP_FLSHTRIGIN/EPHMI_E_T/GPIO7_0_u G8 H I_S/GPIO7 u J I_SL/GPIO7 u I_S/EPHMI_I_S/GPIO7 u H I_SL/EPHMI_I_SL/GPIO7 u J H7 GPIO7 d URT_RX/IR_RX/PWM/GPIO7 u J URT_TX/IR_TX/PWM/EPHMI_E/GPIO7_7_u H8 PIO_ L0 0 V_IO IR_INT 8 PWM 8 LE_TL 8 L_EN RT_INT 8 GPIO7 8 PWR_INT 8 URT_RX 8 URT_TX 8 GPIO7_ 8 PU_ET 8 SMM_PWR 8 IF_POWER 8 GPIO7 U 8 PMI_VSEL HP_ET 8 HMI_E 8 I_S_TP 8 I_SL_TP 8 I_S_HMI 8 I_SL_HMI 8 TX8_RST 8 URT_RX 8 URT_TX 8 _PU 8 uf 080 _GPU uf 080 uf 080 uf 080 uf uf nf 0 nf 7 N _GPU 00 0 uf uf RK88 GPIO/POWER FR_RK88 reate ate: Monday, May, 0 Modify ate: Thursday, ecember, 0 8

11 HMI_OUT UO MU_RK88 HMI_HP_d 8 HMI_TXP G HMI_TXN H HMI_TX0P G0 HMI_TX0N H0 HMI_TXP G HMI_TXN H HMI_TXP G HMI_TXN H HMI_EXTR 7 TX_HP TX_+ TX_- TX_0+ TX_0- TX_+ TX_- TX_+ TX_- R0.K% TX_HP 8 TX_+ 8 TX_- 8 TX_0+ 8 TX_0-8 TX_+ 8 TX_- 8 TX_+ 8 TX_- 8 HMI V0 8 HMI V8 0 _L V8_L 7 8 F F F7 F8 0 F 0 0.7uF uf 00 RK88_O RK88_O HMI interface FR_RK88 reate ate: Monday, May, 0 Modify ate: Thursday, ecember, 0 8

12 U MU_RK88 L domain LVS domain RK88_ L0_HSYN/GPIO_0_d L0_VSYN/GPIO d L0_EN/GPIO d L0_LK/GPIO d TRE_0/L0_0/LVS_0P T7 TRE_/L0_/LVS_0N T8 TRE_/L0_/LVS_P U7 TRE_/L0_/LVS_N U8 TRE_/L0_/LVS_P W7 TRE_/L0_/LVS_N W8 TRE_/L0_/LVS_P Y7 TRE_7/L0_7/LVS_N Y8 TRE_8/L0_8/LVS_P 7 TRE_/L0_/LVS_N 8 TRE_/L0_/LVS_LK0P V7 TRE_/L0_/LVS_LK0N V8 TRE_/L0_/LVS_P U TRE_/L0_/LVS_N U TRE_/L0_/LVS_P V TRE_/L0_/LVS_N V TRE_LK/L0_/LVS_7P TRE_TL/L0_7/LVS_7N L0_8/LVS_8P 7 L0_/LVS_8N 8 L0_0/LVS_P L0_/LVS_N L0_/LVS_LKP Y L0_/LVS_LKN Y L_HSYN L_VSYN L_EN L_LK L_0 L_ L_ L_ L_ L_ L_ L_7 L_8 L_ L_ L_ L_ L_ L_ L_ L_ L_7 L_8 L_ L_0 L_ L_ L_ R K% LVS_EXTR V LVS V0 LVS V8 LVS V 0 7 _L V8_L V_L V_IO RK88_I R 0K L_EN R K Q0 WPM0-/TR SOT R K Q SOT UI MU_RK88 IS_SLK/GPIO_0_d G IS_LRK_RX/GPIO d F IS_LRK_TX/GPIO d E IS_SI/GPIO d G IS_SO0/GPIO d H IS_SO/GPIO d G IS_SO/GPIO d H IS_SO/GPIO_7_d IS_LK/GPIO_0_d F I_S/GPIO u I_SL/GPIO u E SPIF_TX/GPIO d PIO_ Y uf 00 V_L IS_SLK IS_LRK_RX IS_LRK_TX IS_SI IS_SO0 IS_SO IS_SO IS_SO IS_MLK I_S_UIO I_SL_UIO SPIF_TX V_ L_HSYN L_VSYN L_EN L_LK L_0 L_ L_ L_ L_ L_ L_ L_7 L_8 L_ L_ L_ L_ L_ L_ L_ L_ L_7 L_8 L_ L_0 L_ L_ L_ IS_SLK IS_LRK_RX IS_LRK_TX IS_SI IS_SO0 IS_MLK I_S_UIO I_SL_UIO SPIF_TX IS_SO IS_SO IS_SO L_HSYN 8 L_VSYN 8 L_EN 8 L_LK 8 L_0 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_7 8 L_8 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_ 8 L_7 8 L_8 8 L_ 8 L_0 8 L_ 8 L_ 8 L_ 8 IS_SLK 8 IS_LRK_RX 8 IS_LRK_TX 8 IS_SI 8 IS_SO0 8 IS_MLK 8 I_S_UIO 8 I_SL_UIO 8 SPIF_TX 8 IS_SO 8 IS_SO 8 IS_SO 8 Note:Please hold the connection in sequence and use LVS_0~ for single LVS RK88 L/IS ontroler FR_RK88 reate ate: Modify ate: Monday, May, 0 Thursday, ecember, 0 8

13 UQ MU_RK88 HOST_0/M_TX/SIO_0/FLSH_0/GPIO_0_u Y HOST_/M_TX/SIO_/FLSH_/GPIO u V HOST_/M_RX/SIO_/FLSH_/GPIO u HOST_/M_RX/SIO_/FLSH_/GPIO u HOST_/M_TX0/SIO_ET/FLSH_/GPIO u HOST_/M_TX/SIO_WRPRT/FLSH_/GPIO u HOST_/M_RX0/SIO_KPWR/FLSH_/GPIO u HOST_7/M_RX/SIO_INTn/FLSH_7/GPIO_7_u HOST_KOUTP/M_M/FLSH_RY/GPIO_0_u HOST_KOUTN/M_RXV/FLSH0_Sn/FLSH_WP/GPIO u HOST_8/M_RXER/FLSH0_Sn/FLSH_RN/GPIO u E HOST_/M_LK/FLSH0_Sn/FLSH_LE/GPIO u E HOST_/M_TXEN/FLSH0_Sn7/FLSH_LE/GPIO u Y HOST_/M_MIO/FLSH_WRN/GPIO u HOST_/M_RXLK/SIO_M/FLSH_Sn0/GPIO u HOST_/M_RS/SIO_LKOUT/FLSH_Sn/GPIO_7_u HOST_/M_OL/FLSH_QS/FLSH_Sn/GPIO_0_u HOST_/M_TXLK/SIO_PWREN/FLSH_Sn/GPIO u V7 RK88_Q FLSH_ V8 M_TX M_TX M_TX0 M_TX V_LN M_TXEN M_TXLK 7 R R R8 R R R0 8 N R R R R R R PHY_TX PHY_TX M_RX M_RX PHY_TX0 PHY_TX M_RX0 M_RX M_M M_RXV M_LK PHY_TXEN M_MIO M_RXLK PHY_RST PHY_TXLK PHY_TX PHY_TX M_RX M_RX PHY_TX0 PHY_TX M_RX0 M_RX M_M M_RXV M_LK PHY_TXEN M_MIO M_RXLK PHY_RST PHY_TXLK PHY_TX0 R K7 V_LN M_MIO R7 K V_LN PHY_TX PHY_TX R R7 K7 K7 PHY_TX R8 K7 RK88 EthernetM ontroler FR_RK88 reate ate: Modify ate: Monday, May, 0 Thursday, ecember, 0 8

14 /0/00M-PHY PHY_XTL pf Y XOUT GN GN MHz-0ppm RY- PHY_XTL XIN pf If use external clock then the XTL need connect to GN for RTL8E. PHY_TX0 PHY_TX PHY_TX PHY_TX PHY_TXEN PHY_TXLK M_RX0 M_RX M_RX M_RX M_RXV M_RXLK PHY_RST MI+ MI- MI0+ MI0- MI+ MI- MI+ MI- LE_ LE0_0 MI0+ 8 MI0-8 MI+ 8 MI- 8 MI+ 8 MI- 8 MI+ 8 MI- 8 LE_ 8 LE0_0 8 M_LK R R N R PHY_XTL PHY_LKOUT M_M M_MIO M_LK _EPHY V_LN _EPHY MI0+ MI0- MI+ MI- MI+ MI- MI+ MI- U0 MI[0]+ MI[0]- MI[]+ MI[]- 7 8 MI[]+ MI[]- MI[]+ MI[]- N REGOUT 8 GN(EP) REGOUT V_LN PHY_LKOUT REG GN 7 LK REG PHY_XTL PHY_XTL _EPHY RSET ENSWREG REG KXTL KXTL 0 RSET ENSWREG 8 7 RXTL/PHY RX0/SELRGV RX/TXLY RX/N0 RX/N RX INT TX TX0 TX R V_LN R PHY_RST LE/PHY LE0/PHY0 PME LE_RXLY MIO M 0 PHYRST 8 7 TXTL TX TX R N.K% LE_ LE0_0 PHY_PME LE_RXLY M_MIO M_M PHYRST PHY_TXEN PHY_TX PHY_TX 0R PHYRST V_LN _EPHY PHY_PME _EPHY R N nf R R7 R R R R7 R R K7 K7 N PHY_RXV LE_ LE0_0 PHY ddress=00(rtl8e) N N PHY_RX PHY_RX onfig for all capability K7 K7 N LE_RXLY R8 Without RX elay PHY_RX Without TX elay PHY_PME PHY_INT ENSWREG R R8 R0 R R R0 R R R N N K7 K7 K7 N N K7 K7 0R onnect ENSWREG to to enable Switching regulator or connect ENSWREG to GN to disable Switching regulator. V_LN V_LN V_LN V_LN V_LN V_LN V_LN V_LN V_LN V_LN.7uF RTL8E-V-G _EPHY PHY_RXV PHY_RX0 PHY_RX PHY_RX PHY_RX PHY_RXLK PHY_INT PHY_TXLK PHY_TX0 PHY_TX V_LN V_LN REGOUT L.uH/. IN_X Inductance close to PIN8 0 uf 00 R N PHY_RX0 R K7 Pull down for.v RGMII(RTL8/8E) Pull up for.v RGMII (RTL8/8E) Pull up. /.8V RGMII (RTL8E-VL only) V_LN PHY_INT PHY_RX0 PHY_RX PHY_RX PHY_RX R8 R R70 R7 R R R R M_RX0 M_RX M_RX M_RX V_LN N PHY_RXLK PHY_RXV R7 R7 lose to PHY R R M_RXLK M_RXV REG lose to PIN. 70.7uF 00 7 /0/00M-PHY FR_RK88 reate ate: Monday, May, 0 Modify ate: Thursday, ecember, 0 8

15 UH MU_RK88 H URT0_RX/GPIO_0_u G URT0_TX/GPIO d URT0_TSn/GPIO u URT0_RTSn/GPIO u H SIO0_0/GPIO u H SIO0_/GPIO u G SIO0_/GPIO u H7 SIO0_/GPIO_7_u H8 SIO0_M/GPIO_0_u G8 SIO0_LKOUT/GPIO d F SIO0_ET/GPIO u E SIO0_WP/GPIO d SIO0_PWR/GPIO d F8 SIO0_KPWR/GPIO d E8 SIO0_INTn/GPIO u GPIO_7_u PIO_ RK88_H URT0_RX URT0_TX URT0_TS URT0_RTS SIO0_0 SIO0_ SIO0_ SIO0_ SIO0_M SIO0_LK T_WKE GPIO WIFI_REG_ON T_RST WIFI_HOST_WKE T_HOST_WKE 77 VIO_WL URT0_RX URT0_TX URT0_TS URT0_RTS SIO0_0 SIO0_ SIO0_ SIO0_ SIO0_M SIO0_LK T_WKE WIFI_REG_ON T_RST WIFI_HOST_WKE T_HOST_WKE GPIO URT0_RX 8 URT0_TX 8 URT0_TS 8 URT0_RTS 8 SIO0_0 8 SIO0_ 8 SIO0_ 8 SIO0_ 8 SIO0_M 8 SIO0_LK 8 T_WKE 8 WIFI_REG_ON 8 T_RST 8 WIFI_HOST_WKE 8 T_HOST_WKE 8 GPIO 8 RK88 SIO0 ontroler FR_RK88 reate ate: Modify ate: Monday, May, 0 Thursday, ecember, 0 8

16 U MU_RK88 HOST_0/TS_0/IF_/GPIO_0_d Y HOST_/TS_/IF_/GPIO d Y HOST_/TS_/IF_/GPIO d Y HOST_/TS_/IF_/GPIO d V HOST_KINP/TS_/IF_/GPIO d U HOST_KINN/TS_/IF_7/GPIO d U HOST_/TS_/IF_8/GPIO d U HOST_/TS_7/IF_/GPIO_7_d V HOST_/TS_SYN/IF_VSYN/GPIO_0_d R HOST_7/TS_VLI/IF_HREF/GPIO d R8 HOST_WKK/GPS_LK/TS_LKOUT/IF_LKIN/GPIO d V HOST_WKREQ/TS_FIL/IF_LKOUT/GPIO d R R7 IF_0/GPIO d R IF_/GPIO d R IF_/GPIO d R IF_/GPIO_7_d P I_SL/GPIO_0_u R I_S/GPIO u IF_ IF_ IF_ IF_ IF_ IF_7 IF_8 IF_ IF_VSYN IF_HREF IF_LKI IF_LKO IF_0 IF_ IF_PN0 IF_PN I_SL I_S IF_ IF_ IF_ IF_ IF_ IF_7 IF_8 IF_ IF_VSYN IF_HREF IF_LKI IF_LKOUT IF_0 IF_ IF_PN0 IF_PN I_SL I_S IF_ 8 IF_ 8 IF_ 8 IF_ 8 IF_ 8 IF_7 8 IF_8 8 IF_ 8 IF_VSYN 8 IF_HREF 8 IF_LKI 8 IF_LKOUT 8 IF_0 8 IF_ 8 IF_PN0 8 IF_PN 8 I_SL 8 I_S 8 RK88_ VPIO_ U0 0 R R7 0R N/0R V8_VP V8_VP IF_LKO R R IF_LKOUT 8 8pF UW MU_RK88 RK88_W MIPI_RX_0P G MIPI_RX_0N H MIPI_RX_P G MIPI_RX_N H MIPI_RX_LKP G MIPI_RX_LKN H MIPI_RX_P G MIPI_RX_N H MIPI_RX_P H8 MIPI_RX_N H7 MIPI_RX_REXT MIPI_RX V8 0 R.0K% MIPI_RX_0P 8 MIPI_RX_0N 8 MIPI_RX_P 8 MIPI_RX_N 8 MIPI_RX_LKP 8 MIPI_RX_LKN 8 MIPI_RX_P 8 MIPI_RX_N 8 MIPI_RX_P 8 MIPI_RX_N 8 V8_L UX MU_RK88 RK88_X MIPI_TX/RX_0P E0 MIPI_TX/RX_0N F0 MIPI_TX/RX_P E MIPI_TX/RX_N F MIPI_TX/RX_LKP E MIPI_TX/RX_LKN F MIPI_TX/RX_P E MIPI_TX/RX_N F MIPI_TX/RX_P F MIPI_TX/RX_N R MIPI_TX/RX_REXT MIPI_TX/RX V8.0K% MIPI_TX/RX_0P 8 MIPI_TX/RX_0N 8 MIPI_TX/RX_P 8 MIPI_TX/RX_N 8 MIPI_TX/RX_LKP 8 MIPI_TX/RX_LKN 8 MIPI_TX/RX_P 8 MIPI_TX/RX_N 8 MIPI_TX/RX_P 8 MIPI_TX/RX_N 8 V8_L UV MU_RK88 RK88_V MIPI_TX_0P G7 MIPI_TX_0N G8 MIPI_TX_P F7 MIPI_TX_N F8 MIPI_TX_LKP E7 MIPI_TX_LKN E8 MIPI_TX_P 7 MIPI_TX_N 8 MIPI_TX_P 7 MIPI_TX_N 8 R MIPI_TX_REXT E MIPI_TX V8.0K% MIPI_TX_0P 8 MIPI_TX_0N 8 MIPI_TX_P 8 MIPI_TX_N 8 MIPI_TX_LKP 8 MIPI_TX_LKN 8 MIPI_TX_P 8 MIPI_TX_N 8 MIPI_TX_P 8 MIPI_TX_N 8 V8_L UN MU_RK88 ep_tp_out/st_extr ep_lkm_in/mipi_lli_extr 7 Note:Placed close to the transmitter side T TEST ep_tx0p G ep_tx0n H ep_txp G ep_txn H ep_txp G ep_txn H ep_txp G7 ep_txn H7 ep_xup G8 ep_xun H8 EPTX0P EPTX0N EPTXP 7 00 EPTXN 7 00 EPTXP EPTXN EPTXP EPTXN EP_TX0P 8 EP_TX0N 8 EP_TXP 8 EP_TXN 8 EP_TXP 8 EP_TXN 8 EP_TXP 8 EP_TXN 8 EPUXP 8 EPUXN 8 R K% ep_extr 8 RK88_N ep V0 Y7 ep V8 7 _L V8_L isplay/vp Interface FR_RK88 reate ate: Monday, May, 0 Modify ate: Thursday, ecember, 0 8

17 UJ MU_RK88 F URT_RX/TS0_0/GPIO_0_u 7 URT_TX/TS0_/GPIO d H URT_TSn/TS0_/GPIO u URT_RTSn/TS0_/GPIO u 7 SPI0_LK/URT_TSn/TS0_/GPIO u SPI0_Sn0/URT_RTSn/TS0_/GPIO u 7 E SPI0_TX/URT_TX/TS0_/GPIO d F SPI0_RX/URT_RX/TS0_7/GPIO_7_u G SPI0_Sn/TS0_SYN/GPIO_0_u TS0_VLI/GPIO d E TS0_LK/GPIO d 8 TS0_ERR/GPIO d URT_RX 8 URT_TX 8 URT_TS 8 URT_RTS 8 SPI0_LK 8 SPI0_SN0 8 SPI0_TX 8 SPI0_RX 8 SPI0_SN 8 GPIO 8 GPIO 8 GPIO 8 RK88_J PIO_ Y 0 R0 R 0R N/0R V_IO V_8 TV /SPI Interface FR_RK88 reate ate: Modify ate: Monday, May, 0 Thursday, ecember, 0 7 8

18 V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_SYS V_LN VIO_WL VIO_WL V_SYS V_EFUSE V_IO V_8 V_8 V_8 V_8 V_IO V_IO V_IO V_IO V_IO V_IO V_IO V8_VP V8_VP V_ V_ L_ L_ L_ L_ L_ L_ L_7 L_ L_ L_ L_8 L_ L_0 L_8 OTG_P OTG_M HOST_P HOST_M HOST_M HOST_P HSI_T HSI_STROE L_ L_ L_ L_ L_ L_ L_0 L_ L_ L_7 TX_HP TX_- TX_+ TX_0- TX_0+ TX_- TX_+ TX_- TX_+ MIPI_TX_P MIPI_TX_0N MIPI_TX_0P MIPI_TX_LKN MIPI_TX_LKP MIPI_TX_N MIPI_TX_P MIPI_TX_N MIPI_TX_P MIPI_TX_N MIPI_RX_N MIPI_RX_0P MIPI_RX_0N MIPI_RX_LKP MIPI_RX_LKN MIPI_RX_P MIPI_RX_N MIPI_RX_P MIPI_RX_N MIPI_RX_P EP_TX0N EP_TX0P EP_TXN EP_TXP EP_TXN EP_TXP EP_TXP EP_TXN EPUXP EPUXN MI0+ MI0- MI- MI+ MI- MI+ MI- MI+ LE_ LE0_0 POWER_ON PWR_EN_SYS I0_S_PMI, I0_SL_PMI, SMM_0 SMM_ SMM_ SMM_ SMM_LK SMM_M SMM_ET efuse_pwr OTG_VUS_RV HOST_VUS_RV VP_PWR PMU_GPIO0 XNN_PWN PHONE_TL SPI_LK SPI_SN0 WORK_LE S_JTG_TMS S_JTG_TO S_JTG_TK S_JTG_TI POWER_LE HU_RST I_S I_SL I_S_HMI I_SL_HMI TX8_RST I_S_TP I_SL_TP URT_TX URT_RX _IN0 REOVER _IN IS_LRK_RX IS_SLK IS_SI IS_LRK_TX IS_MLK IS_SO0 SPIF_TX I_S_UIO I_SL_UIO IS_SO IS_SO IS_SO URT0_TX URT0_TS URT0_RTS SIO0_0 SIO0_ SIO0_ SIO0_ SIO0_LK SIO0_M WIFI_REG_ON WIFI_HOST_WKE T_RST T_WKE T_HOST_WKE URT0_RX URT_TS 7 URT_RTS 7 URT_TX 7 URT_RX 7 SPI0_RX 7 SPI0_TX 7 SPI0_LK 7 SPI0_SN0 7 GPIO 7 GPIO 7 SPI0_SN 7 GPIO 7 MIPI_TX/RX_N MIPI_TX/RX_0P MIPI_TX/RX_0N MIPI_TX/RX_LKP MIPI_TX/RX_LKN MIPI_TX/RX_P MIPI_TX/RX_N MIPI_TX/RX_P MIPI_TX/RX_P MIPI_TX/RX_N PWR_EN RESET, HMI_E SMM_PWR PU_ET URT_RX URT_TX GPIO7_ IF_POWER HP_ET RT_INT OTG_I OTG_ET FLSH0_RN FLSH0_LE FLSH0_LE FLSH0_RY GPIO GPIO8_0_U GPIO8_0_ GPIO8 GPIO7 GPIO7 U GPIO0 U GPIO0_7_U FLSH0_WRN FLSH0_S0 FLSH0_S FLSH0_S RT_LKOUT PWM PWR_INT LE_TL IR_INT IF_VSYN IF_HREF IF_LKI IF_LKOUT IF_0 IF_ IF_PN0 IF_PN I_SL I_S IF_ IF_ IF_ IF_ IF_7 IF_8 IF_ IF_ L_VSYN L_HSYN L_LK L_EN reate ate: Modify ate: MXM onnector FR_RK88 Wednesday, March 8, 0 Thursday, ecember, reate ate: Modify ate: MXM onnector FR_RK88 Wednesday, March 8, 0 Thursday, ecember, reate ate: Modify ate: MXM onnector FR_RK88 Wednesday, March 8, 0 Thursday, ecember, T0 TEST P_0 T0 TEST P_0 J 0- J J 0- J T TEST P_0 T TEST P_0