a31_pad_std

Transcription

1 PU.0V./.V PUS ebug Value an Not be hanged. Vpp=.V.V V-PM-PUS=.V V-HMI=.0V V-HP=.0V V-MIPI=.0V V-US=.0V V-P=.0V V-RT=.0V V-PLL=.0V V-P=.0V 0 mil lose to. PUS-URX PUS-TMS PUS-TK PUS-TO PUS-TI PUS-URX PUS-TMS PUS-TK PUS-TO PUS-TI JTG-SEL0 JTG-SEL P-RESET# VR VRP VR LR0 JTG-SEL JTG-SEL0 XMI XKI XKO XKI XKO XMI XMO RT-VIO P-KKO LR0 HPOM HPP VRP VR VR PU-VF PU-VF XMO HPP PLLTEST PLLV PLLVREG S0G S0G0 S0G SG SG0 SG PU-VSW PLLV PLLTEST SG S0G S0G0 S0G PLLVREG PU-VSW SG SG0 UOOT V-HMI V-US V-US V-HMI V-MIPI V-HP V-P V-SYS V-PUS V-PU V-PU V-GPU V-PM-PUS V-PM-PUS V-MIPI V-HP V-P VRT V-PLL V-PU V-PUS V-GPU V-SYS V-P OOT-SEL V-PM-PUS OOT-SEL0 PMU-SK PMU-S PM0 PM PM PM PM P-KKO P-NMI# P-RESET# HTX0P HTXP HTX0N HTXN HTXP HTXN HTXP HTXN HSL HHP HS UOOT US-M0 US-P0 US-M US-P US-M US-P LR0 MI-HIS MI-MIS MIP MIN MIP MIN MIP MIN HPOMF HPOM HPR HPL PU-VF SPKR SPKL SI-0N SI-0P SI-N SI-P SI-KN SI-KP SI-0N SI-0P SI-N SI-P SI-KN SI-KP URT-IO US-ITRL US0-VUSET GTX0 GTX GTX GTX URT-TX URT-RX URT-RTS URT-TS S0-ET GTXEN GTXLK GRX0 GRX GRX GRX US0-IET US0-RVVUS GRXV GRXLK ETXRR G-IO-ON GLKIN GM GMIO PHOUTN PHOUTP PHINP PHINN LINEINR LINEINL PL PL PL PL PL IR-RX TPX TPX TPY TPY PM PM SI-N SI-P SI-N SI-P SI-P SI-N SI-P SI-N TP-WKEUP TP-INT esign Name ate: Sheet of llwinner Technology o.,ltd PU _P_ST Wednesday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd PU _P_ST Wednesday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd PU _P_ST Wednesday, March, 0 R 0K R 0K TP STMS TP STMS 0 uf 0 uf TP TP 0uF/V 00 0uF/V uf uf TP STK TP STK R 00K % R 00K % SW sw_p_x_h SW sw_p_x_h 0uF/V 00 0uF/V 00 uf uf TP STO TP STO 0 0.uF 00.uF 00 nalog Interface HMI US RTP MIPI SI MIPI SI udio odec -G0i UM nalog Interface HMI US RTP MIPI SI MIPI SI udio odec -G0i UM HTX0P F HTX0N G HTXP F HTXN G HTXP E HTXN E HTXP F HTXN G V-HMI W HSL HS HHP UM0 T UP0 T UM U UP U V-US V UM V UP V TPX G TPX N TPY L TPY J PHOUTN L PHOUTP L PHINP J PHINN J HIS K MIS K MIINN N MIINP M MIINN K MIINP K MIINN J MIINP J VR K VR J V L VRP H LINEINR H LINEINL H J HPOUTR H HPOUTL H HPOMF G HPOM G HPP N V-HP G LR0 M LR M SI-0N SI-0P E SI-N 0 SI-P E0 SI-N SI-P E SI-N SI-P E SI-KN SI-KP E V-MIPI W SI-0N F SI-0P G SI-N F0 SI-P G0 SI-N F SI-P G SI-N F SI-P G SI-KN F SI-KP G LINEOUTR L LINEOUTL L 0 pf 0 pf uf uf TP STI TP STI GM L MIS -G0i UE GM L MIS -G0i UE P0/ETX0/L-0/URT-TR/P-EINT0 P/ETX/L-/URT-SR/P-EINT P/ETX/L-/URT-/P-EINT P/ETX/L-/URT-RING/P-EINT P/ETX/L-/URT-TX/P-EINT P/ETX/L-/URT-RX/P-EINT P/ETX/L-/URT-RTS/P-EINT P/ETX/L-/URT-TS/P-EINT P/ETXLK/L-/ELK-IN0/P-EINT P/ETXEN/L-/S-M/S-M/P-EINT P0/EGTXLK/L-0/S-LK/S-LK/P-EINT0 P/ERX0/L-/S-0/S-0/P-EINT P/ETX/L-/S-/S-/P-EINT P/ERX/L-/S-/S-/P-EINT P/ERX/L-/S-/S-/P-EINT P/ERX/L-/LK-OUT/P-EINT P/ERX/L-/MI-LK/P-EINT P/ERX/L-/MI-IN/P-EINT P/ERX/L-/LK-OUT/P-EINT E P/ERXV/L-/PWM-P/P-EINT E P0/ERXLK/L-0/PWM-N/P-EINT0 E P/ETXERR/L-/SPI-S0/P-EINT E P/ERXERR/L-/SPI-LK/P-EINT F P/EOL/L-/SPI-MOSI/P-EINT F P/ERS/L-LK/SPI-MISO/P-EINT F P/ELKIN/L-E/SPI-S/P-EINT F P/EM/L-HSYN/LK-OUT/P-EINT G P/EMIO/L-VSYN/ELK-IN/P-EINT G V0-P F0 V-P G0 R 0M-% R 0M-% 0 pf 0 pf.uf 00.uF 00 uf uf X X R0 -% R0 -% 0 pf 0 pf R R R N/ R N/ uf uf.uf 00.uF 00 uf uf pf pf PUS GPIO SYS trl ebug LK SR RT/PLL -G0i U PUS GPIO SYS trl ebug LK SR RT/PLL -G0i U PL0/TWI-SK P PL/TWI-S R PL/URT-TX R PL/URT-RX R PL/IR-RX R PL/PL-EINT0/TMS0 T PL/PL-EINT/TK0 U PL/PL-EINT/TO0 U PL/PL-EINT/TI0 T PM0/PM-EINT0 M PM/PM-EINT M PM/PM-EINT/WIRE K PM/PM-EINT M PM/PM-EINT N PM/PM-EINT N PM/PM-EINT N PM/PM-EINT/RT-KO N V-PM R VQE P UOOT-SEL JTG-SEL0 F JTG-SEL G OOT-SEL0 F OOT-SEL G TEST F NMI# P RESET# P XKI P XKO R VIO-RT T V-RT R XMI G XMO F PLLTEST V V-PLL V -PLL V S0G T S0G0 U S0G V SG SG0 SG PLLV W PLLVREG W PU-VSW H PUS GPU PU SYS OM -G0i U PUS GPU PU SYS OM -G0i U V0-PUS P V-PUS P V0-PU J V-PU J V-PU J V-PU J PU-VF F V-PU K V-PU K V-PU K V-PU K V-PU K V-PU L V0-PU L V-PU L V-PU L V-PU L V-PU M V-PU M V-PU M V-PU M V-PU M V0-PU N V-PU N V-PU N V0-GPU J V-GPU J0 V-GPU J V-GPU K V-GPU K0 V-GPU K V-GPU L V-GPU L0 V-GPU L V-GPU M V0-GPU M0 V-GPU M V0-SYS T V-SYS T V-SYS T V-SYS U V-SYS U V-SYS U V-SYS V V-SYS V V-SYS V V-SYS W V0-SYS W V-SYS W 0 J J K K K L L L M M 0 M N N0 N N N N V-PU N P P0 P 0 P P P P P P P R R0 R 0 R R R R R R R T T T 0 T T U U U U U U V V 0 V W W Y Y F E E X M-0pF-0PPM OS X M-0pF-0PPM OS R N/ R N/ 0 0 0uF/V 00 0uF/V R 0K R 0K uf uf uf uf TP SURX TP SURX uf uf uf uf.uf 00.uF 00

2 R././.V R/LVR/LPR Please copy RM P template and follow P layout guide. The circuit is only for single-side P layout. V-RM=.V V-LL =.V S0Q S0Q S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q S0QS0 S0QS0# S0QS S0QS# S0QS S0QS# S0QS S0QS# S0QM0 S0QM S0QM S0QM S00 S0 S0 S0 S0 S0 S0 S0 S0 S0 S00 S0 S0 S0 S0 S00 S0 S0 S0K S0K# S0KE0 S0WE# SS# S0S# S0S0# S0OT0 SST S0VREF S0K# S0K S0K# S0K S0VREF S0VREF S0VREF S0 S00 S0 S0 S0 S0 S0 S0 S0 S0 S0 S00 S0 S0 S0 S0 S0 S0Q0 S0Q S0Q S0Q S0Q S0Q S0Q S0Q S00 S0 S0 S0S# SS# S0WE# S0S0# S0KE0 S0VREF S0OT0 S0K S0K# S0QS0 S0QS0# S0QS S0QS# S0QM0 S0QM S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q S0Q SST S00 S0 S0 S0 S0 S0 S0 S0 S0 S0 S00 S0 S0 S0 S0 S0 S00 S0 S0 SS# S0S# S0S0# S0KE0 S0WE# S0VREF S0OT0 S0Q S0Q S0Q S0Q S0Q0 S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q S0Q0 S0Q S0QS# S0QS S0K S0K# S0QS S0QS# S0QM S0QM SST V-RM V-LL V-RM V-RM V-RM V-RM V-RM V-RM V-RM V-RM V-RM esign Name ate: Sheet of llwinner Technology o.,ltd Rx- _P_ST Wednesday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd Rx- _P_ST Wednesday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd Rx- _P_ST Wednesday, March, 0 R -% R -% U R-M* FG0PX U R-M* FG0PX 0 N P P N P P R R T R 0 L R N T T M 0 M N M QL0 E QL F QL F QL F QL H QL H QL G QL H QU0 QU QU QU QU QU QU QU K J K# K WE L RS# J S# K S# L KE K VREF M VREFQ H OT K VQ# VQ# VQ# F VQ# VQ# H VQ# VQ# H VQ# E VQ# V# R V# N V# V# K V# G V# K V# V# N V# R VSSQ# VSSQ# VSSQ# G VSSQ# E VSSQ# VSSQ# E VSSQ# VSSQ# F VSSQ# G VSS# E VSS# M VSS# P VSS# T VSS# J VSS# VSS# G VSS# J VSS# VSS#0 M VSS# P VSS# T QSL F QSL# G QSU QSU# ML E MU N# J N# L N# J N# L ZQ L RESET T uf uf R K-% R K-%.uF 00.uF 00 R R R K-% R K-% RM0 -G0i U RM0 -G0i U S0Q0 G S0Q J S0Q F S0Q K S0Q G S0Q K S0Q F S0Q J S0Q F S0Q K S0Q0 G S0Q K S0Q G S0Q J S0Q F S0Q J S0Q Y S0Q S0Q W S0Q S0Q0 W S0Q S0Q Y S0Q S0Q W S0Q S0Q V S0Q S0Q W S0Q S0Q0 V S0Q S0QS0 H S0QS0# H S0QS H S0QS# H S0QS S0QS# S0QS Y S0QS# Y S0QM0 L S0QM L S0QM S0QM S0K P S0K# R S0KE0 R S0KE L S0WE# M SS# L S0S# M S0S0# M S0S# K S0OT0 L S0OT J SST R S00 N S0 U S0 P S0 N S0 U S0 N S0 U S0 P S0 V S0 P S00 T S0 U S0 T S0 R S0 V S0 T S00 M S0 T S0 N S0ZQ H S0VREF R S0LLV V S0V0 H S0V J S0V K S0V L S0V M S0V M S0V N S0V N S0V P S0V P S00 T S0 T0 S0 U S0 U0 S0 V S0 W S0 W S0 Y S0 Y S0 0 0uF/V uF/V 00 R R 0 0 R -% R -% 0 0 uf uf uf uf uf uf 0 0uF/V uF/V uF/V uF/V 00 U R-M* FG0PX U R-M* FG0PX 0 N P P N P P R R T R 0 L R N T T M 0 M N M QL0 E QL F QL F QL F QL H QL H QL G QL H QU0 QU QU QU QU QU QU QU K J K# K WE L RS# J S# K S# L KE K VREF M VREFQ H OT K VQ# VQ# VQ# F VQ# VQ# H VQ# VQ# H VQ# E VQ# V# R V# N V# V# K V# G V# K V# V# N V# R VSSQ# VSSQ# VSSQ# G VSSQ# E VSSQ# VSSQ# E VSSQ# VSSQ# F VSSQ# G VSS# E VSS# M VSS# P VSS# T VSS# J VSS# VSS# G VSS# J VSS# VSS#0 M VSS# P VSS# T QSL F QSL# G QSU QSU# ML E MU N# J N# L N# J N# L ZQ L RESET T 0 0 N/0pF N/0pF 0 0 R -% R -% 0 uf 0 uf

3 R././.V R/LVR/LPR V-RM=.V V-LL =.V SQ S0 SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQS0 SQS0# SQS SQS# SQS SQS# SQS SQS# SQM0 SQM SQM SQM S S S S S S S S S S0 S S S S S0 S S SK SK# SKE0 SWE# SRS# SS# SS0# SOT0 SRST SVREF SK# SK SK# SK SVREF SVREF SVREF S S S0 S S S S S S S S S S0 S S S S SQ0 SQ SQ SQ SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ S0 S S SRS# SS# SS0# SKE0 SK SK# SWE# SVREF SOT0 SRST SQM0 SQS0 SQS0# SQM SQS SQS# SQ SQ SQ SQ SQ SQ SQ0 SQ SQ SQ SQ SQ SQ0 SQ SQ SQ S0 S S S S S S S S S S0 S S S S S SVREF SOT0 SS# SRS# SWE# S0 S S SS0# SKE0 SQM SQS SQS# SK SK# SQS SQS# SQM SRST V-RM V-LL V-RM V-RM V-RM V-RM V-RM V-RM V-RM V-RM esign Name ate: Sheet of llwinner Technology o.,ltd 0 Rx- _P_ST Monday, March 0, 0 esign Name ate: Sheet of llwinner Technology o.,ltd 0 Rx- _P_ST Monday, March 0, 0 esign Name ate: Sheet of llwinner Technology o.,ltd 0 Rx- _P_ST Monday, March 0, uf uf uf uf R R R -% R -% R -% R -% uf uf RM -G0i U RM -G0i U SQ0 E SQ E SQ E SQ SQ SQ SQ SQ E SQ G SQ G SQ0 F SQ F SQ G SQ F SQ F SQ G SQ SQ SQ SQ E SQ0 E SQ SQ E SQ E SQ F SQ F SQ G SQ G SQ F SQ G SQ0 G SQ F SQS0 E SQS0# SQS F SQS# G SQS SQS# E SQS G SQS# F SQM0 E SQM G SQM F SQM G SK G SK# G0 SKE0 F0 SKE 0 SWE# F SRS# SS# SS0# E SS# SOT0 F SOT SRST 0 S0 F S S S G S E S G S E S E S F S F S0 S E S G S E0 S S F S0 E S G S SZQ SVREF SLLV W SV0 R SV T SV U SV SV SV 0 SV SV SV SV S0 V0 S W0 S S S S S S S S uf uf 0 0uF/V uF/V 00 N/0pF N/0pF R K-% R K-% 0 0 U R-M* FG0PX U R-M* FG0PX 0 N P P N P P R R T R 0 L R N T T M 0 M N M QL0 E QL F QL F QL F QL H QL H QL G QL H QU0 QU QU QU QU QU QU QU K J K# K WE L RS# J S# K S# L KE K VREF M VREFQ H OT K VQ# VQ# VQ# F VQ# VQ# H VQ# VQ# H VQ# E VQ# V# R V# N V# V# K V# G V# K V# V# N V# R VSSQ# VSSQ# VSSQ# G VSSQ# E VSSQ# VSSQ# E VSSQ# VSSQ# F VSSQ# G VSS# E VSS# M VSS# P VSS# T VSS# J VSS# VSS# G VSS# J VSS# VSS#0 M VSS# P VSS# T QSL F QSL# G QSU QSU# ML E MU N# J N# L N# J N# L ZQ L RESET T 0 0uF/V uF/V 00 R0 -% R0 -% R K-% R K-% U R-M* FG0PX U R-M* FG0PX 0 N P P N P P R R T R 0 L R N T T M 0 M N M QL0 E QL F QL F QL F QL H QL H QL G QL H QU0 QU QU QU QU QU QU QU K J K# K WE L RS# J S# K S# L KE K VREF M VREFQ H OT K VQ# VQ# VQ# F VQ# VQ# H VQ# VQ# H VQ# E VQ# V# R V# N V# V# K V# G V# K V# V# N V# R VSSQ# VSSQ# VSSQ# G VSSQ# E VSSQ# VSSQ# E VSSQ# VSSQ# F VSSQ# G VSS# E VSS# M VSS# P VSS# T VSS# J VSS# VSS# G VSS# J VSS# VSS#0 M VSS# P VSS# T QSL F QSL# G QSU QSU# ML E MU N# J N# L N# J N# L ZQ L RESET T 0uF/V 00 0uF/V 00 uf uf R R 0 0

4 NN V-P oth emm NN and TSOP NN layout together Nand Flash, emm-nn, etc UG oot: V0-P G Nand/S/SPI V-P G P0/NN0-WE/SPI0-MOSI P/NN0-LE/SPI0-MISO P/NN0-LE/SPI0-LK P/NN0-E P/NN0-E0 P/NN0-RE P/NN0-R0/S-M/S-M P/NN0-R/S-LK/S-LK P/NN0-Q0/S-0/S-0 P/NN0-Q/S-/S- P0/NN0-Q/S-/S- P/NN0-Q/S-/S- P/NN0-Q/S-/S- P/NN0-Q/S-/S- E P/NN0-Q/S-/S- P/NN0-Q/S-/S- P/NN0-Q/NN-Q0/TRE-OUT0 P/NN0-Q/NN-Q/TRE-OUT P/NN0-Q0/NN-Q/TRE-OUT P/NN0-Q/NN-Q/TRE-OUT P0/NN0-Q/NN-Q/TRE-OUT P/NN0-Q/NN-Q/TRE-OUT P/NN0-Q/NN-Q/TRE-OUT P/NN0-Q/NN-Q/TRE-OUT F P/NN0-QS/S-RST/S-RST P/NN0-E P/NN0-E F P/SPI0-S0 -G0i -G0i V-PH PWM0 TWI-SK TWI-S TWI-SK TWI-S V-PH=.0V L-PWM TWI-SK TWI-S TWI-SK TWI-S TWI0 pull-up by V-PE in amera Page TWI-SK TWI-S TWI-SK TWI-S V-PH Pull-Up Resistor for TWIs Toggle and TSOP NN N0WE N0LE N0LE N0E N0E0 NE N0 N N0Q0 N0Q N0Q N0Q N0Q N0Q N0Q N0Q NQ0 NQ NQ NQ NQ NQ NQ NQ N0QS N0E N0E UL 0 NN V0-PH J MIS V-PH G NWE PH0/NN-WE/TRE-OUT NLE PH/NN-LE/TRE-OUT NLE PH/NN-LE/TRE-OUT0 NE PH/NN-E/TRE-OUT NE0 PH/NN-E0/TRE-OUT NRE PH/NN-RE/TRE-OUT NR0 PH/NN-R0/TRE-OUT NR PH/NN-R/TRE-OUT NQS PH/NN-QS/TRE-LK 0 PH/SPI-S0/TMS/PWM-P F SPI-S0 PH0/SPI-LK/TK/PWM-N F SPI-LK PH/SPI-MOSI/TO/PWM-P G SPI-MOSI PH/SPI-MISO/TI/PWM-N G0 SPI-MISO L-PWM PH/PWM0 TWI0-SK PH/TWI0-SK 0 TWI0-S PH/TWI0-S 0 TWI-SK PH/TWI-SK TWI-S PH/TWI-S 0 TWI-SK PH/TWI-SK TWI-S PH/TWI-S URT0-TX PH0/URT0-TX URT0-TX URT0-RX PH/URT0-RX G URT0-RX F PH SPK_MUTE G PH P-SHN# F0 PH PH US-HU-RV G VG_EN PH VG_EN F TVIN_EN PH TVIN_EN L-L-EN PH/SPIF-IN G L-L-EN F PH PH/SPIF-OUT/TRE-TL PH F NE PH/NN-E NE PH0/NN-E R K R K R K R K emm NN emm-m emm-lk emm-0 emm- emm- emm- emm- emm- emm- emm- emm-rst P uf V-PE emm-0 emm- emm- emm- emm- emm- emm- emm- emm-m emm-lk emm-rst V-P V-NN U H H T0 H T J T J T J T J T J T W T W M U LKM RSTN K VI U R0 VSSM P VSSM M VSSM VSSM R K R K V-NN V-P M-SK M-S emm NN N/eMM-G R 0K emm-m M VM N VM T0 VM U VM K VQM W VQM Y VQM VQM VQM K VSSQM Y VSSQM Y VSSQM VSSQM VSSQM MIPI-SI-SK MIPI-SI-S V-NN =.0V V-LPR =.V R V-NN V-P V-P TWI0-SK TWI0-S OOT-SEL0 V-P R 0K N R0 R 0K N0 V-NN V-P R 0K NR R R 0K NR0 V-NN R 0K NWP R N/ /N R N/ R N/ /N V-NN R N/ V R0 N/ NX NRX N NX N0 NE N0E0 N0E N0E N0E N0LE N0LE N0WE NWP NR NRX NR0 NRE NE0 NE NE NE NLE NLE NWE NWP TSSOP E ount() V-NN V-NN U RES# N N R# R# R# R# RE# 0 E# E# N V VSS E# E# LE LE WE# 0 WP# N N N N N NN FLSH G X TSOP- U RES# N N R# R# R# R# RE# 0 E# E# N V VSS E# E# LE LE WE# 0 WP# N N N N N N/NN FLSH X TSOP- Resistor Resistor isconnect isconnect onnect N N N0 N IO IO IO IO 0 N N VSS V VSS N N N IO IO 0 IO IO0 N N N N0 N N N0 N IO IO IO IO 0 N N VSS V VSS N N N IO IO 0 IO IO0 N N N N0 isconnect isconnect onnect V-NN TS0 TS TS N0Q N0Q N0Q N0Q TSLK V N0QS TSM N0Q N0Q N0Q N0Q0 TS V-NN TS0 TS TS NQ NQ NQ NQ TSLK V NQS TSM NQ NQ NQ NQ0 TS N/ N/ R N/ 0 N/.uF 00 R N/.uF 00 NX N0 N0Q N0Q N0Q N0Q0 NRX NR0 NQ NQ NQ NQ0 N/ TSLK TSM TS TS TS TS0 V-NN TSLK TSM TS TS TS TS0 V-NN V-LPR R = =N:Use nand flash. =N =:Use emm nand flash. N/ OOT-SEL R =N =N:oot from raw nand flash =N =:oot from emm nand flash N/ llwinner Technology o.,ltd esign Name _P_ST NN ate: Monday, March 0, 0 Sheet of

5 POWER/PMU.V.V.0V.V.V.V/.V.V.V.V.V.V.~.V.0V.0V.V.V.V V-RM././.V.V.0V Name LO LO LO GPIO0 LO LO LO ELO ELO efault Voltage Maximum urrent omment For GPIO.0V efault ON For GPU.V efault ON For PU.V efault ON For System.V 00m efault ON For RM.V efault ON 0V.V V 0V GPIO 0V GPIO0/LO GPIO/LO LO LO LO LO ELO -SW V-V0 V-V V-PU V-GPU V-SYS V-PUS V-RT V-PG V-P V-P V-P 00m 00m 00m 00m 00m V-WIFI V-LPR R N V-IR V-SI-EN VV-L V-G VV-SI VV-SI VV-L V-L V-SI V-NN V-HMI R R V-PF V-SMM V-LL FV-SI V-PH R R V-SI V-PM-PUS V-PE efault OFF For.V IO/LPR efault ON For SO nalog efault ON efault OFF efault OFF V-HP V-PLL V-P V-HP R uf uf V-MIPI Name LO LO LO LO ELO ELO P-RESET# efault Voltage 0V 0V 0V 0V 0V 0V LO option:.up00.pl.gl0 NOTE: Q vth <.V & R <0mohm@vgs=.V up00 V-RT Maximum urrent 00m 00m 00m 00m 00m 00m EN P-MOSFET option:.ts0.k.e0.wpm U V-RT VIN VOUT Q MMT0 SOT- R0 0K R 00K F R N V-PUS =.V RESET omment efault OFF efault OFF efault OFF efault OFF efault OFF efault OFF V-PUS R K R 0K US0-RVVUS PMU-SK PMU-S P-NMI# R 0 uf 0K SW sw_ts_0_mcd TS-0/M ELO 0V 00m efault OFF For PUS, From / LO.V 00m efault ON For L, From / SW.0V 0.ohm efault OFF For RT RT-V V 0m lways On OPTION: V-RT R 0 0uF/V00 R 0K 0 0uF/V00 0uF/V00 0uF/V00 0 mil 0.uF 00 MT-RV-N POWEN IN 0 mil 0uF/V00 USVUS 0 mil 0uF/V00 0uF/V00 LO 0uF/V00 0uF/V00.uF 00 V-V0 uf R K R 0K LO LO GPIO0/LO GPIO/LO uf uf 0 mil 0 mil 0 mil V-RT 0 mil U P_.0V U0 IN IN N_VUSEN SK S IRQ OK VUS N_TRV TSENSE 0 LOSENSE HSENSEN 0 HSENSEP LX_HG LX_HG VIN_HG VIN_HG P_HG 0 TS R N INPUT VOUT EN YS HGLE ON V_RT LOIN LO LO LO GPIO0/LO GPIO/LO VINT VREF XP N/0 LOs V-US harger & Meter uf / / / / / LOs ELOs SW VIN P LX_ LX_ VIN P 0 SET LO ELOIN LX LO LO ELO ELO LOIN LO LO LX_ LX_ VIN P_ P_ LX_ 0 LX_ VIN P LX VIN P ELO 0 0 mil L.uH_._R<0.R -SW 0 mil 0 mil 0 mil 0 mil V-SYS L.uH_0._R<0.R 0 mil LO LO LO LO V-V0 ELOIN ELO ELO ELO esign Name V-V0 V-GPU L.uH R<0.R R N mil 0 mil 0 mil Inductor option:.sph0metg.swp0srnt.swp0srnt.ellgrn.e0-rms- V-GPU V-PUS.uF 00 PU-VF V-RM V-V0 V-SYS llwinner Technology o.,ltd _P_ST PMU V-PU L 0.uH R<0.R 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0uF/V00 0 mil 0 mil V-RM L.uH R<0.R 0uF/V00 0uF/V00 R N.uF 00.uF 00.uF 00.uF 00.uF 00.uF 00.uF 00.uF 00 0.uF 00.uF 00.uF 00 ate: Wednesday, March, 0 Sheet of

6 POWER-/ J IN -00 POWER INPUT VST ST J con_p_r_xh F FUSE_V_. SS TVS-SMJ TVS-SO V-VST 00 + T 0uF/V 00uF/V P_TH_0P0 IN-V 0.uF/0V 00 R0 00K R00 R N/00K R00 /0V 00 IN N EN L uh-r<0.r- 0 R SW K/% R00 F OMP /V U 00 MPEN R R SOP_EP SS K 0K/% O- N R00 R00 00 TP S 00 0/0V V-V 00 0uF/V 0 IN 00 0uF/V 0.uF/V 00 SO R0 00K Q O SOT- V-P R0 0K 0.uF Q MMT0 SOT- R0 0K R.K N/0.uF IN SO ST-V T N/RF RF RT TT J T T N/ON MM_SM N/TT R0_SMT R0TT R0_SMT V-RT IN SO IN SO VRT V-V0 V-V V-V V-V V-V LE00/LUE R LE00 N/LE00/LUE RN/0 LE00 N/LE00/LUE RN/0 LE00 N/LE00/LUE RN/0 LE00 T 与 T 为钮扣电池封装 T 为法拉电容封装 J 为 PIN 连接器 个物料只能选择一个使用如使用法拉电容及充电钮扣电池时, 则 R 要接上, 以便能够对法拉电容及电池充电 R N/.K IN SO llwinner Technology o.,ltd esign Name _P_ST /-RT ate: Monday, March 0, 0 Sheet of

7 V-P=.0V ual link:lvs0+lvs Single link:lvs0 LVS MIPI RG.V L L-TP V-PE=.V.V SI lose to P. lose to camera. V-SI =.V V-SI =.V FV-SI =.V VV-SI=.V V-SI =.V VV-SI=.V LVS0-P L0- LVS0-0N L0- LVS0-0P L0-0 LVS0-LKP L0- LVS0-N L0- LVS0-P L0- LVS0-N L0- SI-TE L0-VSYN LVS0-LKN L0- L0- LVS0-N L0- LVS0-P LVS-N L0- L0- LVS-P L0- LVS-N L0- LVS-P L0- LVS-0N L0-0 LVS-0P L0-0 L0- LVS-N L0- LVS-P L0- LVS-LKN LVS-LKP L0- L0-E L0-LK L0- L0- L0- L0-HSYN V_LVS LVS0-0N LVS0-0P LVS0-N LVS0-N LVS0-LKN LVS0-N LVS-0N LVS-N LVS-N LVS0-LKP LVS0-P LVS-0P LVS-P LVS-P LVS0-P LVS0-P LVS-LKN LVS-N LVS-LKP LVS-P L0-0 L0- L0- L0- L0-LK L0-E L0-VSYN L0-HSYN L- PWM V_LVS L- TWI-S TWI-SK TP-INT TP-WKEUP SI-MLK SI-0 SI- SI-EN SI- SI-F-IO SI- SI-HSYN PLK SI-0 M-STY-EN M-RESET# SI- PLK SI-MLK L0-L-EN SI-SK SI-VSYN SI-MLK SI- SI- SI- SI- M-STY-EN SI-PLK SI-S SI-HSYN SI- SI- SI- SI-0 M-RESET# SI-EN SI-F-IO V-P L_V IN-V V-V V-V V-V V-V IN-V V-V V-V V-V V-PE V-SI V-V V-V V-V FV-SI V-V VV-L VV-SI VV-SI L0- L0- L0- L0-LK L0-E L0-HSYN L0-VSYN L0-0 L0- L0- L0- L0- L0- L0- L0- L0- L0- L0-0 L0- L0- L0- L0- L0- L0- L0- L0- L0- L0-0 PWM0 L-L-EN TP-INT PWM0 L-L-EN SI-PLK SI-MLK SI-HSYN SI-VSYN URT-TX URT-RX SI- SI- SI- SI- SI- SI- SI- SI- SI-0 SI- MIPI-SI-MLK TWI-S TWI-SK TP-WKEUP TWI0-S TWI0-SK SI-0N SI-0P SI-N SI-P SI-KN SI-KP SI-P SI-N SI-P SI-N MIPI-SI-MLK SI-0N SI-0P SI-N SI-P SI-KN SI-KP SI-N SI-P SI-N SI-P TWI-SK TWI-S SPI-S0 SPI-LK SPI-MOSI SPI-MISO M-RESET# PH TX RX RTS TS URT-TX URT-RX TPX TPX TPY TPY P PM PM PM esign Name ate: Sheet of llwinner Technology o.,ltd ISPLY-M.0 _P_ST Thursday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd ISPLY-M.0 _P_ST Thursday, March, 0 esign Name ate: Sheet of llwinner Technology o.,ltd ISPLY-M.0 _P_ST Thursday, March, 0 TP TP TP TP R N/00K R N/00K N N R N/ R00 R N/ R00 R 0K R 0K Q MMT0 SOT- Q MMT0 SOT- TP TP SI TS -G0i UI SI TS -G0i UI PE0/SI-PLK/TS-LK/PE-EINT0 PE/SI-MLK/TS-ERR/PE-EINT PE/SI-HSYN/TS-SYN/PE-EINT PE/SI-VSYN/TS-VL/PE-EINT PE/SI-0/URT-TX/PE-EINT PE/SI-/URT-RX/PE-EINT PE/SI-/URT-RTS/PE-EINT PE/SI-/URT-TS/PE-EINT PE/SI-/TS-0/PE-EINT PE/SI-/TS-/PE-EINT PE0/SI-/TS-/PE-EINT0 PE/SI-/TS-/PE-EINT PE/SI-/TS-/PE-EINT PE/SI-/TS-/PE-EINT PE/SI-0/TS-/PE-EINT PE/SI-/TS-/PE-EINT PE/MSI-MLK/PE-EINT V-PE F J ON_0P_x_IP_R0 ON_0P_x_IP_R0 J ON_0P_x_IP_R0 ON_0P_x_IP_R0 V_0 V_ V_ N _0 _ S0_V0- S0_V0+ S0_V- S0_V+ 0 S0_V- S0_V+ _ - S0_V- S0_V+ S0_V- S0_V+ S_V0- S_V0+ 0 S_V- S_V+ S_V- S_V+ S_V- S_V+ S_V- S_V+ 0 R 0 R 0 TP TP R N/00K R N/00K J ON_P_R0_PH ON_P_R0_PH J ON_P_R0_PH ON_P_R0_PH TP TP TP TP R 0K R 0K TP TP TP TP OQ O0 SOT-- OQ O0 SOT-- TP TP TP TP SW SW_MSK-0/M SW SW_MSK-0/M TP TP R* RN R* RN TP TP TP TP Q MMT0 SOT- Q MMT0 SOT- TP TP TP TP L0 LVS -G0i UH L0 LVS -G0i UH P0/L0-0/LVS0-VP0 T P/L0-/LVS0-VN0 T P/L0-/LVS0-VP U P/L0-/LVS0-VN U P/L0-/LVS0-VP V P/L0-/LVS0-VN V P/L0-/LVS0-VP W P/L0-/LVS0-VN W P/L0-/LVS0-VP Y P/L0-/LVS0-VN Y P0/L0-0/LVS-VP0 W P/L0-/LVS-VN0 W P/L0-/LVS-VP Y P/L0-/LVS-VN Y P/L0-/LVS-VP P/L0-/LVS-VN P/L0-/LVS-VP P/L0-/LVS-VN P/L0-/LVS-VP P/L0-/LVS-VN P0/L0-0 P/L0- P/L0- P/L0- P/L0-LK P/L0-E P/L0-HSYN P/L0-VSYN V0-P V V-P W V-P W TP TP TP TP TP TP TP TP TP TP TP TP TP TP R* RN R* RN TP TP uf uf TP TP TP TP R 0K R 0K N N Q MMT0 SOT- Q MMT0 SOT- TP TP R R TP TP TP TP TP TP R R R R TP TP uf uf TP TP TP TP R 0K R 0K TP TP TP TP TP TP TP TP TP TP R0 R R0 R 0uF/V 00 0uF/V 00 R 0K R 0K N N TP0 TP0 R0 0K R0 0K TP0 TP0 TP TP R 00K R 00K TP0 TP0 R 0K R 0K TP TP R R TP TP R 0K R 0K R 00K R 00K R R J ON_0P_0x_IP_R0 ON_0P_0x_IP_R0 J ON_0P_0x_IP_R0 ON_0P_0x_IP_R J ON_P_R0_PH ON_P_R0_PH J ON_P_R0_PH ON_P_R0_PH TP TP TP TP SW SW_MSK-0/M SW SW_MSK-0/M TP0 TP0 TP TP J ON_0P_x_IP_R0 ON_0P_x_IP_R0 J ON_0P_x_IP_R0 ON_0P_x_IP_R R 0K R 0K TP0 TP0

8 US-HU-OTG&HOST ifferential pairs Z0= 0 ohm V-V US-P0 US-M0 US0-RVVUS US0-VUSET US0-IET US-ITRL US-P0 US-M0 US0-RV US0-VUSET US0-IET US-ITRL V-V U0 IN US0-RV EN 0uF/V R 00 0K OUT ISET US-ITRL R 00K R SY0 K-% SOT-- Q SOT- MMT0 R K-% US0-VUSET lose to PU R K 0.uF/V R 00K USVUS US-M0 US-P0 0.uF/V 00 ES00 ES0 ES00 ES ES00 ES ES00 ES TP0 TP0 US0-IET L 0@00M ES-00-LF l00 Ilim ()=00/Rset (ohm) V-V TP0 TP TP TP U GL0G uf HU-V SSOP- HOST-P HOST-M V P HOST-M R0 M M HOST-P P US-P 0uF/V 00nF P P0 M US-M 00 L L00 HU-V RREF M0 uf HU-X V V 0-00M HU-X XTL V HOST-M XTL EN OVUR# HU-V HU-V HOST-P M OVUR# 0 HU-V 0 P EN R N/ HU-V uf G-M HOST-M V OVUR# PGNG G-P HOST-P M PGNG R 00K ELF R K HU-RST# P ELF RESET# V TEST SSOP 00nF R 0K L 0@00M l00 HOST-M HOST-P HOST-M HOST-P ES00 ES ES00 ES ES00 ES ES00 ES ES-00-LF ES-00-LF V-V HU-V V-V TP TP R 0K Q O SOT- V-V TP HOST-M HOST-P 0uF/V 00 TP TP TP VUS uF/V 00 US-M US-P US-M US-P US-HU-RV US-HU-RV R Q0 MMT0 SOT- ON_P_R0_PH ON_P_R0_PH N 贴装 USWIFI ETV 时, 此连接器 N V-V TP0 TP TP00 ES-00-LF TP0 ES-00-LF ES-00-LF TP R 0K VUS - + I miniusb_pin usb-b-va/mcd N FG0 FG FG FG TP TP TP ES-00-LF ES-00-LF 0 N VUS - + VUS - + F0 F F F con_p_usb_ax US X 0uF/V 00 VUS - + ON_P_R0_PH ON_P_R0_PH N 0K R 0K HU-V R 0K HU-RST# uf V-V R K OVUR# R K HU 电源不能与其他电源公用,HU 的供电要与 US 驱动同步, 同时受驱动的控制, 才可提高 US 兼容性 HU-X pf R0 N Y MHZ/0PF HU-X pf M M M M 0uF/V 00 HOST-M HOST-P 贴装 G 模块时, 此连接器 N llwinner Technology o.,ltd esign Name VUS - + ON_P_R0_PH ON_P_R0_PH N _P_ST US-HU-OTG&HOST.0 ate: Thursday, March, 0 Sheet of

9 Head Phone & Speaker Microphone HPOMF HPOM HPR HPL R R R N/ R R uf uf F 0-00M L00 F 0-00M L00 R HS-MI R L S R L 0/00M L00 ON_HP_PJ_F N PJ-F/M TP TP TP TP TP S L R ES ES-00-LF ES00 ES ES-00-LF ES00 ES ES-00-LF ES00 MIP MIN MI-HIS MIP MIN MI-HIS 00nF 00nF 0uF/V 00 N/pF R0 N/pF R K HS-MI pf HS-MI V-V HS-MI ES ES-00-LF ES00 MI-HIS with current detection function. R 0K SPK_MUTE 低有效 R 0K R 0K Q MMT0 SOT- MUTE 0uF/V 00 uf 00 IN-V ROUTN 00 0pF L M F0 00 uf ROUTP IN-V 00 0pF L M F 00 0 uf 00 0uF/V 00 uf V-V V-V 0 uf 00 IN-V + T 00uF/V P_TH_0P0 ROUTP ES ES-00-LF ES00 V-V R K P-SHN# R.K R0 00K 广告机不会有待机控制, 此部份电路去掉不用 IN-V R 00K 高有效 S Q MMT0 SOT- SPKR SPKR uf uf uf SPKL SPKL uf R0 K R K R K R K uf MUTE V-V 00 0uF/V 00 N_0 RINN RINP MUTE V LINP LINN N_ U PM00 QFNPX IN-V LOUTN PR PVR 0 ROUTN 0 SRN SRP ROUTP PVR PR PL PVL LOUTN SLN SLP LOUTP PVL PL uf 00 F 0-00M L00 0pF 00 N_ S V VLMP 0 VP OS N_ 0 uf 00 F 0-00M L00 0pF 00 LOUTP IN-V S uf 00 0pF uf uf uf 00 0uF/V 0uF/V 00 IN-V N/ N/ N/ 0 N/ R N/0K R N/0K R N/0K R0 N/0K ROUTN LOUTP LOUTN ROUTP ROUTN LOUTP LOUTN ES ES-00-LF ES00 ES ES-00-LF ES00 ES0 ES-00-LF ES00 ON ON_P_R0_PH ON_P_R0_PH TP TP TP TP llwinner Technology o.,ltd esign Name _P_ST UIO.0 ate: Thursday, March, 0 Sheet of

10 HMI/S/TF HMI HMI HTX0P HTX0N HTXP HTXN HTXP HTXN HTXP HTXN HSL HS HHP TX0P TX0N TXP TXN TXP TXN TXP TXN HMI-SL HMI-S HET TXP TXN TXP TXN TX0P TX0N TXP TXN HMI-SL HMI-S HET R K R 0K HSL HS HET HMI-V U FN0-0P 0 IN OUT IN OUT IN OUT IN OUT U FN0-0P 0 IN OUT IN OUT IN OUT IN OUT TXP TXN TXP TXN TX0P TX0N TXP TXN U FN0-0P 0 HMI-SL IN OUT HMI-S IN OUT HMI-V IN OUT HET IN OUT R K R0 K N SO 0 N P G_ N P G_ N 0P G_0 0N LKP G_LK LKN E N SL S G_/E +V HOT_PLUG_ET SHIEL SHIEL SHIEL SHIEL 0 ifferential pairs Z0= 00 ohm LYOUT 差分走线过孔不能超过 个, 有完整铺地 HMI_plug type con_hdmi_a V-V R V-P V-V0 TP TP TP TP TP TP V-V R K R K For oot/storage J0././.V S/MM ard & ebug UJ S0 G G V-PF E PF0/S0-/TMS E PF/S0-0/TI PF/S0-LK/URT0-TX E PF/S0-M/TO PF/S0-/URT0-RX PF/S0-/TK -G0i V-PF V-PF=.0V S0- S0-0 S0-LK S0-M S0- S0- S0- S0-M S0-LK S0-0 S0- S0- R R R R R R R R R0 R R R S SM SLK S0 S S J T M VSS V LK 0 VSS 0 T0 WP 0 T T P P N/SMM/SLOT H_S_R_ S0-ET TP0 S 卡与 TF 卡为二选一贴片 S0- S0- S0-M S0-LK S0-0 S0- S0-ET ES00 ES ES-00-LF ES00 ES ES-00-LF ES00 ES ES-00-LF ES00 ES ES-00-LF ES00 ES ES-00-LF ES00 ES ES-00-LF T T M V LK VSS T0 T # 0 MIROS/TF_SLOT TFLSH S0-ET S0-ET llwinner Technology o.,ltd esign Name _P_ST HMI/S/TF.0 ate: Thursday, March, 0 Sheet 0 of

11 TP TP TP TP ON_P_R0_PH ON_P_R0_PH URT0_RX URT0-RX URT0_TX URT0-TX J 00 0uF/V V-V URT-RX URT-TX URT-RTS URT-TS TX RX V-V 00 URT-RX URT-TX URT-RTS URT-TS 00 uf/v V TOUT RIN ROUT 0 TIN TIN ROUT U + V V- TOUT RIN MXE SSOP_W0_PT0 RTS TS uf/v 00 uf/v 00 uf/v 00 TX RX TX RX V-V ON_P_R0_PH ON_P_R0_PH ON0 TP0 TP TP TP URT-TX R0 N/ TX URT-RX R0 N/ RX URT-RTS R N/ RTS RTS URT-TS R N/ TS TS URT 为 RS 串口 V-V URT-RX URT-IO URT-TX R U RO RE E I SP V 0K R 0K R R V-V ON_P_R0_PH ON_P_R0_PH ON TP TP TP TP URT-TX R0 N/ URT-RX R N/ R R 使用的时候可以将 U 电路去掉不用此时 ON 变为 TTL 串口方式通讯 POWON RESET UOOT LR0 V-P R00 00K-% R N/K N/ U0 O V ST N N0 SL S N/M0 V-V SEURITY I M0 TWI-SK TWI-S ES0 ES-00-LF ES ES-00-LF ES ES-00-LF ES ES-00-LF ON ON_P_R0_PH ON_P_R0_PH U O V ST N N0 SL S N/M0 Option 此为同型号不同封装, 二选一贴片 llwinner Technology o.,ltd esign Name _P_ST URT-SW.0 ate: Monday, March 0, 0 Sheet of

12 GM 0/00/000 RGMII Ethernet PHY.uF 00 V-V0 R 00K U GM-V INPUT VOUT EN YS.uF P-.V 0 00 pf Y MHz/pF pf MI0+ MI0- MI[0]+ V0 MI[0]- MI+ V0_0 MI- MI[]+ EPHY-V MI[]- MI+ V_0 MI- MI[]+ V0 MI[]- MI+ 0 V0_ MI- MI[]+ MI[]- N REGOUT (EP) REGOUT LK VREG VREG EPHY-V V0 RSET ENSWREG EPHY-V 0 LK VREG_ VREG_0 KXTL KXTL V_ V0_ RTL RTLE RXTL/PHY RX0/SELRGV V_0 RX/TXLY RX/N0 RX/N RX INT V_ TX TX0 TX R K-% R RSET ENSWREG V EPHY-V U V0_ LE/PHY LE0/PHY0 PME LE_RXLY MIO M 0 PHYRST V0_0 TXTL TX TX V0 LE- LE0-0 PME LE-RXLY MIO M PHYRST V0 TXTL TX TX Note : The Trace length between La and PHY's Pin must be within 0. cm. J(uF) and K(0.uF) to La must be within 0.cm. RXLY=: LE Low ctive, E, F reserve for EMI. E La L.uH-00m REGOUT PHY0=: LE0 Low ctive c00 uf J PHY=0: LE High ctive LE0-0 LE- 00pF-N 00pF-N K pin,,0 R Reserve for EMI pin, 0 V0 V0 0 RXTL- RX0-SELRGV EPHY-V RX-TXLY RX-N0 RX-N RXLK INT EPHY-V TXLK TX0 TX ifferential pairs Z0= 00 ohm PHYRST EPHY-V R 0K PME INT R0 K R K R /N M-RST EPHY-V GLKIN Place filter network close to LK. Reserved for EMI GLKIN R LK GM-V R R00 pin, EPHY-V GRXLK GTXLK GRXV GRX0 GRX GRX GRX GTXEN GTX0 GTX GTX GTX ETXRR GMIO GM Place filter network close to RX_LK. Reserved for EMI GRXK GTXK GRXTL GRX0 GRX GRX GRX GTXTL GTX0 GTX GTX GTX ERESET# pf-n 0 N-pF R R R R R R K R R R R0 N-pF R R R R R R M-RST RXLK TXLK RXTL- RX0-SELRGV RX-TXLY RX-N0 RX-N TXTL TX0 TX TX TX EPHY-V MIO M V-V > m V-V0 R V-V>00m pin EPHY-V pin, EPHY-V VREG Note : The Trace length from (uf),(0.uf) to Pin,(VREG) must bewithin 0. cm. The trace width from V to Pin, should>0mils. R N-K R K R00 LE0-0 LE- R K RXTL- R N-K PHY ddress=00(rtle) EPHY-V EPHY-V R0 N-K RX0-SELRGV R K EPHY-V Pull down for.v RGMII(RTL/E) R N-K RX-N0 00 uf R K R N-K R0 K MI- MI+ MI- MI+ MI- MI+ MI0- MI0+ 0nF 0nF TP0 TP0 TP0 TP0 TP0 TP0 TP TP TP nf-kv 0 nf-kv 0 N0 F F0 0 T- T+ T- 0/00/000 T+ MGNETIS && RJ T+ LE- Y_LE+ R Y_LE- LE0-0 G_LE- R EPHY-V G_LE+ T- T0- T0+ SHIEL0 SHIEL KRJ-0NL/KY HSIS- HSIS- TP TP TP TP R R R N-K RX-N onfig for all capability N-K RX-TXLY N-K LE-RXLY dd TX/RX elay R K R K R K EPHY-V llwinner Technology o.,ltd esign Name _P_ST GM.0 ate: Monday, March 0, 0 Sheet of

13 USWIFI-P0 V-WIFI WiFi NT USWIFIPIN N/WM-RTETV U UK S MIS V-PG PG0/S-LK/PG-EINT0 PG/S-M/PG-EINT PG/S-0/PE-EINT PG/S-/PG-EINT PG/S-/PG-EINT PG/S-/PG-EINT PG/URT-TX/PG-EINT PG/URT-RX/PG-EINT PG/URT-RTS/PG-EINT PG/URT-TS/PG-EINT PG0/TWI-SK/US-P/PG-EINT0 PG/TWI-S/US-M/PG-EINT PG/SPI-S/IS-MLK/PG-EINT PG/SPI-S0/IS-LK/PG-EINT PG/SPI-LK/IS-LRK/PG-EINT PG/SPI-MOSI/IS-IN/PG-EINT PG/SPI-MISO/IS-OUT/PG-EINT PG/URT-TX/PG-EINT PG/URT-RX/PG-EINT -G0i G F V-PG WL-SIO-LK WL-SIO-M WL-SIO-0 WL-SIO- WL-SIO- WL-SIO- T-URT-RX T-URT-TX T-URT-TS T-URT-RTS WIFI-SHN WIFI-HOST-WKE PG T-PM-LK T-PM-SYN T-PM-OUT T-PM-IN URT-TX URT-RX V-WIFI WL-SIO-LK WL-SIO-M WL-SIO-0 WL-SIO- WL-SIO- WL-SIO- T-URT-RX T-URT-TX T-URT-TS T-URT-RTS M-RESET# T-PM-LK T-PM-SYN T-PM-OUT T-PM-IN URT-TX URT-RX WIFIV N/K R0 N/K R0 N/K R0 N/K R0 N/K R0 N/K R0 N/K R00 N/K R T-URT-RX T-URT-TX T-URT-TS T-URT-RTS T-PM-LK T-PM-SYN T-PM-OUT T-PM-IN L 0@00M L00 0.uF XTL-OUT XTL-IN US-M US-P 0uF/V 00 WIFIV.uF 00 T-HOST-WKE T-WKE R N/ V M P _0 _ NT 贴装 USWIFI ETV 时, 此处为 电阻 N 0 Ohm RF trace 0pF R0 R N/ N NT NT NT--0---S-/INPQ NT--0 NT/efl_r_smt con_ant_efl_r_smt P0 需要框内 和 部分,R,R 就 N P,P0 只需要框内 部分 WL-SIO-0 WL-SIO- WL-SIO- WL-SIO- WL-SIO-M WL-SIO-LK PL PL PL WIFIV K R K R K R K R K R SIO-0 SIO- SIO- SIO- SIO-M SIO-LK R R T-REST WIFIV T-WKE T-HOST-WKE R N/K WIFI-SHN WIFI-HOST-WKE SIO- SIO- SIO-M SIO-LK SIO-0 SIO- WIFIV U P0 WL_REG_ON WL_HOST_WKE SIO_T_ SIO_T_ SIO_T_M SIO_T_LK SIO_T_0 0 SIO_T VIN_LO_OUT VIO XTL_OUT XTL_IN 0 VT T_VIO/N_HOST_WKE T_HOST_WKE T_WKE N_WKE FM_RX _ WL_T_NT _0 N_VSWP_IN N_VSWP_OUT N_VSWPIO URT_TS_N URT_RX URT_TX URT_RTS_N 0 TX TX N_REG_PU N_I_SL _ N_I_S T_RST_N T-URT-TS T-URT-RX T-URT-TX T-URT-RTS T-REST R MLK-IN WIFIV R N/OR XTL-IN 0 R U sc0- NLWZU0 OUT Y IN Vcc OUT Y IN R0 0K Y MHz L=pF R XTL-OUT N/OR P-KKO LK-K L, rated current 00m expectation specification. L0.uH 0.uF 00 VIN_LO LPO PM_OUT PM_LK PM_IN PM_SYN V_TXO TXO_IN _ G_RF _ 0 pf pf.uf 00 LK-K T-PM-OUT T-PM-LK T-PM-IN T-PM-SYN WIFIV R MLK-IN P0 接上此电阻,P 和 P0 不接 llwinner Technology o.,ltd esign Name _P_ST USWIFI-P0.0 ate: Monday, March 0, 0 Sheet of

14 G MOULE RF Microstrip Z0= 0 ohm U 与 MIE 为二选一使用 fter P Power-own, VT-EXT still on, IOs of should be still kept on the right level!! Take are of polarity of the ontrol Signals... -PM-OUT -PM-LK -PM-SYN -PM-IN -URT-TS -URT-RTS -URT-RX -URT-TX G-M G-P PM0 PM PM PM G-IO-ON G-PM-OUT G-PM-LK G-PM-SYN G-PM-IN G-URT-TS G-URT-RTS G-URT-RX G-URT-TX MU-WKEUP-OUT G-ON-N MU-WKEUP-IN G-RST G-IO-ON PHOUTP PHOUTN PHINP PHINN Note: If the POWER Swtich ircuit below do not be used, this TWO Resistor can not be N!! G-VT-P 00nF MU--ON MU-RST-N MU-WKEUP-IN MU-WKEUP-OUT PHOUTN PHOUTP 0nF G-PM-SYN G-PM-LK G-PM-IN G-PM-OUT G-P G-M R0 0 U XK0/MW00_ONN V V 0 V V/N V LE_RV KP_N RESIN_N P_WKEUP_P P_WKEUP_P UX_PM_SYN UX_PM_LK UX_PM_IN UX_PM_OUT URT_TS_N URT_RFR_N URT_RX_T URT_TX_T US_P US_M VREG_MSMP I_SL I_S SPI_S_N/GPIO_ SPI_S_N/GPIO_ SPI_MISO_T/GPIO_0 SPI_MOSI_T/GPIO_ HESET_ET_N 0 uf uf -MIN 0 -MIP pf pf XK0 VREG_USIM USIM_T USIM_LK USIM_RESET MUSIM M MUSIM_P HST_IS MIN MIP MIN MIP HPH_LP HPH_RN 0 ER0P ER0N VREG_GP SIO EN S_LK 0 S_M S_T0 S_T S_T S_T SIM_V SIM_IO SIM_LK SIM_RESET -MIN -MIP uf uf uf uf ER0P ER0N TP TP SPKL SPKR MU-WKEUP-OUT R MU--ON -MIN R -MIP ER0N ER0P MU-WKEUP-IN G-URT-RTS R N/ G-URT-TS R N/ G-URT-RX R N/ G-URT-TX R0 N/ G-PM-LK G-PM-OUT G-PM-IN G-PM-SYN R0 MIE # 0 W_ISLE# PERST# +.Vaux# #.V_ SM_LK 0 SM_T # US_- US_+ 0 #0 LE_WWN# LE_WN# LE_WPN#.V_ 0 #0 +.Vaux# WKE# OEX OEX LKREQ# # REFLK- REFLK+ # UIM_ UIM_ # PERn0 PERp0 # # PETn0 PETp0 # # +.Vaux# +.Vaux# # RSV# RSV# RSV# RSV# +.Vaux# #.V_ UIM_ UIM_T 0 UIM_LK UIM_RESET UIM_VPP MINIPIE SIM_V SIM_IO SIM_LK SIM_RESET SIM_VPP R G-M G-P G-V 0uF/V 00 R R00 R R00 00nF 0 MU--ON MU-RST-N G-VT-P G-VT-P 00nF G-V 00nF LE R G-V PHINP PHINN 0 uf uf ER0N ER0P 00pF 00pF R 0K G-ON-N Q 0 MMT0 pf SOT- G-V + 00uF uf SE_ 00 MU--ON uF SE_ SIM_LK R RUIM_LK SIM_RESET R RUIM_RST MMT0 SOT- SIM_IO R0 RUIM_IO Q SIM_VPP R RUIM0_VPP MU-RST-N R SIM_V R RUIM0_V 0K G-RST pf pf pf pf Q0 0 MMT0 pf SOT- RUIM0_V RUIM_RST PF 00 RUIM0_VPP RUIM_LK R R 00K/% R K/% R RUIM_IO G-EN RUIM_ET R R0 0K 0.uF U R G-IO-ON G-EN EN F K IN L0 LX IN _uh R<0_R SY0 SOT- uf 00 Vout = 0.*(+R/R) 00nF 0 ES0 ES-00-LF ES ES-00-LF RUIM socket ES ES-00-LF ES ES-00-LF G-EN ES ES-00-LF RUIM0_V V-V0 RUIM_RST RUIM0_VPP RUIM_LK RUIM_IO R 00K R K RUIM_ET# ES ES-00-LF V _0 RST VPP LK I/O T0 MM 0 ETET _ SIM SIM_PUSH SIM V _0 RST VPP LK I/O T0 MM ETET 0 N/SPPN PROONN SEN UF PM URT P0/IS0-MLK/URT-TS/MS-MLK/P-EINT0 P/IS0-LK/P-EINT P/IS0-LRK/P-EINT P/IS0-O0/P-EINT P/IS0-O/URT-RTS/P-EINT P/IS0-O/URT-TX/TWI-SK/P-EINT P/IS0-O/URT-RX/TWI-S/P-EINT P/IS0-I/P-EINT -G0i V-P V-P=.V -URT-RTS -PM-LK -PM-SYN -PM-IN -URT-TS -URT-RX -URT-TX -PM-OUT fter P Power-own, VT-EXT still on, IOs of should be still kept on the right level!! Take are of polarity of the ontrol Signals... llwinner Technology o.,ltd esign Name V-P _P_ST G G.0 ate: Thursday, March, 0 Sheet of

15 V-V U P-.V VG-V 0.uF.uF INPUT VOUT EN N 0.uF.uF VG_EN R 0 0.uF 00 N/0.uF R* RN RN00 RN00 R* RN L0- L0- L0-0 L0- L0- L0- L0- L0- VG-V VG-V L0- L0- L0- L0-0 L0- L0- L0- L0- R* RN00 RN RN R* RN uF 0.uF 0.uF L0-E R R VG-V R -% R0 0 G0 G G G G G G G G G LNK SYN L0- L0-0 L0- L0- L0- L0- L0- L0- R R R R R R R R 0 R R0 VE R_set V# 0 LOK 0 RN RN00 R* RN R* RN00 R.K L0-LK R -% U GM Vref OMP IOR IOR IOG IOG 0 V#0 V# IO IO # # 0 0 R R 0.0uF 0.0uF VG-V OR OG O R R/% R R/% R R/% L 0 pf L pf L pf pf 0nH pf 0nH pf 0nH pf pf pf SOT- TS SOT- TS SOT- TS V-V V-V V-V VG_R VG_G VG_ esign Name TP TP TP V-V TP L0-HSYN L0-VSYN L 0@00M l00 VG 0 L-HSYN L-VSYN VG-HSYN VG-VSYN R L-HSYN VG-HSYN llwinner Technology o.,ltd _P_ST SU-F-. TP TP0 V-V VG.0 U L-VSYN V Y VG-VSYN Y Y Y 0 Y Y SNHT0 tssop_ ate: Monday, March 0, 0 Sheet of

16 V-V U P-.V TVIN-V VV-SI HV_V uF.uF TVIN_EN R0 R N/0K INPUT VOUT EN N 0 0.uF 0.uF N/0.uF 0.uF L 0 0@00M 0.uF l00 L 0@00M 0.uF l00 L 0@00M 0.uF l uF 0 0.uF 0.uF.uF PLLV_V.uF V_V.uF L 0@00M l00 TVIN-V HV_V R0.K uf uf PH SI- SI-MLK SI-HSYN R R0 R0 R00 uf V_V SI-VSYN SI- TWI0-S TWI0-SK SI- SI- SI- SI- SI- SI- SI-0 SI- SI-PLK R R R0 R0 * RN00 RN * RN00 RN R R0 0K VSYN/PLI FI/GLO S 0 SL V YOUT0 YOUT HSYN VI INTREQ PN REFN 0 REFM 0 H_ H_V YOUT YOUT YOUT YOUT YOUT 0 YOUT IO_V PLK/SLK EP IPI IPI PLL_ PLL_V XTL XTL RESET TVIN-V 0.uF GM0 U R0 uf PLLV_V R0 N/ M-RESET# X.MHz/PF 0pF 0pF 0.uF R0 R 0K LINEINL LINEINR.uF.uF ON_HP_PJ_F N PJ-F/M llwinner Technology o.,ltd esign Name _P_ST TVIN.0 ate: Thursday, March, 0 Sheet of

17 uf POWEN V-VST R 0K Q MMT0 SOT- U INPUT VOUT EN YS P_.0V SOT- R 0K N/0.0V 00m R 0K R 0K MU_V.uF 0.uF 00 MU_POWEN XKI X V-V MU_V MU-IO MU-IO0 MU-PWM XKO SS SO R 0K MU-KEY V-VST MU_V R 0K U IO S-ELY -H-L V XI XO KEY SOP-P IO SL S IR 0 -EN LE MU_V R N/0K MU_RESET IR MU_POWEN ST-V Q N/SN0 Q N/SN0 V-V N-H R0 /N N-H R /N V-V TWI-SK TWI-S U V IR Receiver OUT IR_ON_P_SIP_R MU_V N/ R 0 R R/N IN 0 SO V-IR R 0K IR IR-RX RESET 0pF 0 0pF Q MMT0 SOT- R 0K MU_RESET R 0K R 0K MU_RESET MU_V R N/0K V-V SW sw_ts_0_mcd TS-0/M N/ R R /N MU-KEY POWEN POWON MU-IO PL R 0K MU-IO MU-IO0 R 0K Q MMT0 SOT- Q0 N/MMT0 N/00K R SOT- R0 N/00K PL R 0 R 0K MU-PWM Q MMT0 SOT- MU-PWM 遥控开关机, 看门狗, 定时开关机功能 : 遥控开关机状态及按键状态 : 在关机状态下,MU 的 V 电源 MU_V 会持续提供, 当 IR 管脚收到 IR 信号或者 MU_KEY 收到信号时 : 则 MU_POWEN 输出一个持续 S 时间的高电平, 同时 ST-V 管脚也持续输出一个 0S 高电平信号, 主控得到这个信号后, 机器开机. 在开机状态下, 当 IR 管脚收到 IR 信号或者 MU_KEY 收到信号时 : MU_POWEN 输出一个持续 S 时间的高电平, 同时 ST-V 管脚也持续输出一个 0S 高电平信号, 主控得到这个信号后, 机器关机. : 看门狗状态 (MU_RESET 默认为高电位 ) : 在关机的状态下,V_V 没有电压过来, 此时 MU-IO0 与 MU-PWM 都是为低, 没有信号过来, 此时 MU_RESET 也无动作 : 在开机的过程中,V_V 有电压过来, 此时 MUIO 这个端口会一直为高, 此时 MU_RESET 也无动作 : 在已经完全开机进入系统后,MU-IO0 这个端口通过主控控制为低, 但此时 MU-PWM 这个管脚会在 秒钟的时间内给一个高脉冲过来, 则 MU_RESET 管脚不动作, 如果 秒钟内 MUPWM 都没有信号给过来, 则 MU_RESET 输出一个时间为 秒钟的高电平出来达到复位作用 ( 备注 : 时序上设定,MUPWM 要比 MUIO 早 S 的时间 秒内是指第一次信号过来后, 间隔 秒钟的时间, 但第二个信号可能在这个 秒的任何时间过来第二个信号过来后, 秒钟的时间重新计数 ) : 定时开关机状态 : 在开机状态下,PU 通过 I 接口给 MU 发定时命令. 在关机状态下, 定时时间完成设备开机,MU-V 是持续供电的, 首先检测 MU-IO 端口 : 如果为高, 则 ST-V 管脚持续输出高电平信号,V 电源开始供电, 设备开机. 为低时, 再检测 MU-IO0 端口, 如果为低, 则 MU-POWEN 输出一个 秒的高电平, 设备开机. 在开机状态下, 定时时间完成设备关机,MU-V 是持续供电的, 同开机检测流程,MU-IO 和 MU-IO0 都是低电平, 则 MU-POWEN 输出一个 秒的高电平, 设备关机. 等待 0 秒后,ST-V 管脚的电平翻转为低电平,V 供电停止. : MU-KEY 按键功能等同与 IR 功能 llwinner Technology o.,ltd esign Name _P_ST MU.0 ate: Thursday, March, 0 Sheet of

18 V-V MU_V MU_V URT-TX URT-RX MU_RX N-H Q N/SN0 V-V MU_TX MU_RESET MU_POWEN MU-IO U P. P. P. P. P. V P. P. P.0/RST_L P./INT P./INT P./INT P./INT0 P./TX 0 P.0/RX N/STW0S SOP-P-SMT 00 R N/0K R N/0 R0 N/0 MU-PWM MU-IO MU_TX MU_RX N-H Q N/SN0 具有定时开关机, 看门狗功能 MU_POWEN MU_POWEN MU_RESET MU_RESET MU-IO0 MU-IO MU-PWM MU-PWM MU-IO MU-IO 遥控开关机及看门狗功能 : 遥控开关机状态 : 在关机状态下,MU 的 V 电源 MU_V 会持续提供, 但此时 MUIO 及 MUPWM 都是低, 当 IR 管脚收到第一次 IR 信号时, 会检测下 MUIO 这个端口 如果为低, 则 POWER 管脚输出一个持续 秒钟的高电平信号, 达到开机目的当 IR 管脚收到第二次 IR 信号时, 也要检测下 MUIO 这个端口, 只有在 MUIO 为低的状态下,MU_POWER 管脚才再次输出一个持续 秒钟的高电平信号, 达到关机的目的, 重复循环这两个状态注意问题点 : MUIO 这个管脚必须在机器开启完全进入到系统后, 主控再经 OG_EN 给出一个高位, 打开 Q 使其为低此处这样设定是为了避免用户在连续按遥控时, 而使 MU 持续间断的输出高低位, 从而扰乱机器的开关机状态 : 看门狗状态 (MU_RESET 默认为高电位 ) : 在关机的状态下,V_V 没有电压过来, 此时 MUIO 与 MUPWM 都是为低, 没有信号过来, 此时 MU_RESET 也无动作 : 在开机的过程中,V_V 有电压过来, 此时 MUIO 这个端口会一直为高, 此时 MU_RESET 也无动作 : 在已经完全开机进入系统后,MUIO 这个端口通过主控控制为低, 但此时 MUPWM 这个管脚会在 秒钟的时间内给一个高脉冲过来, 则 MU_RESET 管脚不动作, 如果 秒钟内 MUPWM 都没有信号给过来, 则 MU_RESET 输出一个时间为 秒钟的低电平出来达到复位作用 ( 备注 : 时序上设定,MUPWM 要比 MUIO 早 S 的时间 秒内是指第一次信号过来后, 间隔 秒钟的时间, 但第二个信号可能在这个 秒的任何时间过来第二个信号过来后, 秒钟的时间重新计数 ) llwinner Technology o.,ltd esign Name _P_ST HMI/S/TF.0 ate: Monday, March 0, 0 Sheet 0 of