本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法

Transcription

1 Verilog HDL 硬件描述语言 原书名 A Verilog HDL Primer (second Edition) 原出版社 Star Gralaxy Publishing 作 者 J.Bhasker 译 者 徐振林等 丛书名 电子工程丛书 出版社 机械工业出版社 书 号 X 页 码 171 出版日期 2000 年 7 月

2 本书简要介绍了 Verilog 硬件描述语言的基础知识, 包括语言的基本内容和基本结构, 以及利用该语言在各种层次上对数字系统的建模方法 书中列举了大量实例, 帮助读者掌握 语言本身和建模方法, 对实际数字系统设计也很有帮助 本书是 Verilog HDL 的初级读本, 适用于作为计算机 电子 电气及自控等专业相关课程的教材, 也可供有关的科研人员作为 参考书 目 录 译者序 3.8 参数 26 前言 第 4 章 表达式 28 第 1 章 简介 操作数 什么是 Verilog HDL? 常数 历史 参数 主要能力 线网 29 第 2 章 HDL 指南 寄存器 模块 位选择 时延 部分选择 数据流描述方式 存储器单元 行为描述方式 函数调用 结构化描述形式 操作符 混合设计描述方式 算术操作符 设计模拟 关系操作符 33 第 3 章 Verilog 语言要素 相等关系操作符 标识符 逻辑操作符 注释 按位操作符 格式 归约操作符 系统任务和函数 移位操作符 编译指令 条件操作符 `define 和 `undef 连接和复制操作 `ifdef `else 和 `endif 表达式种类 `default_nettype 16 第 5 章 门电平模型化 `include 内置基本门 `resetall 多输入门 `timescale 多输出门 `unconnected_drive 和 5.4 三态门 41 `nounconnected_drive 上拉 下拉电阻 `celldefine 和 `endcelldefine MOS 开关 值集合 双向开关 整型数 门时延 实数 实例数组 字符串 隐式线网 数据类型 简单示例 线网类型 解码器举例 未说明的线网 主从触发器举例 向量和标量线网 奇偶电路 寄存器类型 23 第 6 章 用户定义的原语 49

3 6.1 UDP 的定义 组合电路 UDP 时序电路 UDP 初始化状态寄存器 电平触发的时序电路 UDP 边沿触发的时序电路 UDP 边沿触发和电平触发的混合行为 另一实例 表项汇总 52 第 7 章 数据流模型化 连续赋值语句 举例 线网说明赋值 时延 线网时延 举例 主从触发器 数值比较器 58 第 8 章 行为建模 过程结构 initial 语句 always 语句 两类语句在模块中的使用 时序控制 时延控制 事件控制 语句块 顺序语句块 并行语句块 过程性赋值 语句内部时延 阻塞性过程赋值 非阻塞性过程赋值 连续赋值与过程赋值的比较 if 语句 case 语句 循环语句 forever 循环语句 repeat 循环语句 while 循环语句 for 循环语句 过程性连续赋值 赋值 重新赋值 force 与 release 握手协议实例 80 第 9 章 结构建模 模块 端口 模块实例语句 悬空端口 不同的端口长度 模块参数值 外部端口 举例 89 第 10 章 其他论题 任务 任务定义 任务调用 函数 函数说明部分 函数调用 系统任务和系统函数 显示任务 文件输入 / 输出任务 时间标度任务 模拟控制任务 定时校验任务 模拟时间函数 变换函数 概率分布函数 禁止语句 命名事件 结构描述方式和行为描述方式的 混合使用 层次路径名 共享任务和函数 值变转储文件 举例 VCD 文件格式 指定程序块 强度 驱动强度 电荷强度 竞争状态 116 第 11 章 验证 编写测试验证程序 波形产生 118

4 值序列 重复模式 测试验证程序实例 解码器 触发器 从文本文件中读取向量 向文本文件中写入向量 其他实例 时钟分频器 阶乘设计 时序检测器 132 第 12 章 建模实例 简单元件建模 建模的不同方式 时延建模 条件操作建模 同步时序逻辑建模 通用移位寄存器 状态机建模 交互状态机 Moore 有限状态机建模 Mealy 型有限状态机建模 简化的 21 点程序 153 附录 语法参考 157 参考文献 172

5 1 Verilog HDL 1.1 Verilog HDL Verilog HDL Verilog HDL Verilog HDL Verilog HDL Ve r i l o g C Verilog HDL Verilog HDL, 1.2 Verilog HDL 1983 Gateway Design Automation Verilog HDL Verilog HDL 1990 Open Verilog International O V I Ve r i l o g 1992 O V I Verilog OVI I E E E Verilog 1995 I E E E IEEE Std Ve r i l o g 1.3 Ve r i l o g a n d o r n a n d U D P p m o s n m o s Gateway Design Automation Cadence Design Systems

6 2 Verilog HDL Verilog HDL Verilog HDL I E E E Verilog E D A Verilog HDL P L I P L I Verilog RT L Verilog HDL Verilog HDL RT L 1-1 Verilog HDL Verilog HDL & RTL Verilog HDL I E E E 2 Verilog HDL 3 Verilog HDL

7 Verilog HDL 6 Verilog HDL 7 Verilog HDL 8 U D P 9 1 0

8 2 HDL H D L 2.1 Verilog ; ; m o d u l e m o d u l e _ n a m e (p o r t _ l i s t) ; D e c l a r a t i o n s : reg, wire, parameter, input, output, inout, function, task,... S t a t e m e n t s : Initial statement Always statement Module instantiation Gate instantiation UDP instantiation Continuous assignment m o d u l e, 2-1 m o d u l e H a l f A d d e r (A, B, Sum, Carry) ; i n p u t A, B; o u t p u t Sum, Carry; a s s i g n #2 Sum = A ^ B; a s s i g n #5 Carry = A & B; m o d u l e H a l f A d d e r 4 : A B S u m C a rry, 1,, 2-1

9 2 HDL5 A B 1) 2) 3) 4) Verilog HDL 2.2 Verilog HDL a s s i g n #2 S u m = A ^ B; # 2 2 : ` timescale 1ns /100ps 1 n s 100ps ( 0. 1 n s ), #2 2 n s, Verilog HDL IEEE Ve r i l o g HDL 2.3 : a s s i g n [d e l a y] L H S _ n e t = RHS_ expression;,,,

10 6 Verilog HDL ` t i m e s c a l e 1ns/ 1ns m o d u l e D e c o d e r 2 x 4 (A, B, EN, Z) ; i n p u t A, B, EN; o u t p u t [ 0 :3] Z; wire Abar, Bbar; assign #1 Abar = ~ A; / / 1 assign #1 Bbar = ~ B; / / 2 assign #2 Z[0] = ~ (Abar & Bbar & EN) ; assign #2 Z[1] = ~ (Abar & B & EN) ; assign #2 Z[2] = ~ (A & Bbar & EN) ; assign #2 Z[3] = ~ (A & B & EN) ; m o d u l e / / 3 / / 4 / / 5 / / 6 `, ` t i m e s c a l e 1 n s 1 ns # 1 # ns D e c o d e r 2 x A b a r B b a r ( ) E N 5 ns, E N Z[ 0 ] 7 ns 0 A 15 ns, Z[ 0 ] Z[ 1 ] 5 Z[ 2 17 ns 0 1 A b a r 16 ns A b a r Z[ 0 ] 18 n s 1, ) initial

11 2 HDL7 2) always, a l w a y s 0 a l w a y s m o d u l e F A _ S e q (A, B, Cin, Sum, Cout ); i n p u t A, B, Cin ; o u t p u t Sum, Cout; r e g Sum, Cout; r e g T1, T2, T3; a l w a y ( A o r B o r C i n ) Sum = (A ^ B) ^ Cin; T1 = A & Cin; T2 = B & Cin; T3 = A & B; C o u t = (T 1 T 2) T 3; m o d u l e FA _ S e q S u m C o u t T 1 T 2 T 3 always, reg (reg ) always ) ( - ) A B C i n A B C i n always A B C i n : 1) : 2) : S u m = (A ^ B) ^ C i n; #4 T 1 = A & C i n; 4 4 S u m = #3 (A^ B) ^ C i n;, 3 S u m 0 always 8 i n i t i a l ` t i m e s c a l e 1ns / 1ns

12 8 Verilog HDL m o d u l e Test (Pop, Pid ); o u t p u t Pop, Pid; r e g Pop, Pid; i n i t i a l P o p = 0; m o d u l e P i d = 0; P o p = #5 1; P i d = #3 1; Pop = #6 0; P i d = #2 0; // 1 // 2 // 3 // 4 // 5 // i n i t i a l 0 ns, initial ns 0, P o p 5 ns 4 5, P i d 8 ns P o p 14 ns 0 P i d 16 ns 6 i n i t i a l 8 i n i t i a l 2-5 Test 2.5 Verilog HDL : 1) ( ) 2) ( ) 3) ( ) 4) ( ) 2-4 m o d u l e F A _ S t r (A, B, Cin, Sum, Cout ); i n p u t A, B, Cin ; o u t p u t Sum, Cout; w i r e S1, T1, T2, T3; x o r X 1 (S1, A, B), X 2 (Sum, S1, Cin) ; a n d

13 2 HDL9 A 1 (T3, A, B ), A 2 (T2, B, Cin), A 3 (T1, A, Cin), o r O1 (Cout, T1, T2, T3) ; m o d u l e x o r a n d o r S 1 T 1 T 2 T 3, x o r a n d o r X 1 X 2 A 1 S 1 x o r X 1 A B X m o d u l e F o u r B i t F A (FA, FB, FCin, FSum, FCout ); p a r a m e t e r S I Z E = 4; i n p u t [S I Z E:1] FA, FB; o u t p u t [S I Z E:1] F S u m i n p u t F C i n; i n p u t F C o u t; w i r e [ 1: S I Z E 1] F T e m p; F A _ S t r F A 1(.A (F A[1]),.B(F B[1]),.C i n(f C i n),.s u m(f S u m[1]),.c o u t(f T e m p[ 2 ])), F A 2(.A (F A[2]),.B(F B[2]),.C i n(f T e m p[ 1 ]),.S u m(f S u m[2]),.c o u t(f T e m p[ 2 ])), F A 3(F A[3], F B[3], F T e m p[2], F S u m[3], F T e m p[ 3 ], F A 4(F A[4], F B[4], F T e m p[3], F S u m[4], F C o u t) ; m o d u l e 4 FA 1 FA 2.p o rt _ n a m e (n e t _ n a m e) FA 3 FA 4 FA 4 FA[ 4 ] FA _ S t r A F B[ 4 ] FA _ S t r B

14 10 Verilog HDL a l w a y s i n i t i a l a l w a y s i n i t i a l a l w a y s i n i t i a l 1 m o d u l e F A _ M i x (A, B, Cin, Sum, Cout ); i n p u t A,B, Cin; o u t p u t Sum, Cout; r e g C o u t; r e g T1, T2, T3; w i r e S 1; x o r X 1(S1, A, B ); // a l w a y ( A o r B o r C i n ) T1 = A & Cin; T2 = B & Cin; T3 = A & B; C o u t = (T 1 T 2) T 3; // always a s s i g n S u m = S 1 ^ C i n; // m o d u l e A B A B C i n always S 1 C i n 2.7 Verilog HDL To p 2. 3 FA _ S e q t i m e s c a l e 1 n s/1 n s m o d u l e T o p; // r e g PA, PB, PCi; w i r e PCo, PSum; // FA_Seq F1(PA, PB, PCi, PSum, PCo ); // i n i t i a l : O N L Y O N C E r e g [3:0] P a l; // 4, Pal 8 f o r (P a l = 0; P al < 8; P a l = Pal + 1)

15 2 HDL11 m o d u l e {PA, PB, PCi} = P a l; #5 $d i s p l a y ( PA, PB, PCi = %b%b%b, PA, PB, PCi, : : : PCo, PSum=%b%b, PCo, PSum) ; PA FA _ S e q A P B FA _ S e q B f o r PA P B P C i for $d i s p l a y $ d i s p l a y $d i s p l a 5 P a l -, ONLY _ O N C E 2-7 PA, PB, PCi = 000 ::: PCo, PSum = 00 PA, PB, PCi = 001 ::: PCo, PSum = 01 PA, PB, PCi = 010 ::: PCo, PSum = 01 PA, PB, PCi = 011 ::: PCo, PSum = 10 PA, PB, PCi = 100 ::: PCo, PSum = 01 PA, PB, PCi = 101 ::: PCo, PSum = 10 PA, PB, PCi = 110 ::: PCo, PSum = 10 PA, PB, PCi = 111 ::: PCo, PSum = To p R S _ F F 2-8 ` t i m e s c a l e 10 n s / 1 n s m o d u l e R S _ F F (Q, Qbar, R, S) ; o u t p u t Q, Qbar ; i n p u t R, S; 2-8 n a n d #1 (Q, R, Qbar) ;

16 12 Verilog HDL nand #1 (Qbar, S, Q,) ; / / m o d u l e m o d u l e T e s t; r e g TS, TR; w i r e TQ, TQb ; / / RS_FF NSTA (.Q(T Q),.S(T S),.R(T R),.Q b a r(t Q b)); / / // i n i t i a l : T R = 0; T S = 0; #5 T S = 1; #5 T S = 0; T R = 1; #5 T S = 1; T R = 0; #5 T S = 0; #5 T R = 1; // i n i t i a l $m o n i t o r ("At time %t,", t $ i m e, "TR = %b, TS=%b, TQ=%b, TQb= %b", TR, TS, TQ, TQb) ; m o d u l e R S _ F F 1 R Q b a r T Q T+ 1 Te s t R S _ F F T S T R $m o n i t o r 2-9 ` t i m e s c a l e 2-9 Te s t

17 2 HDL13 At time 0, TR=0, TS=0, TQ=x, TQb= x At time 10, TR=0, TS=0, TQ=1, TQb= 1 At time 50, TR=0, TS=1, TQ=1, TQb= 1 At time 60, TR=0, TS=1, TQ=1, TQb= 0 At time 100, TR=1, TS=0, TQ=1, TQb= 0 At time 110, TR=1, TS=0, TQ=1, TQb= 1 At time 120, TR=1, TS=0, TQ=0, TQb= 1 At time 150, TR=0, TS=1, TQ=0, TQb= 1 At time 160, TR=0, TS=1, TQ=1, TQb= 1 At time 170, TR=0, TS=1, TQ=1, TQb= 0 At time 200, TR=0, TS=0, TQ=1, TQb= 0 At time 210, TR=0, TS=0, TQ=1, TQb= 1 At time 250, TR=1, TS=0, TQ=1, TQb= 1 At time 260, TR=1, TS=0, TQ=0, TQb= ` t i m e s c a l e i n i t i a l always B u l l s E y e 2-10 BullsEye D e c o d e 2 x 4 9 Verilog HDL Verilog HDL a s s i g n Reset = #2 ^ WriteBus;

18 3 Verilog Verilog HDL Ve r i l o g 3.1 Verilog HDL ( i d e n t i f i e r ) $ ( C o u n t COUNT _ R 1 _ D 2 R 56 _ 68 F I V E $ / / C o u n t (escaped identifier ) \ ( ) \ 7400 \.*.$ \{******} \ ~Q \O u t G a t e O u t G a t e \ O u t G a t e O u t G a t e Verilog HDL A a l w a y s ( ) A LWAY S( ) \initial i n i t i a l 3.2 Verilog HDL /* : */ // : 3.3 Verilog HDL Verilog

19 3 Verilog 15 initial begint o p = 3 b001; #2 T o p = 3 b011; : i n i t i a l begin T o p = 3 b001; #2 T o p = 3 b 011 ; 3.4 $ 0 0 $d i s p l a y ("Hi, you have reached LT today"); /* $d i s p l a y */ $t i m e // ` Verilog : `define, `undef `ifdef, `else, `endif `default_nettype `include `resetall `timescale `unconnected_drive, `nounconnected_drive `celldefine, `endcelldefine `define `undef ` d e f i n e C #define : ` d e f i n e M A X _ B U S _ S I Z E r e g [ `M A X _ B U S _ S I Z E - 1:0 ] A d d R e g; ` d e f i n e ` d e f i n e M A X B U S S I Z E `undef : ` d e f i n e W O R D 16 //... w i r e [ `W O R D : 1] Bus;

20 16 Verilog HDL... ` u n d e f W O R D // ` u n d e f, W O R D `ifdef `else `endif ` i f d e f W I N D O W S p a r a m e t e r WORD_SIZE = 16 ` e l s e p a r a m e t e r W O R D _ S I Z E = 32 ` i f W I N D O W S ` e l s e `ifdef `default_nettype `default_nettype wand `include ` i n c l u d e, : ` i n c l u d e.. /.. /primitives.v../../ p r i m i t i v e s. v `resetall ` r e s e t a l l `timescale Verilog HDL ` t i m e s c a l e ` t i m e s c a l e ` t i m e s c a l e t i m e _ u n i t / t i m e _ p r e c i s i o n t i m e _ u n i t t i m e _ p re c i s i o n s m s u s n s p s f s ` t i m e s c a l e 1 n s / p s 1ns, 100 p s `timescale, :

21 3 Verilog 17 ` t i m e s c a l e 1ns/ 100ps m o d u l e A n d F u n c (Z, A, B ); o u t p u t Z; i n p u t A, B; a n d # (5.22, 6.17 ) A l (Z, A, B); // m o d u l e n s 1/10 ns 100 ps ns, ns ` t i m e s c a l e, ` t i m e s c a l e 1 0 n s / 1 n s ns, n s ` t i m e s c a l e ` t i m e s c a l e ` r e s e t a l l ` t i m e s c a l e ` t i m e s c a l e 1ns/ 100ps m o d u l e A n d F u n c (Z, A, B ); o u t p u t Z; i n p u t A, B; a n d # (5.22, 6.17 ) A l (Z, A, B) ; m o d u l e ` t i m e s c a l e 10ns/ 1ns m o d u l e T B; r e g PutA, PutB; w i r e G e t O; i n i t i a l P u ta = 0; P u t B = 0; #5.21 P u t B = 1; #10.4 P u t A = 1; #15 P u t B = 0; A n d F u n c A F 1(GetO, PutA, PutB) ; m o d u l e ` t i m e s c a l e ` t i m e s c a l e ns, ns; ns, ns, ns T B 100 ps T B 100 ps 52 ns 520*100 ps *100 ps *100 ps 100 A n d F u n c T B A d d F u n c T B ` t i m e s c a l e

22 18 Verilog HDL `unconnected_drive `nounconnected_drive ` u n c o n n e c t e d _ d r i v e p u l l 1... /* */ ` n o u n c o n n e c t e d _ d r i v e `unconnected_drive pull0... /* */ ` n o u n c o n n e c t e d _ d r i v e `celldefine `endcelldefine ` c e l l d e f i n e m o d u l e F D 1 S 3 A X (D, CK, Z) ;... m o d u l e ` c e l l d e f i n e P L I 3.6 Verilog HDL 1) 0 0 2) 1 1 3) x 4) z z 0 0 z x z 0 x 1 z 0 X 1 Z Verilog HDL Verilog HDL 1) 2) 3) _ 3.6.1

23 3 Verilog 19 1) 2) [s i z e ] base value s i z e b a s e o O b B d D h H v a l u e b a s e x z a f 5'O37 4'D2 4'B1x_01 7'Hx 4'hZ 4'd-4 8'h 2 A 3'b001 (2+3)'b x( x), x x x x x x x 4 z( z), z z z z, : ` b : x z 4 x z 3 x z 1 x z 'o721 'haf x z x z 10'b10 10'bx0x1 0, x, x x x x x x x 0 x 1 3 ' b _ 'b011 5'H0FFF 5'H1F z z

24 20 Verilog HDL 1) // 1 2) 23_5.1e ; 3.6E e E ( ) 5 E Ve r i l o g , : "INTERNAL ERROR" " R E A C H E D > H E R E " 8 A S C I I 8 A S C I INTERNAL ERROR 8 * 14 r e g [1 : 8*14] M e s s a g e;... M e s s a g e = "INTERNAL ERROR" (\ ) \n \t \\ \ \" " \ Verilog HDL 1) net type Ve r i l o g z 2) register type a l w a y s i n i t i a l x 3.7.1

25 3 Verilog 21 wire tri wor trior wand triand trireg tri1 tri0 supply0 supply1 n e t _ k i n d [m s b:l s b] net1, net2,..., n e t N; n e t _ k i n d m s b l s b 1 w i r e Rdy, Start; //2 1 w a n d [2:0] A d d r; //A d d r 3 w o r R d e;... a s s i g n R d e = B l t & W y l;... a s s i g n Rde = K b l K i p; R d e R d (wor) 1. wire t r i ( t r i ) w i r e R e s e t; w i r e [3:2] Cla, Pla, Sla; t r i [ M S B 1 : L S B +1] A r t; wire ( t r i ) 0 1 x z 0 0 x x 0 1 x 1 x 1 x x x x x z 0 1 x z a s s i g n C l a = P l a & S l a;... a s s i g n Cla = P l a ^ S l a; C l a

26 22 Verilog HDL C l a C l a 01 x, 11 z C l a x 1 x ( 0 1 x, x z x) 2. wor t r i o r 1 1 ( t r i o r ) w o r [M S B:L S B] A r t; t r i o r [M A X 1: M I N 1] Rdx, Sdx, Bdx; wor ( t r i o r ) 0 1 x z x x x 1 x x z 0 1 x z 3. wand t r i a n d ( w a n d ) 0 0 ( t r i a n d ) w a n d [-7 : 0] D b u s; t r i a n d Reset, Clk; wand ( t r i a n d ) 0 1 x z x 1 x 0 x x x z 0 1 x z 4. trireg ( t r i r e g ) z x t r i r e g [1:8] Dbus, Abus; 5. tri0 t r i 1 t r i 0 t r i 1 0 t r i 1 t r i 0 [ 3:3] G n d B u s; t r i 1 [ 0 : 5] OtBus, ItBus; t r i 0 t r i 1 tri0 (tri1) 0 1 x z 0 0 x x 0 1 x 1 x 1 x x x x x z 0 1 x 0 ( 1 )

27 3 Verilog supply0 s u p p l y 1 s u p p l y 0 0 s u p p l y 1 : s u p p l y 0 Gnd, ClkGnd; s u p p l y 1 [2:0] Vcc; Verilog HDL 1 ` d e f a u l t _ n e t t y p e ` d e f a u l t _ n e t t y p e n e t _ k i n d `default_nettype wand s c a l a re d v e c t o re d v e c t o re d, : wire vectored[3:1] G r b; // G r b[ 2 ] G r b [ 3 : 2 ] wor scalared [4:0] B e s t; // w o r [4:0] B e s t B e s t [ 2 ] B e s t [ 3 : 1 ] reg integer time real realtime 1. reg r e g r e re g r e g [ m s b: l s b] reg1, reg2,... r e g N; m s b l s b 1 r e g [3:0] S a t; //S a t 4 r e g C n t; r e g [1:32] Kisp, Pisp, Lisp; //1, r e g [1:4] C o m b;

28 24 Verilog HDL... C o m b = 2; //C o m b C o m b = 5; 2. //C o m b r e g [ m s b: 1 s b] m e m o r y 1 [ u p p e r 1: l o w e r 1], m e m o r y 2 [u p p e r 2: l o w e r 2],... r e g [0:3 ] M y M e m [ 0 : 63 ] //M y M e m r e g B o g [ 1 : 5 ] //B o g 5 1 M y M e m B o g 2 p a r a m e t e r A D D R _ S I Z E = 16, W O R D _ S I Z E = 8; r e g [1: W O R D _ S I Z E] R a m P a r [ A D D R _ S I Z E 1 : 0], D a t a R e g; R a m P a r 16 8 D a t a R e g 8 r e g [1:5] D i g; //D i g 5... D i g = 5'b11011;, r e g B O g[1:5]; //B o g B o g = 5'b11011; r e g [0:3] X r o m [ 1 : 4 ]... X r o m[1] = 4'hA; X r o m[2] = 4'h8; X r o m[3] = 4'hF; X r o m[4] = 4'h2; 1) $re a d m e m b 2) $re a d m e m b r e g [1:4] RomB [7:1] ; $ r e a d m e m b ("ram.patt", RomB); R o m b r a m. p a t t

29 3 Verilog $ r e a d m e m b 7 R o m b $ r e a d m e m b $r e a d m e m b ("ram.patt", R o m B, 5, 3); R o m b[ 5 ],R o m b[ 4 ] R o m b[ 3 ] $r e a d m e m b ("rom.patt", R o m B, 6); // 6 1 $r e a d m e m b ( "rom.patt",r o m B, 6, 4); // Integer i n t e g e r integer1, integer2,... intergern [m s b:1 s b] ; m s b l s b 32 i n t e g e r A, B, C; // i n t e g e r Hist [3:6]; // 2 B B[ 6 ] B[ ] r e g r e g [31:0] B r e g; i n t e g e r B i n t;... //B i n t[ 6 ] B i n t[ 20 : 10 ]... B r e g = B i n t; / B r e g[ 6 ] B r e g[ 20 : 10 ] B i n t / :

30 26 Verilog HDL i n t e g e r J; r e g [3:0] B c q; J = 6; B c q = J; //J 32 ' b // B c q 4 ' b 0110 B c q = 4'b0101. J = B c q; //J 32 ' b J = 6; B c q = J; //J 32 ' b //B c q 4 ' b time t i m e t i m e t i m e time_id1, time_id2,..., t i m e _ i d N [ m s b:1 s b] ; m s b l s b 64 : t i m e E v e n t s [0:31]; // t i m e C u r r T i m e; 5. real r e a l t i m e //C u r r T i m e / / r e a l r e a l _ r e g 1, r e a l _ r e g 2,..., r e a l _ r e g N; // r e a l t i m e r e a l t i m e _ r e g 1, r e a l t i m e _ r e g 2,..., r e a l t i m e _ r e g N; r e a l t i m e r e a l : r e a l Swing, Top; r e a l t i m e C u r r T i m e; r e a l 0 r e a l x z r e a l 0 r e a l R a m C n t;... R a m C n t = 'b01x1z; R a m C n t ' b p a r a m e t e r p a r a m 1 = c o n s t _ e x p r 1, param2 = c o n s t _ e x p r 2,..., p a r a m N = c o n s t _ e x p r N; p a r a m e t e r L I N E L E N G T H = 132, A L L _ X _ S = 16'bx; p a r a m e t e r B I T = 1, B Y T E = 8, P I = 3.14; p a r a m e t e r S T R O B E _ D E L A Y = ( B Y T E + B I T) / 2;

31 3 Verilog 27 p a r a m e t e r T Q _ F I L E = " /h o m e/b h a s k e r/t E S T/ a d d. t q " ; 9 1 C O u n T, 1_2 M a n y, \**1, R e a l?, \wait, Initial Verilog HDL 5 7'o44, 'Bx0, 5'bx110, 'ha0, 10'd2, 'hzf 6 Q p r r e g [1:8*2] Q p r;... Q p r = "ME" ; 7 8 Verilog HDL 9 i n t e g e r [0:3] R i p p l e; 10 m e m A. d a t a

32 4 Verilog HDL 4.1 1) 2) 3) 4) 5) 6) 7) 8) ,7 // 4'b10_11, 8'h0A // 'b1, 'hfba // // "BOND" // 8 A S C I I ' b ' b ' d 'o i n t e g e r C o n e;... C o n e = -44/4 C o n e = -6'o54/ 4; 44 6 ' o ' o 5

33 4 29 C o n e 11 C o n e p a r a m e t e r L O A D = 4'd12, S T O R E = 4'd10; L O A D S TO R E w i r e [0:3] P r t; w i r e B d q; //P r t 4 //B b q a s s i g n P r t = -3; P rt a s s i g n P r t = 4'HA; P rt : i n t e g e r TemA, TemB; r e g [1:5] S t a t e; t i m e Q u e [ 1 : 5 ]; r e g TemA = -10; //T e m A TemA = 'b1011; // T e m A 11 State = -10; State = 'b1011; //S t a t e //S t a t e n e t _ o r _ r e g _ v e c t o r [b i t _ s e l e c t _ e x p r] S t a t e [1] && S t a t e [4] // P r t [0] Bbq // x z x S t a t e [x] C o n e

34 30 Verilog HDL n e t _ o r _ r e g _ v e c t o r [m s b _ c o n s t _ e x p r:1 s b _ c o n s t _ e x p r] S t a t e [1:4] P r t [1:3] // // x z m e m o r y [w o r d _ a d d r e s s] r e g [1:8] A c k, D r a m [ 0 : 63 ];... A c k = D r a m [60]; // 60 D r a m [60] [2] D r a m [60] [2:4] A c k [2] Ack [ 2 : 4 ] $ $t i m e + S u m O f E v e n t s (A, B) /* $t i m e S u m O f E v e n t s */ Verilog HDL 1) 2) 3) 4) 5) 6) 7) 8) 9)

35 4 31 A + B - C (A + B ) - C // A? B : C? D : F A? B : (C? D : F) // (A? B : C)? D : F : + * / % 7/4 1 7%4 3-7%4-3 X Z X 'b10x1 + 'b01111 ' bx x x x x

36 32 Verilog HDL 1. reg [0:3] Arc, Bar, Crt; reg [0:5] F r x;... Arc = B a r + C r t; F r x = B a r + C r t; B a r C rt A rc 4 F rx F rx B a t C rt 6 F r x [ 1 ] Verilog HDL w i r e [4:1] Box, Drt; w i r e [1:5] C f g; w i r e [1:6] P e g; w i r e [1:8] A d t;... a s s i g n A d t = (B o x + C f g) + (D r t + P e g) ; B o x C f g 8 2. r e g [0:5] B a r; i n t e g e r T a b;... B a r = -4'd12; // B a r T a b = -4'd12; // T a b 'd12 / 4 // / 4 // - 3 B a r ' b B a r 52 ' b Ta b 12

37 B a r = - 4'd12/4; T a b = - 4'd12 /4; B a r = - 12/4 T a b = - 12/4 B a r Ta b B a r B a r B a 3 B a r = 4-6; T a b = 4-6; B a r 62 2 Ta b B a r = -2 + (-4); T a b = -2 + (-4); B a r Ta b > < >= <= 1 0 X Z X 23 > < 8'hxFF x 0 'b1000 > = 'b01110 'b01000 > = 'b : = =!=

38 34 Verilog HDL = = =!= = 0 1 x z x z x x z x D a t a = 'b11x0; A d d r = 'b11x0; D a t a = = A d d r x D a t a = = = A d d r 1 0 2'b10 = = 4'b0010 4'b0010 = = 4'b : && ( ) ( ) ( ) 0 1, : C r d = 'b0; //0 Dgs = 'b1; //1 : C r d && D g s C r d D g s D g s 0 ( ) 1 ( ) 0 ( ) A _ B u s = 'b0110; B _ B u s = 'b0100; : A _ B u s B _ B u s A _ B u s && B _ B u s : 1 1! A _ B u s! B _ B u s x

39 4 35!x x : ~ & ^ ~^, ^~, A = 'b0110; B = 'b0100; : A B A & B , 0, 'b0110 ^ 'b10000 : 'b00110 ^ 'b10000 ' b 10110

40 36 Verilog HDL : & ( ) x z x ~& ( ) & ( ) x z x ~ ( ) ^ ( ) x z x 1, 0 ~^ ( ) ^, A = 'b0110; B = 'b0100; : B 1 & B 0 ~ A 1 : x, M y R e g = 4'b01x0 ^M y R e g x i f : i f ( ^M y R e g = = = 1'bx) $ d i s p l a y ("There is an unknown in the vector MyReg!") x : << ( ) >> ( ) 0 x z, x : r e g [ 0 7] Q r e g... Q r e g = 4'b0111;

41 4 37 : Q r e g >> 2 8 ' b _ N u m B i t s 32'b1 << N u m B i t s //N u m B i t s w i r e [0:3] D e c o d e O u t = 4'b1 << A d d r e s s [ 0 : 1 ] ; A d d re s s[0:1] 0, 1, 2 3 D e c o d e O u t 4 ' b ' b ' b ' b : c o n d_e x p r? e x p r 1 : e x p r 2 c o n d _ e x p r ( 1 ) e x p r 1 c o n d _ e x p r ( 0 ) e x p r 2 c o n d _ e x p r x z e x p r 1 e x p r 2 : x : w i r e [0:2] S t u d e n t = M a r k s > 18? G r a d e _ A : G r a d e _ C; M a r k s > 18;, G r a d e _ A S t u d e n t; M a r k s < =18, G r a d e _ C S t u d e n t 5 a l w a y s #5 C t r = (C t r!= 25)? (C t r + 1) : 5; C t r 25, 1 C t r 25, C t r : {e x p r 1, e x p r 2,... e x p r N} : w i r e [7:0] D b u s; w i r e [11:0] A b u s; a s s i g n D b u s [7:4] = {D b u s [0], D b u s [1], D b u s[2], D b u s[ 3 ]}; // 4 a s s i g n D b u s = {Dbus [3:0], D b u s [ 7 : 4 ]}; // 4 4,, {D b u s,5} / / : {r e p e t i t i o n _ n u m b e r {expr1, expr2,...,exprn }} A b u s = {3{4'b1011}}; // 12 ' b 1011 _ 1011 _ 1011 A b u s = {{4{D b u s[7]}}, D b u s}; / /

42 38 Verilog HDL {3{1'b1}} 111 {3{Ack}} {A c k, A c k, A c k} 4.3 : 1), ' b ) R E D : p a r a m e t e r R E D = 4'b1110 1,, 1. G AT E _ D E L AY, , 8 Verilog A d d re s s _ B u s, C o n t ro l _ B u s [ 15 : 0 ] A b u s [ 0 : 9 ] B b u s [ 6 : 1 ] 5. Qparity 8 6., N e x t S t a t e C u rre n t S t a t e R E S E T, N e x t S t a t e G O C u rre n t S t a t e G O N e x t S t a t e B U S Y C u rre n t S t a t e B U S Y N e x t S t a t e R E S E T [ ] 8. A B C D B u s Q[0:3]? B u s A [ 0 : 3 ] B u s Y [ 20 : 15 ] B u s R [ 10 : 1 ]?

43 5 Verilog HDL 5.1 Verilog HDL 1) and, nand,or, nor, x o r, x n o r 2) buf, not 3) bufif0, bufif1, notif0,notif1 4) pullup, pulldown 5) MOS cmos, nmos, pmos, rcmos, rnmos, rpmos 6) tran,tranif0, tranif1, rtran, rtranif0, rt r a n i f 1 g a t e _ t y p e[i n s t a n c e _ n a m e] (term1, term2,...,termn ); i n s t a n c e _ n a m e g a t e _ t y p e t e r m / : g a t e _ t y p e [i n s t a n c e _ n a m e 1] (term11, term12,...,term1n ), [i n s t a n c e _ n a m e 2] (term21, term22,...,term2n ),... [i n s t a n c e _ n a m e M] (termm1, termm2,...,termmn ); 5.2 : and nand nor or xor xnor 1 : m u l t i p l e _ i n p u t _ g a t e _ t y p e [i n s t a n c e _ n a m e] (OutputA, Input1, Input2,...,InputN ); 5-1

44 40 Verilog HDL 5-2 and A 1(Out1, In1, In2) ; a n d R B X (Sty, Rib, Bro, Qit, Fix ); x o r (Bar, Bud[ 0 ],B u d[1], B u d[ 2 ]), (Car, Cut [0], C u t[ 1 ]), (Sar, Sut[2], S u t[1], S u t[0], S u t[ 3 ]); 5-2 A 1 O u t 1 I n 1 I n 2 R B X S t y 4 R i b B ro Q i t F i x B a r B u d[ 0 ] B u d[ 1 ] B u d[ 2 ] z x z

45 : buf not 5-3 : m u l t i p l e _ o u t p u t _ g a t e _ t y p e [i n s t a n c e _ n a m e] (Out1, Out2,... OutN,InputA ); : 5-3 b u f B 1 Fan [ 0 ] Fan [ 1 ] Fan [ 2 ] Fan [ 3 ] C l k ; n o t N 1 P h A P h B R e a d y ; C l k B 1 4 F a n[ 0 ] F a n[ 3 ] R e a d y N 1 P h A P h B : 5.4 : bufif0 bufif1 notif0 notif1 t r i s t a t e _ g a t e[i n s t a n c e _ n a m e] (OutputA, InputB,ControlC ); O u t p u t A I n p u t B C o n t ro l C 5-4 z b u f i f 0 1 z b u f i f 1 0 z n o t i f 0 1 z n o t i f 1 0 z : b u f i f 1 BF1 D b u s M e m D a t a S t r o b e n o t i f 0 N T 2 (Addr, Abus, Probe) ; S t ro b e 0 b u f i f 1 B F 1 D b u s M e m D a t a D b u s 2 P ro b e 1 A d d r A b u s A d d r

46 42 Verilog HDL /z 0 z pullup pulldown 1 0 p u l l _ g a t e[i n s t a n c e _ n a m e] (O u t p u t A) ; 1 p u l l u p PUP (P w r) ; P U P P w r MOS M O S cmos pmos nmos rcmos rpmos rnmos

47 5 43 p m o s ( p M O S ) n m o s ( n M O S ) r n m o s ( r ) r p m o s g a t e _ t y p e[i n s t a n c e _ n a m e] (OutputA, InputB, ControlC ); n m o s r n m o s 0 p m o s r p m o s 1 z 5-5 n m o s p m o s r n m o s r p m o s ( ) r p m o s r m o s nmos p m o s p m o s P 1 (BigBus, SmallBus, GateControl ); r n m o s R N 1 (ControlBit, ReadyBit, Hold ); P 1 p m o s S m a l l B u B i g B u s G a t e C o n t ro l 1 /z 1 z c m o s ( m o s ) r c m o s ( c m o s ) (r)cmos [i n s t a n c e _ n a m e] (OutputA, InputB, NControl, PControl); n P c m o s ( r c m o s ) p m o s r p m o s n m o s ( r n m o s ) (r)cmos

48 44 Verilog HDL 5.7 tran rtran tranif0 rtranif0 tranif1 rtranif1 4 t r a n r t r a n t r a n r t r a n ( t r a n ) ( r ) t r a n [i n s t a n c e _ n a m e] (SignalA, SignalB) ; S i g n a l A S i g n a l B g a t e _ t y p e[i n s t a n c e _ n a m e] (SignalA, SignalB, ControlC ); S i g n a l A S i g n a l B t r a n i f 0 t r a n i f 0 C o n t ro l C 1 t r a n i f 1 r t r a n i f 1 C o n t ro lc 0 r t r a n r t r a n i f 0 r t r a n i f gate_type [d e l a y] [i n s t a n c e _ n a m e] (t e r m i n a l _ l i s t) ; 0 1) 2) 3) ( d ) 2 (d1, d2) 3 (da, db, dc) 0 d d 1 d A 0 d d 2 d B t o _ x 0 d m i n (d1, d2) min (da, db, dc) 0 d min (d1, d2) d C m i n m i n i m u m x ( t o _ x ) Verilog HDL ` t i m e s c a l e, n o t N 1 (Qbar, Q) ; 0 n a n d #6 (Out, In1, In2) ;

49 x 6 a n d #(3,5) (Out, In1, In2, In3) ; 3 5 x n o t i f 1 #(2,8,6) (Dout, Din1, Din2) ; x ( ) 2 ( z) 3 min:typ:max m i n : t y p : m a x minimum: typical: maximum n a n d #(2:3:4, 5:6:7) (Pout, Pin1, Pin2) ; ( ) g a t e _ t y p e [d e l a y]instance_name [l e f t b o u n d : r i g h t b o u n d] (l i s t _ o f _ t e r m i n a l _ n a m e s) ; l e f t b o u n d r i g h t b o u n d 0 w i r e [3:0] Out, InA, InB;... n a n d G a n g [3:0] (Out, InA, InB) ; n a n d Gang3 (O u t[3], I n A[3], I n B[ 3 ]), G a n g 2 (O u t[2], I n A[2], I n B[ 2 ]), G a n g 1 (O u t[ 1 ], I n A[1], I n B[ 1 ]), Gang0 (O u t[0], I n A[ 0 ], I n B[ 0 ]); 5.10 Verilog HDL 1 ` d e f a u l t _ n e t t y p e

50 46 Verilog HDL ` d e f a u l t _ n e t t y p e n e t _ t y p e `default_nettype wand w a n d ` d e f a u l t _ n e t t y p e ` re s e t a l l ( ) m o d u l e M U X 4 x 1 (Z, D 0, D 1, D 2, D 3, S 0, S 1) ; o u t p u t Z; i n p u t D 0, D 1, D 2, D 3, S 0, S 1; a n d (T 0, D 0, S 0 b a r, S 1 b a r), (T 1, D 1, S 0 b a r, S 1), (T 2, D 2, S 0, S 1 b a r), (T 3, D 3, S 0, S 1), n o t (S 0 b a r, S 0), (S 1 b a r, S 1) ; o r (Z, T 0, T 1, T 2, T 3,); m o d u l e? o r Z (Z, T 0, T 1, T 2, T 3); // Verilog HDL Z Verilog HDL m o d u l e D E C 2 4 (A, B, E n a b l e, Z) ; i n p u t A, B, E n a b l e; o u t p u t [0:3] Z ; w i r e Abar, Bbar; n o t # ( 1, 2 ) V 0 (A b a r, A), V 1(Bbar, B ); n a n d # (4,3) N 0 (Z[3], Enable, A,B), N 1 (Z[0], Enable, Abar,Bbar), N 2 (Z[1], Enable, Abar,B), N 3 (Z[2], Enable, A,Bbar), m o d u l e

51 D m o d u l e M S D F F (D, C, Q, Q b a r) ; i n p u t D, C ; o u t p u t Q, Q b a r ; n o t NT1 (N o t D, D), NT2 (N o t C, C), N T 3 (N o t Y, Y) ; n a n d N D 1 (D 1, D, C), N D 2 (D 2, C, N o t D), N D 3 (Y, D 1, Y b a r), N D 4 (Y b a r, Y, D 2), N D 5 (Y 1, Y, N o t C), N D 6 (Y 2, N o t Y, N o t C), N D 7 (Q, Q b a r, Y 1), N D 8 (Q b a r, Y 2, Q) ; m o d u l e m o d u l e Parity_9_Bit (D, Even,Odd) ; i n p u t [0:8] D ; o u t p u t Even, Odd;

52 48 Verilog HDL x o r # ( 5, 4 ) XE0 (E 0, D[ 0 ],D[ 1 ]), XE1 (E 1, D[ 2 ],D[ 3 ]), XE2 (E 2, D[ 4 ],D[ 5 ]), XE3 (E 3, D[ 6 ],D[ 7 ]), XF0 (F 0, E 0, E 1), XF1 (F 1, E 2, E 3), XH0 (H 0, F 0, F 1), X E V E N (Even, D [ 8 ], H0) ; n o t #2 X O D D (Odd, Even ); m o d u l e Va l i d A B 5-12

53 6 Verilog HDL Verilog U D P U D P U D 6.1 UDP U D P U D p r i m i t i v e U D P _ n a m e (OutputName, List_of_inputs ) O u t p u t _ d e c l a r a t i o n L i s t _ o f _ i n p u t _ d e c l a r a t i o n s [R e g _ d e c l a r a t i o n] [I n i t i a l _ s t a t e m e n t] t a b l e L i s t _ o f _ t a b e l _ e n t r i e s t a b l e p r i m i t i v e U D P U D P U D P 0 1 x( z ) z x U D P U D P 1) 2) ( ) 6.2 UDP U D P x 2-1 p r i m i t i v e MUX2x1 (Z, Hab, Bay, Sel) ; o u t p u t Z; i n p u t Hab,Bay, Sel; t a b l e // Hab Bay Sel : Z 0? 1 : 0 ; 1? 1 : 1 ;? 0 0 : 0 ;? 1 0 : 1 ; 0 0 x : 0 ;

54 50 Verilog HDL 1 1 x : 1 ; t a b l e p r i m i t i v e? 0 1 x ( H a b) B a y S e l 01x ( ) x( 6-1 U D P 4-1 ) m o d u l e MUX4x1 (Z, A, B, C, D, Sel) ; i n p u t A, B, C, D; i n p u t [2:1] S e l ; o u t p u t Z; p a r a m e t e r trise = 2, tfall = 3; MUX2x1 #(trise, tfall) (TL, A, B, Sel[ 1 ]), (TP, C, D, Sel[ 1 ]), (Z, TL, TP, Sel[ 2 ]); m o d u l e U D P 2 U D P 0 1 x( ) 6.3 UDP U D P 1 U D P U D P U D P ( ) U D P i n i t i a l r e g _ n a m e = 0,1,or x; U D P UDP D U D P 0 p r i m i t i v e Latch (Q, Clk, D) ; o u t p u t Q; r e g Q; i n p u t Clk, D; t a b l e

55 6 51 // Clk D Q(State) Q( n e x t ) 0 1 :? : 1 ; 0 0 :? : 0 ; 1? :? : - ; t a b l e p r i m i t i v e - U D P D UDP U D P D p r i m i t i v e D _ E d g e _ F F (Q, Clk, Data) ; o u t p u t Q ; r e g Q ; i n p u t Data, Clk; i n i t i a l Q = 0; table // Clk Data (State) Q Q( n e x t ) (01) 0 :? : 0 ; (01) 1 :? : 1 ; (0x) 1 : 1 : 1 ; (0x) 0 : 0 : 0 ; // (?0)? :? : - ; // :? (??):? : - ; t a b l e p r i m i t i v e ( 01 ) 0 1 ( 0 x ) 0 x (? 0 ) ( 0, 1 x) 0 (??) x D _ E d g e _ F F U D P 4 m o d u l e R e g 4 (Clk, Din, Dout) ; input C l k ; i n p u t [0:3] D i n; o u t p u t [0:3] D o u t; D _ E d g e _ F F D L A B 0 (Dout[0],Clk, Din[0]), D L A B 1 (Dout[1],Clk, Din[1]), D L A B 2 (Dout[2],Clk, Din[2]), D L A B 3 (Dout[3],Clk, Din[3]), m o d u l e 6.3.4

56 52 Verilog HDL D U D P p r i m i t i v e D_Async_FF (Q, Clk, Clr, Data) ; o u t p u t Q; r e g Q; i n p u t Clr, Data, Clk; t a b l e // Clk Clr Data (State) Q Q( n e x t ) (01) 0 0 :? : 0 ; (01) 0 1 :? : 1 ; (0x) 0 1 : 1 : 1 ; (0x) 0 0 : 0 : 0 ; // (?0) 0? :? : - ; (??) 1? :? : 0 ; 1? :? : 0; t a b l e p r i m i t i v e U D P 2 1 p r i m i t i v e M a j o r i t y 3(Z, A, B, C) ; i n p u t A, B, C; o u t p u t Z table //A B C : Z 0 0? : 0 ; 0? 0 : 0 ;? 0 0 : 0 ; 1 1? : 1 ; 1? 1 : 1 ;? 1 1 : 1 ; t a b l e p r i m i t i v e 6.5 U D P 0 0 ( A B ) A B 1 1 * (??) x r ( 01 )? 0 1 x f ( 10 ) b 0 1 p ( 0 1 ) ( 0x) (x1 ) n ( 1 0 ) ( 1x) (x0 )

57 U D P U D P? 2. UDP? 3. U D P? U D P 5. T U D P T U D P J K J K 0 J 0 K 1 0 J 1 K 0 1 J K 1

58 7 Verilog HDL ( ) 7.1 ( ) ( a s s i g n LHS_target = RHS_expression ; w i r e [3:0] Z, Preset, Clear; // a s s i g n Z = Preset & Clear; // Z Preset & Clear a s s i g n? ( ) P re s e t C l e a r Z : 1) 2). 3) 4) 5) a s s i g n BusErr = Parity (One & OP ) ; a s s i g n Z = ~ (A B) & (C D) & (E F) ; A B C D E F Z wire C o u t, C i n ; w i r e [3:0] Sum, A, B;... a s s i g n {Cout, Sum } = A + B + Cin; A B 4 5 (Cout 1 Sum 4 ) 4 S u m 5 ( ) C o u t

59 7 55 a s s i g n M u x = (S = = 0)? A : 'bz, M u x = (S = = 1)? B : 'bz, M u x = (S = = 2)? C : 'bz, M u x = (S = = 3)? D : 'bz; 4 a s s i g n M u x = (S = = 0)? A : 'bz; a s s i g n M u x = (S = = 1)? B : 'bz; a s s i g n M u x = (S = = 2)? C : 'bz; a s s i g n M u x = (S = = 3)? D : 'bz; m o d u l e F A _ D f (A, B, Cin, Sum, Cout) ; i n p u t A, B, Cin; o u t p u t Sum, Cout ; a s s i g n S u m = A ^B ^Cin; a s s i g n C o u t = (A & Cin) (B & Cin ) (A & B) ; m o d u l e ( ), A 7.3 : w i r e [3:0] S u m = 4'b0; w i r e C l e a r = 'b1; w i r e A _ G T _ B = A > B, B_GT_A= B > A; w i r e C l e a r ; a s s i g n C l e a r = 'b1; w i r e C l e a r = 'b1; 7.4, 0 assign #6 Ask = Quiet L a t e; 6 5 L a t e A s k 11( = 5 +6)

60 56 Verilog HDL a s s i g n #4 Cab = Drm; D r m 9 C a b D r m 8 0 C a b D r m ) 2) 3) : assign # (rise, fall, turn-off) L H S _ t a r g e t = R H S _ e x p r e s s i o n; 0 a s s i g n #4 A s k = Q u i e t L a t e; // One delay value. a s s i g n # (4,8) A s k = Q u i c k ; // Two delay values. a s s i g n # (4,8,6) A r b = & DataBus; // Three delay values. a s s i g n B u s = MemAddr [7:4]; // No delay value. x x z x 4 ( ) 0? 0 0

61 7 57 z 7.5 w i r e #5 A r b; A r b A r b A r a s s i g n # 2 Arb = Bod & Cap; 10 B o d 2 A r b 12 A r b 17( = ) A 2 w i r e #2 A = B - C; 7.6 // Verilog HDL m o d u l e M S D F F _ D F (D, C, Q, Qbar) ; i n p u t D, C; o u t p u t Q, Qbar ; w i r e NotC, NotD, NotY, Y, D1, D2, Ybar, Y1, ; Y2 a s s i g n N o t D = ~ D; a s s i g n N o t C = ~ C; a s s i g n N o t Y = ~ Y; a s s i g n D 1 = ~ (D & C) ; a s s i g n D 2 = ~ (C & NotD) ;

62 58 Verilog HDL a s s i g n Y = ~ (D1 & Ybar ); a s s i g n Ybar = ~ (Y & D2) ; a s s i g n Y1 = ~ (Y & NotC ); a s s i g n Y2 = ~ (NotY & NotC) ; a s s i g n Q = ~ (Qbar & Y1) ; a s s i g n Q b a r = ~ (Y2 & Q) ; m o d u l e ( ) m o d u l e MagnitudeComparator (A, B, AgtB, AeqB, AltB ); p a r a m e t e r BUS = 8; p a r a m e t e r EQ_DELAY = 5, LT_DELAY = 8, GT_DELAY = 8; i n p u t [1 : BUS]A, B; o u t p u t AgtB, AeqB, AltB; a s s i g n #EQ_DELAY AeqB = A = = B; a s s i g n #GT_DELAY AgtB= A > B; a s s i g n #LT_DELAY AltB= A < B; m o d u l e 1.? 2. 2? tri0 [4:0] Q b u s; a s s i g n Q b u s = S b u s; a s s i g n Q b u s = P b u s; P b u s S b u s z Q b u s?

63 8 U D P Verilog HDL Verilog HDL 8.1 1) initial 2) always i n i t i a l a l w a y s i n i t i a l a l w a y s i n i t i a l a l w a y s initial initial initial 0 initial i n i t i a l [t i m i n g _ c o n t r o l] p r o c e d u r a l _ s t a t e m e n t p r o c e d u r a l _ s t a t e m e n t p r o c e d u r a l _ a s s i g n m e n t(blocking or non-blocking )// p r o c e d u r a l _ c o n t i n u o u s _ a s s i g n m e n t c o n d i t i o n a l _ s t a t e m e n t c a s e _ s t a t e m e n t l o o p _ s t a t e m e n t w a i t _ s t a t e m e n t d i s a b l e _ s t a t e m e n t e v e n t _ t r i g g e r s e q u e n t i a l _ b l o c k p a r a l l e l _ b l o c k task_enable (user or system) (... ) i n i t i a l i n i t i a l 0 i n i t i a l i n i t i a l r e g Y u r t;... i n i t i a l Y u r t = 2;

64 60 Verilog HDL i n i t i a l i n i t i a 0 Yu rt 0 2 i n i t i a l r e g C u r t;... i n i t i a l #2 C u r t = 1; C u rt 2 1 i n i t i a l 0 2 i n i t i a l p a r a m e t e r S I Z E = 1024; r e g [7:0] R A M [ 0 :S I Z E- 1 ]; r e g R i b R e g; i n i t i a l : S E Q _ B L K _ A i n t e g e r I n d e x; R i b R e g = 0; f o r (I n d e x = 0; I n d e x < S I Z E; I n d e x = I n d e x + 1) R A M [I n d e x] = 0;... C S E Q _ B L K _ A I n d e x i n i t i a l I n d e x 1 i n i t i a l 0 i n i t i a l / / p a r a m e t e r A P P L Y _ D E L A Y = 5; r e g[ 0 : 7 ]p o r t _ A;... i n i t i a l P o r t _ A = ' h 20 ; #APPLY_DELAY Port_A= 'hf2; #APPLY_DELAY Port_A= 'h41; #APPLY_DELAY Port_A= 'h0a; P o rt _ A initial I n i t i a l

65 always i n i t i a l a l w a y s i n i t i a l a l w a y s a l w a y s [t i m i n g _ c o n t r o l] p r o c e d u r a l _ s t a t e m e n t always C l k = ~ C l k; // a l w a y s a l w a y s 0 a l w a y s a l w a y s always #5 C l k = ~ C l k; // 10 a l w a y s 10 a l w a y s r e g [0:5] I n s t r R e g; r e g [3:0] A c c u m; w i r e E x e c u t e C y c l e; a l w a y (E c e c u t e C y c l e) c a s e(i n s t r R e g[ 0 : 1 ]) 2'b00: S t o r e (Accum, InstrReg[ 2 : 5 ]); 2'b11: L o a d (Accum, InstrReg[ 2 : 5 ]); 2'b01: J u m p (I n s t r R e g[ 2 : 5 ]); 2 ' b 10 :; c a s e / /S t o r e L o a d J u m p (... ) a l w a y s E x e c u t e C y c l e D m o d u l e D F F(Clk, D, Set, Q, Qbar ); i n p u t Clk, D, Set; o u t p u t Q, Qbar; r e g Q, Qbar; a l w a y s w a i t (S e t == 1) #3 Q = 1; #2 Q b a r = 0;

66 62 Verilog HDL w a i t (S e t == 0); a l w a y (n e g e d g e C l k) if (S e t!= 1) #5 Q = D; #1 Q b a r = ~ Q; m o d u l e 2 a l w a y s a l w a y s a l w a y s a l w a y s i n i t i a l 0 1 i n i t i a l 2 a l w a y s m o d u l e T e s t X o r B e h a v i o r; r e g Sa, Sb, Zeus; i n i t i a l S a = 0; S b = 0; #5 S b = 1; #5 S a = 1; #5 S b = 0; a l w a y (Sa or Sb ) Zeus = Sa ^ Sb; a l w a y (Z e u s) $d i s p l a y ("At time %t, S a = %d, S b = %d, Z e u s = %b", $t i m e, S a, S b, Z e u s) ; m o d u l e 3 i n i t i a l S a 0 0 i n i t i a l 3 5 S b 5 1 S a 5 0 i n i t i a l a l w a y s S a S b a l w a y s a l w a y s S a S b i n i t i a l S a S b a l w a y s

67 8 63 Z e u s 2 a l w a y $ d i s p l a y a l w a y s Z e u s S a S b Z e u s 8-2 5, Sa = 0, Sb = 1, Zeus = 1 10, Sa = 1, Sb = 1, Zeus = 0 15, Sa = 1, Sb = 0, Zeus = ) 2) #delay procedural_statement #2 Tx = R x- 5 ; 2 i n i t i a l #3 W a v e = 'b0111; #6 W a v e = 'b1100; #7 W a v e = 'b0000; i n i t i a l #d e l a y; parameter O N _ D E L A Y = 3, O F F _ D E L A Y = 5; a l w a y s # O N _ D E L A Y; // O N _ D E L A Y R e f C l k = 0; # O F F _ D E L A Y; // O F F _ D E L A Y R e f C l k = 1; 8-2 Sa Sb Zeus # Strobe Compare = TX a s k ;

68 64 Verilog HDL # P E R I O D / 2 Clock = C l o c k 0 #0; // x z, a l w a y s 1) 2) 1. event procedural_statement (p o s e d g e C l o c k) C u r r _ S t a t e = N e x t _ S t a t e; C l o c k, C l o c (n e g e d g e R e s e t) C o u n t = l a Z o o = F o o; R e s e t, C l a F o o Z o o C l a C l a,f o o Z o e v e n t ; i n i t i a l t i m e RiseEdge, OnDelay; i n i t i a l (p o s e d g e C l o c k A) ; R i s e E d g e = $t i m e; (n e g e d g e C l o c k A) ; O n D e l a y = $t i m e - R i s e E d g e; $d i s p l a y ("The on-period of clock is %t.", D e l a y) (p o s e d g e C l e a r or negedger e s e t)

69 8 65 Q = (Ctrl_A o r C t r l _ B) D b u s = 'b z; o r 1 Verilog HDL p o s e d g e n e g e d g e 1 -> x 1 -> z 1 -> 0 x -> 0 z -> 0 0 -> x 0 -> z 0 -> 1 x -> 1 z -> 1 2. w a i t (C o n d i t i o n) p r o c e d u r a l _ s t a t e m e n t w a i t (S u m > 22) S u m = 0; w a i t (D a t a R e a d y) D a t a = B u s; w a i t (P r e s e t) ; S u m 22 S u m 0 D a t a R e a d y D a t a R e a d y 1 B u s D a t a P re s e t Ve r i l o g H D L 1) (... ) 2) (f o r k... j o i n)

70 66 Verilog HDL [:b l o c k _ i d{d e c l a r a t i o n s} ] p r o c e d u r a l _ s t a t e m e n t ( s ) // : #2 S t r e a m = 1; #5 S t r e a m = 0; #3 S t r e a m = 1; #4 S t r e a m = 0; #2 S t r e a m = 1; #5 S t r e a m = 0; ( 5 ) P a t = M a s k M a e g e d g e C l k) ; F F = & P a t C l k : S E Q _ B L K r e g[0:3] S a t ; S a t = Mask & Data; F F = ^S a t; S E Q _ B L K 2

71 f o r k j o i n( ) ( ) f o r k [:b l o c k _ i d{d e c l a r a t i o n s} ] p r o c e d u r a l _ s t a t e m e n t(s) ; j o i n // f o r k #2 S t r e a m = 1; #7 S t r e a m = 0; #10 S t r e a m = 1; #14 S t r e a m = 0; #16 S t r e a m = 1; #21 S t r e a m = 0; j o i n a l w a y s :S E Q _ A #4 D r y = 5; // S1 f o r k: P A R _ A // S 2 #6 C u n = 7; //P1 : S E Q _ B // P 2 E X E = B o x; //S6 #5 J a p = E x e; //S7 #2 D o p = 3; //P3 #4 G o s = 2; //P4 #8 P a s = 4; //P5 j o i n

72 68 Verilog HDL #8 B a x = 1; //S3 #2 Z o o m = 52; //S4 #6 $s t o p; //S5 a l w a y s S E Q_A ( S 1 S 2 S 3 S 4 S 5 ) a l w a y s 0 D ry 4 5 PA R _ A 4 ( P 1 P 2 P 3 P 4 P 5 ) 4 C u n 10 D o p 6 G o s 8 P a s 12 S E Q _ B 4 S 6 S 7 J a p 9 PA R _ A 12 S B a x S 4 22 Z o o m 28 $ s t o p a l w a y s i n i t i a l a l w a y s r e g[1:4] E n a b l e, A, B;... #5 E n a b l e = ~A ^ ~B; E n a b l e 5 E n a b l e a l w a y s a l w a y (A o r B o r C o r D) :A O I r e g T e m p 1, T e m p 2; Temp1 = A & B; Temp2 = C & D; Temp1 = Temp1 T e m p 2 ;

73 8 69 Z = ~T e m p 1; /* 4 : Z = ~((A & B) (C& D) ); */ a l w a y s A B C D Te m p 1 Te m p 1 Te m p 2 Te m p 1 1) 2) D o n e = #5 'b1; D o n e = #5 'b1; // T e m p = 'b1; #5 D o n e = T e m p; // Q o s e d g e C l k ) D; // T e m p = o s e d g e C l k) Q = T e m p; // ( ) r e p e a t(e x p r e s (e v e n t _ e x p r e s s i o n) 1 D o n e = r e p e a (n e g e d g e C l k A) A _ R E G + B _ R E G A _ R e g + B _ R e g C l k A D o n e

74 70 Verilog HDL T e m p = A_REG + B _ R E (n e g e d g e C l k A) (n e g e d g e C l k A) ; D o n e = T e m p; = R e g A = 52; a l w a y o r B o r C i n) : C A R R Y _ O U T r e g T 1, T 2, T 3 ; T 1 = A & B; T 2 = B & C i n; T 3 = A & C i n; C o u t = T 1 T 2 T 3; T 1 T 1 T 2 T 3 i n i t i a l C l r = #5 0; C l r = #4 1; C l r = #10 0; 0 C l r 5 C l r 4 1 ( 0 9 ) C l r ( 0 19 ) 8-6 C l r 8-6 A r t = 0;

75 8 71 A r t = 1; A rt 1 A rt 0 A rt 0 1 A rt < = L o a d <= 32; R e g A <= L o a d; R e g B <= S t o r e; ( ) ( 0 ) 10 L o a d 1 32 L o a d ( 1 ) R e g A i n i t i a l C l r <= #5 1; C l r <= #4 0; C l r <= #10 0; C l r 5 1 C l r 4 0 ( 0 4 ) 3 C l r 10 0 ( 0 10 ) C l r i n i t i a l C b n <= 0; C b n <= 1; i n i t i a l C b n Cbn = x Verilog HDL

76 72 Verilog HDL Ve r i l o g C b n 0 1 reg [0:2] Q _ S t a t e; i n i t i a l Q _ S t a t e = 3 b 011 ; Q _ S t a t e <= 3 b 100 ; $d i s p l a y ( Current value of Q_State is, %b Q _ S t a t e) ; #5; // $d i s p l a y ( The delayed value of Q_State is, %b Q _ S t a t e) ; i n i t i a l Current value of Q_State is 011 The delayed value of Q_State is 100 Q _ S t a t e 3 b 011 ( ) Q _ S t a t e ( 0 ) 3 b 100 $d i s p l a y Q _ S t a t e 3 b 011 # 5 Q _ S t a t e Q _ S t a t e 5 $d i s p l a y Q _ S t a t e 8.4.4? a l w a y s i n i t i a l = = = a s s i g n ( a s s i g n 8 8 ) m o d u l e P r o c e d u r a l; r e g A, B, Z; a l w a y Z = A; A = B; m o d u l e

77 8 73 m o d u l e C o n t i n u o u s w i r e A, B, Z; a s s i g n Z = A; a s s i g n A = B; m o d u l e B 10 ns A 10 B Z B Z A B A Z A Z A B A a l w a y s A a l w a y s Z A 8.5 if i f i f(c o n d i t i o n _ 1) p r o c e d u r a l _ s t a t e m e n t _ 1 {else if (c o n d i t i o n _ 2) p r o c e d u r a l _ s t a t e m e n t _ 2} {e l s e p r o c e d u r a l _ s t a t e m e n t _ 3} c o n d i t i o n _ 1 p ro c e d u r a l _ s t a t e m e n t _ 1 condition_1 0 x z p ro c e d u r a l _ s t a t e m e n t _ 1 e l s e i f(s u m < 60) G r a d e = C; T o t a l _ C = Total _c + 1; else if(s u m < 75) G r a d e = B; T o t a l _ B = T o t a l _ B + 1; e l s e G r a d e = A; T o t a l _ A = T o t a l _ A + 1; i f - i f - e l s e i f(c l k) i f(r e s e t) Q = 0; e l s e Q = D;

78 74 Verilog HDL e l s e i f? i f (C l k) i f (R e s e t)? Verilog HDL e l s e e l s e i f e l s e i f i f i f(s u m < 100) S u m = S u m + 10; i f(n i c k e l _ I n) D e p o s i t = 5; e l s e i f (D i m e _ I n) D e p o s i t = 10; else if (Q u a r t e r _ I n) D e p o s i t = 25; e l s e D e p o s i t = E R R O R; i f(c t r l) i f( ~C t r l 2) M u x = 4'd2; e l s e M u x = 4'd1; e l s e i f( ~C t r l 2) M u x = 4'd8; e l s e M u x = 4'd4; 8.6 case c a s e c a s e(c a s e _ e x p r) c a s e _ i t e m _ e x p r{,c a s e _ i t e m _ e x p r} :p r o c e d u r a l _ s t a t e m e n t [d e f a u l t:p r o c e d u r a l _ s t a t e m e n t] c a s e c a s e c a s e _ e x p r 1 c a s e x z c a s e parameter M O N = 0, T U E = 1, W E D = 2, T H U = 3, F R I = 4, SAT = 5, S U N = 6; r e g [0:2] D a y;

79 8 75 i n t e g e r P o c k e t _ M o n e y; c a s e (D a y) T U E : P o c k e t _ M o n e y = 6; M O N, W E D : P o c k e t _ M o n e y = 2; F R I, S A T, S U N : P o c k e t _ M o n e y = 7; d e f a u l t : P o c k e t _ M o n e y = 0; c a s e // 1 // 2 // 3 // 4 D a y M O N W E D 2 3 F R I S AT S U N 4 T H U 111 c a s e m o d u l e A L U (A, B, OpCode, Z) ; i n p u t [3:0] A, B; i n p u t [1:2] O p C o d e; o u t p u t [7:0] Z; r e g [7:0] Z; p a r a m e t e r A D D _ I N S T R = 2'b10, S U B _ I N S T R = 2'b11, M U L T _ I N S T R = 2'b01, D I V _ I N S T R = 2'b00; (A o r B o r O p C o d e) c a s e (O p C o d e) A D D _ I N S T R: Z = A + B; S U B _ I N S T R: Z = A -B; M U L T _ I N S T R: Z = A * B; D I V _ I N S T R: Z = A / B; c a s e m o d u l e c a s e? c a s e c a s e (3'b101 << 2) 3'b100 : $d i s p l a y ( "First branch taken!"); 4'b0100 : $d i s p l a y ( "Second branch taken!"); 5'b10100: $d i s p l a y ( "Third branch taken!"); d e f a u l t : $d i s p l a y ( "Default branch taken!"); c a s e Third branch taken! ' b 101 < < 2 5 ' b case c a s e x z c a s e

80 76 Verilog HDL c a s e x c a s e z x z c a s e x c a s e c a s e c a s e z c a s e z ( ) c a s e x x z c a s e z c a s e( M a s k ) 4'b1??? : D b u s[4] = 0; 4'b01?? : D b u s[3] = 0; 4'b001? : D b u s[2] = 0; 4'b0001 : D b u s[1] = 0; c a s e? z, c a s e z M a s k 1 1 ( ) D b u s[ 4 ] 0 M a s k ( ) D b u s [ 3 ] Verilog HDL 1) forever 2) repeat 3) while 4) for forever f o r e v e r p r o c e d u r a l _ s t a t e m e n t f o r e v e r 0 i n i t i a l C l o c k = 0; # 5 f o r e v e r #10 C l o c k = ~C l o c k; C l o c k repeat repeat r e p e a t(l o o p _ c o u n t) p r o c e d u r a l _ s t a t e m e n t

81 8 77 x z 0 r e p e a t (C o u n t) S u m = S u m + 10; r e p e a t (S h i f t B y) P _ R e g = P _ R e g << 1; r e p e a t, r e p e a t(c o u n (p o s e d g e C l k) S u m = S u m + 1; //repeat C l k C l k S u m 1 Sum = r e p e a t(c o u n (p o s e d g e C l k) S u m + 1; // Sum + 1 C l k r e p e a t(n U M _ O F _ T I M E (n e g e d g e C l o c k Z) ; r e p e a t ClockZ N U M _ O F _ T I M E S while while w h i l e(c o n d i t i o n) p r o c e d u r a l _ s t a t e m e n t x z 0 w h i l e (B Y > 0 ) A c c = A c c << 1; B y = B y - 1; for for f o r(i n i t i a l _ a s s i g n m e n t ; c o n d i t i o n ; s t e p _ a s s i g n m e n t) p r o c e d u r a l _ s t a t e m e n t f o r i n i t i a l _ a s s i g n m e n t c o n d i t i o n s t e p _ a s s i g n m e n t i n t e g e r K; for (K=0 ; K M A X _ R A N G E ; K = K + 1) i f(a b u s[k] == 0) A b u s[k] = 1;

82 78 Verilog HDL else if (A b u s[k] == 1) A b u s[k] = 0; e l s e $d i s p l a y( "A b u s[k] is an x or a z"); end 8.8 a l w a y s i n i t i a l i n i t i a l a l w a y s 1) 2) m o d u l e D E F(D, C l r, C l k, Q) ; i n p u t D, C l r, C l k; o u t p u t Q; r e g Q; a l w a y l r) i f(!c l r) a s s i g n Q = 0; // D Q e l s e d e a s s i g n Q; a l w a y e g e d g e C l k) Q = D; m o d u l e C l r 0 a s s i g n Q 0 C l k D Q C l r 1 C l k Q a s s i g n r e g[3:0] P e s t;...

83 8 79 P e s t = 0;... a s s i g n P e s t = H t y ^ M t u;... assign P e s t = 2; // P e s t... d e a s s i g n P e s t; //Pest 2... a s s i g n P e s t[2] = 1; /* */ P e s t H t y M t u force release f o r c e r e l e a s e a s s i g n d e a s s i g n f o r c e r e l e a s e f o r c e f o r c r e l e a s e f o r c e f o r c e r e l e a s e w i r e P r t;... o r #1 (P r t, S t d, D z x) ; i n i t i a l f o r c e P r t = Dzx & S t d; #5; // 5 release P r t; f o r c e P rt r e l e a s e P rt f o r c e 5 D z x S t d r e g[2:0] C o l t;... C o l t = 2; f o r c e C o l t = 1;... r e l e a s e C o l t;... a s s i g n C o l t = 5;... f o r c e C o l t = 3;... // Colt 1

84 80 Verilog HDL r e l e a s e C o l t; // C o l t 5... f o r c e C o l t[1:0] = 3; /* */ C o l t 1 C o l t 1 f o r c e r e l e a s e C o l t C o l a l w a y s a l w a y s a l w a y a l w a y s 10 R X, M P, R X R e a d y M P M P A c k R X ' t i m e s c a l e 1 n s / 100 p s m o d u l e I n t e r a c t i n g (S e r i a l _ I n, C l k, P a r a l l e l _ O u t) i n p u t S e r i a l _ I n, C l k; o u t p u t [0:7] P a r a l l e l _ O u t; r e g [0:7] P a r a l l e l _ O u t; r e g R e a d y, A c k; w i r e [0:7] d a t a; ' i n c l u d e "Read_Word.v" //R e a d _ W o r d a l w a y s : R X R e a d _ W o r d(s e r i a l _ I n, C l k, D a t a) ; // R e a d _ W o r d D a t a R e a d _ W o r 10 n s R e a d y = 1; w a i t(a c k) ; R e a d y = 0; # 40 ; a l w a y s : M P # 25 ;

85 8 81 P a r a l l e l _ O u t = D a t a; A c k = 1; #25 A c k = 0; w a i t (r e a d y) ; m o d u l e R e a d y A c k 8-9 MP initial a l w a y s a l w a y s casex c a s e 8. a l w a y s w i r e 9. 5 ns i n i t i a l 1 f o r e v e r a l w a y s a l w a y x p e c t e d o r O b s e r v e d) if (E x p e c t e d!== O b s e r v e d) $d i s p l a y ("MISMATCH: Expected = %b,observed = %b" Expected, Observed) ; $s t o p; 11. a l w a y s N e x t S t a t e A N e x t S t a t e B : C l o c k P 5 ns 1 C u rre n t S t a t e 5 3 ns 7 a l w a y (p o s e d g e C l o c k P) #7 N e x t S t a t e A = C u r r e n t S t a t e;