國立交通大學 電子工程學系 電子研究所碩士班 碩士論文 佈局最佳化的低壓元件堆疊來達成 高壓積體電路之靜電放電防護設計 Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consi

Transcription

1 國立交通大學 電子工程學系 電子研究所碩士班 碩士論文 佈局最佳化的低壓元件堆疊來達成 高壓積體電路之靜電放電防護設計 Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration 研究生 : 廖顯峰 (Seian-Feng Liao) 指導教授 : 柯明道教授 (Prof. Ming-Dou Ker) 中華民國一 四年九月

2 佈局最佳化的低壓元件堆疊來達成高壓積體電路之靜電放電防護設計 Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration 研究生 : 廖顯峰 指導教授 : 柯明道教授 Student: Seian-Feng Liao Advisor: Prof. Ming-Dou Ker 國立交通大學 電子工程學系 電子研究所 碩士論文 A Thesis Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electronics Engineering September 2015 Hsinchu, Taiwan, Republic of China 中華民國一 四年九月

3 佈局最佳化的低壓元件堆疊來達成 高壓積體電路之靜電放電防護設計 學生 : 廖顯峰 指導教授 : 柯明道教授 國立交通大學 電子工程學系 電子研究所碩士班 Abstract (Chinese) 靜電放電防護和閂鎖效應 (latchup) 預防是在積體電路中兩個重要的可靠度議題, 尤其是在高壓應用方面 靜電放電可能發生在積體電路產品製造 封裝 組裝的過程中, 通常會造成在積體電路中嚴重的損害, 而在電路正常操作情況下, 雜訊可能會觸發積體電路內部的寄生電晶體, 所以在高壓靜電放電防護設計中, 必須使持有電壓 (holding voltage) 高於電路操作電壓, 否則在應用上可能會發生閂鎖效應 (latchup) 高壓的靜電防護設計中, 通常使用橫向擴散電晶體 (lateral diffused MOS, LDMOS), 但通常橫向擴散電晶體的持有電壓小於電路的操作電壓, 會有閂鎖效應的風險, 因此提出使用低壓電晶體來做堆疊結構來達到在高壓中靜電防護有著高持有電壓的一種方法, 藉由調整元件的不同堆疊個數, 使得在不同高壓應用來提供有效的靜電防護 i

4 在此篇論文中, 實驗並驗證堆疊結構, 藉由多種不同的佈局方式來增加元件的靜電耐受度, 並且使用不同的防護環 (guard-ring) 的佈局方式, 探討對持有電壓的影響 此外, 使用不同傳輸線脈衝產生器 (transmission line pulsing, TLP) 脈衝寬度對持有電壓的影響, 以及試著減少其佈局面積達到相同的靜電耐受度 ii

5 Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration Student: Seian-Feng Liao Advisor: Prof. Ming-Dou Ker Department of Electronics Engineering &Institute of Electronics National Chiao-Tung University Abstract Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. ESD may occur accidentally during the fabrication, package, and assembling processes of IC products, which often caused serious damages on ICs. During normal circuit operation, the noise might unpredictably trigger the parasitic BJT of the ESD devices. Furthermore, to avoid latchup issue, the holding voltage (V h ) should be larger than the supply voltage of the internal circuits in ESD protection design for HV applications. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (V h ) of LDMOS after snapback was smaller than the circuit operating voltage (V CC ). Thus, the LDMOS was sensitive to latchup issue. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in iii

6 HV circuits. By adjusting the stacking numbers of stacked PMOSs, it can provide effective ESD protection for various HV applications. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed about different layout parameters to effectively improve ESD robustness of ESD devices. The guard-ring layout on the stacked LV devices was further investigated holding voltage in silicon chip. In addition, the pulse width of the transmission line pulsing (TLP) system was also investigated holding voltage in silicon chip. Decreasing the layout area to get high ESD robustness and latchup-free immunity for HV applications. iv

7 Acknowledgements 首先要感謝柯明道老師, 在碩士班這兩年的指導, 在上台報告時, 老師總能很快地指出問題所在, 讓我能透過問題, 仔細思考後, 得到新的知識, 也非常謝謝老師可以推薦我去公司工讀實習, 能夠提早一步進入業界探索 在此也要感謝 世界先進積體電路股份有限公司, 在我去工讀的期間, 感謝元件工程處的各位, 以及幫助過我操作失效分析機台及量測的同仁, 謝謝你們的幫忙, 在公司內, 遇到任何問題, 大家總是能夠一起討論, 並且解決問題, 才能夠讓我的研究順利完成 而研究群的各位, 也在研究有困難時, 可以一起討論的夥伴們, 感謝群祐學長 伯硯學長 倍如學姊 Karuna 學長 艾菲學長 志聰學長 嘉岑學長 界廷學長 凱能學長 冠宇學長 建豪學長 美蓮學姊 品歆學姊 信宏學長 同屆同學, 一起打拼的義傑 子毅 睿宏 菀學, 學弟妹們, 柏翰 易翰 鼎洋 道一 力瑾和安妮 感謝實驗室的大家, 有問題時可以一起討論, 也能一起運動, 出遊 而我的好朋友們, 子駒 銘哲 智州, 能夠一起分享共同興趣, 使得生活不會無聊, 也感謝逢甲電機系壘的學長學弟們, 能夠在我畢業後, 還能陪我一起打球及比賽, 也感謝一直一來的的心靈導師怡旬, 總是在我遇到心情低落時, 能夠當我最好的靠山, 以及任老師, 讓我在有所抉擇時, 給我最好的建議, 以及幫助過我的大家, 謝謝你們 而最感謝的就是我的家人, 能夠給我那麼好的環境, 一路上的照顧及栽培, 讓我能毫無顧忌地專心研究, 才會有現在的我, 以及我的女朋友凱婷, 總是能夠包容我的一切, 以及給我加油打氣, 讓我能夠一路走來, 可以如此順遂, 畢業之後, 我也會繼續努力, 不會讓你們失望 廖顯峰 104 年 9 月於竹塹交大 v

8 Contents Abstract (Chinese)..... i Abstract... iii Acknowledgements... v Contents..... vi List of Tables... viii List of Figures... xi Chapter 1 Introduction Motivation ESD Protection Scheme in High-Voltage Integrated Circuits Measurement Methods Thesis Organization... 5 Chapter 2 Layout Optimization on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection Stacked Low-Voltage PMOS in a 0.5-μm HV Process Stacking Units Device Types Experiment Results Stacked Low-Voltage PMOS in a 0.25-μm BCD Process Typical Devices Layout Parameters of Test Devices Experiment Results Discussion Summary Chapter 3 Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection Stacked Low-Voltage PMOS with Different Guard Ring Layout in a 0.5-μm HV Process Test Devices Experimental Results Different Guard Ring Layout of Stacked Low-Voltage PMOS measured by TLP with different pulse widths in a 0.5-μm HV Process Different TLP Pulse Widths Experiment Results Different Guard Ring Layout of Stacked Low-Voltage PMOS vi

9 measured by TLP in a 0.25-μm BCD Process Test Devices Experiment Results Discussion Summary Chapter 4 Conclusions and Future Works Conclusions Future Work New Type Device Guard Ring in Real Circuit Application Reference Vita PUBLICATION LIST vii

10 List of Tables Table 2.1 The measurement data of device Table 2.2 The measurement data of device Table 2.3 The measurement data of device Table 2.4 The measurement data of device Table 2.5 The measurement data of devices with guard-ring layout type one Table 2.6 The measurement data of devices with guard-ring layout type two Table 2.7 The measurement data of typical stacked LV PMOSs Table 2.8 The measurement data of full silicide (no RPO) stacked LV PMOSs Table 2.9 The measurement data of silicide blocking (RPO_0μm) stacked LV PMOSs Table 2.10 The measurement data of silicide blocking (RPO_-0.03μm) stacked LV PMOSs Table 2.11 The measurement data of silicide blocking (RPO_-0.06μm) stacked LV PMOSs Table 2.12 The measurement data of stacked LV PMOSs with d1 4μm Table 2.13 The measurement data of stacked LV PMOSs with d1 6μm Table 2.14 The measurement data of stacked LV PMOSs with drain contact number Table 2.15 The measurement data of stacked LV PMOSs with d1 4μm and drain contact number Table 2.16 The measurement data of stacked LV PMOSs with d1 6μm and drain contact number Table 2.17 The measurement data of stacked LV PMOSs with channel length 1μm Table 2.18 The measurement data of stacked LV PMOSs with total width 600μm and the single finger width 50μm Table 2.19 The measurement data of LV PMOS with different layout parameters Table 2.20 The measurement data of 2-PMOSs with different layout parameters Table 2.21 The measurement data of 3-PMOSs with different layout parameters Table 2.22 The measurement data of 4-PMOSs with different layout parameters Table 2.23 The measurement data of 5-PMOSs with different layout parameters Table 2.24 The measurement data of 6-PMOSs with different layout parameters Table 2.25 The measurement data of 7-PMOSs with different layout parameters Table 2.26 The measurement data of 8-PMOSs with different layout parameters Table 2.27 The measurement data of 9-PMOSs with different layout parameters Table 2.28 The measurement data of 10-PMOSs with different layout parameters Table 3.1 Summary of 2-PMOSs stacked structure with different guard-ring types.. 80 viii

11 Table 3.2 Summary of 3-PMOSs stacked structure with different guard-ring types.. 82 Table 3.3 Summary of 2-PMOSs with different guard-ring types measured by 100-ns TLP Table 3.4 Summary of 2-PMOSs with different guard-ring types measured by 200-ns TLP Table 3.5 Summary of 2-PMOSs with different guard-ring types measured by 500-ns TLP Table 3.6 Summary of 2-PMOSs with different guard-ring types measured by 800-ns TLP Table 3.7 Summary of 3-PMOSs with different guard-ring types measured by 100-ns TLP Table 3.8 Summary of 3-PMOSs with different guard-ring types measured by 200-ns TLP Table 3.9 Summary of 3-PMOSs with different guard-ring types measured by 500-ns TLP Table 3.10 Summary of 3-PMOSs with different guard-ring types measured by 800-ns TLP Table 3.11 Summary of 2-PMOSs with different guard-ring types measured by different TLP pulse width Table 3.12 Summary of 3-PMOSs with different guard-ring types measured by different TLP pulse width Table 3.13 The measurement data of type A (typical stacked LV PMOSs) Table 3.14 The measurement data of type B (12μm) Table 3.15 The measurement data of type B (10μm) Table 3.16 The measurement data of type B (8μm) Table 3.17 The measurement data of type B (6μm) Table 3.18 The measurement data of type B (4μm) Table 3.19 The measurement data of type B (2μm) Table 3.20 The measurement data of type C (12μm) Table 3.21 The measurement data of type C (11μm) Table 3.22 The measurement data of type C (10μm) Table 3.23 The measurement data of type C (9μm) Table 3.24 Area information and comparison of 2-PMOSs Table 3.25 Area information and comparison of 3-PMOSs Table 3.26 Area information and comparison of 4-PMOSs Table 3.27 Area information and comparison of 5-PMOSs Table 3.28 Area information and comparison of 6-PMOSs Table 3.29 Area information and comparison of 7-PMOSs Table 3.30 Area information and comparison of 8-PMOSs ix

12 Table 3.31 Area information and comparison of 9-PMOSs Table 3.32 Area information and comparison of 10-PMOSs Table 3.33 Multi-finger uniform turn-on of type A (typical) Table 3.34 Multi-finger uniform turn-on of type B (12μm) Table 3.35 Multi-finger uniform turn-on of type C (12μm) Table 3.36 Summary of 60V ESD devices Table 3.37 Summary of 80V ESD devices x

13 List of Figures Fig. 1.1 A typical whole-chip ESD protection scheme... 2 Fig. 1.2 The ESD protection design window [10]... 3 Fig. 1.3 Equivalent circuits of (a) HBM and (b) MM... 4 Fig. 2.1 Equivalent circuits of (a) a single LV PMOS and (b) stacked LV PMOSs structure... 7 Fig. 2.2 The cross-section views of PMOS stacking unit drawn with (a) the drain contact to poly-gate edge (d1) spacing of 0.7μm, (b) the d1 spacing of 1.25μm, (c) the d1 spacing of 1.75μm, and (d) the d1 spacing of 1.25μm... 7 Fig. 2.3 The two types of guard-ring layout for 3-PMOSs stacked structure, (a) with one whole p-ring and NWELL spacing of 4μm and (b) with one whole p-ring and NWELL spacing of 8μm... 8 Fig. 2.4 The cross-sectional views of stacked structure with two LV PMOSs drawn with (a) the NWELL spacing of 4μm (type one) and (b) the NWELL spacing of 8μm (type two). Each LV PMOS has its own separated N-well in the stacked structure... 9 Fig. 2.5 The TLP-measured I-V characteristics of device 1 with different guard-ring layouts Fig. 2.6 The TLP-measured I-V characteristics of device 2 with different guard-ring layouts Fig. 2.7 The TLP-measured I-V characteristics of device 3 with different guard-ring layouts Fig. 2.8 The TLP-measured I-V characteristics of device 4 with different guard-ring layouts Fig. 2.9 The TLP-measured I-V characteristics of devices with guard-ring layout type one Fig The TLP-measured I-V characteristics of devices with guard-ring layout type two Fig The cross-section view of typical PMOS Fig The (a) schematic of stacked LV PMOSs with different stacking numbers and (b) top view for 3-PMOSs stacked structure Fig The TLP-measured I-V characteristics of typical stacked LV PMOSs Fig The TLP-measured I-V characteristics of full silicide (no RPO) stacked LV PMOSs Fig The TLP-measured I-V characteristics of silicide blocking (RPO_0μm) stacked LV PMOSs xi

14 Fig The TLP-measured I-V characteristics of silicide blocking (RPO_-0.03μm) stacked LV PMOSs Fig The TLP-measured I-V characteristics of silicide blocking (RPO_-0.06μm) stacked LV PMOSs Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 4μm Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 6μm Fig The TLP-measured I-V characteristics of stacked LV PMOSs with drain contact number Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 4μm and drain contact number Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 6μm and drain contact number Fig The TLP-measured I-V characteristics of stacked LV PMOSs with channel length 1μm Fig The TLP-measured I-V characteristics of stacked LV PMOSs with total width 600μm and the single finger width 50μm Fig The TLP measured I-V curves of LV PMOS with different (a) RPO splits and (b) d1 splits Fig The TLP measured I-V curves of LV PMOS with different (c) d1 and drain contact number (co) splits and (d) L splits Fig The TLP measured I-V curves of LV PMOS with different (e) total width splits Fig The TLP measured I-V curves of 2-PMOSs with different (a) RPO splits.. 37 Fig The TLP measured I-V curves of 2-PMOSs with different (b) d1 splits and (c) d1 and drain contact number (co) splits Fig The TLP measured I-V curves of 2-PMOSs with different (d) L splits and (e) total width splits Fig The TLP measured I-V curves of 3-PMOSs with different (a) RPO splits and (b) d1 splits Fig The TLP measured I-V curves of 3-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits Fig The TLP measured I-V curves of 3-PMOSs with different (e) total width splits Fig The TLP measured I-V curves of 4-PMOSs with different (a) RPO splits and (b) d1 splits Fig The TLP measured I-V curves of 4-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits xii

15 Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig The TLP measured I-V curves of 4-PMOSs with different (e) total width splits The TLP measured I-V curves of 5-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 5-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 5-PMOSs with different (e) total width splits The TLP measured I-V curves of 6-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 6-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 6-PMOSs with different (e) total width splits The TLP measured I-V curves of 7-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 7-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 7-PMOSs with different (e) total width splits The TLP measured I-V curves of 8-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 8-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 8-PMOSs with different (e) total width splits The TLP measured I-V curves of 9-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 9-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 9-PMOSs with different (e) total width splits The TLP measured I-V curves of 10-PMOSs with different (a) RPO splits and (b) d1 splits The TLP measured I-V curves of 10-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits The TLP measured I-V curves of 10-PMOSs with different (e) total width splits The optical microscope (OM) pictures of 6-PMOSs with d1_2μm after MM xiii

16 Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6 Fig. 3.7 stress (a) top view and (b) partial enlarged drawing The optical microscope (OM) pictures of 6-PMOSs with d1_6μm after MM stress The optical microscope (OM) pictures of 10-PMOSs with d1_2μm after MM stress The optical microscope (OM) pictures of 10-PMOSs with d1_6μm after MM stress The OM pictures of 10-PMOSs with d1_2μm (typical) after delayer to substrate (a) M P-10-1, (b) M P-10-2, (c) M P-10-3, (d) M P-10-4 (e) M P-10-5, and (f) M P The OM pictures of 10-PMOSs with d1_2μm (typical) after delayer to substrate (g) M P-10-7, (h) M P-10-8, (i) M P-10-9, and (j) M P The OM pictures of 6-PMOSs with d1_6μm after delayer to substrate (a) M Pd-6-1, (b) M Pd-6-1 & M Pd-6-2, (c) M Pd-6-3 & M Pd-6-4, and (d) M Pd-6-5 & M Pd The OM pictures of 10-PMOSs with d1_6μm after delayer to substrate (a) M Pd-10-1 & M Pd-10-2, (b) M Pd-10-3 & M Pd-10-4, (c) M Pd-10-5 & M Pd-10-6, (d) M Pd-10-7 & M Pd-10-8, (e) M Pd-10-9 & M Pd-10-10, and (f) the edge of M Pd The SEM pictures of 10-PMOSs with d1_6μm after delayer to substrate (a) M Pd-10-1, (b) the edge of M Pd The two types of guard-ring layout for 3-PMOSs stacked structure, (a) with one whole p-ring and NWELL spacing of 4μm and (b) with one whole p-ring and NWELL spacing of 8μm... 8 The four types of guard-ring layout for 3-PMOSs stacked structure, (a) without p-ring, (b) with one whole p-ring and NWELL spacing of 4μm, (c) with one whole p-ring and NWELL spacing of 8μm, and (d) with inserted p-ring to surround each LV PMOS The cross-sectional views of stacked structure with two LV PMOSs drawn with (a) without p-ring, (b) the NWELL spacing of 4μm, (c) the NWELL spacing of 8μm, and (d) with inserted p-ring to surround each LV PMOS. Each LV PMOS has its own separated N-well in the stacked structure The TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts The TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts The TLP-measured I-V characteristics of the stacked 2-PMOSs and 3-PMOSs with the guard-ring layout of type D The 100-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts The 200-ns TLP-measured I-V characteristics of 2-PMOSs with different xiv

17 guard-ring layouts Fig. 3.8 The 500-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Fig. 3.9 The 800-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Fig The TLP-measured I-V characteristics of 2-PMOSs_type A with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type A with different TLP pulse widths Fig The TLP-measured I-V characteristics of 2-PMOSs_type B with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type B with different TLP pulse widths Fig The TLP-measured I-V characteristics of 2-PMOSs_type C with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type C with different TLP pulse widths Fig The TLP-measured I-V characteristics of 2-PMOSs_type D with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type D with different TLP pulse widths Fig The 100-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Fig The 200-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Fig The 500-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Fig The 800-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Fig The TLP-measured I-V characteristics of 3-PMOSs_type A with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type A with different TLP pulse widths Fig The TLP-measured I-V characteristics of 3-PMOSs_type B with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type B with different TLP pulse widths Fig The TLP-measured I-V characteristics of 3-PMOSs_type C with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type C with different TLP pulse widths Fig The TLP-measured I-V characteristics of 3-PMOSs_type D with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type D with different TLP pulse widths Fig The Tek370-measured I-V characteristics of 2-PMOSs with different guard-ring layouts xv

18 Fig The Tek370-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Fig The three types of guard-ring layout for 3-PMOSs stacked structure, (a) type A (typical), (b) type B, and (c) type C Fig The schematic of 3-PMOSs in BCD process Fig The cross-sectional views of stacked structure with two LV PMOSs drawn (a) type A (typical), (b) type B (12μm), and (c) type C (12μm) Fig The TLP-measured I-V characteristics of type A (typical stacked LV PMOSs) Fig The TLP-measured I-V characteristics of type B (12μm) Fig The TLP-measured I-V characteristics of type B (10μm) Fig The TLP-measured I-V characteristics of type B (8μm) Fig The TLP-measured I-V characteristics of type B (6μm) Fig The TLP-measured I-V characteristics of type C (12μm) Fig The TLP-measured I-V characteristics of type C (11μm) Fig The TLP-measured I-V characteristics of type C (10μm) Fig The TLP-measured I-V characteristics of type C (9μm) Fig The TLP-measured I-V characteristics of 2-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 3-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 4-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 5-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 6-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 7-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 8-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 9-PMOSs with different types of layout Fig The TLP-measured I-V characteristics of 10-PMOSs with different types of layout Fig The V h and I t2 of stacked PMOSs with the type A of guard ring layout Fig The V h and I t2 of stacked PMOSs with the type B of guard ring layout Fig The V h and I t2 of stacked PMOSs with the type C of guard ring layout Fig The TLP-measured I-V characteristics of 60V ESD devices xvi

19 Fig The TLP-measured I-V characteristics of 80V ESD devices Fig. 4.1 The cross-sectional views of new type stacked structure with two LV PMOSs drawn Fig. 4.2 The top view of new type stacked structure in real circuit application xvii

20 Chapter 1 Introduction In this chapter, the motivation of this thesis is depicted first. The chapter shows the advantage of stacking in high-voltage (HV) applications, and different guard-ring layout types can achieve both of good ESD robustness and high latchup-free immunity with reasonable total layout area. Electrostatic discharge (ESD) protection scheme reveals the typical arrangement for integrated circuits (ICs). It also introduces the concerns of ESD protection design and testing methods. Finally, thesis organization is included in the end of this chapter. 1.1 Motivation Electrostatic discharge (ESD) may occur accidentally to cause damages on IC products during the fabrication, package, and assembling processes, which often caused serious damages on ICs. High-voltage (HV) ICs were found with bad ESD robustness [1]-[2]. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (V h ) of LDMOS after snapback was smaller than the circuit operating voltage (V CC ) [3]-[4]. Thus, the LDMOS was sensitive to latchup issue. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in HV circuits [5]-[7].It is suggested that ICs should require 2kV in human body model (HBM) and 200V in machine model (MM) [8], [9]. Stacking low-voltage devices is an excellent solution for latchup immunity and ESD robustness. The total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The total trigger voltage (V t1 ) of stacked PMOSs is also the multiple of the trigger voltage of single PMOS. The secondary breakdown current (I t2 ) of stacked PMOSs are almost the same in spite of different stacking numbers [10]. The main layout parameters to 1

21 affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate edge at drain and source regions, the spacing from the drain diffusion to the guard-ring diffusion, and the finger width of each unit finger. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices [11]. Try to use different layout methods to improve ESD robustness on stacking low-voltage devices effectively. In addition, the ESD devices should be surrounded by the guard ring in real circuit application. The ESD device without the guard ring can reduce the layout area, but it might cause the latchup issue under the normal circuit operation. 1.2 ESD Protection Scheme in High-Voltage Integrated Circuits A typical whole-chip ESD protection scheme is shown in Fig The ESD stresses on each I/O pin have four stress modes of pin combination with the relatively grounded GND pin or VDD/VCC pin [12]. The ESD stresses could also happen from the VCC pin to the GND pin with positive or negative voltage pulses [12]. Stacked devices can be the ESD protection cells at the input or output pads or the power-rail ESD clamp between the VCC/GND power lines. Fig. 1.1 A typical whole-chip ESD protection scheme The typical I-V characteristics of ESD protection devices are illustrated in Fig

22 Breakdown voltage (V BD ) and supply voltage (V DD or V CC ) of the internal circuits divide the plot into three parts. The middle part is the desired ESD protection window. The green curve is an example of the desired ESD device s I-V characteristics. To get an effective ESD protection, the trigger voltage (V t1 ) should be smaller than breakdown voltage of the internal circuits. Furthermore, to avoid latchup issue, the holding voltage (V h ) should be larger than the supply voltage of the internal circuits. The on-resistance of an ESD protection device should be as small as possible to get a high ESD robustness. The I-V characteristics of ESD devices should fit into this window for both effective ESD protection and latchup-free design. Fig. 1.2 The ESD protection design window [10] 1.3 Measurement Methods ESD could induce serious yield > loss in ICs. Change may accumulate in human bodies and machines. When one pin connected to ground, the ESD current may damage ICs. It is suggested that ICs should require 2kV in human body model (HBM) and 200V in machine 3

23 model (MM). There are several ways to test ESD robustness. The equivalent models of HBM and MM are illustrated in Fig (a) (b) Fig. 1.3 Equivalent circuits of (a) HBM and (b) MM Transmission line pulse (TLP) system can measure the ESD-related device parameters for ESD protection design. The Barth pulse curve tracer 4002 TLP is used to measure the TLP I-V curve. It is common to use 100-ns pulse width. It can be obtained device parameters such as trigger voltage (V t1 ), holding voltage (V h ), secondary breakdown current (I t2 ) and on-resistance (R on ) from TLP I-V curve. Higher secondary breakdown current usually means a higher ESD level. The holding voltage of n-channel LDMOS in an HV BCD process has been investigated by TLP measurements with different pulse widths and dc curve tracer. It is found that the holding voltages of an n-channel LDMOS measured by 100-ns TLP system and curve tracer are substantially different [13]. The I-V curve of the long pulse width TLP measured by TLP celestron-1 in this thesis. The TLP I-V curve can be measured by 100-ns, 200-ns, 500-ns and 800-ns pulse width. The I-V curve can be measured by curve tracer Tek370 in a dc condition. During latchup test, the positive or negative current of up to 200mA will be directly applied to the I/O pin [14]. Such latchup-test current will be injected into the substrate through the on-chip ESD device that is often drawn with the I/O pad together to provide ESD protection. 4

24 1.4 Thesis Organization This thesis focuses on optimization of stacked low-voltage devices for good ESD robustness and latchup immunity. In chapter 1, it introduces research motivation, measurement methods and an ESD protection scheme. It describes the dependence of layout parameters on ESD robustness of stacked LV PMOSs in chapter 2. Chapter 3 shows stacked PMOSs with different guard ring layouts for HV ESD protection. In this thesis, the stacked LV PMOS devices have been successfully verified in a VIS 0.5-μm HV process and 0.25-μm 80V BCD process. In chapter 4, conclusions and future work. 5

25 Chapter 2 Layout Optimization on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection Stacking is a good way to reach high holding voltage for high-voltage ESD protection. The trigger voltage and the holding voltage of stacked configuration can be adjusted to meet different HV applications. In this chapter, the dependence of layout parameters on ESD robustness of stacked LV PMOSs. In this work, the stacked LV PMOS devices have been successfully verified in a VIS 0.5-μm HV process and 0.25-μm 80V BCD process. 2.1 Stacked Low-Voltage PMOS in a 0.5-μm HV Process Stacking Units A PMOS was fabricated in a 0.5-μm HV process, which has a device dimension of W/L = 800μm/0.5μm. The equivalent circuits are showed in Fig The stacked LV PMOSs with two and three stacking numbers are investigated in this work, which are designed to meet 20-V and 30-V HV applications. There are four different stacking units, the spacing from drain contact to poly-gate edge (d1) of PMOS devices are investigated through the fabricated test chips. The cross-section view of PMOS stacking units are showed in Fig The d1 spacing of stacking units are drawn with 0.7μm, 1.25μm, 1.75μm, and 2.25μm in Fig. 2(a), Fig. 2(b), Fig. 2(c) and Fig. 2(d). 6

26 (a) (b) Fig. 2.1 Equivalent circuits of (a) a single LV PMOS and (b) stacked LV PMOSs structure (a) (b) (c) (d) Fig. 2.2 The cross-section views of PMOS stacking unit drawn with (a) the drain contact to poly-gate edge (d1) spacing of 0.7μm, (b) the d1 spacing of 1.25μm, (c) the d1 spacing of 1.75μm, and (d) the d1 spacing of 1.25μm 7

27 2.1.2 Device Types The ESD devices should be surrounded by the guard ring in real circuit application. These four kinds of devices have different types of the guard ring layouts. There are two types (type one and type two) of the guard ring layouts to surround the stacked PMOSs, as shown in Fig. 2.3, where 3-PMOSs stacked structure is demonstrated. In type one and type two, the stacked PMOSs were surrounded by one P-ring that is typically connected to cathode. The NWELL spacing between each N-well in the type one (type two) is 4μm (8μm). The clearance of P-ring to the N-well edge is kept at 2.7μm, which is a layout rule specified by the foundry in the given 0.5-μm process. (a) (b) Fig. 2.3 The two types of guard-ring layout for 3-PMOSs stacked structure, (a) with one whole p-ring and NWELL spacing of 4μm and (b) with one whole p-ring and NWELL spacing of 8μm 8

28 Each LV PMOS in the stacked configuration is drawn with the total channel width of 800μm and a channel length of 0.5μm. The cross-sectional view of stacked structure with two LV PMOSs is shown in Fig The NWELL spacings of the two LV PMOSs are drawn with 4μm and 8μm in Fig. 2.4(a) and Fig. 2.4(b), respectively. The gate of each PMOS is connected to its local high potential point, so each PMOS in the stacked structure is kept in the off state during the normal circuit operation. The P+ diffusion (drain) of the bottom PMOS in the stacked PMOSs is connected to the cathode. The P-ring is connected to the cathode, which is typically biased at ground with the common p-substrate. (a) (b) Fig. 2.4 The cross-sectional views of stacked structure with two LV PMOSs drawn with (a) the NWELL spacing of 4μm (type one) and (b) the NWELL spacing of 8μm (type two). Each LV PMOS has its own separated N-well in the stacked structure Experiment Results All test devices of stacked PMOSs had been fabricated in a 0.5-μm HV process. Each PMOS in all stacked structure is drawn with a channel width of 800μm and a channel length 9

29 of 0.5μm. Every layout type has 2-PMOSs and 3-PMOSs stacked structures. The TLP-measured I-V characteristics of device 1 with the two types of guard ring layout are shown in Fig The detailed characteristics of device 1 stacked structure with different guard-ring types are listed in Table 2.1. Fig. 2.5 The TLP-measured I-V characteristics of device 1 with different guard-ring layouts Table 2.1 The measurement data of device 1 In Table 2.1, the trigger voltage of stacked PMOSs is the multiple of the trigger voltage of single PMOS, but the holding voltage of type one is smaller than type two. It will be discussed about guard-ring layout in the chapter 3. The breakdown voltage of stacked PMOSs 10

30 is the multiple of the breakdown voltage of single PMOS. The breakdown voltage is defined the off current equal 1μA in DC measurement. All of stacked structure with two guard-ring types can pass 4.5 kv in the human-body-model (HBM) ESD test and 300 V in the machine-model (MM) ESD test. The TLP-measured I-V characteristics of device 2 with the two types of guard ring layout are shown in Fig The detailed characteristics of device 2 stacked structure with different guard-ring types are listed in Table 2.2. Fig. 2.6 The TLP-measured I-V characteristics of device 2 with different guard-ring layouts Table 2.2 The measurement data of device 2 11

31 The TLP-measured I-V characteristics of device 3 with the two types of guard ring layout are shown in Fig The detailed characteristics of device 3 stacked structure with different guard-ring types are listed in Table 2.3. Fig. 2.7 The TLP-measured I-V characteristics of device 3 with different guard-ring layouts Table 2.3 The measurement data of device 3 12

32 The TLP-measured I-V characteristics of device 4 with the two types of guard ring layout are shown in Fig The detailed characteristics of device 4 stacked structure with different guard-ring types are listed in Table 2.4. Fig. 2.8 The TLP-measured I-V characteristics of device 4 with different guard-ring layouts Table 2.4 The measurement data of device 4 The TLP-measured I-V characteristics of the stacked 2-PMOSs and 3-PMOSs with the guard-ring layout type one (type two) are compared in Fig. 2.9 (Fig. 2.10). The detailed 13

33 characteristics of different devices with same type guard ring layout are listed in Table 2.5 and Table 2.6. Fig. 2.9 The TLP-measured I-V characteristics of devices with guard-ring layout type one Table 2.5 The measurement data of devices with guard-ring layout type one 14

34 Fig The TLP-measured I-V characteristics of devices with guard-ring layout type two Table 2.6 The measurement data of devices with guard-ring layout type two From the experimental results, the larger d1 parameter can cause larger I t2 of stacked PMOS devices. From above results with TLP-measured I t2 and ESD test, the device 4 among is the best choice for the stacked PMOSs structure for HV ESD protection. All of device 4 15

35 with two guard-ring types can pass 5.5 kv in the human-body-model (HBM) ESD test and 300 V in the machine-model (MM) ESD test. The holding voltage of type one still suffers latchup risk for 20V and 30V application. During ESD zapping, the ESD current unpredictably trigger the other parasitic BJT of the ESD devices. It induces the holding voltage (V h ) of type one smaller than the holding voltage (V h ) of type two. Guard-ring layout will be discussed in the Chapter 3. The type two among is the best choice for the stacked PMOSs structure for HV ESD protection. 2.2 Stacked Low-Voltage PMOS in a 0.25-μm BCD Process Typical Devices The test devices were all fabricated in a VIS 0.25-μm Bipolar-CMOS-DMOS (BCD) process. The main layout parameters to affect ESD robustness of ESD devices are the silicide blocking, the spacing from drain contact to poly-gate edge (d1), contact number, the channel length, and total width. The optimized layout parameters have been verified to effectively improve ESD robustness of ESD devices. Try to achieve this concept in stacked LV PMOS structure. Stacking number was from 1 to 10 in this test. Typical PMOS devices in this investigation, the clearance from the resist-protection-oxide (RPO) to poly-gate edge, the clearance from the drain contact to poly-gate edge (d1), the drain contact number (co), the channel length (L), the single finger width, and the total width are kept at 0.3μm, 2μm, 2, 0.8μm, 30μm,and 360μm, respectively. The cross-section view of typical PMOS stacking unit is showed in Fig

36 Fig The cross-section view of typical PMOS Low-voltage devices should be surrounded by isolation ring for HV applications. Isolation rings are composed by a HV-NWELL ring and a HV-PWELL ring. The P+ diffusion (drain) of the bottom PMOS in the stacked PMOSs is connected to the cathode. The HV-PWELL ring is connected to the cathode, which is typically biased at ground with the common p-substrate. The HV-NWELL ring is tied to relative high potential point. Fig. 2.12(a) and Fig. 2.12(b) show the schematic of stacked LV PMOSs for HV ESD protection and the top view respectively. (a) (b) Fig The (a) schematic of stacked LV PMOSs with different stacking numbers and (b) top view for 3-PMOSs stacked structure 17

37 2.2.2 Layout Parameters of Test Devices There are four splits about RPO effect of PMOS, which focus on full silicide (no RPO) and silicide blocking. The RPO spacing is decrease from 0.3μm (typical) to -0.06μm at the drain region. There are several splits about the drain contact to poly-gate edge (d1) effect and drain contact number (co). The spacings of the drain contact to poly-gate edge (d1) are 2μm (typical), 4μm, and 6μm, and the clearance variation on the drain contact number (co) splits from 2 (typical) to 4. There are two splits about channel length (L) effect of PMOS, the clearance variation are 0.8μm (typical) and 1μm. The clearance variation on total width splits from 360μm (typical) to 600μm. The single finger width of the PMOS devices with total width of 360μm (typical) and 600μm are 30μm and 50μm, respectively Experiment Results The TLP measured I-V characteristics of typical stacked LV PMOSs are shown in Fig The holding voltages of stacked LV PMOSs with different stacking numbers can be found in Fig The total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The total trigger voltage of stacked PMOSs is also the multiple of the trigger voltage of single PMOS. The secondary breakdown current (I t2 ) of stacked PMOSs are almost the same in spite of different stacking numbers. The detailed characteristics of typical stacked LV PMOSs are listed in Table 2.7. The TLP measured I-V characteristics of full silicide (no RPO) stacked LV PMOSs are shown in Fig All of full silicide (no RPO) stacked LV PMOSs can pass 4 kv in the human-body-model (HBM) ESD test and 200 V in the machine-model (MM) ESD test. The detailed characteristics of full silicide (no RPO) stacked LV PMOSs are listed in Table 2.7. The TLP measured I-V characteristics of silicide blocking stacked LV PMOSs are shown in Fig. 2.14, Fig. 2.15, Fig The spacings of RPO are 0μm (overlap poly-gate), -0.03μm, and -0.06μm. The detailed characteristics of silicide blocking stacked LV PMOSs are listed in Table 2.8, Table 2.9, and Table

38 Fig The TLP-measured I-V characteristics of typical stacked LV PMOSs Table 2.7 The measurement data of typical stacked LV PMOSs 19

39 Fig The TLP-measured I-V characteristics of full silicide (no RPO) stacked LV PMOSs Table 2.8 The measurement data of full silicide (no RPO) stacked LV PMOSs 20

40 Fig The TLP-measured I-V characteristics of silicide blocking (RPO_0μm) stacked LV PMOSs Table 2.9 The measurement data of silicide blocking (RPO_0μm) stacked LV PMOSs 21

41 Fig The TLP-measured I-V characteristics of silicide blocking (RPO_-0.03μm) stacked LV PMOSs Table 2.10 The measurement data of silicide blocking (RPO_-0.03μm) stacked LV PMOSs 22

42 Fig The TLP-measured I-V characteristics of silicide blocking (RPO_-0.06μm) stacked LV PMOSs Table 2.11 The measurement data of silicide blocking (RPO_-0.06μm) stacked LV PMOSs 23

43 All of silicide blocking stacked LV PMOSs can pass 4.5 kv in the human-body-model (HBM) ESD test and 300 V in the machine-model (MM) ESD test. Three silicide blocking devices have almost similar I t2 and ESD robustness. The ESD robustness of stacked PMOS devices with silicide blocking on drain side are better than stacked PMOS devices with full silicide in the TLP test. The TLP measured I-V characteristics of stacked LV PMOSs with different drain contact to poly-gate edge (d1) are shown in Fig. 2.18, Fig The spacings of d1 are 4μm and 6μm. The detailed characteristics of stacked LV PMOSs with different drain contact to poly-gate edge (d1) are listed in Table 2.12 and Table Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 4μm All of stacked LV PMOSs with d1 4μm can pass 7 kv in the human-body-model (HBM) ESD test and 450 V in the machine-model (MM) ESD test. The ESD robustness of stacked LV PMOSs with d1 4μm are better than typical stacked PMOS devices in the TLP test. 24

44 Table 2.12 The measurement data of stacked LV PMOSs with d1 4μm Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 6μm 25

45 Table 2.13 The measurement data of stacked LV PMOSs with d1 6μm All of stacked LV PMOSs with d1 6μm can pass 6 kv in the human-body-model (HBM) ESD test and 400 V in the machine-model (MM) ESD test. The TLP measured I-V characteristics of stacked LV PMOSs with different drain contact number (co) effect are shown in Fig The number of drain contact number (co) is 4. The detailed characteristics of stacked LV PMOSs with different drain contact number effect are listed in Table All of stacked LV PMOSs with drain contact number 4 can pass 5 kv in the human-body-model (HBM) ESD test and 350 V in the machine-model (MM) ESD test. Furthermore, to get good ESD robustness, d1 effect and drain contact number effect are considered simultaneously. The TLP measured I-V characteristics of stacked LV PMOSs with different d1 and drain contact number are shown in Fig and Fig The detailed characteristics of stacked LV PMOSs with different d1 and drain contact number are listed in Table 2.15 and Table

46 Fig The TLP-measured I-V characteristics of stacked LV PMOSs with drain contact number 4 Table 2.14 The measurement data of stacked LV PMOSs with drain contact number 4 27

47 Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 4μm and drain contact number 4 Table 2.15 The measurement data of stacked LV PMOSs with d1 4μm and drain contact number 4 28

48 Fig The TLP-measured I-V characteristics of stacked LV PMOSs with d1 6μm and drain contact number 4 Table 2.16 The measurement data of stacked LV PMOSs with d1 6μm and drain contact number 4 29

49 All of stacked LV PMOSs with d1 4μm and drain contact number 4 can pass 7.5 kv in the human-body-model (HBM) ESD test and 500 V in the machine-model (MM) ESD test. All of stacked LV PMOSs with d1 6μm and drain contact number 4 can pass 6.5 kv in the human-body-model (HBM) ESD test and 450 V in the machine-model (MM) ESD test. From the above experiments, d1 effect and drain contact number effect of stacked LV PMOSs can get good ESD robustness. The TLP measured I-V characteristics of stacked LV PMOSs with channel length effect are shown in Fig The channel length of stacked LV PMOSs is 1μm. The detailed characteristics of stacked LV PMOSs with channel length effect are listed in Table All of stacked LV PMOSs with channel length 1μm can pass 5 kv in the human-body-model (HBM) ESD test and 350 V in the machine-model (MM) ESD test. Fig The TLP-measured I-V characteristics of stacked LV PMOSs with channel length 1μm 30

50 Table 2.17 The measurement data of stacked LV PMOSs with channel length 1μm The TLP measured I-V characteristics of stacked LV PMOSs with total width effect are shown in Fig The total width of stacked LV PMOSs is 600μm, and the single finger width of stacked LV PMOSs is 50μm. The total width of typical stacked LV PMOSs is 360μm, and the single finger width of typical stacked LV PMOSs is 30μm. The detailed characteristics of stacked LV PMOSs with total width 600μm are listed in Table All of stacked LV PMOSs with total width 600μm can pass 8 kv in the human-body-model (HBM) ESD test and 500 V in the machine-model (MM) ESD test. 31

51 Fig The TLP-measured I-V characteristics of stacked LV PMOSs with total width 600μm and the single finger width 50μm Table 2.18 The measurement data of stacked LV PMOSs with total width 600μm and the single finger width 50μm 32

52 2.2.4 Discussion From the above experiments, ESD robustness of stacked LV PMOSs with different layout parameters are better than those of typical ones. Therefore, the trigger voltage and the holding voltage of stacked configuration can be adjusted to meet different HV applications. Stacking numbers of the stacked LV PMOSs were fabricated and verified from one to ten for different HV applications. Layout parameters were investigated to study its impact on ESD protection performance from stacking number one to ten, respectively. There are RPO, drain contact to poly-gate edge (d1), drain contact number (co), channel length (L), and total width effect. The TLP measured I-V curves of LV PMOS with different RPO splits (typical_0.3μm, 0μm, -0.03μm, -0.06μm, and no RPO) are compared in Fig. 2.25(a). The TLP measured I-V curves of LV PMOS with different d1 splits (typical_2μm, 4μm, and 6μm) are compared in Fig. 2.25(b). The TLP measured I-V curves of LV PMOS with different d1 and drain contact number splits (typical_d1_2μm_co_2, d1_2μm_co_4, d1_4μm_co_4, and d1_6μm_co_4) are compared in Fig. 2.25(c). The TLP measured I-V curves of LV PMOS with different L splits (typical_0.8μm and 1μm) are compared in Fig. 2.25(d). The TLP measured I-V curves of LV PMOS with different total width (TW) splits (typical_360μm and 600μm) are compared in Fig. 2.25(e). The total width of LV PMOS is 600μm, and the single finger width of LV PMOS is 50μm. The total width of LV PMOS is 360μm, and the single finger width of typical LV PMOS is 30μm. The detailed characteristics of LV PMOS with different layout parameters are listed in Table

53 (a) Fig The TLP measured I-V curves of LV PMOS with different (a) RPO splits and (b) d1 splits (b) 34

54 (c) Fig The TLP measured I-V curves of LV PMOS with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 35

55 (e) Fig The TLP measured I-V curves of LV PMOS with different (e) total width splits Table 2.19 The measurement data of LV PMOS with different layout parameters 36

56 From the above experiments, the breakdown voltages of LV PMOS are almost the same in DC measurement. The holding voltages and the trigger voltages of LV PMOS are almost the same in TLP measurement. From above results with TLP-measured I t2 and ESD test, ESD robustness of LV PMOS with full silicide (no RPO) is bad. The LV PMOS with silicide blocking leads to a higher ESD robustness. Generally, the LV PMOS with a larger clearance drain contact to poly-gate edge, the more drain contact number, a wider channel width, a bigger total width leads to higher ESD robustness. LV PMOS with d1_6μm, d1_6μm_co_4, and TW_600μm can pass 8 kv in the human-body-model (HBM) ESD test and 450 V in the machine-model (MM) ESD test. The TLP measured I-V curves of 2-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.26(a) ~ (e). The detailed characteristics of 2-PMOSs with different layout parameters are listed in Table Fig The TLP measured I-V curves of 2-PMOSs with different (a) RPO splits (a) 37

57 (b) Fig The TLP measured I-V curves of 2-PMOSs with different (b) d1 splits and (c) d1 and drain contact number (co) splits (c) 38

58 (d) Fig The TLP measured I-V curves of 2-PMOSs with different (d) L splits and (e) total width splits (e) 39

59 Table 2.20 The measurement data of 2-PMOSs with different layout parameters The breakdown voltages of 2-PMOSs stacked structure are also almost the same in DC measurement. The holding voltage of 2-PMOSs stacked structure is two times of the holding voltage of single PMOS. The trigger voltage of 2-PMOSs stacked structure is also double of the trigger voltage of single PMOS in TLP measurement. The 2-PMOSs with d1_6μm, d1_6μm_co_4, and TW_600μm can pass 8 kv in the human-body-model (HBM) ESD test and 500 V in the machine-model (MM) ESD test. The TLP measured I-V curves of 3-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.27(a) ~ (e). The detailed characteristics of 3-PMOSs with different layout parameters are listed in Table

60 (a) Fig The TLP measured I-V curves of 3-PMOSs with different (a) RPO splits and (b) d1 splits (b) 41

61 (c) Fig The TLP measured I-V curves of 3-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 42

62 Fig The TLP measured I-V curves of 3-PMOSs with different (e) total width splits (e) Table 2.21 The measurement data of 3-PMOSs with different layout parameters 43

63 In Table 2.21, the breakdown voltages in different layout consideration are almost the same. As seen in Table 2.21, the trigger voltage of 3-PMOSs stacked structure is triple of the trigger voltage of single PMOS, and the holding voltage of 3-PMOSs stacked structure is also triple of the holding voltage of single PMOS. The trigger voltages and the holding voltages of 3-PMOSs stacked structure are also the same. ESD robustness of 3-PMOSs with d1_6μm, d1_6μm_co_4, and TW_600μm can pass 8 kv in the human-body-model (HBM) ESD test and 500 V in the machine-model (MM) ESD test. The TLP measured I-V curves of 4-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.28(a) ~ (e). The detailed characteristics of 4-PMOSs with different layout parameters are listed in Table The TLP measured I-V curves of 5-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.29(a) ~ (e). The detailed characteristics of 5-PMOSs with different layout parameters are listed in Table The TLP measured I-V curves of 6-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.30(a) ~ (e). The detailed characteristics of 6-PMOSs with different layout parameters are listed in Table The TLP measured I-V curves of 7-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.31(a) ~ (e). The detailed characteristics of 7-PMOSs with different layout parameters are listed in Table The TLP measured I-V curves of 8-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.32(a) ~ (e). The detailed characteristics of 8-PMOSs with different layout parameters are listed in Table

64 (a) Fig The TLP measured I-V curves of 4-PMOSs with different (a) RPO splits and (b) d1 splits (b) 45

65 (c) Fig The TLP measured I-V curves of 4-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 46

66 Fig The TLP measured I-V curves of 4-PMOSs with different (e) total width splits (e) Table 2.22 The measurement data of 4-PMOSs with different layout parameters 47

67 (a) Fig The TLP measured I-V curves of 5-PMOSs with different (a) RPO splits and (b) d1 splits (b) 48

68 (c) Fig The TLP measured I-V curves of 5-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 49

69 Fig The TLP measured I-V curves of 5-PMOSs with different (e) total width splits (e) Table 2.23 The measurement data of 5-PMOSs with different layout parameters 50

70 (a) Fig The TLP measured I-V curves of 6-PMOSs with different (a) RPO splits and (b) d1 splits (b) 51

71 (c) Fig The TLP measured I-V curves of 6-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 52

72 Fig The TLP measured I-V curves of 6-PMOSs with different (e) total width splits (e) Table 2.24 The measurement data of 6-PMOSs with different layout parameters 53

73 (a) Fig The TLP measured I-V curves of 7-PMOSs with different (a) RPO splits and (b) d1 splits (b) 54

74 (c) Fig The TLP measured I-V curves of 7-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 55

75 Fig The TLP measured I-V curves of 7-PMOSs with different (e) total width splits (e) Table 2.25 The measurement data of 7-PMOSs with different layout parameters 56

76 (a) Fig The TLP measured I-V curves of 8-PMOSs with different (a) RPO splits and (b) d1 splits (b) 57

77 (c) Fig The TLP measured I-V curves of 8-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 58

78 Fig The TLP measured I-V curves of 8-PMOSs with different (e) total width splits (e) Table 2.26 The measurement data of 8-PMOSs with different layout parameters 59

79 The TLP measured I-V curves of 9-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.33(a) ~ (e). (a) Fig The TLP measured I-V curves of 9-PMOSs with different (a) RPO splits and (b) d1 splits (b) 60

80 (c) Fig The TLP measured I-V curves of 9-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 61

81 (e) Fig The TLP measured I-V curves of 9-PMOSs with different (e) total width splits The detailed characteristics of 9-PMOSs with different layout parameters are listed in Table Table 2.27 The measurement data of 9-PMOSs with different layout parameters 62

82 The TLP measured I-V curves of 10-PMOSs with different layout parameters splits (RPO, d1, drain contact number, L, and TW) are compared in Fig. 2.34(a) ~ (e). (a) Fig The TLP measured I-V curves of 10-PMOSs with different (a) RPO splits and (b) d1 splits (b) 63

83 (c) Fig The TLP measured I-V curves of 10-PMOSs with different (c) d1 and drain contact number (co) splits and (d) L splits (d) 64

84 (e) Fig The TLP measured I-V curves of 10-PMOSs with different (e) total width splits The detailed characteristics of 10-PMOSs with different layout parameters are listed in Table Table 2.28 The measurement data of 10-PMOSs with different layout parameters 65

85 From above results with TLP-measured I t2 and ESD test, ESD robustness of 9-PMOSs with d1 splits and drain contact number splits has different results. ESD robustness of 10-PMOSs with d1 splits and drain contact number splits also has different results. ESD robustness of stacking number 9 and 10 is lower than that of stacking number from 1 to 8. The optical microscope (OM) pictures of 6-PMOSs with d1_2μm (typical) are shown in Fig after MM stress. ESD robustness of 6-PMOSs with d1_2μm (typical) can pass 400 V in the machine-model (MM) ESD test, and that failed 450 V in the machine-model (MM) ESD test. The optical microscope (OM) pictures of 6-PMOSs with d1_6μm are shown in Fig after MM stress. ESD robustness of 6-PMOSs with d1_6μm can pass 600 V in the machine-model (MM) ESD test, and that failed 650 V in the machine-model (MM) ESD test. The optical microscope (OM) pictures of 10-PMOSs with d1_2μm (typical) are shown in Fig after MM stress. ESD robustness of 10-PMOSs with d1_2μm (typical) can pass 450 V in the machine-model (MM) ESD test, and that failed 500 V in the machine-model (MM) ESD test. The optical microscope (OM) pictures of 10-PMOSs with d1_6μm are shown in Fig after MM stress. ESD robustness of 10-PMOSs with d1_6μm only pass 400 V in the machine-model (MM) ESD test, and that failed 450 V in the machine-model (MM) ESD test. (a) (b) Fig The optical microscope (OM) pictures of 6-PMOSs with d1_2μm after MM stress (a) top view and (b) partial enlarged drawing 66

86 Fig The optical microscope (OM) pictures of 6-PMOSs with d1_6μm after MM stress Fig The optical microscope (OM) pictures of 10-PMOSs with d1_2μm after MM stress 67

87 Fig The optical microscope (OM) pictures of 10-PMOSs with d1_6μm after MM stress From above pictures, the OM pictures of 10-PMOSs with d1_6μm after MM stress can directly clear to see the failure position, but other OM pictures can t. After delayer to substrate, ESD failure positions of stacked PMOS structure can be seen directly. The names of 6-PMOSs with d1_2μm are M P-6-1, M P-6-2, M P-6-3, M P-6-4, M P-6-5, M P-6-6 from top to bottom, respectively. The names of 10-PMOSs with d1_2μm are M P-10-1, M P-10-2, M P-10-3, M P-10-4, M P-10-5, M P-10-6, M P-10-7, M P-10-8, M P-10-9, M P from top to bottom, respectively. The names of 6-PMOSs with d1_6μm are M Pd-6-1, M Pd-6-2, M Pd-6-3, M Pd-6-4, M Pd-6-5, M Pd-6-6 from top to bottom, respectively. The names of 10-PMOSs with d1_6μm are M P-10-1, M P-10-2, M Pd-10-3, M Pd-10-4, M Pd-10-5, M Pd-10-6, M Pd-10-7, M Pd-10-8, M Pd-10-9, M Pd from top to bottom, respectively. 68

88 The optical microscope (OM) pictures of 10-PMOSs with d1_2μm (typical) are shown in Fig after delayer to substrate. (a) (b) (c) (d) (e) (f) Fig The OM pictures of 10-PMOSs with d1_2μm (typical) after delayer to substrate (a) M P-10-1, (b) M P-10-2, (c) M P-10-3, (d) M P-10-4 (e) M P-10-5, and (f) M P

89 (g) (h) (i) (j) Fig The OM pictures of 10-PMOSs with d1_2μm (typical) after delayer to substrate (g) M P-10-7, (h) M P-10-8, (i) M P-10-9, and (j) M P From Fig. 2.39, every PMOS of 10-PMOSs with d1_2μm (typical) can clear to see failure positions after delayer to substrate. It proves the ESD current gets through every stacked parasitic PNP under ESD stress, and every PMOS can turns on uniformity. The optical microscope (OM) pictures of 6-PMOSs with d1_6μm are shown in Fig after delayer to substrate. The optical microscope (OM) pictures of 10-PMOSs with d1_6μm 70

90 are shown in Fig after delayer to substrate. The scanning electron microscope (SEM) pictures of 10-PMOSs with d1_6μm are shown in Fig after delayer to substrate. (a) (b) (c) (d) Fig The OM pictures of 6-PMOSs with d1_6μm after delayer to substrate (a) M Pd-6-1, (b) M Pd-6-1 & M Pd-6-2, (c) M Pd-6-3 & M Pd-6-4, and (d) M Pd-6-5 & M Pd

91 (a) (b) (c) (d) (e) (f) Fig The OM pictures of 10-PMOSs with d1_6μm after delayer to substrate (a) M Pd-10-1 & M Pd-10-2, (b) M Pd-10-3 & M Pd-10-4, (c) M Pd-10-5 & M Pd-10-6, (d) M Pd-10-7 & M Pd-10-8, (e) M Pd-10-9 & M Pd-10-10, and (f) the edge of M Pd

92 (a) Fig The SEM pictures of 10-PMOSs with d1_6μm after delayer to substrate (a) M Pd-10-1, (b) (b) the edge of M Pd

93 From Fig. 2.40, every PMOS of 6-PMOSs with d1_6μm can see failure positions after delayer to substrate. It proves the ESD current also gets through every stacked parasitic PNP under ESD stress, and every PMOS can turns on uniformity. Due to the spacing of d1 become wider, and the parasitic PNPs path become longer. Instead of getting through stacked parasitic PNPs, the ESD current unpredictably gets through the parasitic path from P+ diffusion (drain) to HVNW-ring. From Fig and Fig. 2.42, the ESD failure positions located on the top of 10-PMOSs. For the experiment results, the 9-PMOSs and 10-PMOSs with d1_6μm are not good options. 2.3 Summary Optimization of stacked LV PMOS for high-voltage ESD protection needs to notice layout consideration. From above results, stacked PMOSs with larger d1 have good ESD robustness in 0.5-μm and 0.25-μm. However, 9-PMOSs and 10-PMOSs with larger d1 got lower ESD robustness due to the parasitic path from P+ diffusion (drain) to HVNW-ring damage. From above results, layout optimization for stacked LV PMOSs (1-PMOS to 8-PMOSs) to get higher ESD robustness: d1_6 μm and TW_600 μm. From above results, layout optimization for stacked LV PMOSs (9-PMOS and 10-PMOSs) to get higher ESD robustness: d1_4 μm and TW_600 μm. The holding voltages of stacked LV PMOS with different guard-ring layout have some different. The guard-ring layout on the stacked LV PMOS devices was further investigated in next chapter. 74

94 Chapter 3 Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection PMOS is a non-snapback device, and it is a good choice for latchup-free design. In this chapter, Stacked PMOSs with different guard ring layouts have been investigated in a 0.5-μm HV process for HV applications. The holding voltages of stacked PMOSs with different guard ring layouts have been investigated by TLP systems with different pulse widths and the curve tracer. In addition, stacked PMOSs with different guard ring layouts have been investigated to save layout area in a 0.25-μm BCD process for HV applications. 3.1 Stacked Low-Voltage PMOS with Different Guard Ring Layout in a 0.5-μm HV Process Test Devices The ESD devices should be surrounded by the guard ring in real circuit application. The ESD device without the guard ring can reduce the layout area, but it might cause the latchup issue under the normal circuit operation. Therefore, the on-chip ESD devices were often surrounded by the guard ring to prevent latchup issue in the IC products. In this work, the stacked LV PMOSs with two or three stacking numbers for HV applications were fabricated and verified in the silicon chip. Especially, different guard ring layouts on the stacked PMOSs were investigated to study its impact to ESD protection performance. The transmission line pulse (TLP) and ESD tester are used to verify the stacked 75

95 PMOSs with different guard ring layouts for HV applications. The test structures of stacked PMOSs with different stacking numbers and layout arrangements were fabricated in a 0.5-μm high-voltage process. The stacked LV PMOSs with two and three stacking numbers are investigated in this work, which are designed to meet 20-V and 30-V HV applications. Each LV PMOS in the stacked configuration is drawn with the total channel width of 800μm and a channel length of 0.5μm. There are four types (type A, type B, type C, and type D) of the guard ring layouts to surround the stacked PMOSs, as shown in Fig. 3.1, where 3-PMOSs stacked structure is demonstrated. In type A, the stacked PMOSs were not surrounded by P-ring, which is used as the base line for reference. In type B and type C, the stacked PMOSs were surrounded by one P-ring that is typically connected to cathode. The NWELL spacing between each N-well in the type B (type C) is 4μm (8μm). In type D, each PMOS in the N-well of the 3-PMOSs stacked structure was fully surrounded by the P-ring. The clearance of P-ring to the N-well edge is kept at 2.7μm, which is a layout rule specified by the foundry in the given 0.5-μm process. The cross-sectional view of stacked structure with two LV PMOSs is shown in Fig The cross-sectional view of the stacked PMOSs without surrounded by P-ring is shown in Fig. 3.2(a). The NWELL spacings of the two LV PMOSs are drawn with 4μm and 8μm in Fig. 3.2(b) and Fig. 3.2(c), respectively. The cross-sectional view of the stacked PMOSs with inserted p-ring to surround each LV PMOS is shown in Fig. 3.2(d). The gate of each PMOS is connected to its local high potential point, so each PMOS in the stacked structure is kept in the off state during the normal circuit operation. The P+ diffusion (drain) of the bottom PMOS in the stacked PMOSs is connected to the cathode. The P-ring is connected to the cathode, which is typically biased at ground with the common p-substrate. If the deep N-Well is provided in the process, the P-ring can be isolated to the common substrate. 76

96 (a) (b) (c) (d) Fig. 3.1 The four types of guard-ring layout for 3-PMOSs stacked structure, (a) without p-ring, (b) with one whole p-ring and NWELL spacing of 4μm, (c) with one whole p-ring and NWELL spacing of 8μm, and (d) with inserted p-ring to surround each LV PMOS 77

97 (a) (b) (c) (d) Fig. 3.2 The cross-sectional views of stacked structure with two LV PMOSs drawn with (a) without p-ring, (b) the NWELL spacing of 4μm, (c) the NWELL spacing of 8μm, and (d) with inserted p-ring to surround each LV PMOS. Each LV PMOS has its own separated N-well in the stacked structure 78

98 3.1.2 Experimental Results All test devices of stacked PMOSs had been fabricated in a 0.5-μm HV process. Each PMOS in all stacked structure is drawn with a channel width of 800μm and a channel length of 0.5μm. Every layout type has 2-PMOSs and 3-PMOSs stacked structures. The 100-ns TLP-measured I-V characteristics of two stacked PMOSs with the four types of guard ring layout are shown in Fig Fig. 3.3 The TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts In Fig. 3.3, the holding voltage of 2-PMOSs stacked structure is two times of the holding voltage of single PMOS. The trigger voltage of 2-PMOSs stacked structure is also double of the trigger voltage of single PMOS in TLP measurement. In Fig. 3.3, the trigger voltages of the 2-PMOSs stacked structure with different guard-ring layouts are almost the same, but the holding voltage of type A is smaller than those of other types. Type B is better than type A, because it adds one guard ring to surround itself. The holding voltage of type B still suffers 79

99 latchup risk for 20V application. The holding voltages of type C and type D are better (higher) than that of type A and type B, and they can achieve latchup-free design for 20V application. However, the layout area of type D is smaller than the layout area of type C, as well as the type D has the best I t2 among all guard-ring types. The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table 3.1. The breakdown voltages of type C and type D are almost the same as those of type A and type B in DC measurement. All of 2-PMOSs stacked structure with different guard-ring types can pass 3.5 kv in the human-body-model (HBM) ESD test and 250 V in the machine-model (MM) ESD test. Table 3.1 Summary of 2-PMOSs stacked structure with different guard-ring types The TLP-measured I-V characteristics of three stacked PMOSs with the four types of guard ring layout are shown in Fig As seen in Fig. 3.4, the trigger voltage of 3-PMOSs stacked structure is triple of the trigger voltage of single PMOS. In Fig. 3.4, the trigger 80

100 voltages in different guard-ring types are almost the same, but the holding voltage of type A is still the smallest among the four types of guard ring layout. Type A and type B would suffer latchup risk for 30V high voltage application. The holding voltages of type C and type D are better (higher) than those of type A and type B, which can achieve latchup-free design for 30V application. The total layout area of type D is also smaller than that of type C, as well as the type D has the best I t2 among the four guard-ring types. Fig. 3.4 The TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table 3.2. The breakdown voltages of all guard-ring types almost have the same value. The MM ESD level (300V) of type C and type D are better than that (250V) of type A and type B. Except type A, all layout types of 3-PMOSs stacked structure can pass 3.5 kv in the HBM ESD test. 81

101 Table 3.2 Summary of 3-PMOSs stacked structure with different guard-ring types From above results with 100-ns TLP-measured I t2 and ESD test, the type D among the four types of guard-ring layout is the best choice for the stacked PMOSs structure for HV ESD protection. The TLP-measured I-V characteristics of the stacked 2-PMOSs and 3-PMOSs with the guard-ring layout of type D are compared in Fig As seen in Fig. 3.5, the holding voltage can be linearly increased in the PMOSs stacked structure by adjusting the stacking number. The trigger voltage can also be linearly increased in the PMOSs stacked structure. Moreover, the I t2 of PMOSs stacked structure with different stacking numbers can be kept almost the same. Different stacking numbers on the stacked PMOSs can be adjusted for various HV applications to achieve latchup-free immunity on the ESD protection device. 82

102 Fig. 3.5 The TLP-measured I-V characteristics of the stacked 2-PMOSs and 3-PMOSs with the guard-ring layout of type D 3.2 Different Guard Ring Layout of Stacked Low-Voltage PMOS measured by TLP with different pulse widths in a 0.5-μm HV Process Different TLP Pulse Widths The test devices were all the same in chap3.1. There are four types (type A, type B, type C, and type D) of the guard ring layouts to surround the stacked PMOSs. From above results, the stacked PMOSs with guard-ring layout of type D can achieve both of good ESD robustness and high latchup-free immunity with reasonable total layout area. Furthermore, the test devices measured by 100-ns, 200-ns, 500-ns, 800-ns TLP systems, and curve tracer. In this work, the stacked LV PMOSs with two or three stacking numbers for HV applications were fabricated and verified in the silicon chip. Especially, different TLP pulse widths on the stacked PMOSs were investigated to study its impact to the holding voltages of the stacked PMOSs with different guard ring layouts. 83

103 3.2.2 Experiment Results The 100-ns TLP-measured I-V characteristics of 2-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table 3.3. Fig. 3.6 The 100-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Table 3.3 Summary of 2-PMOSs with different guard-ring types measured by 100-ns TLP 84

104 The 200-ns TLP-measured I-V characteristics of 2-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table 3.4. Fig. 3.7 The 200-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Table 3.4 Summary of 2-PMOSs with different guard-ring types measured by 200-ns TLP 85

105 The 500-ns TLP-measured I-V characteristics of 2-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table 3.5. Fig. 3.8 The 500-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Table 3.5 Summary of 2-PMOSs with different guard-ring types measured by 500-ns TLP 86

106 The 800-ns TLP-measured I-V characteristics of 2-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table 3.6. Fig. 3.9 The 800-ns TLP-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Table 3.6 Summary of 2-PMOSs with different guard-ring types measured by 800-ns TLP 87

107 The different pulse widths TLP-measured I-V characteristics of 2-PMOSs_type A are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 2-PMOSs_type A with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 2-PMOSs_type A with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type A with different TLP pulse widths 88

108 The different pulse widths TLP-measured I-V characteristics of 2-PMOSs_type B are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 2-PMOSs_type B with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 2-PMOSs_type B with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type B with different TLP pulse widths 89

109 The different pulse widths TLP-measured I-V characteristics of 2-PMOSs_type C are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 2-PMOSs_type C with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 2-PMOSs_type C with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type C with different TLP pulse widths 90

110 The different pulse widths TLP-measured I-V characteristics of 2-PMOSs_type D are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 2-PMOSs_type D with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 2-PMOSs_type D with different TLP pulse widths Fig The V h and I t2 of 2-PMOSs_type D with different TLP pulse widths 91

111 The 100-ns TLP-measured I-V characteristics of 3-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table 3.7. Fig The 100-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Table 3.7 Summary of 3-PMOSs with different guard-ring types measured by 100-ns TLP 92

112 The 200-ns TLP-measured I-V characteristics of 3-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table 3.8. Fig The 200-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Table 3.8 Summary of 3-PMOSs with different guard-ring types measured by 200-ns TLP 93

113 The 500-ns TLP-measured I-V characteristics of 3-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table 3.9. Fig The 500-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Table 3.9 Summary of 3-PMOSs with different guard-ring types measured by 500-ns TLP 94

114 The 800-ns TLP-measured I-V characteristics of 3-PMOSs with the four types of guard ring layout are shown in Fig The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table Fig The 800-ns TLP-measured I-V characteristics of 3-PMOSs with different guard-ring layouts Table 3.10 Summary of 3-PMOSs with different guard-ring types measured by 800-ns TLP 95

115 The different pulse widths TLP-measured I-V characteristics of 3-PMOSs_type A are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 3-PMOSs_type A with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 3-PMOSs_type A with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type A with different TLP pulse widths 96

116 The different pulse widths TLP-measured I-V characteristics of 3-PMOSs_type B are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 3-PMOSs_type B with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 3-PMOSs_type B with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type B with different TLP pulse widths 97

117 The different pulse widths TLP-measured I-V characteristics of 3-PMOSs_type C are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 3-PMOSs_type C with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 3-PMOSs_type C with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type C with different TLP pulse widths 98

118 The different pulse widths TLP-measured I-V characteristics of 3-PMOSs_type D are shown in Fig The holding voltages (V h ) and secondary breakdown current (I t2 ) of 3-PMOSs_type D with different TLP pulse widths are shown in Fig Fig The TLP-measured I-V characteristics of 3-PMOSs_type D with different TLP pulse widths Fig The V h and I t2 of 3-PMOSs_type D with different TLP pulse widths 99

119 The Tek370-measured I-V characteristics of 2-PMOSs with the four layout types are shown in Fig The Tek370-measured I-V characteristics of 3-PMOSs with the four layout types are shown in Fig Fig The Tek370-measured I-V characteristics of 2-PMOSs with different guard-ring layouts Fig The Tek370-measured I-V characteristics of 3-PMOSs with different guard-ring layouts 100

120 The Tek370 I-V curve can show snapback and the holding voltage of the device in a dc condition. Due to the self-heating effect, the values of holding voltage measured by Tek370 are not real. Before the real values of holding voltage measured by Tek370, the devices are failed. The detailed characteristics of 2-PMOSs stacked structure with different guard-ring types are listed in Table The detailed characteristics of 3-PMOSs stacked structure with different guard-ring types are listed in Table Table 3.11 Summary of 2-PMOSs with different guard-ring types measured by different TLP pulse width Table 3.12 Summary of 3-PMOSs with different guard-ring types measured by different TLP pulse width 101

121 In chapter 3.1, the holding voltages of the type A for 2-PMOSs and 3-PMOSs are lower than supply voltages (20V and 30V), and the holding voltages of the type B for 2-PMOSs and 3-PMOSs are also lower than supply voltages (20V and 30V). The holding voltages of the type C are almost same as the type D for 2-PMOSs and 3-PMOSs, but the layout areas of the type C are bigger than the type D for 2-PMOSs and 3-PMOSs. Due to the pulse widths of TLP increase, the holding voltages of the type C for 2-PMOSs and 3-PMOSs are lower than that under 100-ns TLP stress. The holding voltages of the type D for 2-PMOSs and 3-PMOSs are almost same under different TLP pulse width stress. In addition, I t2 of all types of stacked PMOS are also lower since the pulse widths of TLP become longer. Stacked PMOSs under 100-ns TLP pulse width get the highest I t2, and stacked PMOSs under 800-ns TLP pulse width are the lowest. From above results with different pulse widths TLP-measured I t2 and ESD test, the type D among the four types of guard-ring layout is the best choice for the stacked PMOSs structure for HV ESD protection. 3.3 Different Guard Ring Layout of Stacked Low-Voltage PMOS measured by TLP in a 0.25-μm BCD Process Test Devices From chapter 3.1 and 3.2, the ESD devices should be surrounded by the guard ring. The test devices were all fabricated in a VIS 0.25-μm BCD process. PMOS devices in this investigation, the clearance from the resist-protection-oxide (RPO) to poly-gate edge, the clearance from the drain contact to poly-gate edge (d1), the drain contact number (co), the channel length (L), the single finger width, and the total width are kept at 0.3μm, 2μm, 2, 0.8μm, 30μm,and 360μm, respectively. Stacking number was from 1 to 10 in this test. There are three types (type A, type B, and type C) of the guard ring layouts to surround 102

122 the stacked PMOSs, as shown in Fig. 3.32, where 3-PMOSs stacked structure is demonstrated. Guard rings are composed by a HV-NWELL ring and a HV-PWELL ring. Fig show the schematic of 3-PMOSs. (a) (b) (c) Fig The three types of guard-ring layout for 3-PMOSs stacked structure, (a) type A (typical), (b) type B, and (c) type C Fig The schematic of 3-PMOSs in BCD process 103

123 The cross-sectional view of stacked structure with two LV PMOSs is shown in Fig The cross-sectional view of type A (typical) is shown in Fig. 3.34(a). The cross-sectional view of type B is shown in Fig. 3.34(b). The cross-sectional view of type C is shown in Fig. 3.34(c). (a) (b) Fig The cross-sectional views of stacked structure with two LV PMOSs drawn (a) type (c) A (typical), (b) type B (12μm), and (c) type C (12μm) 104

124 In type A (typical), the HV-PWELL ring is usually tied to the lowest potential point, and the HV-NWELL ring is tied to relative high potential point. In type B and type C, the HV-NWELL ring is tied to relative high potential point. The spacing between each HV-NWELL ring in the type B is 12μm. The HVNW spacing spites from 12μm to 2μm, and the PWELL under the STI is connected between two HV-NWELL rings. The spacing between each HV-NWELL ring in the type C is 12μm. The HVNW spacing spites from 12μm to 9μm, and the length of the PWELL spites from 4μm to 1μm. The position of the PWELL is under middle of the STI between two HV-NWELL rings. The transmission line pulse (TLP) and ESD tester are used to verify the stacked PMOSs with different guard ring layouts for HV applications Experiment Results The TLP measured I-V characteristics of type A (typical stacked LV PMOSs) are shown in Fig The total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The total trigger voltage of stacked PMOSs is also the multiple of the trigger voltage of single PMOS. The secondary breakdown current (I t2 ) of stacked PMOSs are almost the same in spite of different stacking numbers. The detailed characteristics of type A (typical stacked LV PMOSs) are listed in Table The TLP measured I-V characteristics of type B are shown in Fig The spacing between each HV-NWELL ring is 12μm. The detailed characteristics of type B (12μm) are listed in Table The TLP measured I-V characteristics of type B (10μm) are shown in Fig The detailed characteristics of type B (10μm) are listed in Table The TLP measured I-V characteristics of type B (8μm) are shown in Fig The detailed characteristics of type B (8μm) are listed in Table The TLP measured I-V characteristics of type B (6μm) are shown in Fig The detailed characteristics of type B (6μm) are listed in Table The detailed characteristics of type B (4μm) are listed in Table The 105

125 detailed characteristics of type B (2μm) are listed in Table Fig The TLP-measured I-V characteristics of type A (typical stacked LV PMOSs) Table 3.13 The measurement data of type A (typical stacked LV PMOSs) 106

126 Fig The TLP-measured I-V characteristics of type B (12μm) Table 3.14 The measurement data of type B (12μm) 107

127 Fig The TLP-measured I-V characteristics of type B (10μm) Table 3.15 The measurement data of type B (10μm) 108

128 Fig The TLP-measured I-V characteristics of type B (8μm) Table 3.16 The measurement data of type B (8μm) 109

129 Fig The TLP-measured I-V characteristics of type B (6μm) Table 3.17 The measurement data of type B (6μm) 110

130 Table 3.18 The measurement data of type B (4μm) Table 3.19 The measurement data of type B (2μm) 111

131 The TLP measured I-V characteristics of type C (12μm) are shown in Fig The spacing between each HV-NWELL ring is 12μm. The length of the PWELL is 4μm, and the position of the PWELL is under the middle of the STI between two HV-NWELL rings. The detailed characteristics of type C (12μm) are listed in Table Fig The TLP-measured I-V characteristics of type C (12μm) Table 3.20 The measurement data of type C (12μm) 112

132 The TLP measured I-V characteristics of type C (11μm) are shown in Fig The length of the PWELL is 3μm. The detailed characteristics of type C (11μm) are listed in Table Fig The TLP-measured I-V characteristics of type C (11μm) Table 3.21 The measurement data of type C (11μm) 113

133 The TLP measured I-V characteristics of type C (10μm) are shown in Fig The length of the PWELL is 2μm. The detailed characteristics of type C (10μm) are listed in Table Fig The TLP-measured I-V characteristics of type C (10μm) Table 3.22 The measurement data of type C (10μm) 114

134 The TLP measured I-V characteristics of type C (9μm) are shown in Fig The length of the PWELL is 1μm. The detailed characteristics of type C (9μm) are listed in Table Fig The TLP-measured I-V characteristics of type C (9μm) Table 3.23 The measurement data of type C (9μm) 115

135 From table 3.14, table 3.15, table 3.16, and table 3.17 (type B), the DC breakdown voltages of 7-PMOSs are limited by HV-NWELL/PWELL junction. The numbers of stacked PMOSs are 8, 9, and 10, DC breakdown voltages are also limited by HV-NWELL/PWELL junction. From table 3.18, and table 3.19, the DC breakdown voltages of stacked PMOSs are lower. Due to the spacings of HV-NWELL and another HV-NWELL are too closer, the DC breakdown voltages of stacked PMOSs are not the multiple of the DC breakdown voltage of single PMOS. From table 3.20, table 3.21, table 3.22, and table 3.23 (type C), the DC breakdown voltages of stacked PMOSs are the multiple of the DC breakdown voltage of single PMOS. The total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The total trigger voltage of stacked PMOSs is also the multiple of the trigger voltage of single PMOS. The secondary breakdown current (I t2 ) of stacked PMOSs are almost the same in spite of different stacking numbers Discussion The TLP measured I-V curves of 2-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 2-PMOSs with different types of guard ring layout are listed in Table Table 3.24 also shows area information. Guard rings occupy lots of area. The total area are composed by LV PMOS area and guard ring area. Higher I t2, smaller total area and higher V h are important for the stacking purpose, so combine these parameters into the factor, (I t2 x V h )/A, for evaluating performance. The TLP measured I-V curves of 3-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 3-PMOSs with different types of guard ring layout are listed in Table

136 Fig The TLP-measured I-V characteristics of 2-PMOSs with different types of layout Table 3.24 Area information and comparison of 2-PMOSs 117

137 Fig The TLP-measured I-V characteristics of 3-PMOSs with different types of layout Table 3.25 Area information and comparison of 3-PMOSs 118

138 The TLP measured I-V curves of 4-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 4-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 4-PMOSs with different types of layout Table 3.26 Area information and comparison of 4-PMOSs 119

139 The TLP measured I-V curves of 5-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 5-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 5-PMOSs with different types of layout Table 3.27 Area information and comparison of 5-PMOSs 120

140 The TLP measured I-V curves of 6-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 6-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 6-PMOSs with different types of layout Table 3.28 Area information and comparison of 6-PMOSs 121

141 The TLP measured I-V curves of 7-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 7-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 7-PMOSs with different types of layout Table 3.29 Area information and comparison of 7-PMOSs 122

142 The TLP measured I-V curves of 8-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 8-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 8-PMOSs with different types of layout Table 3.30 Area information and comparison of 8-PMOSs 123

143 The TLP measured I-V curves of 9-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 9-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 9-PMOSs with different types of layout Table 3.31 Area information and comparison of 9-PMOSs 124

144 The TLP measured I-V curves of 10-PMOSs with the three types of guard ring layout are shown in Fig The detailed characteristics of 10-PMOSs with different types of guard ring layout are listed in Table Fig The TLP-measured I-V characteristics of 10-PMOSs with different types of layout Table 3.32 Area information and comparison of 10-PMOSs 125

145 From above tables, the numbers of stacked PMOSs are from two to six, the type B of guard ring layout is good choice for ESD protection. The factor, (I t2 x V h )/A, of the type B gets higher value, and the value of the type A is smallest. The type B performs best in this factor, and is suitable for the number of stacked PMOSs from two to six. However, the numbers of stacked PMOSs are from seven to ten, the DC breakdown voltages of stacked PMOSs are lower than expected supply voltages. The type C performs best in this factor, and is suitable for the number of stacked PMOSs from seven to ten. Table 3.33 shows the type A (typical) for stacked PMOSs can multi-finger uniform turn-on. Table 3.34 shows the type B (12μm) for stacked PMOSs can multi-finger uniform turn-on. Table 3.35 shows the type C (12μm) for stacked PMOSs also can multi-finger uniform turn-on. Table 3.33 Multi-finger uniform turn-on of type A (typical) 126

146 Table 3.34 Multi-finger uniform turn-on of type B (12μm) Table 3.35 Multi-finger uniform turn-on of type C (12μm) From above tables, the factor, (I t2 x V h )/A, of the type A almost gets same value. The type B and the type C also gets similar value, respectively. The stacked PMOSs with different guard ring layout types can turn-on uniformity. It is good for high-voltage ESD protection. 127

147 The holding voltages (V h ) and secondary breakdown current (I t2 ) of stacking number _type A are shown in Fig Fig The V h and I t2 of stacked PMOSs with the type A of guard ring layout The holding voltages (V h ) and secondary breakdown current (I t2 ) of stacking number _type B are shown in Fig Fig The V h and I t2 of stacked PMOSs with the type B of guard ring layout 128

148 The holding voltages (V h ) and secondary breakdown current (I t2 ) of stacking number _type C are shown in Fig Fig The V h and I t2 of stacked PMOSs with the type C of guard ring layout In the three types of different guard ring layout, the total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The secondary breakdown current (I t2 ) of stacked PMOSs are almost the same in spite of different stacking numbers. The type B and type C can reduce the layout area, and they have the same ESD robustness with the type A. For high-voltage ESD protection, the TLP measured I-V curves of 60V ESD devices are shown in Fig V ESD devices include the 60V typical HV PMOS and the type C_PMOS x8_hvnw_12μm. The 60V typical HV PMOS is drawn with the total width of 5000μm and a channel length of 0.45μm. Each LV PMOS in the stacked configuration is drawn with the total width of 360μm and a channel length of 0.8μm. The detailed characteristics of 60V ESD devices are listed in Table

149 Fig The TLP-measured I-V characteristics of 60V ESD devices Table 3.36 Summary of 60V ESD devices For high-voltage ESD protection, the TLP measured I-V curves of 80V ESD devices are shown in Fig V ESD devices include the 80V typical HV PMOS and the type C_PMOS x10_hvnw_12μm. The 80V typical HV PMOS is drawn with the total width of 130

150 5000μm and a channel length of 0.45μm. Each LV PMOS in the stacked configuration is drawn with the total width of 360μm and a channel length of 0.8μm. The detailed characteristics of 80V ESD devices are listed in Table Fig The TLP-measured I-V characteristics of 80V ESD devices Table 3.37 Summary of 80V ESD devices 131

151 The typical HV devices have larger layout area, but they have lower ESD robustness. After the trigger voltages, the typical HV devices are failed. However, stacked PMOSs have high holding voltage and good ESD robustness. The stacked PMOSs are the best choice for HV ESD protection. 3.4 Summary Stacked PMOSs with different guar-ring layouts has been investigated in a 0.5-μm HV process for HV applications. From above results with TLP-measured I t2 and ESD test, the type D among the four types of guard-ring layout is the best choice for the stacked PMOSs structure for HV ESD protection. The stacked PMOSs with guard-ring layout of type D can achieve both of good ESD robustness and high latchup-free immunity with reasonable total layout area. Stacked PMOSs were verified in a VIS 0.25-μm BCD process. From the chapter 3.3, the type B and type C have same ESD robustness with the type A (typical), but they have smaller layout area. By adjusting the stacking numbers of stacked PMOSs, it can provide effectively ESD protection for various HV applications. The stacked configuration of LV PMOSs with optimized guard-ring layout is recommended for on-chip ESD protection design in HV IC products. 132

152 Chapter 4 Conclusions and Future Work 4.1 Conclusions Stacked PMOSs have been verified their good ESD robustness with high holding voltage. The dependence of layout parameters on ESD robustness of stacked LV PMOSs. In this work, the stacked LV PMOS devices have been successfully verified in a VIS 0.5-μm HV process and 0.25-μm 80V BCD process. Stacked LV PMOSs have better ESD robustness in different HV process. Stacked PMOSs with different guar-ring layouts has been investigated in a 0.5-μm HV process for HV applications. From the chapter 3.1 and 3.2, the stacked PMOSs with guard-ring layout of type D can achieve both of good ESD robustness and high latchup-free immunity with reasonable total layout area. By adjusting the stacking numbers of stacked PMOSs, it can provide effectively ESD protection for various HV applications. Stacked PMOSs with different guar-ring layouts has been investigated in a 0.25-μm BCD process for HV applications. The ESD devices should be surrounded by the guard ring in real circuit application. The ESD device can reduce the layout area, and it can achieve same ESD robustness and high latchup-free immunity. 4.2 Future Work New Type Device The cross-sectional view of stacked structure with two LV PMOSs is shown in Fig The new type device have not PWELL under the STI. The DC breakdown voltage is not limited by HVNW/PWELL junction. The spacing between each HV-NWELL ring in the new type is 12μm. The HVNW spacing spites from 12μm to 4μm. 133

153 Fig. 4.1 The cross-sectional views of new type stacked structure with two LV PMOSs drawn Guard Ring in Real Circuit Application In chapter 3.3, the type C of guard ring layout can reduce layout area, and they also have good ESD robustness. In addition, the ESD devices should be surrounded by the P+ guard ring in real circuit application. The ESD device without the P+ guard ring can reduce the layout area, but it might cause the latchup issue under the normal circuit operation. The top view of new structure is shown in Fig The spacing between HV-NWELL ring and P+ guard ring in new type need to spite. Fig. 4.2 The top view of new type stacked structure in real circuit application 134