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1 國立交通大學管理學院 ( 工業工程與管理學程 ) 碩士班碩士論文以 WIP SPC 改善晶圓代工廠生產週期之個案研究 The Study of the Cycle Time Improvement by WIP SPC for IC Foundry Manufacturing 研究生 : 林育成指導教授 : 李榮貴博士中華民國九十六年一月

2 以 WIP SPC 改善晶圓代工廠生產週期之個案研究 The Study of the Cycle Time Improvement by WIP SPC for IC Foundry Manufacturing 研究生 : 林育成指導教授 : 李榮貴博士 Student: Yu-Cheng Lin Advisor: Dr. Rong-Kwei Li 國立交通大學管理學院 ( 工業工程與管理學程 ) 碩士班碩士論文 A Thesis Submitted to Department of Industrial Engineering and Management College of Management National Chiao Tung University In Partial Fulfillment of the Requirements For the Degree of Master of Science In Industrial Engineering and Management Jan Hsinchu, Taiwan, Republic of China 中華民國九十六年一月

3 以 WIP SPC 改善晶圓代工廠生產週期之個案研究學生 : 林育成指導教授 : 李榮貴博士國立交通大學管理學院 ( 工業工程與管理學程 ) 碩士班中文摘要投片到產出的時間稱為生產週期 (Cycle time), 半導體產品從投入到產出通常需一到二個月的時間因為對市場的反應時間很長, 所以生產週期一直是晶圓代工廠影響客戶滿意度的重要指標之一, 不良的生產週期常造成客戶抱怨, 甚至訂單流失 ; 而且半導體工廠的投資額高, 生產週期代表的是資金的堆積所以晶圓代工廠一直都投注大量人力於生產週期的管理與改善一般工廠做生產週期的管理通常只是根據經驗訂定 Turn Rate 及標準在製品量 (STD WIP), 再據以拉貨和消 WIP, 沒有一套較完整的生產週期管理理論當工廠狀況改變, 如產品組合改變或產能使用率改變, 此時根據 Little s law 可以預知生產週期及在製品量將會跟著改變, 過去經驗也跟著不適用目前絕大多數的工廠並無法反應此狀況, 以至於產品組合改變或產能使用率改變都須經過一段爭執的陣痛期, 當情況穩定時, 經驗能派上用場, 管理才又上軌道本論文期望發展出一套計算標準在製品 (STD WIP) 的方式, 再利用 SPC (Statistical Process Control) 的觀念, 訂定 WIP 上下限, 當超出上下限則採取適當的派工以修正 WIP Profile, 如此可以降低 WIP 水位, 生產週期也得以逐步降低關鍵詞 : 晶圓代工生產週期時間達交率派工在製品管理 i

4 The Study of the Cycle Time Improvement by WIP SPC for IC Foundry Manufacturing Student: Yu-Cheng Lin Advisor: Dr. Rong-Kwei Li Department of Master Program of Industrial Engineering and Management National Chiao Tung University ABSTRACT The definition of cycle time is the time from the wafer start to the wafer output. It usually takes one or two months to get the product since customer decides to produce it. Cycle time is a critical factor for customer satisfaction because it represents the response time to the market. Long cycle time also reflects the ineffective investment for the capital. Cycle time is very important for foundry because long cycle time will cause customer unsatisfied and the order loss. Consequently, all of the foundries put lots of human source in the cycle time improvement. Usually, we make decisions based on the experience in cycle time management. We have no mechanism or theory for cycle time management. We do WIP management based on turn rate and standard WIP set by experiences. But the experience didn t mean the optimal solution, when the situation changed, the cycle time or the standard WIP will also be changed. The experience will not always be applicable. If we only have the experience and no mechanism, management will not be work out. After interview several foundry fab managers, all of the fab can t reflect the situation. That is, all of them will have an impact period after product mix or utilization varied. In this study, we want to develop a formula for standard WIP and use SPC concept to set WIP upper/lower limit. When WIP exceed the limit, it will trigger action plans to compensate WIP profile. If WIP profile balances, we don t need too much WIP. So WIP level could be reduced and cycle time also could be reduced. Key words: Foundry, Cycle Time, Delivery, Dispatch, WIP Management ii

5 目錄頁次中文摘要英文摘要 i ii 目錄 iii 表目錄 iv 圖目錄 v 符號說明 vi 一緒論問題描述研究目的研究方法研究範圍與限制二文獻探討投料法則派工法則三個案研究個案現況 Cycle Time 改善方法分析 WIP SPC 方法說明四 WIP SPC 效果驗證生產數據比較分析有效性驗證其他效益五結論及未來研究方向參考文獻 iii

6 表目錄頁次表 3-1: High Utilization Equipment Group 表 3-2: STD WIP and Target T/R 表 3-3: STD WIP 分配及 STD WIP Upper/Lower Limit 表 3-4: 派工法則評分表表 3-5: Utilization FCST 表 4-1: 改善前改善後之生產數據表 4-2: 生產週期之假設檢定 iv

7 圖目錄頁次圖 3-1: STD WIP SPC 概念圖圖 3-2: 派工法則示意圖圖 5-1: 改善前改善後之 WIP 與 cycle time 相關圖圖 5-2: 改善前改善後之 utilization 與 CLIP 相關圖 v

8 符號說明 Theoretical Cycle Time : 一批貨從投片到產出, 所有 Process time 加總 Avail Process Time i Running WIP i Waiting WIP i Group Capacity i X ij TCT ij : 機台可提供生產的時間 (%), 即 1-Down%-PM% : 第 i 個製程步驟所花的生產時間 : 第 i 個機台群組上正在 Run 的 WIP 量 : 第 i 個機台群組前等待進入機台 Run 的 WIP 量 : 第 i 個機台群組可提供的產能 : 第 i 種產品第 j 個區段的 X-Ratio : 第 i 種產品第 j 個區段的 Theoretical Cycle Time vi

9 1.1 DRAM - (cycle time) (STD WIP) (WIP) (STD WIP) 1.2 1

10 1.3 WIP WIP SPC WIP SPC

11 Cycle Time 2.1 Simulation cycle time [Glassey et al.1988a,b; Wein 1988; Miller 1990] (open-loop) (close-loop) (Uniform Loading) : (1) (Fixed WIP;FW) (2) (Constant WIP; CONWIP) JIT (3) Starvation Avoidance(SA) SA Glassey and Resende [Glassey and Resende,1988] WIP B/N (move 3

12 loss) B/N (L) (, >0) WIP SA Unif/Fixed WIP (4) Workload Regulating (WR) Workload Regulating (WR) Wein [Wein,1988] [u1] ( ;W) SA (5) (Drum-Buffer-Rope;DBR) DBR (Drum) (Buffer) (Rope) [ 2003] DBR Drum (Drum) (backwards) drum Rope : : - - : - - : - 4

13 - - : : 2.2 (Dispatching) : (1) (First In First Out; FIFO) (2) (Earliest Due Date; EDD) (3) (Critical Ratio; CR) CR (4) (Minimum Slack Time; MST) ; (5) (Short Remaining Processing Time; SRPT) 5

14 3.1 IC (Generic Logic) (Mixed Mode) (High Voltage) time-to-market Cycle Time (Work in Process, WIP) Move Move (High utilization) cycle time cycle time 6

15 (Capacity Loss) 3.2 Cycle Time Cycle time Cycle time Cycle time (Actual Cycle Time) (Dynamic Cycle Time) : (1).Actual Cycle time (2).Dynamic Cycle time Actual cycle time WIP / Move Cycle time WIP Move Move WIP WIP WIP Move cycle time Move WIP WIP WIP cycle time cycle time : (1). Move WIP (2). WIP Move WIP : (1). Move WIP 7

16 3.3 WIP SPC WIP (setup) (Rework) WIP WIP WIP TOC cycle time TOC Thin Oxide+HTOX ( 90% ) 14 10% 10% 14 WIP 5 1. Cycle time WIP 2. WIP WIP 3. SPC WIP WIP balance 4. WIP 5. line balance loss WIP 1~5 8

17 3-1 High Utilization Equipment Group No Equipment Jul-06 Aug-06 Sep-06 Oct-06 Nov-06 Dec-06 Util. Tools Util. Tools Util. Tools Util. Tools Util. Tools Util. Tools 1 PECVD - SiH % % % % % % Lam4500/4520(SOGEB) 105.2% % % % % % Thin Oxide / HTOX 97.1% % % % % % Oxide CMP (EBARA) 100.0% % % % % % Metal Etcher - Hitachi % % % % % % Metal Etcher - Hitachi % % % % % % Gate Oxide 97.1% % % % % % UTC 91.6% % % % % % Mid Current Implanter 89.9% % % % % % Metal Etcher - W Plug EB 100.0% % % % % % PECVD - SIN 92.6% % % % % % Sputter 88.9% % % % % % PECVD - SiH4&SiON&SiN 99.2% % % % % % SAUSG 85.6% % % % % % PRS 87.1% % % % % % HDPCVD (PS) 92.1% % % % % % TEL 85S 93.1% % % % % % HDPCVD (STI) 88.8% % % % % % High Current Implanter 79.2% % % % % % NS 81.5% % % % % % Asher 82.7% % % % % % TEL DRM 85.8% % % % % % BPSG Flow 79.7% % % % % % Vacuum / SOG Baking 81.5% % % % % % Metal Etcher - DDPSM 81.0% % % % % % RTP - Metal 81.4% % % % % % Oxide CMP (Mirra Mesa) 72.7% % % % % % Laser Mark 74.0% % % % % % PETEOS 68.8% % % % % % SOG Coater 77.2% % % % % % OPRS (EKC) 73.3% % % % % % W CMP 77.8% % % % % % RE 74.7% % % % % % OZ % % % % % % Alloy 74.3% % % % % % WCVD 73.3% % % % % % Wafer Scrubber 72.0% % % % % % WCMP - Buffing 74.8% % % % % % MOCVD 72.5% % % % % % LamTCP9400/Alliancechamber 68.2% % % % % % 14.0 Step 1: WIP Little s Law ( = / ) Cycle time Output WIP Level = Cycle Time * Output 9

18 Step 2: WIP Profile WIP WIP Cycle time WIP? 60,000pcs Stage 120 STD Move = 60,000*120/30 = 240,000 Turn Rate Gate oxide process step Gate oxide furnace turn rate 1.2 Gate oxide furnace STD WIP = STD Move / STD turn = (60,000*1/30)/1.2=1,667pcs gate oxide furnace turn rate standard STD WIP STD WIP STD WIP WIP WIP Running WIP Fab PM PM Run Run WIP Running WIP WIP Waiting WIP PM WIP Loss (1). Running WIP? Running WIP WIP WIP running WIP Process Time (batch type) Furnace run 6 1 WIP Furnace 6 Running WIP 6 Running WIP X-ratio X-ratio 3.8 Running WIP 10

19 WIP 40% r Group i Group run WIP i Run WIP i =Run WIP Level * Process Time i / Theoretical Cycle Time (2). Waiting WIP? Waiting WIP WIP Loss (Utilization ) ( ) STD Waiting WIP = * r n i STD Wait WIP i n n j ( n j ) n* Util Wait WIP Level* C i / j (1 Avail ) * Avail * Max(0, 100%)* Group Capacity n j j= 1 r n n j ( n j ) n* Util ( ( C i ) j (1 Avail ) * Avail * Max(0, 100%)* Group Capacity n j i= 1 j= 1 i STD Running WIP i and STD Waiting WIP i i STD WIP i = STD Running WIP i + STD Waiting WIP i Example: Gate oxide I-line Stepper Gate oxide I-line 2 Gate oxide process time 6 I-line process time WIP5,000 pcs Running WIP 2,000 Waiting WIP3,000 Gate oxide 11 80% avail 88% Group capacity 10,000 pcs I-line Stepper 10 99% avail 92% Group capacity 12,000 pcs Running WIP : Gate oxide Running WIP : 2,000*6/(6+44/60*2)=1,607 I-line Running WIP : 2,000*(44/60*2)/(6+44/60*2)=393 Waiting WIP : 11

20 Gate Oxide (EQP Variability impact) : (C * (1 0.88) * 0.88 = 2.1* 10,000 = 21,000 * (11* 80%/(11 1) 100%) C * (1 0.88) (11 1) * 0.88 (11 11) I- line Stepper (EQP Variability impact) : (C * (1 0.92) * 0.92 = 9.1* 12,000 = 109,200 * (10 * 99%/(10 1) 100%) C * (1 0.92) (10 1) * 0.92 (10 10) * (11* 80%/(11 11) 100%))*10,000 * (10 * 99%/(10 10) 100%))*12,000 Gate Oxide STD Waiting WIP=3,000*21,000/(21, ,200)=484 I-line Stepper STD Waiting WIP=3,000*109,200/(21, ,200)=2,516 STD WIP :Gate Oxide STD WIP = STD Running WIP + STD Waiting WIP = 1, =2,091I-line STD WIP = STD Running WIP + STD Waiting WIP = 393+2,516=2,909 STD WIP STD WIP WIP I-line I-line STD WIP I-line WIP STD WIP Profile, 300~500 (Theory of Constraints, TOC) [Goldratt et al. 1986a,b; Goldratt et al. 1990a,b] Stage KSR(Key Stage Report) Stage Stage stage 100~150 stage DPSN Generic Logic HV stage stage stage 10 sector S1~S10 stage 10 stage 12

21 WIP WIP profile sector sector : WIP WIP Profile i, j Little s Law : WIP = CT * Output i j STD WIP ij = CT ij *Output ij =X-ratio ij * Theoretical CT ij * Output ij, X-ratio ij = (Full Process CT / Theoretical CT ) of Part i STD X-ratio j STD WIP j = n i = 1 Output * X i ij * TCT ij n j= 1 Xij *TCTij = CT Target i Wait Time = WIP/Capacity * Process Time Wait Time / Process Time = X ratio = WIP / Capacity = WIP / (Tool Qty * Batch Size) EX: GateOx 11 set WIP 2000pcs, X-Ratio = 2000/(11*150)= STD WIP and Target T/R Sector STD WIP Target T/R TTL % D P E T Avg. D P E T S1 6,210 8% 4,967 1, S2 13,868 18% 10,529 2,018 1, S3 7,757 10% 4,685 1,212 1, S4 18,987 25% 7,160 4,105 2,650 5, S5 8,968 12% 1,214 2,309 5, S6 8,623 11% 1,217 2,253 5, S7 3,546 5% , S8 2,707 4% , S9 3,756 5% 526 1,195 2, S10 1,571 2% 1, TTL 75, % 27,343 12,659 13,761 22,

22 Step 3: Profile STD WIP Formula 10 (Sector) STD WIP STD WIP WIP (control limit) WIP control limit WIP Upper Limit Target WIP Lo Normal Lower Limit Hi Lo Priority Change S1 S2 S3 S4 S1 S2 S3 S4 WIP Profile Change WIP 3-1 STD WIP SPC S1 S2 S3 S4 3-3 STD WIP STD WIP Upper/Lower Limit Sector STD WIP Target T/R Low Limit Upper Limit TTL % D P E T Avg. D P E T S1 6,210 8% 4,967 1, ,589-10% 6, % S2 13,868 18% 10,529 2,018 1, ,481-10% 15, % S3 7,757 10% 4,685 1,212 1, ,982-10% 8, % S4 18,987 25% 7,160 4,105 2,650 5, ,088-10% 20, % S5 8,968 12% 1,214 2,309 5, ,071-10% 9, % S6 8,623 11% 1,217 2,253 5, ,761-10% 9, % S7 3,546 5% , ,482-30% 4, % S8 2,707 4% , ,895-30% 3, % S9 3,756 5% 526 1,195 2, ,629-30% 4, % S10 1,571 2% 1, ,100-30% 2, % TTL 75, % 27,343 12,659 13,761 22, :DBR FIFO 14

23 3-1 : (1). Set Set S n high priority if S n WIP over upper limit (2). Set S n-1 high priority if WIP of S n below lower limit (3). If S n below lower limit and S n-1 over upper limit, S n-1 High Priority lot double (4). If consecutive sectors (ex:s n &S n+1 ) below lower limit, upside priority forward and quantity of upside priority sectors = below lower limit sectors, Sector S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 Rule Discription WIP N N L H L L N N N N Init. Score See Dispatching Rule Qty Gap ,000 3,000-1,000-2, Qty Gap = Act WIP - STD WIP Gap Accu , ,000-2, Gap Accu. n = Qty Gap n + Gap Accu. n+1 Gap Score +1 If Gap-Accu.<0 & Qty Gap >0 & Init. Score =0, Gap Scroe = +1 Score Score = Init. Score + Gap Score WIP W/S WIP S1 S2 S3 S4 S5 3-2 S1 S2 S3 S4 S5 Note: +1 means 30% WIP upside priority to (2,20), W/S +1 means more wafer start +2 means 60% WIP upside priority to (2,20) S6 S6 Step 4: Murphy Utilization FCST System ( 3-4 ) (FCST) 15

24 B/N Setup Setup Cycle Time Profile (Buffer Management) : ( ) (WIP ) ( ) 3-5 Utilization FCST EQP. Group D01 D02 D03 D04 D05 D06 D07 High Temp 102.6% 72.9% 83.6% 110.2% 136.5% 185.6% 266.3% High Current Implanter 71.5% 68.4% 82.2% 95.0% 102.1% 121.0% 146.9% Mid Current Implanter 92.5% 98.0% 118.4% 145.0% 187.3% 237.9% 308.6% SIN 90.3% 92.8% 76.1% 61.0% 96.2% 129.1% 188.4% NS 108.5% 56.2% 61.3% 100.2% 95.0% 80.6% 74.5% Gate Oxide 87.7% 83.1% 99.3% 85.2% 84.9% 70.3% 85.6% D-POLY 96.7% 68.3% 86.7% 111.1% 103.7% 91.3% 75.7% Thin Oxide 115.9% 91.2% 65.3% 76.3% 86.6% 112.6% 129.1% HTO 65.5% 50.7% 65.5% 77.9% 55.6% 67.0% 69.6% ANNL 79.7% 101.2% 104.3% 110.7% 123.1% 145.4% 175.7% BPSG FLOW + S/D 76.7% 68.6% 57.3% 46.7% 63.3% 59.0% 67.1% ALLOY (AL9) 62.2% 80.0% 95.9% 86.9% 77.8% 83.8% 84.6% ALLOY (Baking + Curing) 70.4% 83.8% 72.5% 95.4% 83.4% 95.7% 94.4% BPSG (DSABP) 87.2% 67.6% 59.6% 46.4% 61.6% 60.8% 61.9% SIH4 99.8% 114.9% 128.9% 148.3% 178.0% 205.7% 235.6% Sputter (non_mocvd,non_ms 87.9% 69.8% 83.3% 83.5% 83.1% 85.9% 90.0% Sputter (MOCVD) 92.7% 77.8% 71.3% 87.2% 74.8% 77.2% 79.5% Sputter (Al - MS) 57.0% 97.3% 68.9% 80.8% 96.3% 74.4% 74.1% WCVD 87.2% 91.6% 86.8% 93.7% 89.6% 94.0% 88.4% 16

25 Step 5: WIP Level Cycle Time WIP 60,000pcs Stage 120 turn rate 3.0 Cycle time 40 STD WIP = 60,000*40/30=80,000 STD WIP WIP WIP 5% STD WIP = 80,000*95%=76,000 Cycle Time Target 76,000/60,000*30=38 STD WIP 17

26 WIP SPC 4.1 WIP STD WIP SPC WIP control limit (action plan) WIP balance loss WIP WIP WIP cycle time Per layer cycle time (days/l) 4-1 (May-06~Jul-06) 1.84 (Aug-06~Oct-06) 1.60 Wafer out per month (pcs) 54,500 61,400 Average WIP (pcs) 79,400 83,175 CLIP (%) 92.5% 98.4% Daily Move 208, ,278 Stepper Utilization 90.2% 97.8% 4.2 WIP cycle time May-06~Jul-06 ( 92 ) ( 1 =1.84, 2 =0.15) Aug-06~Oct-06 (WIP SPC, 2 =1.60, 2 =0.02)? 4-2 (cycle time) May-Jul Aug-Oct = =1.60 ( 2 ) (Z) 7.01 H 0 : 1 <= 2 Z > 1.65 H 1 : 1 > 2 =5% Reject H : WIP (WIP SPC) Cycle time 18

27 95% 4.3 Supervisor STD WIP SPC Supervisor (CLIP; Customer Line Item Performance CVP; Customer Volume Performance) Priority Line balance Move Line balance Supervisor Line balance Supervisor Supervisor STD WIP SPC Supervisor Line balance STD WIP SPC Priority Supervisor 19

28 Move WIP WIP SPC Cycle Time 5-1 (Jul-06~Oct-06) WIP (move) cycle time 1.6 /Layer 300,000 WIP CT Move , , , , , , ,000 50, , , , ,139 74,039 77,020 79,369 84,161 85, May-06 Jun-06 Jul-06 Aug-06 Sep-06 Oct WIP cycle time 120% 100% 80% 60% 40% Output Utilization CLIP 99% 99% 100% 95% 94% 96% 95% 97% 98% 98% 92% 82% 64,038 59,450 61,100 61,028 53,502 48, , ,000 80,000 60,000 40,000 20% 20,000 0% May-06 Jun-06 Jul-06 Aug-06 Sep-06 Oct utilization CLIP 20

29 5-2 (Jul-06~Oct-06) (utilization) CLIP(Customer Line Item Performance) 95% 98% STD WIP 10 stage WIP SPC WIP Profile STD WIP WIP STD WIP (1).Recipe match dispatching (Furnace / CS) (Chemical Station) (Recipe) 2 lot run run lot lot, WIP, STD WIP (2). (Photo) Photo critical layer lot P1 1A-I200 critical Contact 1A-I200 1A-I200 lot run run lot Photo WIP STD WIP STD WIP 21

30 Glassey C.R. and Resende, M.G.C., Closed-loop Job Release Control for VLSI Circuit Manufacturing, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No.1, pp , February Lawton, J.W., Drake, A., Henderson, R., Wein, L.M., Whitney, R., and Zuanich, D., Workload Regulating Wafer Release in a GaAs Fab Facility IEEE Int l Semiconductor Manufacturing Science Symposium, pp , Miller, D.J. Simulation of a semiconductor manufacturing line, Communication of The ACM 33/10, pp , Wein, L.M., Scheduling Semiconductor Wafer Fabrication, IEEE Transactions on Semiconductor Manufacturing, Vol.1, No.3,pp , August

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(Electronic Data Interchange) (Executive Information System) (Economic Order Quantity) (Enterprise Resource Planning) (Flexible Manufacture System) (F (Activity-Based Costing) (Activity-Based Budgeting) (Activity-Base Management) (Advanced Planning and Scheduling) Application Service Provider (Available To Promise) (Bill Of Material) (Business Process