國 立 交 通 大 學

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1 國立交通大學 電子工程學系電子研究所碩士班 碩士論文 具有真空間隙之 T 型閘極低溫多晶矽薄膜電晶體之性能與可靠度之研究 Study on the Performance and Reliability of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps 研究生 : 林偉凱 指導教授 : 鄭晃忠博士 Wei-Kai Lin Dr. Huang-Chung Cheng 中華民國九十七年七月

2 具有真空間隙之 T 型閘極低溫多晶矽薄膜電晶體之性能與可靠度之研究 Study on the Performance and Reliability of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps 研究生 : 林偉凱 指導教授 : 鄭晃忠 Student:Wei-Kai Lin Advisor:Huang-Chung Cheng 國立交通大學 電子工程學系電子研究所 碩士論文 A Thesis Submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical and Computer Engineering National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master of Science in Electronics Engineering July 2008 Hsinchu, Taiwan, Republic of China 中華民國九十七年七月

3 具有真空間隙之 T 型閘極低溫多晶矽薄膜電晶體 之性能與可靠度之研究 研究生 : 林偉凱 指導教授 : 鄭晃忠博士 國立交通大學 電子工程學系電子研究所碩士班 摘要 系統面版 (System on Panel, SOP) 應用為複晶矽薄膜電晶體技術發展的理想目標, 除高性能與高可靠度的要求外, 必須兼具成本考量 傳統之汲極工程雖可降低漏電流與提升可靠度, 卻伴隨著驅動電流的衰減, 已有一些技術提出可以改善這些現象, 然而卻大幅提昇元件製作的成本 在這篇論文裡, 我們將提出一種低製作成本的元件結構, 利用該結構來增進複晶矽薄膜電晶體的電特性與可靠度 首先, 我們藉由模擬分析證實具有真空間隙之 T 型閘極結構能有效舒緩複晶矽薄膜電晶體汲極端的大電場及碰撞游離 (Impact ionization) 的現象, 尤其在具 i

4 較薄的閘極氧化層之元件中, 此一效應越趨明顯 實驗結果顯示具有真空間隙之 T 型閘極複晶矽薄膜電晶體擁有極佳的開關特性比, 由於 T 型閘極複晶矽薄膜電晶體中的偏移區域 (Offset) 有次閘極 (Sub-Gate) 的協助導通, 我們觀察到所提出的新穎結構在大幅度抑制元件漏電流的同時仍維持驅動電流的大小 此外具真空間隙之 T 型閘極結構亦成功改善因汲極端大電場所造成的扭結效應 (Kink effect) 接著, 藉由電特性的對稱性分析, 我們證實所提出的 T 型閘極製作方式為自我對準 (Self-aligned) 製程 另外, 我們也觀察到所提出的新穎結構能降低汲極端的垂直電場進而增加閘極電壓的操作範圍 最後, 我們也研究具有真空間隙之 T 型閘極複晶矽薄膜電晶體在熱載子應力測試下的可靠度 利用典型的熱載子劣化分析, 證實所提出的新穎結構在可靠度測試後的劣化程度較傳統元件的輕微很多, 這也驗證了所提出的元件確實具有可實際應用的價值 ii

5 Study on the Performance and Reliability of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps Student: Wei-Kai Lin Advisor: Dr. Huang-Chung Cheng Department of Electronics Engineering & Institute of Electronics National Chiao Tung University ABSTRACT System on panel (SOP) is the admirable goal of polycrystalline silicon (poly-si) thin film transistors (TFTs) applications. For such applications, poly-si TFTs must have high performance and high reliability with low production cost. Conventional structure of drain engineering can reduce the leakage current and improve the reliability. Nevertheless, the driving capability is also decayed at the same time. In previous works, some techniques were proposed to modify the predicament; however the fabrication cost is remarkably increased due to their additional lithography step or complex process. In this thesis, a novel drain-field-relief structure with a simple fabrication process was introduced to improve the performance and reliability of poly-si TFTs. In the beginning, device simulation was carried out to verify the effects of iii

6 vacuum gap on the electric field near the drain junction. The electric field and impact ionization rate were significantly suppressed in those T-Gate TFTs, especially with thinner gate insulator. Experimental results revealed that T-Gate TFTs had excellent on/off current ratio exceeding Due to the sub-gate coupling to the offset region, it was observed that the leakage current is dramatically suppressed while as the magnitude of driving current almost keeps the same level as that for the conventional one. Furthermore, kink effect was also reduced by T-Gate structure. By the symmetry analysis of electrical characteristics, the self-alignment property of T-shaped-gate formation was verified. Besides, the improvement of oxide breakdown characteristics was observed to enlarge the operation range of gate bias. Finally, we also examine the reliability of the proposed devices with typical hot carrier stress. The conventional devices exhibit serious degradation such as decayed transconductance, worse drain induced barrier lowering (DIBL), and larger threshold voltage shift. The proposed devices, have much superior immunity to the hot carrier degradation as compared with the conventional ones under the same stress condition. As a consequence, the proposed T-Gate TFTs have not only low-cost fabrication process but also excellent performance and better reliability. iv

7 誌 謝 謹以此論文, 獻給我的父母林建裕先生與藍婉女士以及家人們 感謝爸媽從小以來的教育養成, 更謝謝你們無私的犧牲與支持, 同時也給我極大的空間與信任, 讓我自由發展, 在我無助的時候給予最大的支持, 讓我能夠勇於接受下一次的挑戰 感謝我的論文指導教授鄭晃忠博士, 老師在研究上的熱心指導以及謙恭溫和的處世態度, 讓我獲益良多 感謝戴亞翔教授, 以及中華映管股份有限公司, 讓我有機會參與交映計畫, 學生藉由執行計畫的過程, 學習到許多知識 感謝這兩年帶著我成長學長們 特別感謝廖大傳學長的細心指導, 辛苦你了, 你細心的從基本的機台操作跟製程經驗教起, 到實驗的理論分析, 讓我得以順利邁向畢業之路 感謝賴立軒學長在實驗上的支持, 在工作忙碌之餘抽空指導, 由於你的鼎力協助, 這份論文才得以完成 感謝實驗室的張國瑞學長 林高照學長 蔡春乾學長 李逸哲學長 張加聰學長 楊柏宇學長 賴瑞霖學長 陳柏廷學長在知識上的傳承 ; 也感謝韋凱方學長 王祐圻學長 陳俠威學長 張佩琪學姐的相伴, 少了學長姐的架子, 多的是朋友的熱絡, 讓我在實驗室裡過的很快樂 ; 感謝實驗室同學林君翰 李建穎 涂仕煒 李序恆 許育瑛 劉政欽與實驗室的學妹弟們, 無論是作實驗時的陪伴 私底下的玩樂都相當愉快, 由於你們在生活上的陪伴和打氣, 讓我這一路走來更加的輕鬆快樂 感謝國立交通大學奈米中心及國家奈米元件實驗室及其所有工程師和技術員提供優良的設備與研究環境, 在此由衷的感謝 最後感謝所有曾經幫助過我的朋友們, 謝謝你們 v

8 Contents Abstract (in Chinese).i Abstract (in English). iii Acknowledgements (in Chinese) v Contents...vi Table Lists...viii Figure Captions..x ============================================================= Chapter 1 Introduction Overview of Low-Temperature Polycrystalline Silicon Thin-Film Transistors (LTPS TFTs) Key Processes in the Fabrication of LTPS TFTs Crystallization of Amorphous Silicon Thin Films Defect Passivation Electrical Characteristics of Poly-Si TFTs Reliability Issues of LTPS TFTs Drain Engineering Motivation Thesis Organization 13 Chapter 2 Characterization of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps Introduction Introduction to T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin-Film Transistors (T-Gate LTPS TFTs) with Vacuum Gaps 15 vi

9 2.1.2 Introduction to Excimer Laser Crystallization (ELC) Technique Simulation Analyses of T-Gate LTPS TFTs with Vacuum Gaps Fabrication of T-Gate LTPS TFTs with Vacuum Gaps Fabrication Sequence of T-Gate LTPS TFTs with Vacuum Gaps Material Analyses of ELC Poly-Si Thin Films Electrical Characterization of T-Gate LTPS TFTs with Vacuum Gaps Basic Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps Series Resistance Analyses of T-Gate LTPS TFTs with Vacuum Gaps Symmetry of Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps Oxide Breakdown Characteristics of T-Gate LTPS TFTs with Vacuum Gaps Summary 29 Chapter 3 Reliability Analyses of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps Introduction Effects of Drain Avalanche Hot Carrier (DAHC) Stress on T-Gate LTPS TFTs with Vacuum Gaps Summary...35 Chapter 4 Conclusions References...82 Vita...94 vii

10 Table Lists Chapter 1 Table 1-1 The performances and the related processes of LTPS TFTs for the SOP roadmap are going on in the future.. 39 Chapter 2 Table 2-1 Electrical characteristics of T-Gate and conventional TFTs with gate oxide of 400 Å, channel width of 10 μm and gate length of 5 μm 40 Table 2-2 Maximum leakage and on-state current of T-Gate and conventional TFTs (fixed channel width of 10 μm and gate length of 5 μm) with different gate oxide thicknesses...40 Table 2-3 Electrical characteristics of T-Gate TFTs before and after NH 3 passivaiotn for 1HR..41 Table 2-4 Average and standard deviation of 30 measured I samples of T-Gate TFTs. The thickness of gate oxide is 400 Å. The vacuum gaps height is 1000 Å.41 Chapter 3 Table 3-1 Table 3-2 Parameter variation and corresponding possible degradation mechanisms.42 Electrical parameters of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds...42 Table 3-3 Electrical parameters of the conventional TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds..43 viii

11 Table 3-4 Electrical-parameter shift of the T-Gate and conventional TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds.43 Table 3-5 Electrical parameters of the T-Gate TFTs without plasma passivation before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds...44 ix

12 Figure Captions Chapter 1 Fig. 1-1 Fig. 1-2 Fig. 1-3 The offset TFTs structure proposed by Jung-In Han et al 45 The LDD TFTs structure proposed by Shunji Seki et al..45 The FID TFTs structure proposed by Joon-Ha Park et al 46 Fig. 1-4 The GOLDD TFTs structure proposed by Mutsuko Hatano et al 46 Fig. 1-5 The Air-Gap TFTs structure proposed by Min-Cheol Lee et al...47 Chapter 2 Fig. 2-1 (a) The device structure of proposed T-Gate LTPS TFTs with vacuum gaps (b) The schematic illustration of the equivalent device structure of the proposed T-Gate LTPS TFTs with vacuum gaps 47 Fig. 2-2 The schematic illustration of the low energy regime corresponding to energy densities that (a) partially melting the a-si thin film (b) completely melting the a-si thin film (c) nearly completely melting the a-si thin film 48 Fig. 2-3 The two-dimensional electrical potential distributions of (a) the conventional TFTs. (b) T-Gate TFTs, respectively...49 Fig. 2-4 (a) The lateral electric fields and (b) the vertical electric fields along channel layer of both conventional and proposed T-Gate TFTs 50 Fig. 2-5 The lateral electric fields of (a) conventional and (b) T-gate TFTs with varied x

13 channel lengths 51 Fig. 2-6 The impact ionization coefficients of (a) conventional and (b) T-gate TFTs with varied channel lengths.52 Fig. 2-7 The lateral electric fields of (a) conventional and (b) T-gate TFTs with varied oxide thicknesses.53 Fig. 2-8 The impact ionization coefficients of (a) conventional and (b) T-gate TFTs with varies oxide thicknesses..54 Fig. 2-9 The fabrication process of T-Gate LTPS TFTs.55 Fig The SEM image of the in-situ vacuum gaps under the T-shape gate structure..59 Fig SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density is (a) 225 mj/cm 2 and 98% overlapping, (b) 257 mj/cm 2 and 98% overlapping, (c) 263 mj/cm 2 and 98%overlapping, and (d) 257 mj/cm 2 and 99% overlapping 60 Fig The SEM graphs of the grain size corresponding to laser-energy densities and overlapping in SLG region..62 Fig Cross-section SEM graphs and embedded TEM image of excimer laser crystallized polycrystalline silicon..62 Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å...63 Fig Output characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å...63 Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å...64 Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 800 Å...64 Fig The schematic illustration of the equivalent structure of T-Gate TFTs compared to xi

14 conventional TFTs in which the thickness of gate oxide is 400 Å...65 Fig The schematic illustration of the equivalent structure of T-Gate TFTs compared to conventional TFTs in which the thickness of gate oxide is 800 Å 66 Fig Turn-On resistance as a function of channel length at different gate voltages for conventional TFTs.67 Fig Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 500 Å..67 Fig Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å 68 Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with and without NH 3 plasma passivation 68 Fig The schematic definition of the forward- and reverse-mode measurements.69 Fig Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs before NH 3 plasma passivation 69 Fig The schematic definition of the forward and reverse modes.70 Fig The statistical bar chart of the drain current difference ( I) between forwardand reverse-modes for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å and the L subgate is 2500 Å without plasma passivation..70 Fig Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs with NH 3 1-HR plasma passivation..71 Fig The statistical bar chart of the drain current difference ( I) between forward and reverse modes for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å and the L subgate is 2500 Å with 1-HR NH 3 plasma passivation.71 Fig Gate oxide breakdown fields of T-Gate and conventional TFTs 72 Fig Simulated electric fields in the gate oxide of T-Gate and conventional TFTs xii

15 Chapter 3 Fig. 3-1 Transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds...73 Fig. 3-2 Transfer characteristics of the conventional TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds.73 Fig. 3-3 Threshold voltage shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds...74 Fig. 3-4 Transconductance shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds...74 Fig. 3-5 DIBL shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds.75 Fig. 3-6 Potential barrier for carrier transport raised by filled negative trap states (or charges) in poly-si channel near drain..75 Fig. 3-7 Schematic diagram of traps in drain depletion region and the corresponding energy band diagram of Off-stated poly-si TFT.76 Fig. 3-8 Comparison of electric fields in the interface of gate oxide and poly-si near drain between before and after creation of positive oxide charges..76 Fig. 3-9 Schematic illustration of localized positive oxide charges trapped near drain region after drain avalanche hot carrier stress 77 Fig Reverse-mode measured transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds 77 Fig Transfer characteristics measured at V D =3V of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 xiii

16 seconds 78 Fig Transfer characteristics measured at V D =3V of the T-Gate TFTs before and after oxide electron trap stress at V D = 0 V and V G = 20 V from 0 to 1000 seconds...78 Fig Leakage current variation measured at V D =3V of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds 79 Fig Leakage current variation measured at V D =3V of the T-Gate TFTs before and after oxide electron trap stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds 79 Fig Transfer characteristics of the T-Gate TFTs without plasma passivation before and after hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds.80 Fig Transconductance shift of T-Gate TFTs with and without plasma passivation after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds 80 Fig DIBL shift of T-Gate TFTs with and without plasma passivation after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds 81 xiv

17 Chapter 1 Introduction An Overview of Low Temperature Poly-Si (LTPS) TFTs Thin-film transistors (TFTs) have become crucial devices of modern active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) applications [1.1]-[1.5]. Generally, amorphous silicon (a-si:h) TFTs are the pixel switching elements in AMLCD industry. Amorphous silicon TFTs exhibit low leakage current because of their high off-state resistivity. In addition, they are compatible with large glass substrate for low temperature process. However, the electrical characteristics of a-si TFTs such as carrier mobility (typically below 1 cm 2 /V-s) are inadequate for peripheral circuits. That is, additional integrated circuits (ICs) are needed to support the function of gate drivers and source drivers to drive a display panel. This will lead to high cost and poor reliability. On the other hand, low-temperature polycrystalline silicon (LTPS) TFTs possesses superior carrier mobility [1.6], greater device reliability, CMOS process capability [1.7], and low temperature process compatibility. Therefore, LTPS TFTs have been investigated to achieve the goal of integrating peripheral circuit in a single panel, which is known as system on panel (SOP) [1.8]. Furthermore, LTPS TFTS have the potential to fulfill the 3-dimentional integrated circuits [1.9]. Table 1-1 shows the SOP technique roadmap where LTPS TFTs performance and related process are going on in the feature. [1.10]. 1

18 1.2 Key Processes in the Fabrication of LTPS TFTs Crystallization of Amorphous Silicon (A-Si) Thin Films The crystallized poly-si thin films always serve as active layer or channel in the poly-si TFTs. As a result, the quality of crystallized poly-si thin films profoundly affects the performance of poly-si TFTs. The defect density is generally a gauge for assessing the quality of poly-si. Reducing defect density in polycrystalline material will make it approach the quality of single-crystalline material, which will lead to better performance of polycrystalline device. In the last two decades, various technologies have been proposed for a-si crystallization on foreign material. They are always classified into two groups: solid phase crystallization and liquid phase crystallization. In solid phase crystallization, thermal annealing provides the energy required for grain nucleation and growth. In general, intrinsic solid phase crystallization (SPC) needs a long duration to fully crystallize a-si at low temperature. For amorphous silicon thin films deposited at temperatures below 600 C, thermal crystallization for several hours (~ 20 h) at 600 C is required to convert them into final polycrystalline form. The grains resulting from this process are generally elliptical in shape due to preferential growth in the <112> direction [1.30], and dendritic due to the formation of twin along (111) boundaries. However, due to the low temperature used, long crystallization durations of several hours are necessary, and large defect density exists in crystallized poly-si. It is well known that SPC temperatures of a-si can be lowered by the addition of certain metals [1.11]-[1.20]. When a certain metal, for example, Al [1.11], Cu [1.12], 2

19 Au [1.13], Ag [1.14], Pd [1.15], or Ni [1.16], is deposited on a-si, the a-si crystallizes to poly-si at a lower temperature than its SPC temperature. Generally, such behavior is called metal induced crystallization (MIC). The reaction between a metal and a-si occurs at an interlayer by diffusion and it lowers the crystallization temperature [1.11]-[1.16]. Such enhancement of crystallization is due to an interaction of the free electrons from the metal with covalent Si bonds near the growing interface [1.17]. Considering the metal-si eutectic temperature, an a-si thin film can be crystallized at below 500 C. Among various metals, Ni has been shown to be the best candidate of inducing lateral crystallization at low temperature for fabricating good-performance poly-si TFTs. A large amount of reports have demonstrated that good-performance LTPS TFTs can be fabricated using Ni metal induced lateral crystallization (Ni-MILC) [1.21]-[1.26]. However, in spite of low crystallization temperature, metal contamination is a serious problem in metal-induced crystallized poly-si. A presently widely used method to prepare poly-si on foreign substrates is laser crystallization. Laser crystallization is a much faster process than SPC and MIC and can produce large grained poly-si with a low dislocation density. The basic principle of laser crystallization is the transformation from amorphous to crystalline silicon by melting the silicon for a very short time. Poly-Si with large grains results from the subsequent solidification [1.27]. Strictly speaking, laser crystallization is not a low temperature process as the silicon is heated well above 1200 C. However, the high temperatures are only sustained for a very short time. Due to the short time scale the thermal strain on the low-temperature substrates does not lead to severe damage or destruction of these substrates. Laser crystallization of amorphous silicon has been a subject of intense research for a considerable time. Laser crystallization of a-si can be performed using a variety of lasers and different techniques [1.28]-[1.31]. However, excimer laser 3

20 crystallization (ELC) is by far the most widely used method at the moment [1.32], [1.33]. The principal advantage of excimer lasers is the strong absorption of UV light in silicon. In consequence, most of the laser energy is deposited close to the surface of the thin film and the thermal strain on the substrate is much lower than in case of lasers with longer wavelength. The basic transformation processes for excimer laser crystallization are divided into three crystallization regimes depending on the applied laser fluences and are relatively well understood [1.34], [1.35]. During ELC process, a-si thin films absorb the light, then melt and recrystallize in a short period of time, forming poly-si grain (~1μm). For the volume expansion from liquid to solid phase, surface roughness (usually called protrusion) occurs after the ELC process Defect Passivation The electrical behavior of a poly-si TFT is dominated by the effects of defect states within the poly-si thin film. The high density of defect states result in poor device performance, such as low field-effect mobility, large leakage current, large threshold voltage, and large subthreshold swing. The incorporation of hydrogen into the channel layer (also called hydrogenation) to passivate the defect states is effective and essential for attaining good device performance and also for improving the uniformity of device performance. Because significant hydrogen diffusion occurs at temperatures above 350 o C, the defects passivation process must be performed after all the high-temperature-processing steps in the poly-si TFT fabrication processes, consequently, the channel poly-si thin film may be covered by one or more layers which can significantly impede the defect passivation process. There are four methods that have been used to date to introduce hydrogen into 4

21 channel poly-si thin film including furnace annealing, radio-frequency (RF) plasma [1.36], [1.37] solid-source diffusion [1.38], and H + ion implantation [1.39]. Simple annealing in H 2 ambient is not sufficient for poly-si TFTs due to poor diffusivity of molecular hydrogen in silicon. RF plasma exposure in a parallel-plate reactor is widely used as it has resulted in excellent TFT performance. However, very long process times are usually required for the passivating species to diffuse into the channel poly-si thin film [1.37], so that the throughput of this method is unacceptably low. However, with the use of a low-temperature (< 300 o C) source/drain formation process (e.g. employing ion-shower doping), it is possible to perform the hydrogenation step prior to the deposition of gate dielectric and gate electrode layers, so that the throughput issue for this step can be eliminated. On the other hand, it has been reported that TFTs exposed to hydrogen plasma suffer from poor hot carrier endurance and a low thermal stability due to the weak Si-H bond [1.40]. NH 3 and N 2 have also been proposed instead of H 2. Better hot carrier endurance has been shown as the Si-N bond is stronger than Si-H bond [1.40], [1.41]. Alternative approach, which generates high-density plasma, such as ECR and TCP, may result in equivalent performance with high throughput [1.42]. Solid-source diffusion refers to the process of depositing a SiN x passivation layer with extremely high concentrations of hydrogen. Rather than requiring a separate hydrogen or nitrogen plasma deposition step to repair the dangling bonds, a high hydrogen concentration passivation layer is deposited by PECVD followed by a short thermal anneal at 450 o C. This process may result in good TFT performance and uniformity while improving factory throughput and minimizing additional tool costs. It is perhaps the lowest cost hydrogenation approach. The hydrogen can also be introduced into channel poly-si thin film via ion implantation. The high-energy hydrogen implantation is substituted for H 2 plasma 5

22 step. However, expensive equipment and relative high doses (> cm -2 ) are required. In addition, it requires an additional annealing step at 250 ~ 400 o C as long as 1 hour to anneal out the damage. 1.3 Electrical Characteristics of Poly-Si TFTs In comparison with single-crystalline silicon (c-si), poly-si is rich in grain boundary defects as well as intra-grain defects, and the electrical activity of these charge-trapping centers profoundly affects the electrical characteristics of poly-si TFTs. The turn-on characteristics, such as threshold voltage, substhreshold swing, and field-effect mobility of poly-si TFTs are much inferior to those of c-si counterparts due to the fullness of defect states in the device active region. Devices whose channels have more defects simply require larger gate voltage in order to fill the greater number of traps before the device can turn on. Carrier mobility is degraded by scattering with charge-trapping centers and surmounting the potential barrier height which is built by charged traps [1.43]. An anomalous high leakage current is also found in poly-si TFTs, and the dominant leakage current mechanism is the field emission via the traps by high electric field near the drain junction [1.44]-[1.46]. In addition to reducing the defect density, another approach to reduce the anomalous high leakage current is to adopt drain-field-relief structures, such as LDD and offset gate structure. The floating-body architecture and charge trapping by defect states result in serious avalanche induced effects in poly-si TFTs [1.47]. Due to impact ionization occurring in the high electric field region at the drain end of the channel, holes are injected into the floating body forcing further electron injection from the source, and 6

23 then collected by the drain. This added drain current augments impact ionization which, in turn, forward biases the floating body harder, thereby causing a regenerative action which leads to a premature breakdown. As a result, the output characteristics exhibit an anomalous current increase in the saturation regime, and such a phenomenon is often called kink effect [1.48]. The avalanche induced effects become more severe as the TFT size is reduced due to the enhancement of impact ionization caused by increasing the electric field. Therefore, more severe short channel effects are shown in poly-si TFTs compared to the c-si counterparts, including significant threshold voltage shifts and degradation in drain breakdown voltage as the gate length decreases [1.49], [1.50]. Since the high electric field region at the drain end of the channel place a profound influence on electrical characteristics of poly-si TFTs, the important work to improve the performance of poly-si TFTs is to reduce the undesired effects, which result from the high drain electric field by modifying the architecture of poly-si TFTs. The other effective approach is to reduce defect traps by promoting the quality of poly-si thin films. 1.4 Reliability Issues of LTPS TFTs The stability of device characteristics under long-term operation is indispensable for circuit applications. As a result, the reliability of LTPS TFTs must be taken into consideration when they are applied to advanced circuitry such as data-driver in AMLCDs or driving elements in AMOLEDs. The unique processes used in the fabrication of LTPS TFTs and the nature of crystallized poly-si make the reliability issues in LTPS TFTs different from those in the conventional MOSFETs. 7

24 A major problem in gate dielectric thin films is local breakdown due to the poor interface with the rough silicon surface after excimer laser annealing (ELA).So that the gate dielectric thin films have been deposited thicker than necessary to overcome the surface roughness, which reduces TFT driving capability. The gate oxide used in LTPS TFTs is generally deposited at low temperature by CVD methods. Consequently, it always exhibits poorer physical and electrical quality, such as low density, high gate leakage current, and low breakdown field as compared to high-temperature thermal grown oxide used in MOSFETs. In addition, the mobile ions, Si-H and/or Si-OH bonds, and fixed charges existing in low-temperature deposited gate oxide are also the potential causes of instability of LTPS TFTs [1.52]-[1.56]. Crystallized poly-si is generally full of weak strain Si-Si bonds and dangling bonds. Besides, the hydrogenation process also creates a large amount of weak Si-H bonds in poly-si. These weak bonds can easily be broken during device operation, which will result in the variation of device characteristics [1.57], [1.58]. The glass is a kind of poor thermal-conducting substrate. Heat generated during device operation can be thus hardly released. Hence, the device temperature can rise to a degree which makes bonds breaking, or even burns out the device. Such a phenomenon is called self-heating. The degradation rate caused by self-heating depends on the operation power and the capability of heat dissipation of the device. In general, wide-channel TFTs and/or small-dimension TFTs suffer from serious self-heating [1.59]-[1.62]. The surface roughness of poly-si resulted from laser crystallization will enhance the local electric field near the interface between gate oxide and channel poly-si, which will also degrade the reliability of TFT under high gate bias operation. The hot carrier effects originated from high electric field near the drain junction have been widely investigated in MOSFETs. Meanwhile, it is also another important 8

25 reliability issue in LTPS TFTs. Conduction carriers can obtain energy from the high electric field and become hot. And then, these high-energy carriers can easily break weak bonds existed in poly-si, which creates lots of defect states and oxide charges. Serious degradation can be generated in the hot carrier operation mode, and the degree of degradation depends on the strength of electric field, that is,the energy of the hot carriers. Generally, in order to reduce the hot carrier degradation, electric-field-relief TFT structures, such as LDD, offset drain, and gate-overlapped LDD are introduced. 1.5 Drain Engineering Polycrystalline silicon (poly-si) thin-film transistors (TFTs) are currently investigated for applications in active matrices liquid crystal displays (AMLCDs). The possibility to integrate on the same substrate driving circuit as well as switching devices seems to represent a major advantage of the poly-si technology over the amorphous silicon one. For switching devices applications, the off-state leakage current of TFTs is the major concern. Although the field effect mobility of poly-si TFTs is much higher than that of amorphous TFTs, the higher anomalous off-state leakage currents in poly-si TFTs are also found. The leakage currents can be reduced by either decreasing the trap state density or reducing the high electric field near the drain junction. For the driving circuit applications, the hot carriers phenomena are likely to occur in poly-si TFTs, where supply voltages can be relatively high in the range V [1.63]. As well known in crystalline Si (c-si) MOSFET s, hot carrier phenomena are strongly depended upon the maximum electric field near the drain junction [1.64]. It is worth pointing out that in poly-si TFTs, due to the high density 9

26 of trap states localized at the grain boundaries, it is possible to achieve high electric fields, even at moderate biases. Moreover, poly-si TFTs also suffer from floating body effect due to impact ionization occurring in the high electric field region at the drain end of the channel. This effect results in an increase of the output conductance, and it is responsible for degradation of the device characteristics both in digital and in analog applications such as noise margins and available voltage gain loss [1.65]. All these undesirable effects, including off-state leakage currents, hot carriers reliability, kink effect are all related to the high electric field near the drain junction. For the further development, high versatile circuits and systems need to be fully integrated on the display panel substrate, which is the concept of system-on-panel (SOP). As performance and complexity requirements increase, there is a need to scale down device geometries to achieve higher speeds and packing densities. Unfortunately, those undesirable effects in the electrical characteristics that mentioned above become particularly important as the channel length and gate insulator thickness are reduced. Those all are increased with the higher drain electric field near the drain junction. These undesirable effects prohibit the use of LTPS TFTs in many high-performance circuit applications. Therefore, the drain-field-relief structure plays an essential role for the future prospection. Device structures which can reduce the electric field near the drain junction can be adopted to reduce the leakage current of poly-si TFTs. Lightly doped drain (LDD) and offset gate are commonly used structures for reducing leakage current. Besides, an additional advantage of such structures is enhancing the hot carrier endurance by the electric field relief. The typical offect and LDD structure are shown in Figs.1-1 and 1-2, respectively. However, although the high resistivity of LDD and offset regions can effectively reduce the leakage current, unfortunately, the driving capability of TFTs is also degraded thereby. The resistivity of LDD regions depends 10

27 on the length of LDD and the dose in LDD. In order to reduce leakage current without degrading driving current significantly and to get a maximum on/off current ratio, the length and dose of LDD should be carefully determined. As well as LDD structure, the length of offset region of offset gate structure should be carefully determine to keep the driving capability. Recently, advanced field-relief-structure such as field induced drain (FID) [1.66], [1.67] and gate-overlapped LDD (GOLDD) structure has been adopted to suppress the high drain field effects for improving device reliability and reducing leakage current while a high on-state current remains. The FID and GOLDD structure are shown in Figs.1-3 and 1-4, respectively. In FID structures, the offset region is coupled by a sub-gate. The sub-gate is biased to induce inversion carriers in the offset region when the TFTs operate in the on state, so that the inversion carriers contribute to a lower resistivity in on state. In GOLDD structures, the LDD region is overlapped under gate edge. As well as FID structures, the surface of LDD region is inverted to a lower resistivity current path when the TFTs operate in the on state. A high on/off ratio can be achieved by such those advanced application because reducing leakage current while a high on-state current remains. However, the formation of FID or GOLDD structure generally requires an additional lithography step or complex fabrication process. Besides increasing fabrication cost, the misalignment in layer registration can result in asymmetrical characteristics of TFT and poor uniformity of TFT performance, especially for large-area glass substrates. Many other structures have been proposed to enhance TFT performance, such as the active poly-si gate [1.68], [1.69], the multi-gate structure [1.70], the elevated channel structure [1.71], and the four-terminal TFT structure [1.72] etcetera. Most of 11

28 the newly developed structures can effectively improve the characteristics of conventional TFTs, especially in decreasing the anomalous leakage current in the off-state of poly-si TFTs. In general, the reliability of poly-si TFTs can also be enhanced by utilizing these structures because of the reduction of electric field near the drain junction. 1.6 Motivation In order to realize the concept of system-on-panel (SOP), there is a need to scale down device geometry to achieve better operation speed and higher packing densities. For these applications, poly-si TFTs must possess high performance and reliability while low-cost production is also required to maintain. In previous studies, an offset or lightly doped drain (LDD) structures have been widely used to reduce the leakage current and enhance device reliability by suppressing the electric field near the drain junction. However, it might degrade the device driving capability due to the large series resistance existing in the offset or LDD regions [1-46]. Recently, field induced drain (FID) and gate-overlapped LDD (GOLDD) structures have been adopted to suppress the high drain field effects for improving device reliability and reducing leakage current while a high on-state current is remained. Many processes have also been proposed to produce the gate-overlapped LDD and field induced drain poly-si TFTs [1-66]-[1-67], including nonself-aligned and self-aligned processes. However additional complicated processes or lithography steps must be performed, which result in increasing the fabrication cost. Min-Cheol Lee et al. proposed a FID device structure with a low-cost fabrication process [1-73]. A side etching process was applied to the gate insulator after gate 12

29 electrode was defined to form the air cavities in the gate edge. However, in their device structure, field-relief efficiency is proportional to the air cavity height controlled by the thickness of the gate insulator. That is, the thinner gate insulator indicates the less field-relief efficiency. In other words the thinner gate insulator results in larger electric field near the drain junction but the less field-relief efficiency. From this point of view, such architecture is not appropriate for the shot-channel and thin-oxide device for the future prospection. In this thesis, a novel drain-field-relief structure was introduced. The novel vacuum (the lowest permittivity of k=1 in nature) gaps are in-situ embedded in a T-shaped-gate (T-Gate) structure with a simple process. The vacuum gaps serve as the drain-field-relief elements. The device architecture needs neither additional lithography step nor implantation process, so that a low-cost fabrication process can be achieved. The purpose of this work is to introduce a novel T-Gate structure with vacuum gaps to enhance the electrical stability and suppress the leakage currents while keeping the high driving current. 1.7 Thesis Organization In chapter 1, an overview of LTPS TFTs technology is given. The motivations of this thesis are subsequently explained to introduce this thesis. In chapter 2, experimental processes of T-Gate TFTs are introduced. In order to verify the effect of the vacuum gaps on the electric field near the drain junction, device simulation was carried out by 2 D simulator for semiconductor devices. Several simulations such as lateral and vertical electric field, impact ionization coefficient, and drain breakdown characteristic with various device geometries were 13

30 discussed. Electrical performance of the proposed devices was then revealed. After that, the series resistance of T-Gate TFTs was investigated. In order to verify the side etching process was self-aligned, symmetry of electrical characteristics was discussed. The oxide breakdown characteristic was analyzed finally. In chapter 3, the reliability issues of T-Gate LTPS TFTs with vacuum gaps were investigated by applying several drain avalanche hot carrier (DAHC) stress conditions. Besides, variation of leakage current during DAHC stress was discussed. Finally, conclusions will be given in chapter 4. 14

31 Chapter 2 Characterization of T-Shaped-Gate (T-Gate) Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps Introduction Introduction to T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin-Film Transistors (T-Gate LTPS TFTs) with Vacuum Gaps In this work, a novel and simple process was introduced to fabricate T-Shaped-Gate (T-Gate) structures. The feature of the proposed structure is to embed vacuum (the lowest permittivity of k=1 in nature) [2.1] at the gate edge. Unlike other reported structures, our proposed structure needs neither additional lithography steps nor complex process. Therefore, a low-cost fabrication process can be achieved. The schematic figure of the proposed T-Gate TFTs and its equivalent structure were shown in Figs. 2-1(a) and 2-1(b), respectively. The detail fabrication procedure was discussed in the later chapter. The vacuum gaps can reduce the vertical electric field near the drain due to the lowest permittivity of k=1. The vacuum gaps serve as an equivalent thicker oxide. Because the relative static permittivity of SiO 2 is 3.9, the 15

32 equivalent oxide thickness of the vacuum gap is as high as 3.9 times. In this work, though the height of vacuum gap is only 1000Å, it is equivalent to a 3900 Å-thick SiO 2 film [2.2]-[2.4]. The poly-si region under vacuum gaps can be considered as the offset region and the gate edge over the vacuum cavity serves as a field plate connected with the gate, so that the proposed TFT operates as the field induced drain (FID) TFTs. In this chapter, experimental process of T-Gate TFTs was introduced. The T-shaped-gate structure was analyzed by cross-section scanning electron microscope (SEM) image. In order to verify the effects of the vacuum gap on the electric field near the drain junction, device simulation was carried out by ISE (Integrated System Engineering) 2 D simulator for semiconductor device. Several simulations such as lateral and vertical electric fields, and impact ionization coefficient with various device geometries were discussed. Electrical performances of the proposed devices were then revealed. After that, the series resistance of T-Gate TFTs was investigated. In order to verify the side etching step was a self-aligned process, symmetry of electrical characteristics was also investigated. These results successfully provide the demonstrations of fabricating high-performance T-Gate TFTs using a simple process Introduction to Excimer Laser Crystallization (ELC) Technique In order to prepare poly-si thin films, several ways have been reported including solid phase crystallization (SPC), metal induced lateral crystallization (MILC), and laser annealing [2.7]-[2.10]. Among these methods, the excimer laser annealing (ELA) 16

33 has been considered the most promising one. The excimer laser emits in UV light region with short pulse duration (10-30 ns) by the laser source of ArF, KrF, or XeCl (output wavelengths 193, 248, and 308 nm, respectively) gas source. The strong optical absorption of UV light and small diffusion length during the laser pulse in silicon imply that high temperature can be produced and cause melting of silicon without significant damage of glass substrate [2.11]. In addition, ELA poly-si films possess good crystallinity and few intra-grain defects due to the melt-regrowth process. During ELA process, the mechanism of grain growth is quite sensitive to the laser energy density. Fig. 2-2 schematically illustrates the grain growth corresponding to the different laser energy densities. As shown in Fig. 2-2 (a), if the laser energy density is too small to melt the whole a-si thin film, vertical solidification occurs and the un-melted solid layer remains to be a-si, while the melted Si layer transform into poly-si with small grain size [2.12]. Refer to Fig. 2-2 (b), if the laser energy density is large enough to completely melt the a-si thin film, homogeneous nucleation occurs for deep supercooling, resulting in small grain size [2.13]. Only when the laser energy density is controlled around a specific threshold value large grain as large as 1 μm in diameter can be obtained, as shown in Fig. 2-2 (c). This specific controlled value is so called Super Lateral Growth (SLG) regime [2.14], which vividly illustrates the behavior of melted a-si to recrystallize from very few un-melted Si residues to each other. For the very few residues as seeds, the lateral growth phenomenon causes large grain size. 17

34 2.2 Simulation Analyses of T-Gate LTPS TFTs with Vacuum Gaps In order to verify the effects of the vacuum gaps of T-Gate TFTs on the electric field near the drain junction, the simulations with various channel lengths and gate oxide thicknesses have been carried out by ISE TCAD which is a commonly used 2-D numerical simulator for device analysis [2.16]. The geometrical dimension of vacuum gaps was fixed at which the thickness (T vacuum ) and the length (L sub-gate ) were 600 Å and 0.5 μm, respectively. The channel lengths varied form 10 μm to 1.5 μm, and the gate oxide thicknesses varied form 1000 Å to 100 Å. Fig. 2-3 (a) and Fig. 2-3 (b) show 2-D electrical potential distribution of the conventional and T-Gate TFTs, respectively. It can be seen that the dense equipotential lines near the drain region in conventional TFTs have been relaxed in the T-Gate TFTs. This indicated that electric field is consequently reduced by T-Gate structure. Fig. 2-4 (a) shows the lateral electric field along channel layer of the conventional and proposed T-Gate TFTs structure. It is observed that the lateral electric field near the drain region is sufficiently suppressed about 48.9% by the proposed T-Gate structure. Besides, the vertical electric field near the drain region has a 82.0% drop in comparison with conventional TFTs. The simulation results of the lateral electrical field along the channel with various channel lengths were shown in Figs. 2-5 (a) and (b). It can be observed clearly that the electric field near the drain region is sufficiently suppressed by the proposed T-Gate structure especially when the channel length is scaled down. Furthermore, Figs. 2-6 (a) and (b) show the impact ionization coefficient with different channel lengths. We can observe that the impact ionization coefficient is also reduced because of its 18

35 dependence on the electric field. In addition, Figs. 2-7 and 2-8 show the lateral electric field and impact ionization coefficient along the channel with different oxide thicknesses. We can observe that the lateral electric field and the impact ionization factor are dramatically suppressed when the oxide thickness is decreased to 100 Å. The vacuum cap can be considered as an equivalent thicker oxide. When the thickness of gate oxide decreases to 100 Å, the vacuum cap can still provide a thick oxide near the drain region to suppress the drain electric field. From these simulation results, the T-Gate TFTs with thinner oxide thickness has better field-relief efficiency. 2.3 Fabrication of T-Gate LTPS TFTs with Vacuum Gaps Fabrication Sequence of T-Gate LTPS TFTs with Vacuum Gaps The detailed process flow of device fabrication is shown in Fig. 2-9(a)-(k). At first, a buffer layer that composed of 500 Å SiN and 1300 Å SiO 2 thin film was deposited by plasma-enhanced chemical vapor (PECVD) system on the glass substrate. Then, a 500 Å amorphous silicon (a-si) thin film was deposited by PECVD system on buffer layer. The a-si thin film was transferred into poly-si by 308 nm XeCl excimer laser. Before excimer laser crystallization, dehydrogenation was carried out in order to prevent the hydrogen explosion during laser irradiation. The laser energy density was 257 mj/cm 2 and 99% overlapping. After defining the active layer, 19

36 a 400 Å or 800 Å-thick SiO 2 gate oxide was deposited by PECVD system at 300 C. Then, a 500 Å or 1000 Å-thick Indium Tin Oxides (ITO) was deposited follow by a 2000 Å-thick Mo films was deposited by sputter system sequentially. The stacked Mo/ITO films were simultaneously etched to pattern as the gate electrode. An Oxalic acid, (COOH) 2 2H 2 O, solution was then used to selectively etch the ITO layer without harming Mo thin film to form the T-shaped structure. The side etching length of ITO thin film was carefully controlled to 2500 Å and was confirmed by the scanning electron microscope (SEM) graph. A self-aligned phosphorous implantation was carried out to form source and drain regions. Following that, a 5000Å inter-layer of silane-based SiO 2 was deposited by PECVD system and then densified through rapid thermal annealing (RTA) at 700 C for 30 s. It should be noted that the silane (SiH4) free radicals are very active and chemisorbed on the substrates easily [2.15]. The dopants were activated during the densification of the inter-layer dielectric. Next, after the contact hole opening, 5000 Å Al was deposited and pattern to the interconnect metal. Finally, all TFTs were subjected to the NH 3 plasma passivation treatment at 300 C for 1 hour to passivate the dangling bonds at the poly-si/sio 2 interface and the trap-states of the poly-si film. For the purpose of comparison, the conventional poly-si TFTs without side-etching structure as shown in Fig.2-10 were also fabricated. The channel length (L) and width (W) of device used in this study were 5 μm and 10 μm, respectively. The channel length (L) is defined as the length of Mo gate electrode, the height of vacuum gap is defined as T vacuum, and the length of ITO side etch is defined as L sub-gate and confined to be 2500 Å for all T-Gate devices in this work. L sub-gate and T vacuum are determined according to the simulation results. It should be noted that the vacuum gaps were in-situ formed during the inter-layer dielectric deposition by PECVD because of the chemical properties of silane (SiH4) free radicals. Fig shows the cross-section SEM image of T-Gate 20

37 structure with vacuum gaps. A symmetrical T-shaped gate electrode has been successfully fabricated by the 2500-Å selective etching of ITO film under the Mo layer Material Analyses of ELC Poly-Si Thin Films In this work, a 500 Å a-si thin film was transferred to ploy-si in Super Lateral Growth (SLG) regime mentioned in section Figs. 2-11(a)-(d) show SEM graphs of excimer laser crystallized ploy-si with various laser energy densities and overlapping. Figure 2-12 reveals the dependence of grain size on laser energy densities and overlapping. We can observe that a larger grain size can be achieved by using larger laser energy density within the range from 225 to 263 mj/cm 2 when the overlapping was 98% or 99%. For 98% overlapping, the grain size of poly-si crystallized with laser energy density of 225 mj/cm 2, 257 mj/cm 2, and 263 mj/cm 2 were about 800 Å, 3200 Å and 4600 Å, respectively. However, the large grain of ELC poly-si thin film generally accompanies with poor uniformity and high surface roughness (usually called protrusion) resulted from volume expansion from liquid to solid phase. The protrusion shown in Fig of ELC poly-si thin film could attribute to local breakdown of gate dielectric. Accordingly, it was a trade-off issue between the grain size and surface roughness. The laser energy density of ELC used in this work was 257 mj/cm 2 with 99% overlapping. The grain size of poly-si film was about 3200 Å. 21

38 2.4 Electrical Characterization of T-Gate LTPS TFTs with Vacuum Gaps Basic Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps The method to determinate the threshold voltage (V th ) in this thesis was the constant drain current method that defined as the gate voltage required to achieve a normalized drain current of I D = (W/L) 10-8 A at V D = 0.1 V. The equivalent field effect mobility was extracted from the maximum transconductance in the linear region of I D -V G characteristics at V D = 0.1 V using the formula: gm μ * = (@ VDS = 0.1V )...(1) W Cox ( ) VDS L, where C ox was the gate oxide capacitance per unit area, and the transconductance (g m ) is defined as: I =.(2) D gm VDS =0. 1V Vg The on/off current ratio was defined as the ratio of maximum drain current over minimum drain current at V D = 3 V. Drain Induced Barrier Lowering (DIBL) was defined as the V th difference between V D = 0.1 V and 3 V. Substhreshold Swing (SS) was defined as: 1 log( I D ) SS min VDS = 0. 1V V g.(3) Critical characteristics of the T-Gate TFTs with 400 Å-thick gate oxide were 22

39 summarized in Table 2-1. The effects of different height of vacuum gaps were discussed with 1000 Å and 500 Å. According to Table 2-1, the T-Gate TFTs exhibit superior on/off characteristics which is one order greater than those of conventional structure, especially the T-Gate TFTs with 1000 Å vacuum gap. Meanwhile, the field effect mobility was almost non-changed between T-Gate and conventional TFTs. The weaker substhreshold swing (SS) is caused from the little loss of gate controllability of T-shaped-gate structure. The transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide thickness of 400 Å was shown in Fig Aside from the improvement of on/off ratio, the maximum leakage current (i.e. drain current at V G = -15 V) has a dramatic improvement drop by applying the T-Gate structure. Take the T-Gate TFTs with 400 Å-thick gate oxide for example, the maximum leakage current of T-Gate TFTs with 1000 Å-thick vacuum gaps is A, and that of conventional TFTs is A. Also, it can be observed that the T-Gate TFTs with thicker vacuum gaps have the lower leakage current. The leakage current at large gate bias of LTPS TFTs could be attributed to the high electric field near the drain junction. By applying the T-shaped-gate structure, the maximum electric field near the drain can be effectively decreased from the vacuum gaps. These have been already confirmed by the simulation results in the former chapter. Thus, the magnitude of leakage current in large gate bias (-15 V) can be suppressed three orders in comparison with those conventional TFTs. The magnitude of on-state current of T-Gate TFTs with 1000 Å vacuum gaps decayed about 35% in comparison with the conventional TFTs at the high gate bias (15 V). Despite of the reduction of driving current, the on/off ratio still enhanced about one order. This was attributed to the dramatic reduction on leakage current. 23

40 Similarly, the driving current of T-Gate TFTs with 500 Å vacuum gap decayed about 25% in comparison with the conventional ones at the high gate bias of 15 V. Figure 2-15 shows the output characteristics of T-Gate and conventional TFTs with channel length of 5 μm, channel width of 10 μm, and gate oxide of 400 Å, respectively. We can observe that the kink effect was sufficiently suppressed by T-Gate TFTs as compared to the conventional TFTs under the same bias condition. The phenomenon of impact ionization at the drain junction is the reason for the occurrence of kink current at large drain bias. The simulation results in former chapter pointed that impact ionization coefficient of T-Gate TFTs is much lower than the conventional ones. Consequently, the kink effect can be suppressed by T-Gate structure. In this work, T-Gate TFTs were prepared with two different oxide thicknesses in which were 400 Å and 800 Å. The transfer characteristics of these two kinds of T-Gate TFTs are shown in Figs and 2-29, respectively. The channel width and channel length were 10 μm and 5 μm. T vacuum and L sub-gate were fixed at 1000 Å and 2500 Å, respectively. The leakage current as well as the driving current at large gate bias (i.e. at V G = -15 V and 15 V) are listed at Table 2-2. A better outcome of leakage current reduction is observed in the T-Gate TFTs with thinner gate insulator (i.e. 400 Å) in comparison with the thicker one (i.e. 800 Å). Fig and Fig are the schematic illustrations of the equivalent structure of T-Gate TFTs in which the thickness of gate oxide are 400 Å and 800 Å, respectively. The equivalent oxide thickness at the gate edge of T-Gate TFTs with 400 Å gate oxide is 4400 Å in which is 11 times the thickness of the conventional TFTs. As to the T-Gate TFTs with 800 Å gate oxide, only 6 times is observed. This conclusion is consisted with the simulation result mentioned in section 2.3. Figure 2-23 shows the transfer characteristics of T-Gate TFTs with and without 24

41 NH 3 plasma passivation. Because NH 3 plasma can passivate the dangling bonds at the poly-si/sio 2 interface and the trap-states of the poly-si film, all the electrical characteristics can be improved. The electrical characteristics are listed in Table Series Resistance Analyses of T-Gate LTPS TFTs with Vacuum Gaps In this study, the series resistances (R series ) accompanied with the offset-region resistance (R offset ) were extracted from device characteristics directly. It is well known that the turn-on resistance (R ON ) for devices operation in linear region can be express as: R ON V = I D D V G VD 0 = R channel + R series (4), where R channel and R series represented the channel resistance and the series resistance, respectively, the channel resistance in the linear region can be given approximately by: R channel 1 = (5) WμC OXV G, where C ox was the capacitance per unit area, W, L, and V th were the intrinsic channel width, length, and threshold voltage, respectively. V th is defined, for devices with long channel length. With characteristics of devices with different channel length, the series resistance R series can be extracted by plotting turn-on resistance (R ON ) versus channel length (L) at V D = 0.1 V [2.5]-[2.6]. As shown in Figs. 2-20, 2-21 and 2-22, the extracted series resistance of conventional TFTs is 5.63k ohm. The series resistance of T-Gate TFTs with T vccuum = 25

42 1000 Å and T vccuum = 500 Å were 9.86k ohm and 9.22k ohm, respectively. The difference of series resistance between the proposed T-Gate TFTs and conventional TFTs is only the influence of offset region in the T-Gate TFTs. In the proposed T-Gate TFTs, the offset region provide an additional series resistance beside the conventional parasitic resistance including spreading resistance, sheet resistance, and contact resistance along the current path. Therefore the resistance resulting form the offset region (R offset ) of T-Gate TFTs can be expressed as: R offset = R ( T GateTFTs) R ( Conv. TFTs)....(6) series series, where R offset was the series resistance that results from the offset region in T-Gate TFTs, R series (T-Gate TFTs), R series (Conv. TFTs),were the series resistance of T-Gate TFTs and Conv. TFTs with the same device dimension. According to equation (6), for low drain bias (V D = 0.1 V) the series resistance of offset region (R offset ) has a value of about 4.23k ohm for T vccuum = 1000 Å T-Gate TFTs and about 3.59k ohm for T vccuum = 500 Å T-Gate TFTs. The larger R offset value of T-Gate TFTs with T vccuum = 1000 Å than those with T vccuum = 500 Å was observed. In the T-Gate TFTs, the vacuum serves as the equivalent 3.9 times thicker oxide. As the vacuum gap is higher, the equivalent oxide thickness is thicker. For the 400 Å-thick gate insulator T-Gate TFTs with 1000 Å- and 500 Å-height vacuum gaps, the equivalent oxide thickness at the gate edge was 4400 Å and 2400 Å, respectively. When MOSFET operated in the on-state, the thicker gate insulator induces less inversion carrier. Therefore, the T-Gate TFTs with 1000 Å vacuum gaps had less inversion carrier in the offset region compared to those with 500 Å vacuum gaps, so that the T-Gate TFTs with with 1000 Å vacuum gaps have a larger R offset in on-state. This observation is consisted with the transfer characteristics of T-Gate TFTs as shown in Fig

43 2.4.3 Symmetry of Electrical Characteristics of T-Gate LTPS TFTs with Vacuum Gaps The symmetry of electrical characteristics is discussed to verify the ITO side etching step is a self-aligned process. Figure 2-26 is the schematic illustration of definition of the forward-mode and reverse-mode measurement. There are two possibilities to cause the deviation between forward mode and the reverse mode measurement. One is the asymmetry of side etching of ITO thin film; the other is the grain uniformity variation. Figure 2-27 shows the transfer characteristic of T-Gate TFTs without NH 3 plasma passivation. It is observed that the measured drain current has a difference between forward mode and the reverse mode measurement, especially the leakage current at the small gate bias. The driving current and the leakage current at the large gate bias are almost the same in these two measurement modes. The leakage current in poly-si TFTs at small gate bias is via thermionic emission [2.17]-[2.19], and is dominated by trap density of poly-si film. Consequently, the leakage current difference between these two modes may be arising form the grain uniformity variation. To further affirm the asymmetry of electrical characteristic, the statistical analyses were carried out. 30 samples of T-Gate TFTs without plasma passivation were measured for statistical analyses. In this work, drain-current difference ( I) is defined as: I DF (min) - I DR D = 3 V...(6), where I DF (min) and I DR (min) are the minimum drain-current measured in forward-mode and reverse-mode, respectively. Figure 2-29 shows the statistical bar chart of the drain-current difference ( I) 27

44 between forward mode and reverse mode for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å and the L subgate is 2500 Å without plasma passivation. A normal distribution was found in the statistical bar chart. The same statistical analysis was also performed on T-Gate TFTs with NH 3 plasma passivation for 1HR. Figure 2-30 shows the measured drain currents of forward-mode and reverse-mode measurements after NH 3 passivation were almost the same (i.e. the symmetrical of transfer characteristic). And the statistical bar chart of I is also followed the rules of normal distribution. The mean value of I for T-Gate TFTs with and without NH 3 passivation is 0.06 pa and 0.78 pa, respectively. The standard deviation of I for T-Gate TFTs with and without NH 3 passivation is 0.83 pa and 6.12 pa, respectively. These results indicate that the asymmetry of transfer characteristic can be eliminated by the defect-passivation treatment. And the asymmetrical transfer characteristic of T-Gate TFTs without passivation treatment is because of the grain uniformity variation. Finally, the self-aligned ITO side etching step is verified Oxide Breakdown Characteristics of T-Gate LTPS TFTs with Vacuum Gaps SiO 2 is the preferred material in LTPS TFT production because it forms an excellent interface with poly-si. Hence, a new low temperature gate dielectric process is required for LTPS TFTs. Plasma-enhanced vapor deposition (PECVD) has been the universal choice for forming oxides in LTPS TFT technology due to its capability to process large-area substrates. Good gate dielectric thin films should have high breakdown field (> 8 MV/cm). However, the major problem in gate dielectric thin 28

45 films is the local breakdown due to the poor interface with the protruded silicon surface after excimer laser annealing (ELA) and the poor quality of PECVD oxide. Due to this unavoidable problem, gate dielectric thin films have to be thicker to overcome the poor oxide breakdown characteristics, however, it reduces TFT driving ability. The gate breakdown characteristics of T-Gate and conventional TFTs with 400 Å-thick gate insulator are shown in Fig T-Gate TFTs with 1000 Å-thcik vacuum gap has an excellent breakdown field of about 8.5 MV/cm. It should be noted that the gate oxide was deposited by PECVD system at 300 C. The poor breakdown field of 6.2 MV/cm was observed in the conventional TFTs. This is because not only the lateral electric field but also the vertical electric field near the drain junction is reduced by the T-Gate structure. From Fig. 2-10(b), the maximum vertical electric field of T-Gate TFTs has a 53% reduction near the drain as compared to that of conventional ones. Therefore, the T-Gate TFTs have a larger gate voltage operation than the conventional TFTs. 2.5 Summary In this chapter, we successfully fabricated T-Gate LTPS TFTs by a simple process procedure. The structure of vacuum gaps was confirmed by cross-section SEM graph. Both simulation and fabrication of T-Gate TFTs were executed to characterization of T-Gate LTPS TFTs with vacuum gaps. In the beginning, simulations of electric field and impact ionization coefficient with various channel lengths and gate oxide thicknesses have been carried out. The proposed T-Gate structure can suppress the maximum electric field near the drain 29

46 accompanied with the reduction of impact ionization coefficient, especially in the thin-oxide T-Gate TFTs. In the second part, high-performance T-Gate TFTs with on/off ratio exceeding 10-9 has been fabricated. The maximum leakage current (i.e. drain current at V G = -15V) was observed to have a dramatic improvement (about three orders) by applying T-Gate structure. Meanwhile with the aid of field induced drain (FID) structure, the driving current only decayed about 35% at the high gate bias (i.e. V G = 15 V) as compared to the conventional ones. The series resistance of the offset region that related to the driving current reduction was discussed. In addiction, alleviation of kink effect was also observed due to lower impact ionization by the proposed structure. The T-Gate TFTs with thinner oxide have better field-relief efficiency was found and confirmed by simulation. It is because of the ratio of the equivalent oxide thickness at the gate edge of T-Gate TFTs is higher than that of conventional ones. The symmetry of electrical characteristics was discussed to verify the ITO side-etching step is a self-aligned process. The asymmetrical transfer characteristic of T-Gate TFTs without passivation treatment is attributed to the grain uniformity variation, and the mismatch can be eliminated by passivation treatment. The standard deviation of I for T-Gate TFTs with and without NH 3 passivation was 0.83 pa and 6.12 pa, respectively. In the statistical analyses, a normal distribution was found in the statistical bar chart for I. According, the self-alignment ITO side etching process was verified. Finally, the oxide breakdown field can be promoted from 6.2 MV/cm to 8.5 MV/cm by adopting T-Gate TFTs with 1000 Å-thcik vacuum gaps. 30

47 Chapter 3 Reliability Analyses of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps Introduction For driving circuit operation, unlike the pixel switching, the peripheral driving circuits operate with a relatively high drain voltage bias [3.1]-[3.3]. Accordingly, the hot carrier effect becomes one of the most serious issues affecting the reliability of LTPS TFTs [3.4]. Therefore, the hot carrier effect restricts the LTPS TFTs application on flat panel displays or large-scale integrated circuits (LSIs). In LTPS TFTs, unlike the fundamental MOSFETs, electrical parameters such as the threshold voltage, maximum transconductance, and subthreshold swing deeply depend on the properties of grain, grain boundaries, and poly-si/sio 2 interface. Farmakis et al. have investigated electrical parameters in TFTs as listed in Table 3-1 to clarify the mechanism that degrade device electrical parameters during hot carrier stress [3.5]. The deep trap states in the grain boundaries or poly-si/sio 2 interface mainly affect the threshold voltage. In addition, hot carrier injection into the gate oxide also causes the threshold voltage shift. The generation of tail trap states in the grain boundaries or poly-si/sio 2 interface degrades the maximum transconductance. Furthermore, the subthreshold swing mainly depends on both intra-grain trap states in 31

48 the poly-si film and deep interface trap states. In this chapter, the T-Gate and conventional TFTs are discussed under drain avalanche hot carrier (DAHC) to verify the better reliability of proposed structure. The variation of leakage current after hot carrier stress was investigated by several analyses. 3.2 Effects of Drain Avalanche Hot Carrier (DAHC) Stress on T-Gate LTPS TFTs with Vacuum Gaps Figures 3-1 and 3-2 show the transfer characteristics of the T-Gate and conventional TFTs before and after drain avalanche hot carrier stress at V D = 10 V, V G = 1.5 V from 0 to 1000 seconds, restively. The corresponding extracted electrical parameters are listed in Table 3-2 and Table 3-3. The threshold voltage shift as a function of stress time is shown in Fig The threshold voltage shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V, V G = 1.5 V for 1000 seconds were 0.11 V and 2.7 V, respectively. From Figs. 3-4 and 3-5, the less degradation is observed in T-Gate TFTs. It is obvious that a serious degradation on transconductance, on-current, drain induced barrier lowering (DIBL), and large threshold voltage shift in the conventional TFTs. On the other hand, the proposed T-Gate TFTs show a better immunity on drain avalanche hot carrier stress. In the poly-si TFT s channel, defects in grain boundaries and intra-grains would trap carriers and form potential barriers, affecting the current transport. During the DAHC injection, more trap states (acceptor-like) or negative charges are created, 32

49 raising the barrier height [3.6]-[3.8]. Therefore, serious degradation on I on can be observed clearly. Figure 3-6 shows the plot of the potential barrier for carrier transport induced by filled negative trap states (or negative charges) in the poly-si channel. Additionally, we can observe that the leakage current reduced after DAHC stress. Considering that leakage current is associated with the amount of defects or traps in the drain depletion region, the schematic diagram of the depletion region and the corresponding energy band diagram of the drain in the off-state are shown in Fig The generation of leakage current is attributed to thermionic emission at a low electric field and the field-enhanced emission (i.e., F P emission or trap-assisted band-to-band tunneling) at a high electric filed. Hence, the magnitude of the electrical field and the amount of traps within the drain depletion region are the two important factors considered in studying the variations of leakage current. The reduction of leakage current after DAHC stress is because some positive charges are created in the poor-quality gate oxide near the drain. These positive oxide charges lower the local electric field in the drain depletion region. The electric field near the drain side before and after the creation of positive oxide charges is schematically depicted in Fig The positive oxide charges lift the electric field in the gate oxide but reduce that in the poly-si. Thus, the reduction of the local electric field in the drain depletion region decreases leakage current [3.8]. Furthermore, these positive oxide charges are created in the localized region (i.e. near the drain). This phenomenon could be revealed by Figs. 3-9 and In order to explain this phenomenon, the reverse mode transfer characteristics are measured. Fig shows the reverse mode measured transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. There is no shielding effect of positive oxide charges because of those positive oxide charges are only located near the drain, instead of the entire 33

50 channel region. Another stress condition was applied to T-Gate TFTs to further characterize the local shield effect of positive oxide charges on leakage current variation. Fig shows the transfer characteristics measured at V D = 3 V of the T-Gate TFTs before and after electron oxide trap stress" at V D = 0 V and V G = 20 V from 0 to 1000 seconds. In this stress condition, negative oxide charge was created. The leakage current increased with the stress time as shown in Fig On the other hand, Fig shows the leakage current variation measured at V D =3V of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D =10V, V G =1.5V for 10 to 1000 seconds. The minimum leakage current increased after DAHC stress, while the maximum leakage decreased. The increasing defect density arises form DAHC stress contributes to the increase of the minimum leakage current. The decreased maximum leakage current is attributed to the local shield effect of positive oxide charges in DAHC stress. The reliability of T-Gate TFTs with and without NH 3 passivation was also discussed. Fig shows the transfer characteristics of the T-Gate TFTs without plasma passivation before and after hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. As comparied to the T-Gate TFTs with 1-hour NH 3 passivation 1HR, that without plasma passivation exhibited a better reliability on DAHC, Figs and 3-17 show the transconductance and DIBL degradation of T-Gate TFTs with and without plasma passivation after DAHC, respectively. It was well known that conduction carriers can obtain energy from the high electric field and become hot. These high-energy carriers can easily break weak bonds existing in poly-si during DAHC stress [3.9]. In NH 3 passivation treatment, the incorporation of hydrogen into the channel layer to passivate the defect states is effective and essential for attaining good device performance and also for improving the uniformity 34

51 of device performance, however, the weak Si-H bond contribute to worsen the reliability. 3.3 Summary In this chapter, T-Gate LTPS TFTs have been demonstrated a better immunity on drain avalanche hot carrier stress. In the first part, the effects on DAHC stress of T-Gate TFTs was investigated. After 1000-sec stress, the maximum transconductance decrease about 78% and 83%, and the threshold voltage shift was about 0.11 V and 1.7 V in T-Gate and conventional TFTs, respectively. Similarly, T-Gate TFTs have a smaller DIBL shift of 125 mv in comparison with 2727 mv of the conventional ones. Furthermore, the variation of leakage current after DAHC stress was discussed. Due to the local shield effect of positive oxide charges in DAHC stress, the maximum leakage current decreased but the minimum leakage current increased with the increasing stress time. The increase of minimum leakage current was because more defect states are arisen during DAHC stress. In addition, the positive oxide charges are only located near the drain region, so that the shield effect cannot not be seen in the reverse-mode measurement. Accordingly, the leakage current measured in the reverse-mode almost changes nothing. 35

52 Chapter 4 Conclusions In this thesis, we have demonstrated high performance and high reliability T-Shaped-Gate polycrystalline silicon thin-film transistors fabricated by a low-cost process. The results and discussions are summarized in this chapter. Simulation results show the proposed T-Gate structure can suppress the maximum lateral and vertical electric fields near the drain accompanied with the reduction of impact ionization coefficient. It is more effective for the thinner oxide case. The maximum lateral and vertical electrical fields near the drain are reduced with about 48.9% and 82.0%, respectively. High-performance T-Gate TFTs with on/off ratio exceeding 10 9 have been demonstrated. The maximum leakage current (i.e. the drain current at V G = -15 V and V D = 0.1 V) was distinctly improved to be about three orders lower by applying T-Gate structure. Meanwhile, with the aid of sub-gates of T-Gate TFTs the driving current is only decayed about with 35% at high gate bias (i.e. V G = 15 V) in comparison with that of conventional ones. The resistance of the offset region related to the driving current reduction was also discussed. The offset resistance (R offset ) of T-Gate TFTs is 4.2k ohm, which is 30% of turn-on-resistance (R on ). In addiction, the alleviation of kink effect was also observed due to the lower impact ionization from the proposed structure. T-Gate TFTs with thinner oxide have better field-relief efficiency as compare to those with thicker ones. It is because the vacuum contributes more weighting in the effective oxide thickness for the thinner oxide case. 36

53 The symmetry of electrical characteristics was performed to verify that ITO side etching step was a self-aligned process. The slight asymmetrical transfer characteristics of T-Gate TFTs without passivation treatment were caused from the variation of grain boundary distribution, and the mismatch can be eliminated by further passivation treatment. In the statistical analyses, normal distributions were also found in the statistical bar chart for I (drain current difference between forward and reverse-mode measurement at V D =3V). The standard deviations of I for T-Gate TFTs with and without NH 3 passivation was 0.83 pa and 6.12 pa, respectively. Accordingly, the self-aligned ITO side etching process was verified. Additionally, the oxide breakdown field can be promoted from 6.2 MV/cm to 8.5 MV/cm by adopting the T-Gate TFTs with 1000 Å-thick vacuum gaps. Moreover, T-Gate LTPS TFTs have been demonstrated to a better immunity to drain avalanche hot carrier stress and self heating stress. After 1000sec stress time, the maximum transconductances decrease about 78% and 83% in T-Gate and conventional TFTs, respectively. The threshold voltage shift was about 0.11 V and 1.7 V. Similarly, T-Gate TFTs had a smaller DIBL shift of 125 mv as compared to 2727 mv of the conventional ones. Furthermore, the variation of leakage current after DAHC stress was discussed. Due to the local shield effect of positive oxide charges in DAHC stress, the maximum leakage current decreased with increasing the stress time, but the minimum leakage current increased with increasing the stress time. The increase of minimum leakage current was because more defect states were created during DAHC stress. In addition, the positive oxide charges were only located near the drain region, so that the shield effect cannot be observed in the reverse-mode measurement. Accordingly, the leakage current measured with reverse mode almost change nothing. To sum up, T-Gate structure with vacuum gaps was attractive, especially for the 37

54 thin oxide devices. The characteristics of T-Gate LTPS TFTs with vacuum gaps exhibited excellent on/off current ratio. The leakage current can be decreased dramatically while the driving can be maintained. Besides, the improvement of oxide breakdown characteristics can enlarge the operation range of the gate bias. Furthermore, the proposed T-Gate TFTs have much superior immunity to the hot carrier degradation as compared with the conventional ones. 38

55 Tables Year 98 ~ ~ ~ ~ Generation 1 st Gen. 2 nd Gen. 3 rd Gen. 4 th Gen. Logic frequency 3 MHz 3 MHz ~ 30 MHz > 30 MHz Mobility (cm 2 /Vs) ~ 500 DC/DC, Integrated LCD driver converter, DSP, CPU, LCD driver function D/A converter Digital I/F, Frame memory Photo-sensor Fine Crystallization, Key technology ELA Flat-ELA, Dry lithography, Planarization (design rule) 4 ~5 μm 3 μm Dry < 1 μm 1.5 μm Table 1-1 The performances and the related processes of LTPS TFTs for the SOP roadmap are going on in the future. 39

56 T vacuum Mobility (cm 2 /V s) V th (V) I on / off SS (mv/dec) 1000Å E Å E Å (Conv.) E Table 2-1 Electrical characteristics of T-Gate and conventional TFTs with gate oxide of 400 Å, channel width of 10 μm and gate length of 5 μm. T ox Leakage G = -15 V ; V D = 3 V On G = 15 V ; V D = 3 V 400Å 800Å T-Gate TFTs 6.31E E-4 X(1/3490) Conv. 1.81E E-4 TFTs T-Gate TFTs 1.77E E-4 X (1/26) Conv. 4.72E E-4 TFTs X 0.65 X 0.71 Table 2-2 Maximum leakage and on-state current of T-Gate and conventional TFTs with different gate oxide thickness, the channel width and length were 10μm and 5μm, respectively. 40

57 Mobility (cm 2 /V s) V th (V) Ion/off SS (mv/dec) DIBL (mv) No passivation NH 3 1HR passivaiotn E E Table 2-3 Electrical characteristics of T-Gate TFTs before and after NH 3 passivaiotn for 1HR Average Standard Deviation I for No NH3 plasma 0.78 pa 6.12pA passivation I for NH3 plasma 0.06 pa 0.38 pa passivation1hr Table 2-4 Average and standard deviation of 30 measured I samples of T-Gate TFTs. The thickness of gate oxide was 400Å. The vacuum gaps height was 1000Å. 41

58 Table 3-1 Parameter variation and corresponding possible degradation mechanisms. (Ref. Farmkis et al.,ieee Electron Device Lett., 2001) T-Gate TFTs Mobility Stress Time(sec) (cm 2 /V s) Vth (V) Ion/off DIBL(mV) E E E E E E E Table 3-2 Electrical parameter of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D =10V, V G =1.5V for 10 to 1000 seconds. 42

59 Conv TFTs Mobility Stress Time(sec) (cm 2 /V s) Vth (V) Ion/off DIBL(mV) E E E E E E E Table 3-3 Electrical parameters of the conventional TFTs before and after drain avalanche hot carrier stress at V D =10V, V G =1.5V for 10 to 1000 seconds. T-Gate TFTs Conv. TFTs Vth After 100 sec Gm (%) After 100 sec DIBL (mv) After 100 sec 0.04V 1.41V 66% 80% Table 3-4 Electrical parameters shift of the T-Gate and conventional TFTs before and after drain avalanche hot carrier stress at V D =10V, V G =1.5V for 10 to 1000 seconds. 43

60 without NH 3 passivation Stress Time(sec) Mobility Vth (V) Ion/off DIBL(mV) (cm 2 /V s) E E E E E E E Table 3-5 Electrical parameters of the T-Gate TFTs without plasma passivation before and after drain avalanche hot carrier stress at V D =10V, V G =1.5V for 10 to 1000 seconds. 44

61 Figures Fig. 1-1 The offset TFTs structure proposed by Jung-In Han et al. Fig. 1-2 The LDD TFTs structure proposed by Shunji Seki et al. 45

62 Fig. 1-3 The FID TFTs structure proposed by Joon-Ha Park et al. Fig. 1-4 The GOLDD TFTs structure proposed by Mutsuko Hatano et al. Fig. 1-5 The Air-Gap TFTs structure proposed by Min-Cheol Lee et al. 46

63 Fig. 2-1 (a) The device structure of proposed T-Gate LTPS TFTs with vacuum gaps Fig. 2-1 (b) The schematic illustration of the equivalent device structure of the proposed T-Gate LTPS TFTs with vacuum gaps 47

64 excimer laser irradiation melted Si un-melted a-si vertical regrowth un-melted a-si small-grain poly-si a-si substrate substrate substrate Fig. 2-2 (a) The schematic illustration of the low energy regime corresponding to energy densities that partially melting the a-si thin film excimer laser irradiation small-grain poly-si melted Si homogeneous nucleation substrate substrate substrate Fig. 2-2 (b) The schematic illustration of the high energy regime corresponding to energy densities that completely melting the a-si thin film excimer laser irradiation large-grain poly-si melted Si super lateral growth unmelted residual Si islands substrate unmelted residual Si islands substrate substrate Fig. 2-2 (c) The schematic illustration of the super lateral growth regime corresponding to energy densities that nearly completely melting the a-si thin film 48

65 Fig. 2-3 (a) The two-dimensional electrical potential distributions of the conventional TFTs Fig. 2-3 (b) The two-dimensional electrical potential distributions of the proposed T-Gate TFTs 49

66 Lateral Electric Field (V/cm) 7x10 5 6x10 5 5x10 5 4x10 5 3x10 5 2x10 5 1x Conv. TFTs T-GateTFTs (L Sub-Gate = 2500 A) L= 5 um T ox = 400 A, T Vacuum = 1000 A V G = -15V V D = 3V Source Drain 48.9% Position Along Channel Layer, x (μm) Fig. 2-4 (a) The lateral electric fields along channel layer of the conventional and proposed T-Gate TFTs Vertical Electric Field (V/cm) 1.5x x x Conv. TFT T-GateTFT (L Sub-Gate = 2500A) L= 5 um T ox = 400 A, T Vacuum = 1000 A V G = -15 V V D = 3 V Source Drain 82.0% Position Along Channel Layer, x (μm) Fig. 2-4 (b) The vertical electric fields along channel layer of the conventional and proposed T-Gate TFTs 50

67 Electric Field ( V/cm ) 5x10 5 4x10 5 3x10 5 2x10 5 1x10 5 L=10um L=5um L=2um L=1um V G = 4 V,V D = 12 V,T ox = 1000 A Conv. TFTs Position Along Channel Layer, X ( μm ) Fig. 2-5(a) The lateral electric fields of conventional TFTs with varied channel lengths Electric Field ( V/cm ) 5x10 5 4x10 5 3x10 5 2x10 5 1x10 5 L=10um L=5um L=2um L=1um V G = 4 V, V D = 12 V, T ox = 1000 A T-Gate TFTs Position Along Channel Layer, X ( μm ) Fig. 2-5(b) The lateral electric fields of T-gate TFTs with varied channel lengths 51

68 Impact Ionization coefficient ( cm -1 ) Conv. TFTs L = 10 um L = 5 um L = 2 um L = 1 um V G = 4 V, V D = 12 V,T ox = 1000 A Position Along Channel Layer, X (μm) Fig. 2-6(a) The impact ionization coefficients of conventional TFTs with varied channel lengths Impact Ionization coefficient ( cm -1 ) T-Gate TFTs L = 10 um L = 5 um L = 2 um L = 1 um V G = 4 V, V D = 12 V,T ox = 1000 A Position Along Channel Layer, X ( μm ) Fig. 2-6(b) The impact ionization coefficients of T-gate TFTs with varied channel lengths 52

69 1.0x10 6 Electric Field ( V/cm ) 8.0x x x10 5 V G = 4V, V D =12V, L=5um Conventional TFTs T ox =1000A T ox =500A T ox =100A 2.0x Position Along Channel Layer, X ( μm ) Fig. 2-7(a) The lateral electric fields of conventional TFTs with varied oxide thicknesses Electric Field ( V/cm ) 1.0x x x x10 5 V G =4V, V D =12V, L=5um T-gate TFTs T ox =1000A T ox =500A T ox =100A 2.0x Position Along Channel Layer, X ( μm ) Fig. 2-7(b) The lateral electric fields of T-Gate TFTs with varied oxide thicknesses 53

70 Impact Ionization coefficient ( cm -1 ) V G = 4V, V D =12V, L=5um Conventional TFTs T ox =1000A T ox =500A T ox =100A Position Along Channel Layer, X ( μm ) Fig. 2-8(a) The impact ionization coefficients of conventional TFTs with varies oxide thicknesses Impact Ionization coefficient ( cm -1 ) V G =4V, V D =12V, L=5um T-Gate TFTs T ox =1000A T ox =500A T ox =100A Position Along Channel Layer, X ( μm ) Fig. 2-8(b) The impact ionization coefficients of T-Gate TFTs with varied oxide thicknesses 54

71 Fig. 2-9 (a) Buffer layer deposition on the glass substrate Fig. 2-9 (b) Amorphous Silicon layer deposition by PECVD system Fig. 2-9 (c) Crystallization of the amorphous-si film using excimer laser irradiation Fig. 2-9 (d) Definition of active region 55

72 Fig. 2-9 (e) Gate oxide deposition by PECVD system at 300 C Fig. 2-9 (f) The stacked ITO/Mo layer deposition followed by patterning as the gate electrode Fig. 2-9 (g) Selective side etching of the ITO layer to form the T-shape gate electrode structure 56

73 Fig. 2-9 (h) Self-aligned source and drain implantation to form source and drain region Fig. 2-9 (i) Silane-base SiO x passivation layer deposition by PECVD system resulting in the in-situ vacuum gaps and then dopant activation by RTA system 57

74 Fig. 2-9 (j) Contact hole opening and metallization 58

75 Fig. 2-9 (k) NH 3 plasma passivation Fig. 2-9 (l) The conventional structure Fig The SEM image of the in-situ vacuum gaps under the T-shape gate structure 59

76 Fig. 2-11(a) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 225 mj/cm 2 and 98% overlapping Fig (b) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 257 mj/cm 2 and 98% overlapping 60

77 Fig (c) SEM graphs of excimer laser crystallized polycrystalline silicon. The laser energy density was 263 mj/cm 2 and 98% overlapping Fig (d) SEM graphs of excimer laser crystallized polycrystalline silicon. The 61

78 laser energy density was 257 mj/cm 2 and 99% overlapping Fig The SEM graphs of the grain size corresponding to laser-energy densities and overlapping in SLG region. Fig Cross-section SEM graphs and embedded TEM image of excimer laser 62

79 crystallized polycrystalline silicon Log-scale drain current ( A ) 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 Black:Conv. TFTs Blue: T-Gate TFTs (T vcuum =500A) Red:T-Gate TFTs (T vcuum =1000A) Open: Vd=3V Solid: Vd=0.1V Gate voltage ( V ) Linear-scale drain current ( μa ) Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å. Drain current ( A ) Conv. TFTs T-Gate TFTs T vacuum =1000A V G = 6.5 V Channel Width = 10μm Channel length = 5μm Tox = 400A Drain voltage ( V ) Fig Output characteristics of n-channel T-Gate LTPS TFTs with channel length 63

80 of 5 μm and channel width of 10 μm, and gate oxide of 400 Å. 1E Log-scale drain current ( A ) 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 Black:Conv. TFTs Red:T-Gate TFTs (T vcuum =1000A) Open: Vd=3V Solid: Vd=0.1V Linear-scale drain current ( μa ) Gate voltage ( V ) Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å. 1E Log-scale drain current ( A ) 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 Black:Conv. TFTs Red:T-Gate TFTs (T vcuum =1000A) Open: Vd=3V Solid: Vd=0.1V Linear-scale drain current ( μa ) Gate voltage ( V ) Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with channel length of 5 μm and channel width of 10 μm, and gate oxide of 400 Å. 64

81 Fig The schematic illustration of the equivalent structure of T-Gate TFTs compared to conventional TFTs in which the thickness of gate oxide is 400 Å. 65

82 Fig The schematic illustration of the equivalent structure of T-Gate TFTs compared to conventional TFTs in which the thickness of gate oxide is 800 Å. 66

83 Turn-On Resistance R on (ohm) 12.0k 10.0k 8.0k 6.0k V G =15V V G =14V V G =13V V G =12V V G =11V V G =10V 5.63k ohm Conv. TFTs Tox=400A Channel width=10μm Channel length=5μm Channel Length (μm) Fig Turn-On resistance as a function of channel length at different gate voltages for conventional TFTs Turn-On Resistance R on (ohm) 16k 15k 14k 13k 12k 11k 10k 9k V G =15V V G =14V V G =13V V G =12V V G =11V V G =10V 9.22k ohm T-Gate TFTs T vacuum =500A L sub-gate =2500A Tox=400A Channel width=10μm Channel length=5μm Channel Length (μm) Fig Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 500 Å 67

84 Turn-On Resistance R on (ohm) 16k 15k 14k 13k 12k 11k 10k 9k V G =15V V G =14V V G =13V V G =12V V G =11V V G =10V 9.86k ohm T-Gate TFTs T vacuum =1000A L sub-gate =2500A Tox=400A Channel width=10μm Channel length=5μm Channel Length (μm) Fig Turn-On resistance as a function of channel length at different gate voltages for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å Drain current ( A ) 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 NH 3 passivation 1HR No NH 3 passivation T vacuum =1000A L sub-gate =2500A W10L5 Tox=400A Mobility ( cm 2 /Vs ) 1E Gate voltage ( V ) Fig Transfer characteristics of n-channel T-Gate LTPS TFTs with and without NH 3 plasma passivation 68

85 Fig The schematic definition of the forward- and reverse-mode measurements 1E-4 1E-4 1E-5 Forward D =0.1V 1E-5 Drain current ( A ) 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 Reverse mode@v D =0.1V T vacuum 1000A L sub-gate 2500A Channel width=10μm Channel length=5μm Tox=400A No NH 3 passivation 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-13 1E Gate voltage ( V ) 1E-14 Fig Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs before NH 3 plasma passivation 69

86 Fig The schematic definition of the forward mode and reverse mode without plasma passivation Fig The statistical bar chart of the drain current difference ( I) between forward mode and reverse mode for T-Gate TFTs in which the thickness of vacuum gap is 1000Å and the L subgate is 2500 Å without plasma passivation 70

87 1E-4 1E-4 1E-5 Forward D =0.1V 1E-5 Drain current (A) 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 Reverse D =0.1V T vacuum =1000A L sub-gate =2500A Channel width=10μm Channel length=5μm Tox=400A NH 3 passivation 1HR 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-13 1E E-14 Gate voltage ( V ) Fig Symmetrical transfer characteristics of n-channel T-Gate LTPS TFTs with NH 3 1 HR plasma passivation NH 3 plasma passivation 1HR Fig The statistical bar chart of the drain current difference ( I) between forward mode and reverse mode for T-Gate TFTs in which the thickness of vacuum gap is 1000 Å and the L subgate is 2500 Å with 1-HR NH 3 plasma passivation 71

88 1E-3 1E-3 1E-4 T vacuum = 0 (CONV.) 1E-4 1E-5 T vacuum = 500 A 1E-5 1E-6 T vacuum = 1000 A 1E-6 Gate current (A) 1E-7 1E-8 1E-9 1E-10 1E-11 L sub-gate = 2500 A Channel width = 10 μm Channel length = 5 μm T ox = 400 A 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-12 1E-13 1E-13 1E-14 1E Eeletric Field (MV/cm) Fig Gate oxide breakdown fields of T-Gate and conventional TFTs Electric field (MV/cm) 8M 7M 6M 5M 4M 3M 2M 1M T vacuum =0 (CONV.) T vacuum =1000A V G =25V V D =V S =0V Position Along Channel Layer, X ( um ) Fig Simulated electric fields in the gate oxide of T-Gate and conventional TFTs 72

89 1E-4 Drain currnt ( A ) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 T-Gate TFTs T Vacuum =1000A Channel width=10μm Channel D =0.1V Forward mode Stress condiction V D =10V V G =1.5V 0s 10s 50s 100s 200s 500s 1000s 1E-12 1E-13 1E Gate voltage ( V ) Fig. 3-1 Transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 1E-4 Drain currnt ( A ) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 Conv.TFTs Channel width=10μm Channel D =0.1V Forward mode Stress condiction V D =10V V G =1.5V 0s 10s 50s 100s 200s 500s 1000s 1E Gate voltage ( V ) Fig. 3-2 Transfer characteristics of the conventional TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 73

90 Threshold voltage shift (V) T-Gate TFTs Conv. TFTs Stress time (s) Fig. 3-3 Threshold voltage shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. Transconductance Gm shift (%) Stress time (s) T-Gate TFTs Conv. TFTs Fig. 3-4 Transconductance shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 74

91 T-Gate TFTs Conv. TFTs DIBL shift (mv) Stress time (s) Fig. 3-5 DIBL shift of T-Gate and conventional TFTs after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. Fig. 3-6 Potential barrier for carrier transport raised by filled negative trap states (or charges) in poly-si channel near drain. (Ref. Shen De WANG, et al. JJAP Vol. 44, No. 9A, 2005, pp ) 75

92 Fig. 3-7 Schematic diagram of traps in drain depletion region and corresponding energy band diagram of Off-stated poly-si TFT (Ref. Shen De Wang, et al. JJAP Vol. 44, No. 9A, 2005, pp ) Fig. 3-8 Comparison of electric fields in the interface of gate oxide and poly-si near drain between before and after creation of positive oxide charges (Ref. Shen De Wang, et al. JJAP Vol. 44, No. 9A, 2005, pp ) 76

93 Fig. 3-9 Schematic illustration of localized positive oxide charges trapped near drain region after drain avalanche hot carrier stress for poly-si TFT 1E-4 Drain currnt ( A ) 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 T-Gate TFTs T Vacuum =1000A Channel width=10μm Channel D =0.1V Reverse mode Stress condiction V D =10V V G =1.5V 0s 10s 50s 100s 200s 500s 1000s 1E-13 1E Gate voltage ( V ) Fig Reverse-mode measured transfer characteristics of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 77

94 Drain currnt ( A ) E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 T-Gate TFTs T Vacuum =1000A Channel width=10μm Channel D =3V Forward mode Stress condiction V D =10V V G =1.5V Gate voltage ( V ) 0s 10s 50s 100s 200s 500s 1000s Fig Transfer characteristics measured at V D = 3 V of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. Drain currnt ( A ) E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 T-Gate TFTs T Vacuum =1000A Channel width=10μm Channel D =3V Forward mode Stress condiction V D =0V V G =20V Source floationg Gate voltage ( V ) 0s 10s 50s 100s 200s 500s 1000s Fig Transfer characteristics measured at V D = 3 V of the T-Gate TFTs before and after oxide electron trap stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 78

95 Drain currnt ( A ) 1E-9 1E-10 1E-11 1E-12 0s 10s 50s 100s 200s 500s 1000s 1E Gate voltage ( V ) Fig Leakage current variation measured at V D = 3 V of the T-Gate TFTs before and after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. Drain currnt ( A ) 1E-9 1E-10 1E-11 1E-12 0s 10s 50s 100s 200s 500s 1000s 1E Gate voltage ( V ) Fig Leakage current variation measured at V D = 3 V of the T-Gate TFTs before and after oxide electron trap stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 79

96 Drain currnt ( A ) 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 T-Gate TFTs T Vacuum =1000A Channel width=10μm Channel D =0.1V Forward mode Stress condiction V D =10V V G =1.5V Gate voltage ( V ) 0s 10s 50s 100s 200s 500s 1000s Without NH 3 passivation Fig Transfer characteristics of the T-Gate TFTs without plasma passivation before and after hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. Transconductance Gm shift (%) 10 0 T-Gate TFTs with NH 3 passivation T-Gate TFTs without NH passivation Stress time (s) Fig Transconductance shift of T-Gate TFTs with and without plasma passivation after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 80

97 80 60 T-Gate TFTs with NH 3 passivation T-Gate TFTs without NH 3 passivation DIBL shift (%) Stress time (s) Fig DIBL shift of T-Gate TFTs with and without plasma passivation after drain avalanche hot carrier stress at V D = 10 V and V G = 1.5 V from 0 to 1000 seconds. 81

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110 簡 歷 姓名 : 林偉凱性別 : 男籍貫 : 台北縣生日 : 民國七十二年四月二九日地址 : 台北縣土城市廣興街 53 號 12 樓學歷 : 台北縣立信義國小 ( 民國八十四年六月畢業 ) 台北縣立中山國中 ( 民國八十七年六月畢業 ) 台北市立松山高中 ( 民國九十年六月畢業 ) 國立成功大學工業設計系 ( 民國九十五年六月畢業 ) 國立交通大學電子所 ( 民國九十七年七月畢業 ) 論文題目 : Study on the Performance and Reliability of T-Shaped-Gate Low-Temperature Polycrystalline Silicon Thin Film Transistors with Vacuum Gaps 具有真空間隙之 T 型閘極低溫多晶矽薄膜電晶體之性能與可靠度之研究 94