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1 2.4GHz CMOS PA,,, 2010/07/21

2 Contents 1

3 Introduction 2 PA (Power Amplifier) 2.4GHz : WiMAX, WLAN, Bluetooth

4 Introduction 3 Capacitive cross-coupling Self-biased cascode

5 Schematic 4 Out V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- V Bias4 A (1 st stage), AB (2 nd stage) P out 3dB

6 Proposed circuit 2 Transformer Out 5 V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- V Bias4 The 1st stage The 2nd stage

7 Transformer 6 P sat Z out P sat ( V = DD Z out 2 ) 2 P sat Turn ratio=2:1 Z out (50Ω) ¼Z out (12.5Ω) P sat V ( = DD ( 1 4 ) 2 Z ) out = [W] = 2 ( ) = 2 (2 1 50) [dBm]

8 Transformer 7 Maximum Available Gain [db] =0.7 Maximum Available Gain(MAG)=-1.05 db ( -1.05dB 10 ) = =78.5 % Frequency [GHz] Sim. Meas. Phase [degree] Phase(S31) meas. Phase(S31) sim. Phase(S32) meas. Phase(S32) sim Frequency [GHz]

9 Proposed circuit 3.3V I/O Out 8 Self-biased V DD 2 : 1 V DD V Bias1 V Bias2 V Bias1 V Bias3 In+ In- 3.3V I/O V Bias4 Self-biased

10 Self-biased cascode 9 at the 2 nd stage V dd V Bias C gd v d Voltage v g C bypass v s [ ] C gs v g = C C bypass gd + C gd v d v gd Tr C bypass [1] T. Sowlati, et al., A 2.4-GHz 0.18-µm CMOS Self-Biased Cascode Power Amplifier, IEEE Journal of Solid- State Circuits, pp , 2003

11 Vg 10 Voltage [V] Vd2 Vg2 Vd1 [Self-biased cascode] Time [nsec] V d 19% C bypass =14.5pF

12 Gain degradation 11 Gain [db] Standard cascode Using crosscoupling Self-Biased Pin [dbm] Self-biased

13 Capacitive cross-coupling Self-biased cascode Using capacitive cross-coupling 12 v g = C C bypass gd + C gd v d v g = C bypass C gd C + ( C gd c C c v ) d v g =v d 18% C gd C bypass

14 Vg 2 13 Pin=5dBm 9 V DD 8 7 V Bias -v d Cc v g2 C bypass C gd v d2 v d1 [ Self-biased cascode with ] capacitive cross-coupling V d 18% Voltage [V] Vd2 Vg2 Vd Time [nsec] C bypass =8.6pF

15 Chip micrograph 14 DC pad 2nd stage Transformer 1:2 1fF/µm 2 MIM C bypass = 14.5pF 8.6pF C cc = 1.5pF

16 S-parameter measurement results S21 [db] 20 S22 [db] Sim. Meas Frequency [GHz] Sim. Meas Frequency [GHz]

17 Measuring system 16

18 Large signal measurement result 17 Around 2.4 GHz PAEmax [%], Psat [dbm] PAE max 31 % P sat 27 dbm 25 maxpae Psat Freqency [GHz]

19 Large signal measurement result GHz 40 Pout(Meas.) Gain(Meas.) PAE(Meas.) Pout(Sim.) Gain(Sim.) PAE(Sim.) 50 Pout [dbm], Gain [db] Pin [dbm] PAE [%] P 1dB = 25 dbm P sat = 27.7 dbm Gain = 26.5 db PAE 1dB = 26.8 % PAE max = 34.3 %

20 I-Q constellation measurement 19 QPSK 100Msps(200Mbps) 16QAM 100Msps(400Mbps) 64QAM 100Msps(600Mbps) EVM:6.49% EVM:9.09% EVM:9.13% AWG clock: 10 GS/s

21 Comparison of CMOS PAs 20 [2] [3] [4] [5] This work Technology 90nm 130nm 180nm CMOS V DD 3.3 V 1.2 V 3.3 V 3.3 V 3.3 V Frequency 2.4 GHz P 1dB 27.7 dbm 24 dbm 24.5 dbm 27 dbm 25.2 dbm P sat 30.1 dbm 27 dbm - 31 dbm 27.7 dbm PAE peak 33 % *32 % 31 %@1dB 27 % 34.3 % Area 4.3 mm mm mm mm mm 2 * Drain efficiency [2] D. Chowdhury, et al., A Single-Chip Highly Linear 2.4GHz 30dBm Power Amplifier in 90nm CMOS, IEEE International Solid-State Circuits Conference, pp , 2009 [3] G. Liu, et al., Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off, IEEE Journal Of Solid-State Circuits, vol. 43, No. 3, pp , Mar [4] J. Kang, et al., A Single-Chip Linear CMOS Power Amplifier for 2.4GHz WLAN, IEEE International Solid- State Circuits Conference, pp , 2006 [5] K. An, et al., A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control, IEEE Microwave and Wireless Components Letter, vol. 19, No. 7, pp , July. 2009

22 Conclusion GHz PA TSMC 0.18µm CMOS 3.3V I/O Self-biased Results P 1dB = 25.2dBm, P sat = 27.7dBm, PAE peak =34.3% C bypass 14.5pF 8.6pF(41% )

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94

NANO COMMUNICATION 23 No.3 90 CMOS 94/188 GHz 23 90 CMOS 94/188 GHz A 94/188 GHz Dual-Band VCO with Gm- Boosted Push-Push Pair in 90nm CMOS 90 CMOS 94/188GHz LC class-b 0.70 0.75 mm 2 pad 1 V 19.6 ma (ƒ