ELECTRI C MACHINES AND CONTROL Vol. 14 No. 6 June 2010 FPGA PWM PWM IP PWM PWM PWM PWM FPGA FPGA DSP SPWM FPGA TM 343 A X 2

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1 ELECTRI C MACHINES AND CONTROL Vol. 14 No. 6 June 2010 FPGA PWM PWM IP PWM PWM PWM PWM FPGA FPGA DSP SPWM FPGA TM 343 A X Applicaion of FPGA in high-power muliphase variable speed drives LIU Dong HUANG Jin CHEN Gao YANG Jia-qiang YUAN Bao-cheng JIANG Hai-bo College of Elecrical Engineering Zhejiang Universiy Hangzhou China Absrac Due o he large number of pulse widh modulaion PWM channels required in high-power muliphase variable speed drives and heir synchronizaion problems a muli-pwm generaor based on PWM IP Inellecual Propery core using building block approach was proposed. The muli-pwm generaor wih he same ime base and independen conrol regisers realized synchronizaion of PWM signals and differen modulaion sraegies. Due o he hardware parallelism of Field Programmable Gae Array FPGA he high-performance riangular carrier generaor and high-reliabiliy faul proecion were realized. Based on a digial experimenal plaform conrolled by Digial Signal Processor DSP and FPGA a universal muliphase volage source inverer VSI was consruced and he variable frequency variable volage VVVF conrol sraegy based on sinusoidal PWM SPWM was accomplished on a nine phase inducion machine. The experimen resuls show ha he applicaion of FPGA in high-power muliphase variable speed drives benefis from is universaliy flexibiliy and high reliabiliy. Key words variable speed pulse widh modulaion Field Programmable Gae Array faul proecion C C

2 分频电路控制寄存器译码地址线 3 片选信号 1 和接周期寄存器计数读写信号 1 口电 TPR 器路计数寄存器 TCNT 1 PWM IP Fig. 1 Overall archiecure of universal PWM IP core PWM SPWM TI 30 PWM 4 DSP PWM TMS320C TMS320C28335 MC56F MHz khz FPGA 16 PWM DSP Alera PWM FPGA cyclone EP1C6240C6 405 MHz 300 MHz khz DSP MCU FPGA SPWM /SVPWM PWM 2 Field Programmable Gae Array FPGA 2 I /O PWM IP D PWM PWM FPGA 30 MHz PWM IP PWM 1. 1 PWM IP 数据线 16 死区寄存器 DBCON PWM IP PWM PWM 反相器 IP TI DSP PWM 2 IP Fig. 2 PWM carrier generaor TCON 比较寄存器 CMPR CLK CMPR 影子寄存器比较器死区产生死区寄存器 DBCON 保护封锁 PWM PWM 输出 PWM 上溢或者下溢信号 MHz 16 3 晶振时钟高频时钟锁相环低频时钟可逆计数器 1 可逆计数器 2 超前进位加法器 D 触发器上溢或者下溢信号 16 Principle of he 16-bi high frequency riangular

3 3 16 Fig. 5 Topology of a nine - phase volage sour Pos-simulaion waveforms of he 16-bi high frequency riangular carrier generaor 1.

3 6 FPGA %148% 滋 s %ns 9 65%535 32%767 32%766 32%765 32%764 32%763 37%26 U dc a b c i 32%767 32%766 32%765 32%764 32%763 65%531 65%532 65%533 65%534 65%535 65%534 65%533 65%532 65%531 65%530 九相感应电机 65%535 Fig Fig. 5 Topology of a nine - phase volage sour Pos-simulaion waveforms of he 16-bi high frequency riangular carrier generaor 1. 3 PWM 1ona FPGA PWM IP onb cos 2π /9 sin 2π /9 PWM 1onc 4 PWM IP cos 4π /9 sin 4π /9 1ond 1one = T cos 6π /9 sin 6π /9 s Msin ω * 1 s PWM IP 2 cos 8π /9 sin 8π /9 PWM IP PWM 1onf [ cos 10π /9 sin 10π /9 Mcos ω * s ] + PWM IP 1ong cos 12π /9 sin 12π /9 PWM IP cos 14π /9 sin 14π /9 1onh cos 16π /9 sin 16π /9 1 PWM IP 1oni PWM T s M 1ona 1onb 1onc 1ond 1one 1onf 1ong 1onh 1oni SPWM Fig. 4 片选地址 4 数据总线 16 3 地址线及读写译码电路 PWM#1 PWM#2 PWM#3 n 路 PWM PWM#n 片选 PWM1H PWM1L PWM2H PWM2H PWM3H PWM3H PWMnH PWMnH IP PWM Muli-PWM generaor configured by PWM IP cores 2 FPGA PWM DSP SPWM 5 SPWM DMA 5 SPWM VVVF SPWM 2. 2 FPGA DSP 6 TI 32 DSP TMS320C28335 A /D D /A CAN EEPROM Alera FPGA cyclone EP1C6240C6 SPWM PLC DSP FPGA PWM I /O FPGA DSP

54 14 FPGA FPGA I /O FPGA I /O FPGA DSP 30 MHz DSP GPIO FPGA 3 150 MHz DSP 300 MHz 50 Hz 8 khz 数字信号 D/A 转换触摸屏 CAN 控制器以太网扩展 RAM Fig.

SPWM 9 10 11 SPWM 九相逆变器 SPWM 输出 (200.0%V/div) I H G F E D C B A Fig. 9 9 时间 (2.0%ms/div) SPWM SPWM oupus of he nine phase moor WD 时钟 7 位分频电路 WDKEY 检测 Fig.

4 54 14 FPGA FPGA I /O FPGA I /O FPGA DSP 30 MHz DSP GPIO FPGA MHz DSP 300 MHz 50 Hz 8 khz 数字信号 D/A 转换触摸屏 CAN 控制器以太网扩展 RAM Fig. 6 6 模拟信号模拟信号采样 A/D 转换 FPGA%DSP 接口浮点 FPGA DSP 主控制器计算模块系统界面 IGBT 驱动信号 IGBT 故障信号数字输入 / 输出信号逻辑开关协处理器光纤传送器光纤接收器 IGBT 驱动模块控制系统外国器件 FPGA DSP Conrol plaform based on FPGA and DSP 2. 3 I /O FPGA IGBT FPGA PWM 7 10 FPGA 8 IGBT IGBT FPGA PWM 3 位分频系数 I /O SPWM P N = 15 kw T N = 150 N m U N =230 V I N = 9 A n p = 3 f = 50 Hz YOKOGAWA DL750 SPWM SPWM 九相逆变器 SPWM 输出 (200.0%V/div) I H G F E D C B A Fig. 9 9 时间 (2.0%ms/div) SPWM SPWM oupus of he nine phase moor WD 时钟 7 位分频电路 WDKEY 检测 Fig. 7 WD 检查 7 正常异常异常 8 位 WD 计数器 CLR WD 复位 Block diagram of he wachdog circui 相邻线电压 (100.0%V/div) 相电压 (100.0%V/div) 时间 (10.0%ms/div) 10 Fig. 10 Phase volage and adjacen line volage of he nine phase moor Fig. 8 FPGA FPGA IGBT IGBT CON- CEPT 2SD315A IGBT 8 2SD315A Pos-simulaion waveform of he wachdog circui FPGA FPGA

6 FPGA 55 PWM 12 IGBT PWM FPGA PWM IGBT PWM IGBT 九相电机定子电流 (1.2%A/div) Fig. 11 信号 (2.0%V/div) 信号 (2.0%V/div) 局部放大图 A%%B%%C%D%E%F%G%H%I 11 时间 (5.0%ms/div) Saor currens of he nine phase moor 时间 (20.

5 6 FPGA 55 PWM 12 IGBT PWM FPGA PWM IGBT PWM IGBT 九相电机定子电流 (1.2%A/div) Fig. 11 信号 (2.0%V/div) 信号 (2.0%V/div) 局部放大图 A%%B%%C%D%E%F%G%H%I 11 时间 (5.0%ms/div) Saor currens of he nine phase moor 时间 (20.0% 滋 s/div) 时间 (200.0% 滋 s/div) IGBT 故障信号上桥臂 PWM 信号下桥臂 PWM 信号局部放大图 IGBT 故障信号上桥臂 PWM 信号下桥臂 PWM 信号 12 FPGA PWM Fig. 12 PWM block by FPGA when faul happens 4 FPGA PWM IP PWM FPGA 9 I /O FPGA DSP J ZHAO Pinzhi YANG Guijie LIU Chunlong. Opimal SVPWM algorihm for five-phase VSI J. Elecric Machines and Conrol KATS Y. Adjusable-speed drives wih muliphase moors C / / 1997 IEEE Inernaional Elecric Machines and Drives Conference May Milwaukee USA. TC2 /4. 3. WANG Yehui LIN Yixia YAN Wei. Design of wach - dog im- FPGA J er circui wih CPLD J 1997 TC2 / Y J ZHANG Jingnan CONG Wang DAI Ke. Research on a mahemaical model of a muli-phase Y-coil synchronous moor J. Journal of Harbin Engineering Universiy HOU Lijun SU Yanmin CHEN Lin. DSP-based indirec roor field orien conrol for 15-phase inducion machines C / /2002 IEEE Region 10 Conference on Compuers Communicaions Conrol and Power Engineering Ocober Beijing China FP- GA J YAN Jingbin LIU Jiahui XIE Jinbao e al. FPGA implemenaion of he vecor-conrolled speed servo sysem J. Elecric Machines and Conrol CORDIC FPGA PMSM J z WU Heng WANG Ganquan CHEN Guilin. Applicaion of CORDIC algorihm in FPGA based PMSM conroller J. Elecric Machines and Conrol z PWM J LI Jianlin WANG Liqiao LI Caixia e al. Muli-PWM pulse generaor based on FPGA J. Proceedings of he CSEE PWM J HU Haibing YAO Wenxi JIANG Huihong e al. Design of a u- niversal PWM generaor wih arbirary number of PWM channels J. Transacions of China Elecroechnical Sociey J YANG Jiaqiang HUANG Jin KANG Min e al. Elecronic pole changing echnique of muli-phase inducion moor J. Elecric Machines and Conrol CPLD Elecronic Engineer SVPWM

6 CCM Boos 45 v L1 v v L D1 v D3 C 1 C vc vc 1 v in S R ESR1 R ESR 1 maximum power poin racking MPPT Fig. 1 DC DC 1. CCM Boos S CCM Boos 1 a C 1 i L D

6 CCM Boos 45 v L1 v v L D1 v D3 C 1 C vc vc 1 v in S R ESR1 R ESR 1 maximum power poin racking MPPT Fig. 1 DC DC 1. CCM Boos S CCM Boos 1 a C 1 i L D 16 6 1 6 ELECTRI C MACHINES AND CONTROL Vol. 16 No. 6 Jun. 1 CCM Boos 6131 CCM Boos CCM Boos CISM IISM CISM IISM CCM Boos CISM IISM CCM Boos CISM CISM IISM Boos TM 46 A 17 449X 1 6 44 6 Energy ransmission