4 020 Application Trend and Fabrication Introduction of 3D Integrated Circuits Through Silicon Vias Technology Abstract The three-dimensional integrated circuits through silicon vias (3D IC TSV) technology is a powerful solution for continuing the Moore s law. The 3D silicon packaging integration of active devices with TSV, thinned silicon wafer, and silicon to silicon finepitch interconnections offers many product benefits. The advantages of 3D IC TSV technologies can include the following: multi-functions hetero-integration, power consumption reduction, product miniaturization, device performance enhancements, cost reduction and product for time to market. In this paper, the application trend of 3D IC TSV technology and fabrication introduction of so-called vias-first TSV, vias-middle TSV, vias-last TSV and vias after bonding TSV technologies will be described in detail for readers. Keywords (3D Integrated Circuits Through Silicon Vias (3D IC TSV)) (Application Trend) (Fabrication Introduction) (Vias-first) (Viasmiddle) (Vias-last)(Vias after Bonding)
NANO COMMUNICATION 20 No.3 021 (Integrated Circuits, ICs) (I/O)18 (Moore s law) 32 nm ( ) (Hetero-integration) (Time to market) (Packaging technology) (Wire Bonding) (3D packaging) 1(a) (Flip chip) I/O C4(C4 solder bump) (Bump pitch) 150 µm 1(b) (Multi-chip module, MCM) (Multi-chip package, MCP)PoP(Package on package) PiP(Package in package) (System in package, SiP) 1(c) AMDMCM (Embedded Video Card) (3D Integrated Circuits Through Silicon Vias Technology, 3D IC TSV technology) 3D IC TSV Moore's law (3D Vertical Stacked Packaging) 3D TSV 2D 3D (Wafer Drilling) (Filling) (Wafer Thinning) (Wafer Bonding) 3D TSV (a) [1] (b) [2] (c)mcm [3] 1 º
4 022 2 3D TSV [4] º 3 (Full 3D IC ) [4] º Yole Development 3D IC TSV ( 2 [4] ) (Logic & Analog 3D SoC/SiP) (Wide I/ O Interfaces) (Logic & Memory) LED (HB-LED modules) (Stacked Memories)/ (Power, Analog & RF) (MEMS & Sensors)CMOS (CMOS Image Sensors, CIS) CIS 3D TSVCIS MEMS (Digital signal processor, DSP) (Wafer Level Packaging, WLP)Sony (Active Pixel Sensor) IC(Logic IC)3D TSV CIS Active pixel Logic IC CIS CIS(Chip Scale Package, CSP) MEMS CMOS IC(Application-specific IC, ASIC)/ SiP (DRAM)3D TSVDRAM NAND flash( )
NANO COMMUNICATION 20 No.3 023 ) 59 %Stacked Memories 3D WLP Encapsulation( )23 %CIS MEMS & Sensors HB-LED modules 3D Interposer Module( ) 18 %Logic & analog 3D SoC/SiP Logic & Memory Power, Analog & RF 3D TSV DRAM 4 2013 3D TSV [4] 3D TSV SiP (Mobil RAM) (High Power Consumption) (Wide I/O mobile RAM) Wide I/OI/O 512 1200 DRAM3D TSV DRAM (Elpida) 2011 3D TSV8 GB DRAM (4 DDR3 2 GB) 3D TSV 3D TSV (Full '3D IC')2 3 [4] Full '3D IC' (Analog Chip)(Silicon Interposer) Logic DRAM Flash MEMSRF (CSP) (Intel) (TSMC)(Samsung) SiP 3D TSV ( 4 [4] )3D TSV Stack( 3D TSV5 (TSV) (Cu) (Polysilicon) (Metal bumps) (Bonding Pads) (Sn) (Au) (Re-distribution layers, RDL) 5 (TSV) º
4 024 1 3D IC TSV [5]º [5] TSV 50 µm 5 µm TSV 100 µm 10 µm TSV (Aspect ratio) 10TSV 3 µm 16.7 3D TSV RDL (Layer to layer) (Fan in)(fan out) TSV (Oxide liner) TSV (Adhesion and Diffusion Barrier Layer) (Wettable or Seed Layer) (Passivation Layer)TSV (Ti) (Ta) (Physical Vapor Deposition, PVD) (Au) TSV TSV TSV 1 IMEC 3D IC TSV (Active Devices) (Silicon Interposer) (1)TSV (TSV etch) (2)TSV (TSV fill) (3) (Carrier Bonding) (4) (Wafer Thinning) (5) (Carrier de-bonding) 3D TSV TSV ( TSV etch TSV fill) Via-first( ) Via-middle( ) Via-last( ) Via after bonding( ) 6 [4] Viafirst TSV TSV CMOS ( (FEOL)) 1000 CMOS CMOS Via-first TSV (Heavily Doped Polysilicon) TSV CMOS! ( µ -cm) ( 1.67 µ -cm) Via-middle TSV TSV CMOS ( FEOL) (BEOL) CMOS TSV (450 ) (IC) (Metallization Process) TSV IC Via-first TSV Viamiddle TSV (IC Process) SoC SiP (IC Foundries)
NANO COMMUNICATION 20 No.3 025 6 3D TSV TSV [4] º Via-last TSV TSV CMOS ( FEOL) BEOL Via after Bonding TSV CMOS ( FEOL) BEOL TSV Via-middle TSV Via-last TSV Via after bonding TSV Via-last TSV Via after Bonding TSV TSV (Package House, PH) Via-last TSV Via-last TSV Via after bonding TSV TSV (50 µm ) TSV TSV CIS MEMS & sensors LED Via-last TSV Via after bonding TSV 2D 3D IC TSV
4 026 Wide I/O mobile RAM DDR4 DRAM Wide I/O TSV (High Density) (Small Diameter) (Short Pitch) (Fine Pitch) Via-last TSV Via-middle TSV Via-first TSV Source: Yole Development 7 3D TSV [4] º 3 D T S V ( 1 ) T S V ( T S V formation) (2) (Wafer Handling) (3) (4) (5) (Wafer Test) 7 TSV TSV (Patterning) (Low Undercut) TSV (Deep RIE) (Voidless) TSV (CMP Uniformity)TSV (PH) (Wafer Level) Via-first TSV Viamiddle TSV 50-100 µm (Flexible) (Temporary Carrier)? TSV? (Wafer to Wafer Bonder) 8 3D TSV [4] º (Grinding) (Nailing)TSV CMP Grinding? Grinding (Stress release) PH (Assembly) (W2W) (C2W)
NANO COMMUNICATION 20 No.3 027 (Wide I/O) 0.5 µm (Micro Bumps) (Copper Pillars) (Underfill)? TSV TSV (Yield Inspection) (Reliability Test) TSV I/O 8 3D TSV [4] 41 % TSV 26 % BEOL (Vias Drilling) Vias 2-9 % [3] http://www.anandtech.com/show/4307/amd-launchesradeon-e6760 [4] http://www.i-micronews.com/reports/ [5] Beyne, E., Requirements, challenges and current status of thin wafer carrier systems for 3D TSV thinning and backside processing, Semicon West Conference: 3D IC Manufacturing- From Concept to Commercialization, 13 July 2011, San Francisco, CA, USA. 3D IC TSV Moore s law IC TSV Via-first TSV Via-middle TSV Via-last TSV Via after Bonding TSV TSV TSV etch TSV fill Carrier Bonding Wafer Thinning Carrier de-bonding 3D TSV 3D TSV stack 3D WLP Encapsulation 3D Interposer Module 3D TSV CSP Full 3D IC 3D IC TSV [1] http://www.toshiba.co.jp/about/press/2004_01/pr2101. htm [2] http://www.engr.sjsu.edu/wofmate/semiconductors.htm.