P.1

Size: px

Start display at page:

Download "P.1"

履裤孟
5 years ago
Views:

1 P.1

2 P IC IC 5.

3 P.3 (Interconnection)..

4 P.4 (Wafer) (Chip) (MCM)

5 P.5 電子構裝之主要功能電源供應層 1.有效供應電源信號分佈層 2.提供信號傳輸協助散熱保護元件 3.協助排除耗熱 4.保護電子組件 5.建構人機介面 Images 3D Graphics 建構人機介面

6 P.6 DIP Dual In-Line Package SOP Small Outline Package SOJ Small Outline J-Lead PLCC Plastic Leaded Chip Carrier PGA QFP Quad Flat Pack Pin Grid Array PBGA Plastic ball Grid Array

7 P.7

8 P.8 (Epoxy Molding Compound) (Chip) (Gold Wire) (Lead) (Die Pad) (Silver Epoxy)

9 Ball Grid Array (BGA) P.9

10 P / SMT 1. 2.

11 (Chip Interconnection) P (Wire Bonding) 2. (Flip Chip Bonding) ( ) 3. (TAB Tape Automatic Bonding)

12 P.12 Flip Chip Bonding TAB Wire Bonding /

13 P.13 PTH SMT Area Array Fine Pitch Area Array Direct Chip Attach on Board Chip Scale Pacage BGA PGA QFP TCP TO DIP

14 P IC IC 5.

15 IC - P.15 (Chip) (Leadframe) Wafer Backside Grinding Wafer Sawing Die Bonding Wire Bonding

16 IC - P.16 Transfer Molding Solder Plating Trimming & Forming 1. 1~ % 10% 3.Trimming Trimming 4.

IC P.17 4 11 9 7 1 8 1. (Delamination) 2. 3. 4. (lifted bond) 5.

17 IC P (Delamination) (lifted bond) 5. (Wire sweep) (Passivation) 11. (Mold void) (Die) 10

18 (Popcorn effect) P.18 (Solder Reflow)

19 IC Package P.19

20 P IC IC 5.

21 P.21 (Laminated PCB) (Flexible PCB) (Cofired Ceramics) Thin film on silicon (Deposited Thin Film) Thin film on ceramics Thin film on metal

22 P S 2. S S 3. S S P P S 4. S P S S P

23 PCB P oz B stage(prepreg)

24 P IC IC 5.

25 CSP (Chip Scale Package) P.25 Definition : chip scale package (CSP) is a package whose package-tosilicon area ratio less than 120 percent. CSP is derived from existing packages, that is, it can be any type of packages. Silicon (Flip Chip ) I/O Chip Scale Surface Mount Package area Silicon area < 1.2

26 CSP P (Rigid Substrate Interposer) 2. (Leadframe Type) 3. (Flex circuit Interposer) 4. (Transfer Molding) 5. (Wafer-Level)

27 Flip Chip P.27

28 Flip Chip P.28 fccsp Super FC fcpbga

29 Multi Chip Module P.29 Definition : Multi chip module (MCM) is a module or package which usually contains a high density interconnect substrate, several active and passive components, and a package which can be connected to the next level of interconnection. Chip Chip Chip Chip Chip Single Chip Module Multi Chip Module (MCM)

30 What is KGD? P.30 Known Good Die (KGD) is a die which has been manufactured and delivered in a bare, or minimally packaged die format, which has quality and reliability comparable to its functionally equivalent packaged component, can be interconnected to its next level of packaging by wirebond, tape automated bonding, or flip -chip.

31 MCM Yield as Function of Die Yield P.31 Source : TechSearch International, Inc.

32 P IC IC 5.

33 P.33 A. B. Flip Chip SIP Build-up C.High Tg D. High Dk IC A. MEMS&3D B.SIP(SOP) C.DCA COB SMT

34 System in Package P.34 Integral Substrate O-E Package / EOCB Built-in R Vcc Built-in Active Built-in C System-in-a-Package 3D Package O-E Device Wave guide Z-connection Built-in L GND MEMS / 3D Package Green Packaging

35 P.35 3D Packages Wire Bonding Wireless Bonding (FCB, others) COC (Chip on Chip) CIB (Chip In Board) Through Hole Source:JEITA

36 CiSP Chip in Substrate Package P.36 Source: from ITRI ( )

37 Ultra Thin Wafer P.37 Source:IZM

38 P.38 Lead Free Flip Chip Lead Free SMT BGA on Board Alloy: Sn/Ag/Cu Halogen Free Laminate Material Phosphorous Base Epoxy

Microsoft Word 電子構裝結構分析1221.doc

Microsoft Word 電子構裝結構分析1221.doc 電子構裝結構分析徐祥禎 ( 義守大學機械與自動化工程學系副教授 ) 前言電子構裝 (Electronic Packaging), 主要是利用固定接著技術, 將積體電路 (Integrated Circuit, IC) 晶片固定在承載襯墊 (Die Pad) 上, 並利用細微連接技