基于模型的可编程 SoC 设计与调试 MathWorks China Tom Shan Application Engineer 2015 The MathWorks, Inc. 1
主要内容 介绍 什么是 Zynq? 设计挑战 Zynq 设计 基于 MBD 的可编程 SoC 设计 代码生成 流程 验证和软硬件划分 UDP 接口 Processor In the Loop(PIL) 验证 新增功能 结论 2
什么是 Zynq? ARM Processor Dual Core Cortex -A9 Interface FPGA Fabric 7-series fabric Xilinx 新产品家族 All Programmable System on Chip (SoC) 单个芯片上集成 FPGA Fabric + ARM 使高性能系统开发成为可能 相对传统多芯片解决方案, 降低 BOM 成本 3
Zynq 设计的挑战 ARM Processor C/C++ Software Interface FPGA Fabric HDL Code Hardware FPGA 设计者不熟悉 ARM 嵌入式处理器的设计 DSP/Processor 设计者不熟悉 FPGA 的设计 什么应该采用 FPGA 实现 vs. 什么应该运行在 ARM 上? FPGA 与 ARM 处理器间的接口设计, 无设计规范可循 4
如何应对这些挑战并快速将我的项目在 Zynq 上跑起来? Model-Based Design (MBD) 提供了单一设计环境能 覆盖从需求到快速原型的无缝设计实现 软硬件联合开发有章可循 5
主要内容 介绍 什么是 Zynq? 设计挑战 Zynq 设计 基于 MBD 的可编程 SoC 设计 代码生成 流程 验证和软硬件划分 UDP 接口 Processor In the Loop(PIL) 验证 新增功能 结论 9
基于模型的 Zynq 设计 RESEARCH Embedded Coder ARM DESIGN Top-Level System Model Software Model IMPLEMENTATION REQUIREMENTS Hardware Model HDL Coder FPGA Zynq Template Xilinx Embedded System Integration Real-Time Parameter Tuning and Verification 用户自定义软硬件划分 MathWorks 自动代码生成和 PL/PS 间接口定义 MathWorks 工具自动完成编译, 并自动通过 Xilinx 配置硬件 10
基于模型的 SOC 设计 RESEARCH REQUIREMENTS Embedded Coder ARM DESIGN Top-Level System Model Software Model Hardware Model IMPLEMENTATION Embedded Coder HDL Coder FPGA HDL Coder Zynq Template Xilinx Embedded System Integration C HDL Real-Time Parameter Tuning and Verification GPIO ZedBoard Linux Shell GPIO Linux Kernel Display Controller Processing System (PS) ZedBoard Web Linux Application HDMI Video VGA Video AXI4-Lite Programmable Logic (PL) 11
代码的自动生成 Multi-Domain, Multi-Target Technology Multiple analyses and optimizations Simulink Stateflow IR Analysis/ Transform Intermediate Representation (IR) Analysis/ Transform Target Language Backend C C++ HDL PLC MATLAB Function Multiple Domains Multiple Targets 12
C/C++ 代码的自动生成工具 Embedded Coder Embedded Coder Automatically generate C and C++ optimized for embedded systems Simulink Coder Simulink Coder Automatically generate C and C++ from Simulink models and Stateflow charts MATLAB Coder MATLAB Coder Automatically generate C and C++ from MATLAB code 13
针对目标器件优化的 C/C++ 代码 SIMD intrinsic Fixed-point intrinsic Assembly Optimized libraries 1. Optimize the generated C/C++ code 2. Use the ARM NEON Media Processing Engine 14
VHDL/Verilog 代码自动生成工具 HDL Coder HDL Coder Automatically generate synthesizable RTL code (VHDL or Verilog) from MATLAB code and Simulink Model MATLAB Coder MATLAB Coder Automatically generate C and C++ from MATLAB code 15
HDL Coder 特性 代码生成 与目标器件无关的可综合的 RTL 代码 IEEE 1376 compliant VHDL IEEE 1364-2001 compliant Verilog 验证 自动生成 HDL test-bench 与 ModelSim 或 Incisive* 进行联合仿真 设计自动化 自动调用 Xilinx /Altera 综合工具 针对 area-speed 优化 自动配置 Xilinx Altera 板卡 * HDL Verifier required for co-simulation and FPGA-in-the-loop verification 16
Zynq 设计中基于模型的设计流程 MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW Simulink Model HDL IP Core Generation AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core 18
Zynq 设计中基于模型的设计流程 HDL IP Core Generation MATLAB and Simulink Algorithm and System Design AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink Programmable Logic IP Core External Ports EDK/Vivado Integration EDK/Vivado Integration FPGA Bitstream Zynq Platform Processing System AXI4-Lite AXI Video DMA AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core EDK Project 19
Zynq 设计中基于模型的设计流程 MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW EDK Integration SW Interface Model Generation Simulink Model SW Interface Model Generation FPGA Bitstream Zynq Platform SW Build SW I/O Driver Blocks SW SW Interface Model 20
Demo 23
two step process 24
Zynq Workflow Audio Example 25
Zynq Workflow Audio Example 26
Zynq Workflow Audio Example FPGA 27
Zynq Workflow 28
Zynq Workflow Hardware + Interface to ARM HDL Coder + Vivado 29
Zynq Workflow Interface Model (This will be used to generate C code for the ARM) 30
Zynq Workflow 31
Zynq Workflow AXI4 Interface 32
Zynq Workflow C Code for the ARM Embedded Coder + Xilinx SDK AXI4 Interface 33
Zynq Workflow Targeting the Zynq 34
DEMO (Zynq Workflow) 35
SoC 设计流程 The Design Process Phys Model Phys Model Real Hardware System 36
SoC 设计流程 The Design Process Phys Model Phys Model Real Hardware System 37
SoC 设计流程 The Design Process Phys Model Phys Model Real Hardware System 38
SoC 设计流程 The Design Process Phys Model Phys Model Real Hardware System 39
SoC 设计流程 How can models help you design applications for the Zynq? Simulate on your desktop Model controller and plant system dynamics Design and debug components at control loop fidelity Assemble and verify components at implementation fidelity Prototype on hardware Generate HDL code and build bitstream Generate C code and build ARM executable Collect hardware results and verify against simulation Generate C/HDL code for production Generate and review HDL code report Generate and review C code report Integrate generated code with production environment (ISE/Vivado) 40 40
主要内容 介绍 什么是 Zynq? 设计挑战 Zynq 设计 基于 MBD 的可编程 SoC 设计 代码生成 流程 验证和软硬件划分 UDP 接口 Processor In the Loop(PIL) 验证 新增功能 结论 41
AXI4-Lite Zynq Streaming Interface Support Generate HDL IP core with AXI4-Stream interface Enable high speed data transfer Simplify streaming protocol IP Core Generation Processing System AXI DMA AXI Lite Accessible Registers AXI4-Stream In AXI4-Stream Out AXI4-S Slave AXI4-S Master Algorithm from MATLAB/ Simulink Programmable Logic IP Core External Ports 45
AXI4-Stream Vector Mode Modeling HW and SW together Automatic generation of SW DMA driver Focus on HW/SW Rapid Prototyping Software Subsystem (vector) 1000 1000 Ser DeSer Hardware Subsystem (streaming) HDL DUT Software Subsystem (vector) 1000 1000 Software DMA Driver Software DMA Driver HDL Interface 46
主要内容 介绍 什么是 Zynq? 设计挑战 Zynq 设计 基于 MBD 的可编程 SoC 设计 代码生成 流程 验证和软硬件划分 UDP 接口 Processor In the Loop(PIL) 验证 新增功能 结论 47
结论 : 设计概念总结 将精力集中于系统和算法的设计上 在更高的抽象级上进行设计 AXI4-Lite Interface 自动代码生成及软 / 硬件集成 快速得到设计原型 AXI4-Lite AXI Lite Accessible Registers 灵活调整软硬件的划分 Processor AXI Video DMA AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports FPGA IP Core AXI4-Stream Interface 48
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Thank You 2015 The MathWorks, Inc. 50