7 FPGA 99 VGA FPGA Nios II Nios II Fig 1 Block diagram of video tracking system CMOS FPGA 1 FPGA SOPC Nios II CMOS RGB SDRAM Avalon Nios

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1 DOI: /j Transducer and Microsystem Technologies * FPGA FPGA CMOS SDRAM VGA SOPC SOPC TP 391 A Design of a FPGA-based hardware platform of realtime video tracking system * LIU Zi-yanFENG LiangQI Jia College of Electronics and Information Guizhou University Guiyang China AbstractA FPGA-based hardware platform design of video tracking system is presented which includes DSP CMOS image acquisition multiport SDRAM controller image VGA display SOPC system and PTZ control drive circuit etc. By using the platform real-time image acquisition caching displaying and PTZ driving can be realizedby adding code to SOPC systemdetecting trackingand positioning of moving targets can be realized and rotation direction of PTZ can be changed autonomous tracking can be realized. Key wordsvideo trackingimage processingfpga 0 SOPC FPGA SOPC ARM 2~ DSP 4 FPGA 1 Nios II 2 PWM FPGA ARM DSP FPGA FPGA ASIC SOPC FPGA Nios II Nios II I /O * J

7 FPGA 99 VGA FPGA Nios II Nios II 1 1 5 1 6 2 1 Fig 1 Block diagram of video tracking system CMOS FPGA 1 FPGA SOPC Nios II CMOS RGB SDRAM Avalon Nios II SDRAM 7 1 VGA SDRAM VGA SOPC Nios II 1.

2 7 FPGA 99 VGA FPGA Nios II Nios II Fig 1 Block diagram of video tracking system CMOS FPGA 1 FPGA SOPC Nios II CMOS RGB SDRAM Avalon Nios II SDRAM 7 1 VGA SDRAM VGA SOPC Nios II 1. 2 CMOS Fig 3 Architecture diagram of image capturing 2. 2 VGA 30 RGB FPGA SDRAM 2 SDRAM VGA SDRAM VGA SOPC DE2 70 VGA Nios II 16 D SUB Cyclone II FPGA VGA 2 ADV DAC CMOS SDROM VGA SOPC 4 VGA SDRAM 2. 1 VGA Fig 2 Work flow of video tracking system Terasic TRDB D5M TRDB D5M 500 GPIO FPGA TRDM D5M 3 FPGA FPGA I 2 C CMOS CMOS 3 SDRAM VGA VGA VGA

100 33 4_Port SDRAM 1 FIF02 4_Port SDRAM 2 FIF02 6 4_Port SDRAM Fig 4 4 VGA Image display architecture of VGA 2.

3 _Port SDRAM 1 FIF02 4_Port SDRAM 2 FIF02 6 4_Port SDRAM Fig 4 4 VGA Image display architecture of VGA 2. 3 SDRAM SDRAM FPGA first in first out FIFO SDRAM SDRAM 5 4_Port SDRAM 1 SDRAM 6 4_Port SDRAM Fig 6 Design block diagram of double 4_Port SDRAM CMD control module 2. 4 SOPC CMD SOPC CMD SDRAM SDRAM CMD CMD SDRAM 7 SOPC 输入输出 Fig 5 5 4_Port SDRAM Structure block diagram of 4_Port SDRAM controller VGA SOPC Nios II 7 SOPC Fig 7 SOPC system image processing flow 2 SDRAM 2 4_Port SDRAM SOPC Builder CMOS 2 4_Port SDRAM 1 SOPC Builder FIFO1 10 R 5 G Nios II SDRAM1 4_Port SDRAM 2 FIFO1 5 G 10 B SOPC 1 SDRAM2 VGA 4_Port SDRAM l FIFO1 4_Port SDRAM 2 FIFO1 Nios II 100 MHz SOPC SOPC CPU 1 FPGA 50 MHz

7 FPGA 101 2 FPGA SOPC Builder Nios II Process Nios II 3 SRAM 4 JTAG_UART PLL JTAG_UART PC Nios II PLL 5 PIO ID PIO Fig 10 FPGA hardware resource usage of system platform Nios II Nios 2 II 8.

4 7 FPGA FPGA SOPC Builder Nios II Process Nios II 3 SRAM 4 JTAG_UART PLL JTAG_UART PC Nios II PLL 5 PIO ID PIO Fig 10 FPGA hardware resource usage of system platform Nios II Nios 2 II 8. 1 IDE LCD 6 7 Nios II void task1void* pdata 2. 5 while printf" Hello ucos - II /n" OSTimeDlyHMSM0 3 0 SOPC PWM 8 10 FPGA EP2C70 FPGA LCD 11 LCD Nios II FPGA 8 Fig 8 System block diagram of PTZ control circuit 11 LCD Fig 11 LCD display test of soft core THB7128 Nios II CMOS CMOS C CMOS setup CMOS 9 Fig 9 Driver circuit architecture 3 Altera EP2C70 FPGA CMOS VGA IOWRCMOS_IF_0_BASE 4 0x maxaddr = 640* * 4 IOWRCMOS_IF_0_BASE 7 maxaddr IOWRCMOS_IF_0_BASE 1 0x IOWRCMOS_IF_0_BASE 2 &buffer1 length = 128* 4 IOWRCMOS_IF_0_BASE 3 length IOWRCMOS_IF_0_BASE 6 0x0001 FPGA MHz THB FPGA SOPC Nios II

102 33 1. FPGA D. 2011. 2. D. 2012. 3. FPGA D. 2013. 12 4. FPGA D. Fig 12 Acquisition and display of real-time image 2012. 5. FPGA 4 J. 20103 45-50. 6. FPGA ARM DSP J. 2012 385 243-246.

5 FPGA D D FPGA D FPGA D. Fig 12 Acquisition and display of real-time image FPGA 4 J FPGA ARM DSP J Hsu Yuan Pao Miao Hsiao Chun Tsai Ching Chih. FPGA implementation of a real-time image tracking systemc SICE Annual FPGA Conference 檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸 94 3Guo S X Fukuda T Asaka K. A new type of fish-like underwater microrobot J. IEEE /ASME Transactions on Mechatronics Takagi Kentaro Yamamura Masanori Luo Zhiwei et al. Development of a rajiform swimming robot using ionic polymer artificial musclesc Proceedings of the IEEE /RSJ International Conference on Intelligent Robots and SystemsBeijing Guo S Hata S Sugumoto K et al. Development of a new type of capsule micropumpc International Conference on Robotics and AutomationICRA 99 Detroit Lumia R Shahinpoor M. Microgripper design using electro-active polymersc Proceedings of SPIE the 1999 IEEE International Conference on Robotics and Automation Newport Beach MDK STM32 M STM32F103 J Shahinpoor M Kim K J. Ionic polymer-metal compositei. fundamentalsj. Smart Materials and Structures M M Claudia Bonomo Luigi Fortuna Pietro Giannone et al. A method to characterize IPMC membrane sensord. Ottawa CanadaUniversity of Catania IPMC 檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸檸 ANSYS Bragg 9. J J J J J

Microsoft Word - 32

Microsoft Word - 32 * 基于 Nios II 处理器的 USB 接口设计 * 项目基金 : 获中韩合作项目 Development of Embedded Software and System for Automobile Electronics 的资助 ; 重庆市科技攻关计划项目面向汽车 ABS 嵌入式系统的专用开发平台及其